This patch series adds support to access CSR using both CSR name and
CSR numbers.
Also, we should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec. (e.g.
It's better to have all RISC-V spec related defines in one place
so this patch adds separate asm/encoding.h for such defines which
can be included in assembly as well as C code.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 52 +-
On Mon, Mar 25, 2019 at 03:09:35PM +0530, Kishon Vijay Abraham I wrote:
> Add PCIe RC support for AM654x Platforms in pci-keystone.c
> +static int ks_pcie_am654_msi_host_init(struct pcie_port *pp)
> +{
> + struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
> + struct device *dev = pci->dev;
>
This file is implicitly relying on an instance of including
module.h from .
Ideally, header files under include/linux shouldn't be adding
includes of other headers, in anticipation of their consumers,
but just the headers needed for the header itself to pass
parsing with CPP.
The module.h is
From: Guo Ren
Modify SETUP_MMU macro to fit on both MMU-on or MMU-off enviornment
and vmlinux could bootup from MMU off enviornment for some cases.
Unify the style of _start and _start_smp_secondary in head.S to make
head.S looks more concise and easy to understand.
Signed-off-by: Guo Ren
Cc:
These two files are implicitly relying on an instance of including
module.h from .
Ideally, header files under include/linux shouldn't be adding
includes of other headers, in anticipation of their consumers,
but just the headers needed for the header itself to pass
parsing with CPP.
The module.h
Hi Linus,
The following changes since commit 582549e3fbe137eb6ce9be591aca25ca36b4:
Merge tag 'for-linus' of
git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma (2019-04-10 09:39:04
-1000)
are available in the Git repository at:
On Sat, Apr 13, 2019 at 08:41:33PM +0800, Nicolas Boichat wrote:
Dear stable maintainers,
I encountered a similar issue on a 4.19.33 kernel (Chromium OS). On my
board, the system would not even be able to boot if KASLR decides to
map the linear region to the top of the virtual address space.
On Mon, Mar 25, 2019 at 02:04:41PM +0530, Kishon Vijay Abraham I wrote:
> No functional change. Move host specific platform_get_resource to
> ks_add_pcie_port and the common platform_get_resource (applicable
> to both host and endpoint) to probe. This is in preparation for
> adding endpoint
From: YueHaibing
Fix sparse warning:
fs/eventfd.c:26:1: warning:
symbol 'eventfd_ida' was not declared. Should it be static?
Signed-off-by: YueHaibing
---
fs/eventfd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/fs/eventfd.c b/fs/eventfd.c
index ce8fa15..93b1fa7
On Wed, Apr 10, 2019 at 05:06:10PM -0700, Paul E. McKenney wrote:
> On Wed, Apr 10, 2019 at 01:33:02PM -0700, Paul E. McKenney wrote:
> > On Wed, Apr 10, 2019 at 09:19:18PM +0200, Sebastian Andrzej Siewior wrote:
> > > On 2019-04-10 11:41:05 [-0700], Paul E. McKenney wrote:
> > > > On Wed, Apr 10,
From: YueHaibing
Fix sparse warning:
drivers/interconnect/qcom/qcs404.c:27:21:
warning: symbol 'qcs404_rpm' was not declared. Should it be static?
Signed-off-by: YueHaibing
---
drivers/interconnect/qcom/qcs404.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: YueHaibing
Fix sparse warnings:
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:532:25: warning: symbol
'am33xx_gpio_hwmod_class' was not declared. Should it be static?
arch/arm/mach-omap2/omap_hwmod_33xx_43xx_ipblock_data.c:542:19: warning: symbol
'am33xx_gpio1_hwmod' was not
From: YueHaibing
Fix sparse warnings:
drivers/soc/ti/pm33xx.c:144:27: warning: symbol 'rtc_wake_src' was not
declared. Should it be static?
drivers/soc/ti/pm33xx.c:160:5: warning: symbol 'am33xx_rtc_only_idle' was not
declared. Should it be static?
Signed-off-by: YueHaibing
---
On Sat, Apr 13, 2019 at 4:30 AM Nicholas Mc Guire wrote:
>
> The header clearly identifies this code as GPL V2 or later - so pop
> in the SPDX license identifier.
>
> Signed-off-by: Nicholas Mc Guire
> ---
> arch/arm/mach-imx/mach-mx27ads.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Sat, Apr 13, 2019 at 10:20 AM Markus Kueffner
wrote:
>
> Add Pincfgs to enable the i.MX6's OTG feature for UDOO
>
> Signed-off-by: Markus Kueffner
Reviewed-by: Fabio Estevam
On Mon, Mar 25, 2019 at 03:09:23PM +0530, Kishon Vijay Abraham I wrote:
> pci-keystone driver uses irq_of_parse_and_map to get irq number of
> error_irq. Use platform_get_irq instead and move platform_get_irq()
> and request_irq() of error_irq from ks_pcie_add_pcie_port to ks_pcie_probe
> since
Hi Kishon,
On Mon, Mar 25, 2019 at 03:09:23PM +0530, Kishon Vijay Abraham I wrote:
> pci-keystone driver uses irq_of_parse_and_map to get irq number of
> error_irq. Use platform_get_irq instead and move platform_get_irq()
> and request_irq() of error_irq from ks_pcie_add_pcie_port to
From: YueHaibing
Fix sparse warnings:
fs/orangefs/super.c:155:5: warning: symbol 'orangefs_write_inode' was not
declared. Should it be static?
fs/orangefs/inode.c:387:5: warning: symbol 'orangefs_write_begin' was not
declared. Should it be static?
fs/orangefs/inode.c:445:5: warning: symbol
On Sat, Apr 13, 2019 at 02:19:52AM +, Michael Kelley wrote:
From: Dexuan Cui Sent: Friday, April 12, 2019 4:35 PM
With CONFIG_DEBUG_PREEMPT=y, the put_cpu_ptr() triggiers an underflow
warning in preempt_count_sub().
Fixes: 37cdd991fac8 ("vmbus: put related per-cpu variable together")
There is one compiling error in u2fzero_probe()->u2fzero_init_hwrng(),
this is because HW_RANDOM is not set.
drivers/hid/hid-u2fzero.o: In function `u2fzero_probe':
hid-u2fzero.c:(.text+0xc70): undefined reference to `devm_hwrng_register'
Fixes: 42337b9d4d958("HID: add driver for U2F Zero
Add Pincfgs to enable the i.MX6's OTG feature for UDOO
Signed-off-by: Markus Kueffner
---
Changes in v2:
- put pinctrl_usbotg node after pinctrl_usbh as suggested
- remove unsupported properties from
arch/arm/boot/dts/imx6qdl-udoo.dtsi | 14 ++
1 file changed, 14 insertions(+)
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Dear stable maintainers,
I encountered a similar issue on a 4.19.33 kernel (Chromium OS). On my
board, the system would not even be able to boot if KASLR decides to
map the linear region to the top of the virtual address space. This
happens every 253 boots on average (there are 0xfd possible
Hello Shuah,
did you get the mail related stuff below ?
On Fri, Apr 5, 2019 at 10:17 PM Florian Westphal wrote:
>
> Jeffrin Jose T wrote:
> > A test for the basic NAT functionality uses ip command which
> > needs veth device.There is a condition where the kernel support
> > for veth is not
On Fri, Apr 12, 2019 at 12:05 PM Neil Armstrong wrote:
>
> Add support for the IR decoder input on the X96 Max board.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
On Fri, Apr 12, 2019 at 12:05 PM Neil Armstrong wrote:
>
> Add support for the IR decoder input on the U200 Reference Design board.
>
> Signed-off-by: Neil Armstrong
Reviewed-by: Martin Blumenstingl
Hi Neil,
On Fri, Apr 12, 2019 at 12:05 PM Neil Armstrong wrote:
>
> Amlogic G12A SoCs uses the exact same IR decoder as previous
> families, add the IR node and the pintctrl setting.
as far as I can tell there are either two IR decoders or one updated
IR decoder in G12A and G12B.
I'm using
On Fri, Apr 12, 2019 at 12:03 PM Guillaume La Roque
wrote:
>
> Add TS clock used by two temperature sensor
>
> Signed-off-by: Guillaume La Roque
Reviewed-by: Martin Blumenstingl
On Fri, Apr 12, 2019 at 12:02 PM Guillaume La Roque
wrote:
>
> Add clock id used by temperature sensor for G12A Socs
nit-pick if you have to re-send if for some reason: "used by the
temperature sensors for G12A SoCs" (because as far as I know the two
temperature sensors share this clock)
>
On Fri, Apr 12, 2019 at 11:24 AM Neil Armstrong wrote:
>
> This adds the EE and AO PWM nodes and the possible pinctrl settings.
>
> Signed-off-by: Neil Armstrong
I reviewed the controller definitions and picked three pinctrl nodes -
all of them are fine:
Reviewed-by: Martin Blumenstingl
that
Hi Neil,
On Fri, Apr 12, 2019 at 11:24 AM Neil Armstrong wrote:
>
> For PWM controller in the Meson G12A SoC, the EE domain and AO domain
> have different clock sources. This patch tries to describe them in the
> DT compatible data.
>
> Signed-off-by: Neil Armstrong
> ---
>
From: Kangjie Lu
In case platform_device_alloc fails, the fix returns an error
code to avoid the NULL pointer dereference.
Signed-off-by: Kangjie Lu
Signed-off-by: Srinivas Kandagatla
---
drivers/slimbus/qcom-ngd-ctrl.c | 4
1 file changed, 4 insertions(+)
diff --git
From: Fabrice Gasnier
Add a read only nvmem driver for STM32 factory-programmed memory area
(on-chip non-volatile storage).
Signed-off-by: Fabrice Gasnier
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/Kconfig | 10 +
drivers/nvmem/Makefile | 2 +
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/mxs-ocotp.c | 4
From: Lucas Stach
The i.MX8MQ uses the same OCOTP block as the i.MX7D, but with
fourfold increase in fuse banks.
Signed-off-by: Lucas Stach
Reviewed-by: Abel Vesa
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/imx-ocotp.c | 7 +++
1 file changed, 7 insertions(+)
diff --git
From: Fabrice Gasnier
Add nvmem_cell_read_u16() helper to ease read of an u16 value on consumer
side. This is inspired by nvmem_cell_read_u32() function.
This helper is useful on stm32 that has 16 bits data cells stored in non
volatile memory.
Signed-off-by: Fabrice Gasnier
Signed-off-by:
From: Fabrice Gasnier
Add documentation for STMicroelectronics STM32 Factory-programmed
read only memory area.
Signed-off-by: Fabrice Gasnier
Reviewed-by: Rob Herring
Signed-off-by: Srinivas Kandagatla
---
.../bindings/nvmem/st,stm32-romem.txt | 31 +++
1 file
From: Lucas Stach
The i.MX OCOTP controller is used in numerous Freescale/NXP
SoCs from the MXC family, so the strict dependency on the
i.MX6 SoC is too narrow. Broaden it to cover all the MXC
familiy members.
Signed-off-by: Lucas Stach
Reviewed-by: Abel Vesa
Signed-off-by: Srinivas
From: Chen-Yu Tsai
SID cells are 32-bit aligned, and a multiple of 32 bits in length. The
only outlier is the thermal sensor calibration data, which is 16 bits
per sensor. However a whole 64 bits is allocated for this purpose, so
we could consider it conforming to the rule above.
Also, the
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/imx-iim.c | 4
From: Jorge Ramirez-Ortiz
When the bit_offset in the cell is zero, the pointer to the msb will
not be properly initialized (ie, will still be pointing to the first
byte in the buffer).
This being the case, if there are bits to clear in the msb, those will
be left untouched while the mask will
From: Anson Huang
Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.
Signed-off-by: Anson Huang
Reviewed-by: Mukesh Ojha
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/imx-ocotp.c | 4
From: Yangtao Li
qfprom->sunxi-sid
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Yangtao Li
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
From: Yangtao Li
Updates license to use SPDX-License-Identifier.
Acked-by: Maxime Ripard
Signed-off-by: Yangtao Li
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/sunxi_sid.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git a/drivers/nvmem/sunxi_sid.c
Resending this with cc to linux-kernel@vger.kernel.org
Hi Greg,
Here are some nvmem patches for 5.2 which includes:
- adding support to new stm32, sunix and imx providers
- few general cleanups
- fix for in place buffer reads.
Can you please pick these for 5.2.
thanks,
srini
Anson Huang (3):
From: Yangtao Li
Add support for H6's SID controller. It supports 4K-bit
EFUSE, bigger than before.
Signed-off-by: Yangtao Li
Acked-by: Maxime Ripard
Signed-off-by: Srinivas Kandagatla
---
drivers/nvmem/sunxi_sid.c | 6 ++
1 file changed, 6 insertions(+)
diff --git
From: Chen-Yu Tsai
The sunxi_sid driver currently uses a statically allocated nvmem_config
structure that is updated at probe time. This is sub-optimal as it
limits the driver to one instance, and also takes up space even if the
device is not present.
Modify the driver to allocate the
From: Chen-Yu Tsai
Since the reg_read callbacks already support arbitrary, but 4-byte
aligned. offsets and lengths into the SID, there is no need for another
for loop just to use it to read 1 byte at a time.
Read out the whole SID block in one go.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime
From: Chen-Yu Tsai
The device tree binding already lists compatible strings for these two
SoCs. They don't have the defect as seen on the H3, and the size and
register layout is the same as the A64. Furthermore, the driver does
not include nvmem cell definitions.
Add support for these two
From: Yangtao Li
Add a binding for H6's SID controller.
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
Signed-off-by: Yangtao Li
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/nvmem/allwinner,sunxi-sid.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
From: Fabrice Gasnier
On STM32MP15, OTP area may be read/written by using BSEC (boot, security
and OTP control). BSEC registers set is composed of various regions, among
which control registers and OTP shadow registers.
Secure monitor calls are involved in this process to allow (or deny)
access
From: Chen-Yu Tsai
Originally the SID e-fuses were thought to be in big-endian format.
Later sources show that they are in fact native or little-endian.
The most compelling evidence is the thermal sensor calibration data,
which is a set of one to three 16-bit values. In native-endian they
are in
From: Lucas Stach
Add compatible for i.MX8MQ and add i.MX7D/S, i.MX7ULP and i.M8MQ
to the description.
Signed-off-by: Lucas Stach
Reviewed-by: Rob Herring
Reviewed-by: Abel Vesa
Signed-off-by: Srinivas Kandagatla
---
Documentation/devicetree/bindings/nvmem/imx-ocotp.txt | 4 +++-
1 file
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On 4/13/19 12:02 AM, Dan Murphy wrote:
All
On 4/12/19 2:10 PM, Jacek Anaszewski wrote:
Dan,
On 4/12/19 1:50 PM, Dan Murphy wrote:
Marek
On 4/11/19 5:07 PM, Marek Behun wrote:
Hi Dan,
this probaly was discussed, but I did not follow brightness model
discussions:
what will happen if I
MAINTAINERS contains lower-case and upper-case variants of
Laurent Pinchart's email address.
Only keep the lower-case variant in MAINTAINERS.
Signed-off-by: Lukas Bulwahn
---
MAINTAINERS | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
MAINTAINERS contains a lower-case and upper-case variant of
Michael Hennerich' s email address.
Only keep the lower-case variant in MAINTAINERS.
Signed-off-by: Lukas Bulwahn
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index
Hello!
On 13.04.2019 11:40, Richard Weinberger wrote:
We well need struct nand_controller soon, so more stuff need to
We will, maybe?
be parts of struct nandsim.
While we are here, rename "nand" to "ns" to use the same naming scheme
everywhere in nandsim.
Signed-off-by: Richard
at 16:40, wrote:
Hi.
I've applied this patch, but still getting incomplete report messages.
Does the patch fix the other two issues:
- Five finger tap kill's module so you have to restart it;
- Two finger scoll is working incorrect and sometimes even when you
raised one of two finger still
We well need struct nand_controller soon, so more stuff need to
be parts of struct nandsim.
While we are here, rename "nand" to "ns" to use the same naming scheme
everywhere in nandsim.
Signed-off-by: Richard Weinberger
---
drivers/mtd/nand/raw/nandsim.c | 49 +-
Stop using the legacy interface.
Signed-off-by: Richard Weinberger
---
drivers/mtd/nand/raw/nandsim.c | 78 --
1 file changed, 47 insertions(+), 31 deletions(-)
diff --git a/drivers/mtd/nand/raw/nandsim.c b/drivers/mtd/nand/raw/nandsim.c
index
* Bart Van Assche wrote:
> On Fri, 2019-04-12 at 07:47 +0200, Ingo Molnar wrote:
> > So why don't we add a debug_locks test to lockdep_unregister_key()
> > instead? The general principle to bring lockdep to a screeching halt when
> > bugs are detected, ASAP.
>
> Hi Ingo,
>
> Since this
Convert driver to use devm_ioremap() to simplify memory deallocation
and error handling code. No functional change intended.
Signed-off-by: Andrey Smirnov
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.com
Cc:
Struct thermal_zone_device reference stored as sensor's private data
isn't really used anywhere in the code. Drop it.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc:
Now that driver is converted to use get_temp_id() instead of
get_temp() we no longer need per sensor data. Drop all of the code
related to it.
Signed-off-by: Andrey Smirnov
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc:
On 13/04/2019 10:18, Andrey Smirnov wrote:
> On Thu, Apr 4, 2019 at 1:07 AM Daniel Lezcano
> wrote:
>>
>> Currently when we register a sensor, we specify the sensor id and a data
>> pointer to be passed when the get_temp function is called. However the
>> sensor_id is not passed to the get_temp
Pass all necessary data to qoriq_tmu_register_tmu_zone() directly
instead of passing a paltform device and then deriving it. This is
done as a first step to simplify resource deallocation code.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo
Convert driver to use regmap API, drop custom LE/BE IO helpers and
simplify bit manipulation using regmap_update_bits(). This also allows
us to convert some register initialization to use loops and adds
convenient debug access to TMU registers via debugfs.
Signed-off-by: Andrey Smirnov
Cc: Chris
Tmu_get_temp will get called as a part of sensor registration via
devm_thermal_zone_of_sensor_register(). To prevent it from retruning
bogus data we need to enable sensor monitoring before that. Looking at
the datasheet (i.MX8MQ RM) there doesn't seem to be any harm in
enabling them all, so, for
We can simplify error cleanup code if instead of passing a "struct
platform_device *" to qoriq_tmu_calibration() and deriving a bunch of
pointers from it, we pass those pointers directly. This way we won't
be force to call platform_set_drvdata() as early in qoriq_tmu_probe()
and consequently would
Before returning measured temperature data to upper layer we need to
make sure that the reading was marked as "valid" to avoid reporting
bogus data.
Signed-off-by: Andrey Smirnov
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc:
Add devres wrapper for thermal_add_hwmon_sysfs() to simplify driver
code.
Signed-off-by: Andrey Smirnov
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.com
Cc: linux...@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
Expose thermal readings as a HWMON device, so that it could be
accessed using lm-sensors.
Signed-off-by: Andrey Smirnov
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.com
Cc: linux...@vger.kernel.org
Cc:
Use a local "struct device *dev" for brevity. No functional change
intended.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo Valentin
Cc: Daniel Lezcano
Cc: Angus Ainslie (Purism)
Cc: linux-...@nxp.com
Cc: linux...@vger.kernel.org
Cc:
Everyone:
This series contains patches adding support for HWMON integration, bug
fixes and general improvements (hopefully) for TMU driver I made while
working on it on i.MX8MQ.
Feedback is welcome!
Thanks,
Andrey Smirnov
Changes since [v3]
- Series reabse on top of [rfc]
- Fixed
It's impossible to use this driver outside of Device Tree, so if the
probe function is called, the dev.of_node is guaranteed to not be NULL
and guarding against that is pointless. Drop it.
Signed-off-by: Andrey Smirnov
Acked-by: Daniel Lezcano
Cc: Chris Healy
Cc: Lucas Stach
Cc: Eduardo
On Sat, 13 Apr 2019 01:17:19 -0400
Joshua Kinard wrote:
> On 4/12/2019 07:44, Thomas Bogendoerfer wrote:
> > On Fri, 12 Apr 2019 12:11:06 +0200
> > Alexandre Belloni wrote:
> >
> >> Every patch need a commit message. Maybe you could indicate that this
> >> never gave any issue because parent
On Thu, Apr 4, 2019 at 1:07 AM Daniel Lezcano wrote:
>
> Currently when we register a sensor, we specify the sensor id and a data
> pointer to be passed when the get_temp function is called. However the
> sensor_id is not passed to the get_temp callback forcing the driver to
> do extra allocation
On Sat, Apr 13, 2019 at 1:25 PM Christoph Hellwig wrote:
>
> On Sat, Apr 13, 2019 at 07:39:44AM +, Anup Patel wrote:
> > We should prefer accessing CSRs using their CSR numbers because:
> > 1. It compiles fine with older toolchains.
> > 2. We can use latest CSR names in #define macro names of
On Sat, Apr 13, 2019 at 1:23 PM Christoph Hellwig wrote:
>
> On Sat, Apr 13, 2019 at 07:39:35AM +, Anup Patel wrote:
> > It's better to have all RISC-V spec related defines in one place
> > so this patch adds separate asm/encoding.h for such defines which
> > can be included in assembly as
On Sat, Apr 13, 2019 at 1:24 PM Christoph Hellwig wrote:
>
> I think this should be merged with the next patch. Also please
> only add the CSRs that we actually use.
Sure, will do.
Regards,
Anup
On Fri, Apr 12, 2019 at 05:38:53PM +0800, Mao Han wrote:
> >
> > > + fp = user_backtrace(entry, fp, regs->ra);
> > > + while ((entry->nr < entry->max_stack) &&
> > > + fp && !((unsigned long)fp & 0x3))
> > > + fp = user_backtrace(entry, fp, 0);
> >
> > Please don't indent the
On Sat, 2019-04-13 at 09:14 +0200, Nicholas Mc Guire wrote:
> While preparing a proposed fix for a missing check on zmalloc a few
> other checkpatch warnings poped up - this little set fixes those
> warnings. There is one remaining checkpatch warning but that looks
> like a false-positive to me:
>
On Sat, Apr 13, 2019 at 07:39:44AM +, Anup Patel wrote:
> We should prefer accessing CSRs using their CSR numbers because:
> 1. It compiles fine with older toolchains.
> 2. We can use latest CSR names in #define macro names of CSR numbers
>as-per RISC-V spec.
> 3. We can access newly added
I think this should be merged with the next patch. Also please
only add the CSRs that we actually use.
On Sat, Apr 13, 2019 at 07:39:35AM +, Anup Patel wrote:
> It's better to have all RISC-V spec related defines in one place
> so this patch adds separate asm/encoding.h for such defines which
> can be included in assembly as well as C code.
can be included from assembly just fine already.
and
This patch series adds support to access CSR using both CSR name and
CSR numbers.
Also, we should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec. (e.g.
Each CSR is encoded as 12bit number in RISC-V instructions. This patch
adds defines for CSR numbers to allow us access CSRs using CSR numbers.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/encoding.h | 237 ++
1 file changed, 237 insertions(+)
diff --git
We should prefer accessing CSRs using their CSR numbers because:
1. It compiles fine with older toolchains.
2. We can use latest CSR names in #define macro names of CSR numbers
as-per RISC-V spec.
3. We can access newly added CSRs even if toolchain does not recognize
newly addes CSRs by
It's better to have all RISC-V spec related defines in one place
so this patch adds separate asm/encoding.h for such defines which
can be included in assembly as well as C code.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/csr.h | 52 +-
Even in init the allocation can fail and thus should at least warn so
that the cause can be identified.
Signed-off-by: Nicholas Mc Guire
---
Problem located with an experimental coccinelle script
Note sure if there is a better solution as this is early in the boot
process so not that could be
Current code is using devm_regulator_register() so we don't need to store
*rdev for clean up, use a local variable instead.
Signed-off-by: Axel Lin
---
drivers/regulator/tps6524x-regulator.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git
Sorry for the noise - I accidentally sent out a set of old patches
along with this cleanups set. Only the ARM: imx legacy: should
have goon out.
While preparing a proposed fix for a missing check on zmalloc a few
other checkpatch warnings poped up - this little set fixes those
warnings. There is
The regulator_ops is never changed, make it const.
Signed-off-by: Axel Lin
---
drivers/regulator/tps6524x-regulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/tps6524x-regulator.c
b/drivers/regulator/tps6524x-regulator.c
index
The header clearly identifies this code as GPL V2 or later - so pop
in the SPDX license identifier.
Signed-off-by: Nicholas Mc Guire
---
arch/arm/mach-imx/mach-mx27ads.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index
Checkpatch suggests to place a parenthesis around this complex macro.
Signed-off-by: Nicholas Mc Guire
---
Problem reported by checkpatch
I'm actually not sure this really is improving readability but by
default checkpatch gets it right so...
Patch was compile-tested with: imx_v4_v5_defconfig
provide the proper type for unsigned int.
Signed-off-by: Nicholas Mc Guire
---
Problem reported by checkpatch
Patch was compile-tested with: imx_v4_v5_defconfig (implies
CONFIG_MACH_MX27ADS=y)
Patch is against 5.1-rc4 (localversion-next is 20190412)
arch/arm/mach-imx/mach-mx27ads.c | 4 ++--
of_find_compatible_node() returns a device node with refcount incremented
and thus needs an explicit of_node_put(). Further relying on an unchecked
of_iomap() which can return NULL is problematic here, after all ctrl_base
is critical enough for hix5hd2_set_cpu() to call BUG() if not available
so a
imx_set_aips is assuming that the address returned from of_iomap is
valid which it probably is in the normal case - as the call site
is void error propagation is not possible but never the less at least
a WARN_ON() seems warranted here.
Signed-off-by: Nicholas Mc Guire
Fixes: commit
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