[PATCH 1/7] sched: Remove rq->cpu_load[] update code

With LB_BIAS disabled, there is no need to update the rq->cpu_load[idx] any more. Signed-off-by: Dietmar Eggemann --- include/linux/sched/nohz.h | 8 -- kernel/sched/core.c| 1 - kernel/sched/fair.c| 255 - kernel/sched/sched.h | 6

RE: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox

Hi Sudeep, > Subject: Re: [PATCH 0/2] mailbox: arm: introduce smc triggered mailbox > > On Thu, May 23, 2019 at 10:30:50AM -0700, Florian Fainelli wrote: > > Hi, > > > > On 5/22/19 10:50 PM, Peng Fan wrote: > > > This is a modified version from Andre Przywara's patch series > > > >

[PATCH v2 3/3] math-emu: Use statement expressions to fix Wshift-count-overflow warning

To avoid "shift count >= width of type" warning, using statement expressions to implement the conditional controlling before constant shift The modification in op-2.h is taken from the glibc commit 'sysdeps/unix/sysv/lin ("fe0b1e854ad32")'. Signed-off-by: Vincent Chen --- Changes in v2 - This

[PATCH v2 0/3] nds32: Prevent FPU emulator from incorrectly modifying IEX status

In order for kernel to capture each denormalized output, the UDF trapping enable bit is always raised in $fpcsr. Because underflow case will issue not an underflow exception but also an inexact exception, it causes that the IEX, IEX cumulative exception, flag in $fpcsr to be raised in each

[PATCH v2 2/3] nds32: add new emulations for floating point instruction

The existing floating point emulations is only available for floating instruction that possibly issue denormalized input and underflow exceptions. These existing FPU emulations are not sufficient when IEx Trap is enabled because some floating point instructions only issue inexact exception. This

[PATCH v2 1/3] nds32: Avoid IEX status being incorrectly modified

In order for kernel to capture each denormalized output, the UDF trapping enable bit is always raised in $fpcsr. Because underflow case will issue not an underflow exception but also an inexact exception, it causes that the IEX, IEX cumulative exception, flag in $fpcsr to be raised in each

[PATCH 4/3] perf tools: Remove const from thread read accessors

The namespaces and comm fields of a thread are protected by rwsem and require write access for it. So it ended up using a cast to remove the const qualifier. Let's get rid of the const then. Signed-off-by: Namhyung Kim --- tools/perf/util/hist.c | 2 +- tools/perf/util/thread.c | 12

Re: [PATCH v3 2/2] arm64: cacheinfo: Update cache_line_size detected from DT or PPTT

On Mon, May 27, 2019 at 10:06:08AM +0800, Shaokun Zhang wrote: > cache_line_size is derived from CTR_EL0.CWG field and is called mostly > for I/O device drivers. For HiSilicon certain plantform, like the > Kunpeng920 server SoC, cache line sizes are different between L1/2 > cache and L3 cache

Re: [PATCH v3 1/2] drivers: base: cacheinfo: Add variable to record max cache line size

On Mon, May 27, 2019 at 10:06:07AM +0800, Shaokun Zhang wrote: > Add coherency_max_size variable to record the maximum cache line size > for different cache levels. We will synchronize it with CTR_EL0.CWG > reporting in cache_line_size() for arm64. > > Cc: Greg Kroah-Hartman > Cc: "Rafael J.

[PATCH v1] mm: hugetlb: soft-offline: fix wrong return value of soft offline

Soft offline events for hugetlb pages return -EBUSY when page migration succeeded and dissolve_free_huge_page() failed, which can happen when there're surplus hugepages. We should judge pass/fail of soft offline by checking whether the raw error page was finally contained or not (i.e. the result

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