Hi Ming Lei,
On 03/09/2019 05:30, Ming Lei wrote:
[ ... ]
>>> 2) irq/timing doesn't cover softirq
>>
>> That's solvable, right?
>
> Yeah, we can extend irq/timing, but ugly for irq/timing, since irq/timing
> focuses on hardirq predication, and softirq isn't involved in that
> purpose.
>
>>
> Am 03.09.2019 um 04:38 schrieb Viresh Kumar :
>
> On 02-09-19, 12:55, H. Nikolaus Schaller wrote:
>> +opp1-12500 {
>> +opp-hz = /bits/ 64 <12500>;
>> +// we currently only select the max voltage from table
>> Table 3-3 of the
In function regmap_read(), there're two places which could make the read fail.
First, if "reg" and "map->reg_stride" are not aligned, then remap_read() will
return -EINVAL without initialize variable "val".
Second, _regmap_read() could also fail and return error code if "val" is not
On Thu, Aug 29, 2019 at 09:59:48AM +, David Laight wrote:
> From: Nathan Chancellor
> > Sent: 28 August 2019 19:45
> ...
> > However, I think that -fno-builtin-* would be appropriate here because
> > we are providing our own setjmp implementation, meaning clang should not
> > be trying to do
On Tue, 03 Sep 2019 07:30:04 +0200,
Jian-Hong Pan wrote:
>
> Takashi Iwai 於 2019年9月2日 週一 下午7:41寫道：
> >
> > On Mon, 02 Sep 2019 12:00:56 +0200,
> > Jian-Hong Pan wrote:
> > >
> > > Original pin node values of ASUS UX431FL with ALC294:
> > >
> > > 0x12 0xb7a60140
> > > 0x13 0x4000
> > > 0x14
l fix the
> > issue.
>
> I believe I'm seeing the same issue with next-20190902 in a Linux VM
> running on Hyper-V (next-20190830 is good).
>
> git-bisect points to the same commit in linux-next:
> e013ec23b823 ("fs/namei.c: keep track of nd->root refcount sta
On Mon 02 Sep 06:24 PDT 2019, Lee Jones wrote:
> From: Bjorn Andersson
>
> The Lenovo Yoga C630 is built on the SDM850 from Qualcomm, but this seem
> to be similar enough to the SDM845 that we can reuse the sdm845.dtsi.
>
> Supported by this patch is: keyboard, battery monitoring, UFS storage,
Hi Dan,
On Mon, 2 Sep 2019 22:31:00 -0700 Dan Williams wrote:
>
> On Mon, Sep 2, 2019 at 4:45 PM Stephen Rothwell wrote:
> >
> > Hi Jason,
> >
> > On Mon, 2 Sep 2019 10:51:41 + Jason Gunthorpe
> > wrote:
> > >
> > > On Mon, Sep 02, 2019 at 08:50:17PM +1000, Stephen Rothwell wrote:
> >
Hi,
On 02.09.19 23:16, Andy Shevchenko wrote:
On Mon, Sep 2, 2019 at 11:58 PM Rafael J. Wysocki wrote:
On Thu, Jul 11, 2019 at 12:35 PM Chuanhua Han wrote:
Enable NXP i2c controller to boot with ACPI
Signed-off-by: Meenakshi Aggarwal
Signed-off-by: Udit Kumar
Signed-off-by: Chuanhua
Hi all,
Today's linux-next merge of the devicetree tree got a conflict in:
Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
between commit:
5833f5a5daf3 ("dt-bindings: gpu: mali: Add Samsung exynos5250 compatible")
from the samsung-krzk tree and commit:
553cedf60056
The RTL8723BU suffers the wifi disconnection problem while bluetooth
device connected. While wifi is doing tx/rx, the bluetooth will scan
without results. This is due to the wifi and bluetooth share the same
single antenna for RF communication and they need to have a mechanism
to collaborate.
BT
On Fri, Aug 30, 2019 at 07:46:44PM +0100, Colin King wrote:
> From: Colin Ian King
>
> Currently there are error return paths in ffsReadFile that
> exit via lable err_out that return and uninitialized error
> return in variable ret. Fix this by initializing ret to zero.
>
> Addresses-Coverity:
On Mon, Sep 2, 2019 at 4:45 PM Stephen Rothwell wrote:
>
> Hi Jason,
>
> On Mon, 2 Sep 2019 10:51:41 + Jason Gunthorpe wrote:
> >
> > On Mon, Sep 02, 2019 at 08:50:17PM +1000, Stephen Rothwell wrote:
> > > Hi all,
> >
> > > ERROR: "nd_region_provider_data" [drivers/acpi/nfit/nfit.ko]
Introduce new polling mode for short size transfer. Either the estimated
transfer time is estimated to exceed 200us, or polling loop actually exceeds
200us, it switches to irq mode.
Signed-off-by: Keiji Hayashibara
---
drivers/spi/spi-uniphier.c | 81
When it changes the spi mode, the register is overwritten incorrectly.
This commit fixes this register overwrite.
Signed-off-by: Keiji Hayashibara
---
drivers/spi/spi-uniphier.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
index
This commit removed if() because priv->is_save_param is always true.
Signed-off-by: Keiji Hayashibara
---
drivers/spi/spi-uniphier.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/spi/spi-uniphier.c b/drivers/spi/spi-uniphier.c
index e6ebbb1..d40ad93 100644
---
This series introduces new polling mode and fixes bug.
- Introduce new polling mode for short size transfer. Either the estimated
transfer time is estimated to exceed 200us, or polling loop actually exceeds
200us, it switches to irq mode.
- Fix a bug of register overwrite.
- Minor
Takashi Iwai 於 2019年9月2日 週一 下午7:41寫道：
>
> On Mon, 02 Sep 2019 12:00:56 +0200,
> Jian-Hong Pan wrote:
> >
> > Original pin node values of ASUS UX431FL with ALC294:
> >
> > 0x12 0xb7a60140
> > 0x13 0x4000
> > 0x14 0x90170110
> > 0x15 0x41f0
> > 0x16 0x41f0
> > 0x17 0x90170111
> > 0x18
Hi all,
On Mon, 2 Sep 2019 14:26:40 + "Lendacky, Thomas"
wrote:
>
> On 9/2/19 9:03 AM, Joerg Roedel wrote:
> >
> > tl;dr: And IOMMU commit introduces a new user for sme_active() in
> > generic code, and commit
> >
> > 284e21fab2cf x86, s390/mm: Move sme_active() and
From: Alastair D'Silva
Similar to commit 22e9c88d486a
("powerpc/64: reuse PPC32 static inline flush_dcache_range()")
this patch converts the following ASM symbols to C:
flush_icache_range()
__flush_dcache_icache()
__flush_dcache_icache_phys()
This was done as we discovered a
From: Alastair D'Silva
This operation takes a significant amount of time when hotplugging
large amounts of memory (~50 seconds with 890GB of persistent memory).
This was orignally in commit fb5924fddf9e
("powerpc/mm: Flush cache on memory hot(un)plug") to support memtrace,
but the flush on add
From: Alastair D'Silva
The 'extern' keyword does not value-add for function prototypes.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/cache.h | 8
arch/powerpc/include/asm/cacheflush.h | 6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git
From: Alastair D'Silva
When presented with large amounts of memory being hotplugged
(in my test case, ~890GB), the call to flush_dcache_range takes
a while (~50 seconds), triggering RCU stalls.
This patch breaks up the call into 1GB chunks, calling
cond_resched() inbetween to allow the
From: Alastair D'Silva
This patch adds helpers to retrieve icache sizes, and renames the existing
helpers to make it clear that they are for dcache.
Signed-off-by: Alastair D'Silva
---
arch/powerpc/include/asm/cache.h | 29 +++
From: Alastair D'Silva
This series addresses a few issues discovered in how we flush caches:
1. Flushes were truncated at 4GB, so larger flushes were incorrect.
2. Flushing the dcache in arch_add_memory was unnecessary
This series also converts much of the cache assembler to C, with the
aim of
From: Alastair D'Silva
When calling flush_icache_range with a size >4GB, we were masking
off the upper 32 bits, so we would incorrectly flush a range smaller
than intended.
This patch replaces the 32 bit shifts with 64 bit ones, so that
the full size is accounted for.
Signed-off-by: Alastair
he same issue with next-20190902 in a Linux VM
running on Hyper-V (next-20190830 is good).
git-bisect points to the same commit in linux-next:
e013ec23b823 ("fs/namei.c: keep track of nd->root refcount status")
I can reproduce the issue every time I reboot the system.
Thanks,
Dexuan
On 09/02/2019 11:53 PM, Michael Ellerman wrote:
Segher Boessenkool writes:
On Mon, Sep 02, 2019 at 12:03:12PM +1000, Michael Ellerman wrote:
Michal Suchanek writes:
On bigendian ppc64 it is common to have 32bit legacy binaries but much
less so on littleendian.
I think the toolchain
With the underscore character in the lsm9ds1_imu device name, we get the
following error below, so use a dash, just like the other device names do too.
[3.961399] Unable to handle kernel NULL pointer dereference at virtual
address 0018
[4.010581] Mem abort info:
[
On (09/02/19 11:18), James Byrne wrote:
> Commit 5aa068ea4082 ("printk: remove games with previous record flags")
> abolished the practice of setting the log flag to 'c' for the first
> continuation line and '+' for subsequent lines. Now all continuation
> lines are flagged with 'c' and '+' is
On 02-09-2019 16:15, Jon Hunter wrote:
>
> On 28/08/2019 12:18, Nagarjuna Kristam wrote:
>> Tegra fuse clock handle is retrieved in tegra_fuse_probe().
>> tegra_fuse_readl() is exported symbol, which can be called from drivers
>> at any time. tegra_fuse_readl() enables fuse clock and reads
Use rcu_dereference instead of task_rcu_dereference.
Remove task_rcu_dereference.
Remove the complications of rcuwait that were in place because tasks
on the runqueue were not rcu protected. It is now safe to call
wake_up_process if the target was know to be on the runqueue in the
current rcu
In the ordinary case today the rcu grace period of a task comes when a
task is reaped, well after the task has left the runqueue. This
change guarantees that the rcu grace period always happens after a
task has left the runqueue. As this is something that usaually happens
today I do not expect
Add a count of the number of rcu users (currently 1) of the task
struct so that we can later add the scheduler case and get rid of the
very subtle task_rcu_dereference, and just use rcu_dereference.
As suggested by Oleg have the count overlap rcu_head so that no
additional space in task_struct
I have split this work into 3 simple patches, so the code is straight
forward to review and so that if any mistakes slip in it is easy to
bisect them. In the process of review what it takes to remove
task_rcu_dereference I found yet another user of tasks on the
runqueue in rcu context; the
On Mon, Sep 02, 2019 at 11:57:23AM +0200, Stefano Garzarella wrote:
> >
> > Assuming we miss nothing and buffers < 4K are broken,
> > I think we need to add this to the spec, possibly with
> > a feature bit to relax the requirement that all buffers
> > are at least 4k in size.
> >
>
> Okay,
On Wed, Jul 17, 2019 at 01:30:27PM +0200, Stefano Garzarella wrote:
> In order to reduce the number of credit update messages,
> we send them only when the space available seen by the
> transmitter is less than VIRTIO_VSOCK_MAX_PKT_BUF_SIZE.
>
> Signed-off-by: Stefano Garzarella
> ---
>
Hi all,
After merging the regulator tree, today's linux-next build (powerpc
ppc64_defconfig) failed like this:
ld: drivers/ata/ahci.o:(.opd+0x150): multiple definition of
`regulator_bulk_set_supply_names'; drivers/phy/phy-core.o:(.opd+0x3f0): first
defined here
ld: drivers/ata/ahci.o: in
4.169095][T1] Read of size 4 at addr by task systemd/1
[ 104.176227][T1]
[ 104.178416][T1] CPU: 166 PID: 1 Comm: systemd Not tainted
5.3.0-rc6-next-20190902 #2
[ 104.186504][T1] Hardware name: HPE Apollo 70 /C01_APACHE_MB
, BIOS L50_5.13_1.11 06
From: Kenneth Lee
Uacce (Unified/User-space-access-intended Accelerator Framework) is
a kernel module targets to provide Shared Virtual Addressing (SVA)
between the accelerator and process.
This patch add document to explain how it works.
Signed-off-by: Kenneth Lee
Signed-off-by: Zaibo Xu
From: Kenneth Lee
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
provide Shared Virtual Addressing (SVA) between accelerators and processes.
So accelerator can access any data structure of the main cpu.
This differs from the data sharing between cpu and io device,
Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
provide Shared Virtual Addressing (SVA) between accelerators and processes.
So accelerator can access any data structure of the main cpu.
This differs from the data sharing between cpu and io device, which share
data
> -Original Message-
> From: Cornelia Huck
> Sent: Monday, September 2, 2019 8:07 PM
> To: Parav Pandit
> Cc: alex.william...@redhat.com; Jiri Pirko ;
> kwankh...@nvidia.com; da...@davemloft.net; k...@vger.kernel.org;
> linux-kernel@vger.kernel.org; net...@vger.kernel.org
> Subject:
> -Original Message-
> From: Cornelia Huck
> Sent: Monday, September 2, 2019 8:16 PM
> To: Parav Pandit
> Cc: alex.william...@redhat.com; Jiri Pirko ;
> kwankh...@nvidia.com; da...@davemloft.net; k...@vger.kernel.org;
> linux-kernel@vger.kernel.org; net...@vger.kernel.org
> Subject:
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月3日 0:26
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
Add the TMU (Thermal Monitoring Unit) device node to enable
TMU feature.
Signed-off-by: Yuantian Tang
---
.../arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 108 +++---
1 file changed, 92 insertions(+), 16 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
Changes in v2:
- Prepare arm_smu_flush_ops for override.
- Remove NVIDIA_SMMUv2 and use ARM_SMMUv2 model as T194 SMMU hasn't modified
ARM MMU-500.
- Add T194 specific compatible string - "nvidia,tegra194-smmu"
- Remove tlb_sync hook added in v1 and Override arm_smmu_flush_ops->tlb_sync()
from
Add binding for NVIDIA's Tegra194 Soc SMMU that is based
on ARM MMU-500.
Signed-off-by: Krishna Reddy
---
Documentation/devicetree/bindings/iommu/arm,smmu.txt | 4
1 file changed, 4 insertions(+)
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt
Hi Colin
>Hi Colin
>
>>
>>From: Colin Ian King
>>
>>Currently the check on a non-zero return code in ret is false because
>>ret has been initialized to zero. I believe that ret should be assigned
>>to the return from the call to readl_poll_timeout_atomic before the
>>check on ret. Since ret is
On Wed, Aug 28, 2019 at 04:07:19PM +0200, Thomas Gleixner wrote:
> On Wed, 28 Aug 2019, Ming Lei wrote:
> > On Wed, Aug 28, 2019 at 01:23:06PM +0200, Thomas Gleixner wrote:
> > > On Wed, 28 Aug 2019, Ming Lei wrote:
> > > > On Wed, Aug 28, 2019 at 01:09:44AM +0200, Thomas Gleixner wrote:
> > > > >
On Mon 02 Sep 06:07 PDT 2019, Lee Jones wrote:
> Tested on the Lenovo Yoga C630 where this patch enables USB.
> Without it USB devices are not enumerated.
>
> Signed-off-by: Lee Jones
Reviewed-by: Bjorn Andersson
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
On Mon 02 Sep 06:07 PDT 2019, Lee Jones wrote:
> Tested on the Lenovo Yoga C630 where this patch enables the
> framebuffer (screen/monitor). Without it the device appears
> not to boot.
>
> Signed-off-by: Lee Jones
Reviewed-by: Bjorn Andersson
> ---
> arch/arm64/configs/defconfig | 1 +
>
On Mon 02 Sep 06:07 PDT 2019, Lee Jones wrote:
> Tested on the Lenovo Yoga C630 where this patch enables the
> keyboard, touchpad and touchscreen.
>
> Signed-off-by: Lee Jones
Reviewed-by: Bjorn Andersson
> ---
> arch/arm64/configs/defconfig | 1 +
> 1 file changed, 1 insertion(+)
>
> diff
Heiner Kallweit [mailto:hkallwe...@gmail.com]
> Sent: Tuesday, September 03, 2019 2:37 AM
[...]
> Seeing all this code it might be a good idea to switch this driver
> to phylib, similar to what I did with r8169 some time ago.
It is too complex to be completed for me at the moment.
If this patch
Hi, Fabio
> On Mon, Sep 2, 2019 at 11:05 PM Anson Huang
> wrote:
>
> > + ret = input_register_device(input);
> > + if (ret < 0) {
> > + dev_err(>dev, "failed to register input device\n");
> > + return ret;
> > + }
> > +
> > + pdata->input =
On Tue, 2019-06-25 at 20:52 -0700, Stephen Boyd wrote:
> Quoting Weiyi Lu (2019-06-25 18:05:22)
> > On Tue, 2019-06-25 at 15:14 -0700, Stephen Boyd wrote:
> > > Quoting Weiyi Lu (2019-06-09 20:44:53)
> > > > When using property assigned-clock-parents to assign parent clocks,
> > > > core clocks
Thank you Peter for pointing out my miss, I appreciate that sincerely.
> * MSR_CORE_C3_RESIDENCY: CORE C3 Residency Counter
> * perf code: 0x01
> * Available model: NHM,WSM,SNB,IVB,HSW,BDW,SKL,GLM,
> -
On 2019/9/3 上午9:56, Tiwei Bie wrote:
On Mon, Sep 02, 2019 at 12:15:05PM +0800, Jason Wang wrote:
On 2019/8/28 下午1:37, Tiwei Bie wrote:
Details about this can be found here:
https://lwn.net/Articles/750770/
What's new in this version
==
There are three choices based
Kalle Valo 於 2019年9月2日 週一 下午8:18寫道：
>
> Tony Chuang writes:
>
> >> From: Jian-Hong Pan
> >> Subject: [PATCH v4] rtw88: pci: Move a mass of jobs in hw IRQ to soft IRQ
> >>
> >> There is a mass of jobs between spin lock and unlock in the hardware
> >> IRQ which will occupy much time originally. To
Dear Greg,
Gently ping.
Best Regards,
Chanwoo Choi
On 19. 8. 26. 오전 11:55, Chanwoo Choi wrote:
> Dear Greg,
>
> This is extcon-next pull request for v5.4. I add detailed description of
> this pull request on below. Please pull extcon with following updates.
>
>
> Detailed description for
Add some features as follow:
- Set quartz oscillator load capacitance by DT
(generate more accuracy frequency)
- Set quartz oscillator drive control by DT
(reduce/increase the current consumption)
- Set low jitter mode by DT
(improve jitter performance)
- Set
Add some properties for pcf85263/pcf85363 as follows:
- interrupt-output-pin: string type
- quartz-load-femtofarads: integer type
- nxp,quartz-drive-strength: integer type
- nxp,quartz-low-jitter: bool type
- wakeup-source: bool type
Signed-off-by: Martin Fuzzey
Signed-off-by: Biwen Li
On 03-09-19, 08:08, Viresh Kumar wrote:
> On 02-09-19, 12:55, H. Nikolaus Schaller wrote:
> > + opp1-12500 {
> > + opp-hz = /bits/ 64 <12500>;
> > + // we currently only select the max voltage from table
> > Table 3-3 of the omap3530 Data
Hi Anson,
On Mon, Sep 2, 2019 at 11:05 PM Anson Huang wrote:
> + ret = input_register_device(input);
> + if (ret < 0) {
> + dev_err(>dev, "failed to register input device\n");
> + return ret;
> + }
> +
> + pdata->input = input;
> +
On 02-09-19, 12:55, H. Nikolaus Schaller wrote:
> + opp1-12500 {
> + opp-hz = /bits/ 64 <12500>;
> + // we currently only select the max voltage from table
> Table 3-3 of the omap3530 Data sheet (SPRS507F)
> + //
On 02-09-19, 12:55, H. Nikolaus Schaller wrote:
> With opp-v2 in omap36xx.dtsi and ti-cpufreq driver the
> 1GHz capability is automatically detected.
>
> Signed-off-by: H. Nikolaus Schaller
> ---
> arch/arm/boot/dts/omap3-n950-n9.dtsi | 7 ---
> 1 file changed, 7 deletions(-)
>
> diff
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 23:07
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
Hi Dmitry,
Thanks for your explanation.
If I want to abandon this patch, what's step I need to do?
Many thanks,
Johnny
-Original Message-
From: 'Dmitry Torokhov' [mailto:dmitry.torok...@gmail.com]
Sent: Friday, August 30, 2019 2:30 AM
To: Johnny.Chuang
Cc: linux-kernel@vger.kernel.org;
Hi Jean,
Thanks a lot for your comments. And, yes, it is dangerous that clear all
interrupt bit here based my local test. And about the interrupt flood, I will
show you in attached file. And I agree with you that add SMBALERT interrupt
handler if possible, but I have no idea about what action
>
> Caution: EXT Email
>
> On Fri, Aug 30, 2019 at 05:17:19PM +0800, Biwen Li wrote:
> > Add some properties for pcf85263/pcf85363 as follows:
> > - interrupt-output-pin: string type
> > - quartz-load-capacitance: integer type
> > - quartz-drive-strength: integer type
> > -
Hi Tejun,
Sorry for the late reply.
On Fri, Aug 30, 2019 at 09:58:15PM -0700, Tejun Heo wrote:
> Hello,
>
> On Sat, Aug 31, 2019 at 12:03:26PM +0900, Namhyung Kim wrote:
> > Hmm.. it looks hard to use fhandle as the identifier since perf
> > sampling is done in NMI context. AFAICS the
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 21:38
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 21:37
> To: Xiaowei Bao
> Cc: Kishon Vijay Abraham I ; bhelg...@google.com;
> robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo Li
> ; lorenzo.pieral...@arm.co
> ; a...@arndb.de; gre...@linuxfoundation.org;
>
Hi, Rob
> On Fri, Aug 30, 2019 at 04:53:45PM -0400, Anson Huang wrote:
> > NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as system
> > controller, the system controller is in charge of system power, clock
> > and power key event etc. management, Linux kernel has to communicate
> >
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and power key etc..
Adds i.MX system controller power key driver support, Linux kernel
has to communicate with system controller via MU (message unit) IPC
to get
Select CONFIG_KEYBOARD_IMX_SC_PWRKEY as module by default to
support i.MX8QXP power key driver.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index
Add scu power key node for i.MX8QXP, disabled by default as it
depends on board design.
Signed-off-by: Anson Huang
---
Changes since V1:
- remove "wakeup-source" property, as it is NOT needed for scu mu
interrupt;
---
arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 7 +++
1 file
Enable scu power key for i.MX8QXP MEK board.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index
NXP i.MX8QXP is an ARMv8 SoC with a Cortex-M4 core inside as
system controller, the system controller is in charge of system
power, clock and power key event etc. management, Linux kernel
has to communicate with system controller via MU (message unit)
IPC to get power key event, add binding doc
This patch prints the stddev and hist for the cycles diff of
program block. It can help us to understand if the cycles
is noisy or not.
This patch is inspired by Andi Kleen's patch
https://lwn.net/Articles/600471/
We create new option '--cycles-hist'.
Example:
perf record -b ./div
perf record
Hi Rob,
Thank you for the review and Acked-by.
On 2/9/2019 9:39 PM, Rob Herring wrote:
On Tue, 27 Aug 2019 11:58:25 +0800, "Ramuthevar,Vadivel MuruganX"
wrote:
From: Ramuthevar Vadivel Murugan
Add new vendor specific compatible string to check Intel's Lightning
Mountain(LGM) QSPI
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 21:06
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
On Mon, Sep 02, 2019 at 12:15:05PM +0800, Jason Wang wrote:
> On 2019/8/28 下午1:37, Tiwei Bie wrote:
> > Details about this can be found here:
> >
> > https://lwn.net/Articles/750770/
> >
> > What's new in this version
> > ==
> >
> > There are three choices based on the
Hi Rob,
Thank you for review comments.
On 2/9/2019 9:38 PM, Rob Herring wrote:
On Wed, Aug 28, 2019 at 08:43:14PM +0800, Ramuthevar,Vadivel MuruganX wrote:
From: Ramuthevar Vadivel Murugan
Add a YAML schema to use the host controller driver with the
SDXC PHY on Intel's Lightning Mountain
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 20:55
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 20:46
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
On Mon, 2019-09-02 at 12:53 +0200, Dietmar Eggemann wrote:
> On 22/08/2019 04:17, Rik van Riel wrote:
> > My main TODO items for the next period of time are likely going to
> > be testing, testing, and testing. I hope to find and flush out any
> > corner case I can find, and make sure performance
> -Original Message-
> From: Andrew Murray
> Sent: 2019年9月2日 20:32
> To: Xiaowei Bao
> Cc: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org; Leo
> Li ; kis...@ti.com; lorenzo.pieral...@arm.com; M.h.
> Lian ; Mingkai Hu ; Roy
> Zang ; jingooh...@gmail.com;
>
Hi Sebastian,
On Tue, 3 Sep 2019 at 05:04, Sebastian Reichel wrote:
>
> Hi,
>
> On Wed, Jul 31, 2019 at 06:00:22PM +0800, Baolin Wang wrote:
> > This patch set adds new attributes for userspace, and fixes the the
> > accuracy issue of coulomb counter calculation, as well as optimizing
> > the
Hi, Pavel
> On Mon 2019-09-02 16:45:38, Anson Huang wrote:
> > i.MX8MN DDR4 EVK board has a GPIO LED to indicate status, add support
> > for it.
>
> LED maintainers want to be on the cc list...
The get_maintainer.pl does NOT show the LED maintainers...But I have added it
in V2.
>
> > @@ -15,6
i.MX8MN DDR4 EVK board has a GPIO LED to indicate status,
add support for it.
Signed-off-by: Anson Huang
---
Changes since V1:
- Mention color in the label.
---
arch/arm64/boot/dts/freescale/imx8mn-ddr4-evk.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git
Hi,
Some people are asking whether the display refresh irq could be provided by
qemu vfio display?
Some background: currently, we have two display timers. One is provided by QEMU
UI and the other one is provided by the vgpu. The vgpu display framebuffer
consumers (i.e. QEMU UIs) depend on the
On Tue, 3 Sep 2019 at 04:08, Gustavo A. R. Silva wrote:
>
> Add suffix LL to constant 1000 in order to avoid a potential integer
> overflow and give the compiler complete information about the proper
> arithmetic to use. Notice that this constant is being used in a context
> that expects an
Hi Yizhuo,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3-rc7 next-20190902]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci/linux/commits
>>> +ARM_SMMU_MATCH_DATA(nvidia_smmuv2, ARM_SMMU_V2, NVIDIA_SMMUV2);
>> The ARM MMU-500 implementation is unmodified. It is the way the are
>> integrated and used together(for interleaved accesses) is different from
>> regular ARM MMU-500.
>> I have added it to get the model number and to be
Add suffix LL to constant 1000 in order to avoid a potential integer
overflow and give the compiler complete information about the proper
arithmetic to use. Notice that this constant is being used in a context
that expects an expression of type s64, but it's currently evaluated
using 32-bit
On Mon, 2 Sep 2019 23:28:50 +0200
"Rafael J. Wysocki" wrote:
> On Tue, Aug 6, 2019 at 6:24 AM Daniel Black wrote:
> >
> > ACPI-6.3 corresponds to when hmat revision was bumped from
> > 1 to 2. In this version ACPI_HMAT_MEMORY_PD_VALID was
> > deprecated and made reserved.
> >
> > As such in
On Mon, Sep 02, 2019 at 11:36:51AM +0200, Borislav Petkov wrote:
> On Mon, Sep 02, 2019 at 09:13:42AM +0800, Philip Li wrote:
> > Thanks Boris, it is applied, and will take effect soon.
>
> Seems to has taken effect. I got the first build report.
thanks for the info, Boris, glad to know this.
>
> -Original Message-
> From: Dexuan Cui
> Sent: Monday, August 19, 2019 7:57 PM
> To: ji...@kernel.org; benjamin.tissoi...@redhat.com;
> linux-in...@vger.kernel.org; linux-hyp...@vger.kernel.org; Stephen
> Hemminger ; Sasha Levin
> ; sas...@kernel.org; Haiyang Zhang
> ; KY Srinivasan ;
On Thu, Aug 29, 2019 at 4:28 AM syzbot
wrote:
>
> Hello,
>
> syzbot found the following crash on:
>
> HEAD commit:47ee6e86 selftests/bpf: remove wrong nhoff in flow dissect..
> git tree: bpf-next
> console output: https://syzkaller.appspot.com/x/log.txt?x=16227fa660
> kernel config:
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