On Wed, 20 May 2020 00:41:50 +0200, Lubomir Rintel wrote:
> This describes the bindings for a controller that generates master and bit
> clocks for the I2S interface.
>
> Signed-off-by: Lubomir Rintel
>
> ---
> Changes since v1:
> - Fix commit message wording
> - Define MMP2_CLK_AUDIO_NR_CLKS
>
On Tue, 2020-05-26 at 15:19 -0700, Alex Guzman wrote:
[...]
> When using your patch, I get a hang when trying to use tpm2_getcap,
> and dmesg shows some info.
Are you sure it's all applied? This
> [ 570.913803] tpm_tcg_write_bytes+0x2f/0x40
> [ 570.913805] release_locality+0x49/0x220
> [
On Wed, May 20, 2020 at 12:41:47AM +0200, Lubomir Rintel wrote:
> This is a binding for the MMP2 power management units. As such apart from
> providing the clocks, they also manage the power islands.
>
> Signed-off-by: Lubomir Rintel
>
> ---
> Changes since v2:
> - Added this patch
>
>
Quoting Tiezhu Yang (2020-05-24 20:31:55)
> The return value about hisi_reset_init() is not correct, fix it.
>
> Signed-off-by: Tiezhu Yang
> ---
> drivers/clk/hisilicon/clk-hi3519.c | 4 ++--
> drivers/clk/hisilicon/crg-hi3516cv300.c | 4 ++--
> drivers/clk/hisilicon/crg-hi3798cv200.c | 4
On Tue, 26 May 2020 13:19:36 -0700, Andrii Nakryiko wrote:
> On Tue, May 26, 2020 at 7:02 AM Akira Yokosawa wrote:
>>
>> On Tue, 26 May 2020 19:50:47 +0900, Akira Yokosawa wrote:
>>> On Mon, 25 May 2020 16:31:05 -0700, Andrii Nakryiko wrote:
On Mon, May 25, 2020 at 3:01 PM Akira Yokosawa
Baikal-T1 Boot Controller provides an access to a RO storages, which are
physically mapped into the MMIO space. In particularly there are the
Internal ROM embedded into the SoC with a pre-installed firmware,
externally attached SPI flash (also accessed in the read-only mode) and a
memory region,
On 2020-05-26 14:00, Souptick Joarder wrote:
This code was using get_user_pages(), in a "Case 2" scenario
(DMA/RDMA), using the categorization from [1]. That means that it's
time to convert the get_user_pages() + release_pages() calls to
pin_user_pages() + unpin_user_pages() calls.
There is
From: Colin Ian King
The pointer br_dev is being initialized with a value that is never read
and is being updated with a new value later on. The initialization
is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
randconfig-a001-20200526
i386 randconfig-a004-20200526
i386 randconfig-a003-20200526
i386 randconfig-a006-20200526
i386 randconfig-a002-20200526
i386 randconfig-a005-20200526
x86_64 randconfig-a015-20200526
Hi Zhu,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on vhost/linux-next]
[also build test WARNING on v5.7-rc7 next-20200526]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base
On 5/26/20 4:27 PM, Joe Perches wrote:
On Tue, 2020-05-26 at 11:04 -0600, Shuah Khan wrote:
On 5/22/20 8:26 PM, Joe Perches wrote:
On Fri, 2020-05-22 at 20:19 -0600, Shuah Khan wrote:
get_maintainer.pl picks only the first email address found in the file.
Reorder my email addresses so it
On Fri, 22 May 2020 09:06:23 +0530, Kishon Vijay Abraham I wrote:
> "mem" is not a memory resource and it overlaps with PCIe config space
> and memory region. Removve "mem" from reg binding.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> .../devicetree/bindings/pci/cdns,cdns-pcie-host.yaml
These patches were picked from the following series:
https://lore.kernel.org/netdev/1567779344-30965-1-git-send-email-claudiu.man...@nxp.com/
They have never been resent. I've picked them up, addressed Andrews
comments, fixed some more bugs and asked Claudiu if I can keep their
SOB
tags; he
Modern device tree bindings are supposed to be created as YAML-files
in accordance with dt-schema. This commit replaces the Synopsis
Designware DMA controller legacy bare text bindings with YAML file.
The only required prorties are "compatible", "reg", "#dma-cells" and
"interrupts", which will be
Some devices may lack the support of the hardware accelerated SG list
entries automatic walking through and execution. In this case a burden of
the SG list traversal and DMA engine re-initialization lies on the
DMA engine driver (normally implemented by using a DMA transfer completion
IRQ to
Some hardware aside from default 0/1 may have greater minimum burst
transactions length constraints. Here we introduce the DMA device
and slave capability, which if required can be initialized by the DMA
engine driver with the device-specific value.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Full multi-block transfers functionality is enabled in DW DMA
controller only if CHx_MULTI_BLK_EN is set. But LLP-based transfers
can be executed only if hardcode channel x LLP register feature isn't
enabled, which can be switched on at the IP core synthesis for
optimization. If it's enabled then
Multi-block support provides a way to map the kernel-specific SG-table so
the DW DMA device would handle it as a whole instead of handling the
SG-list items or so called LLP block items one by one. So if true LLP
list isn't supported by the DW DMA engine, then soft-LLP mode will be
utilized to
Baikal-T1 SoC has an DW DMAC on-board to provide a Mem-to-Mem, low-speed
peripherals Dev-to-Mem and Mem-to-Dev functionality. Mostly it's compatible
with currently implemented in the kernel DW DMAC driver, but there are some
peculiarities which must be taken into account in order to have the
This array property is used to indicate the maximum burst transaction
length supported by each DMA channel.
Signed-off-by: Serge Semin
Cc: Alexey Malahov
Cc: Thomas Bogendoerfer
Cc: Arnd Bergmann
Cc: Andy Shevchenko
Cc: linux-m...@vger.kernel.org
---
Changelog v2:
- Rearrange SoBs.
- Move
From: Alex Marginean
Use DT information rather than in-band information from bootloader to
set up MAC for XGMII. For RGMII use the DT indication in addition to
RGMII defaults in hardware.
However, this implies that PHY connection information needs to be
extracted before netdevice creation, when
On Tue, May 26, 2020 at 06:03:35PM -0400, Don Porter wrote:
On 5/26/20 4:27 PM, Sasha Levin wrote:
I'm really worried about the disconnect between how you view the current
state of Graphene (and the industry) vs Intel and the various cloud
providers.
You keep suggesting that its just past the
There are DMA devices (like ours version of Synopsys DW DMAC) which have
DMA capabilities non-uniformly redistributed amongst the device channels.
In order to provide a way of exposing the channel-specific parameters to
the DMA engine consumers, we introduce a new DMA-device callback. In case
if
From: Claudiu Manoil
ENETC has ethernet MACs capable of SGMII and SXGMII but in order to use
these protocols some serdes configurations need to be performed. The
SerDes is configurable via an internal MDIO bus connected to an internal
PCS device, all reads/writes are performed at address 0.
Maximum block size DW DMAC configuration corresponds to the max segment
size DMA parameter in the DMA core subsystem notation. Lets set it with a
value specific to the probed DW DMA controller. It shall help the DMA
clients to create size-optimized SG-list items for the controller. This in
turn
Since some DW DMA controllers (like one installed on Baikal-T1 SoC) may
have non-uniform DMA capabilities per device channels, let's add
the DW DMA specific device_caps callback to expose that specifics up to
the DMA consumer. It's a dummy function for now. We'll fill it in with
capabilities
IP core of the DW DMA controller may be synthesized with different
max burst length of the transfers per each channel. According to Synopsis
having the fixed maximum burst transactions length may provide some
performance gain. At the same time setting up the source and destination
multi size
These patches were picked from the following series:
https://lore.kernel.org/netdev/1567779344-30965-1-git-send-email-claudiu.man...@nxp.com/
They have never been resent. I've picked them up, addressed Andrews
comments, fixed some more bugs and asked Claudiu if I can keep their SOB
tags; he
On Tue, May 26, 2020 at 05:20:17PM -0400, Joel Fernandes wrote:
> > The switch happens on the target with IRQs disabled and rdp->nocb_lock
> > held to avoid races between local callbacks handling and kthread
> > offloaded callbacks handling.
> > nocb_cb kthread is first parked to avoid any
From: Colin Ian King
The variable err is being initialized with a value that is never read
and it is being updated later with a new value. The initialization is
redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
block/blk-crypto-fallback.c |
On 5/26/20 3:29 PM, Zi Yan wrote:
On 8 May 2020, at 16:06, Ralph Campbell wrote:
On 5/8/20 12:51 PM, Christoph Hellwig wrote:
On Fri, May 08, 2020 at 12:20:07PM -0700, Ralph Campbell wrote:
hmm_range_fault() returns an array of page frame numbers and flags for
how the pages are mapped in
On Tue, 26 May 2020 14:58:07 + Luis Chamberlain wrote:
> To those new on CC -- this is intended to be a simple generic interface
> to the kernel to annotate when the firwmare has crashed leaving the
> driver or system in a questionable state, in the worst case requiring
> full system reboot.
From: Colin Ian King
The pointer clk is being initialized with a value that is never read
and is being updated with a new value later on. The initialization
is redundant and can be removed.
Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King
---
On Mon, May 25, 2020 at 12:45:35AM +0100, Al Viro wrote:
> On Wed, May 13, 2020 at 04:33:49AM +0100, Al Viro wrote:
>
> > FWIW, what I'm going to do is
> > * make all callers of copy_regset_to_user() pass 0 as pos
> > (there are very few exceptions - one on arm64, three on sparc32
> > and
On Mon, May 18, 2020 at 09:49:30AM +0900, Steve Lee wrote:
> Add documentation for DT binding of max98390 amplifier driver.
>
> Signed-off-by: Steve Lee
> ---
>
>
> Changed since V4:
> * No changes.
> Changed since V3:
> * No changes.
> Changed since V2:
> * No changes.
>
On Tue, 2020-05-26 at 14:33 -0700, Tadeusz Struk wrote:
> On 5/26/20 1:00 PM, James Bottomley wrote:
> > I don't think there is a root cause other than a TIS TPM is getting
> > annoyed by us cycling localities too rapidly because we don't do an
> > actual TPM operation between request and
From: Antoine Tenart
Date: Tue, 26 May 2020 18:22:52 +0200
> This series aims at reducing the waiting time between MDIO transactions
> when using the MSCC MIIM MDIO controller.
>
> I'm not sure we need patch 4/4 and we could reasonably drop it from the
> series. I'm including the patch as it
Hi,
On Fri, May 22, 2020 at 4:34 AM Srinivas Kandagatla
wrote:
>
> qfprom has different address spaces for read and write. Reads are
> always done from corrected address space, where as writes are done
> on raw address space.
> Writing to corrected address space is invalid and ignored, so it
>
Device hot removals and additions (closure and opening) also present a
valid opportunity for (re-)balancing the channel interrupts across the
available CPUs. Current code balances interrupts as they are offered,
but it does not modify the interrupts-to-CPUs assignment if interrupts
are
The RFC introduces constructs to re-balance the channel interrupts at
CPU hotplug and at device hotplug operations, the latter being indeed
"closure/opening operations" to enable the re-balancing also in cases
when the device is just being closed/re-opened (as in "ethtool -L").
These changes
On Tue, 12 May 2020 22:56:37 -0700, Bjorn Andersson wrote:
> Add a devicetree binding for the Qualcomm peripheral image loader
> relocation information region found in the IMEM.
>
> Reviewed-by: Stephen Boyd
> Signed-off-by: Bjorn Andersson
> ---
>
> Changes since v4:
> - Fixed reg in example
CPU hot removals and additions present an opportunity for (re-)balancing
the channel interrupts across the available CPUs. Current code does not
balance the interrupts at CPU hotplug; furthermore/consequently, the hot
removal path currently fails (to remove the specified CPU) whenever some
Hi,
On Fri, May 22, 2020 at 4:18 AM Srinivas Kandagatla
wrote:
>
> On 21/05/2020 22:28, Doug Anderson wrote:
> > Hi,
> >
> > On Thu, May 21, 2020 at 8:56 AM Srinivas Kandagatla
> > wrote:
> >>
> >> On 21/05/2020 16:10, Doug Anderson wrote:
> On 20/05/2020 23:48, Doug Anderson wrote:
>
On Wed, 13 May 2020 08:11:24 +0800, Anson Huang wrote:
> Convert the i.MX6UL clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> Acked-by: Stephen Boyd
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
>
On Tue, 26 May 2020 13:03:10 +0200 Emanuele Giuseppe Esposito wrote:
> There is currently no common way for Linux kernel subsystems to expose
> statistics to userspace shared throughout the Linux kernel; subsystems have
> to take care of gathering and displaying statistics by themselves, for
>
On Wed, 13 May 2020 08:11:23 +0800, Anson Huang wrote:
> Convert the i.MX6SLL clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> Acked-by: Stephen Boyd
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
>
On Wed, 13 May 2020 08:11:21 +0800, Anson Huang wrote:
> Convert the i.MX6SX clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> Acked-by: Stephen Boyd
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
>
On Wed, 13 May 2020 08:11:20 +0800, Anson Huang wrote:
> Convert the i.MX6Q clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> Acked-by: Stephen Boyd
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
>
On Wed, 13 May 2020 08:11:22 +0800, Anson Huang wrote:
> Convert the i.MX6SL clock binding to DT schema format using json-schema.
>
> Signed-off-by: Anson Huang
> Acked-by: Stephen Boyd
> ---
> Changes since V4:
> - add descriptions for interrupts and each item of it.
> ---
>
On 8 May 2020, at 16:06, Ralph Campbell wrote:
> On 5/8/20 12:51 PM, Christoph Hellwig wrote:
>> On Fri, May 08, 2020 at 12:20:07PM -0700, Ralph Campbell wrote:
>>> hmm_range_fault() returns an array of page frame numbers and flags for
>>> how the pages are mapped in the requested process' page
On Mon, 25 May 2020 17:10:37 +0200, Jonathan Albrieux wrote:
> Add reset-gpio support.
>
> Without reset's deassertion during ak8975_power_on(), driver's probe fails
> on ak8975_who_i_am() while checking for device identity for AK09911 chip.
>
> AK09911 has an active low reset gpio to handle
On 5/26/20 12:34 PM, Vitor Massaru Iha wrote:
To make KUnit easier to use, and to avoid overwriting object and
.config files, the default KUnit build directory is set to .kunit
* Related bug: https://bugzilla.kernel.org/show_bug.cgi?id=205221
Fixed up minor merge conflicts - Shuah Khan
On Mon, May 25, 2020 at 05:10:36PM +0200, Jonathan Albrieux wrote:
> Converts documentation from txt format to yaml.
I would have converted to yaml and do any re-formatting/wording, then
added 'interrupts', but this is fine.
> Signed-off-by: Jonathan Albrieux
> ---
>
On Tue, May 26, 2020 at 05:27:56PM -0400, Joel Fernandes wrote:
> On Tue, May 26, 2020 at 02:09:47PM -0700, Paul E. McKenney wrote:
> [...]
> > > > > BTW, I'm really itching to give it a try to make the scheduler more
> > > > > deadlock
> > > > > resilient (that is, if the scheduler wake up path
On 5/26/20 5:27 PM, Peter Zijlstra wrote:
On Tue, May 26, 2020 at 04:30:58PM -0400, Waiman Long wrote:
On 5/26/20 3:56 PM, Peter Zijlstra wrote:
On Tue, May 26, 2020 at 02:58:50PM -0400, Qian Cai wrote:
I still don't understand why reading all sysfs files on this system
could increase that
On Tue, 2020-05-26 at 11:04 -0600, Shuah Khan wrote:
> On 5/22/20 8:26 PM, Joe Perches wrote:
> > On Fri, 2020-05-22 at 20:19 -0600, Shuah Khan wrote:
> > > get_maintainer.pl picks only the first email address found in the file.
> > > Reorder my email addresses so it finds my linuxfoundation.org
Wrong loop filter flag is unset when tiles enabled flag is not set,
this cause HEVC decoding issues with Rockchip Video Decoder.
Fix this by unsetting the loop filter across tiles enabled flag instead of
the pps loop filter across slices enabled flag when tiles are disabled.
Fixes: 256fa3920874
On Mon, 25 May 2020 17:10:35 +0200, Jonathan Albrieux wrote:
> Reword gpios documentation, add interrupt documentation and fix styles.
> Update example to use interrupts instead of gpios.
>
> Signed-off-by: Jonathan Albrieux
> ---
> .../bindings/iio/magnetometer/ak8975.txt | 19
On Tue, 26 May 2020 13:15:49 -0700, Andrii Nakryiko wrote:
> On Tue, May 26, 2020 at 3:50 AM Akira Yokosawa wrote:
>>
>> On Mon, 25 May 2020 16:31:05 -0700, Andrii Nakryiko wrote:
>>> On Mon, May 25, 2020 at 3:01 PM Akira Yokosawa wrote:
>> [...]
Yes, that should work.
>>>
>>> Ok,
On Tue, May 26, 2020 at 03:44:30PM +0200, Alexander Graf wrote:
>
>
> On 26.05.20 15:17, Greg KH wrote:
> >
> > On Tue, May 26, 2020 at 02:44:18PM +0200, Alexander Graf wrote:
> > >
> > >
> > > On 26.05.20 14:33, Greg KH wrote:
> > > >
> > > > On Tue, May 26, 2020 at 01:42:41PM +0200,
On Wed, May 13, 2020 at 02:59:02PM -0700, Douglas Anderson wrote:
> The ti-sn65dsi86 MIPI DSI to eDP bridge chip has a dedicated hardware
> HPD (Hot Plug Detect) pin on it, but it's mostly useless for eDP
> because of excessive debouncing in hardware. Specifically there is no
> way to disable the
Baikal-T1 Clocks Control Unit is responsible for transformation of a
signal coming from an external oscillator into clocks of various
frequencies to propagate them then to the corresponding clocks
consumers (either individual IP-blocks or clock domains). In order
to create a set of high-frequency
Baikal-T1 is supposed to be supplied with a high-frequency external
oscillator. But in order to create signals suitable for each IP-block
embedded into the SoC the oscillator output is primarily connected to
a set of CCU PLLs. There are five of them to create clocks for the MIPS
P5600 cores, an
Nearly each Baikal-T1 IP-core is supposed to have a clock source
of particular frequency. But since there are greater than five
IP-blocks embedded into the SoC, the CCU PLLs can't fulfill all the
needs. Baikal-T1 CCU provides a set of fixed and configurable clock
dividers in order to generate a
Stephen, Michael, the merge window is upon us, please review/merge in/whatever
this patchset.
Clocks Control Unit is the core of Baikal-T1 SoC responsible for the chip
subsystems clocking and resetting. The CCU is connected with an external
fixed rate oscillator, which signal is transformed into
After being gained by the CCU PLLs the signals must be transformed to
be suitable for the clock-consumers. This is done by a set of dividers
embedded into the CCU. A first block of dividers is used to create
reference clocks for AXI-bus of high-speed peripheral IP-cores of the
chip. The second
On Tue, May 26, 2020 at 08:01:36PM +0300, Paraschiv, Andra-Irina wrote:
>
>
> On 26/05/2020 09:44, Greg KH wrote:
> > On Tue, May 26, 2020 at 01:13:18AM +0300, Andra Paraschiv wrote:
> > > +struct enclave_get_slot_req {
> > > + /* Context ID (CID) for the enclave vsock device. */
> > > + u64
On Tue, May 26, 2020 at 04:05:58PM -0600, William Kucharski wrote:
> Thinking about this, if the intent is to make THP usable for any
> greater than PAGESIZE page size, this routine should probably go back
> to taking a size or perhaps order parameter so it could be called to
> align addresses
On Tue, May 26, 2020 at 09:35:33PM +0300, Paraschiv, Andra-Irina wrote:
>
>
> On 26/05/2020 09:48, Greg KH wrote:
> > On Tue, May 26, 2020 at 01:13:20AM +0300, Andra Paraschiv wrote:
> > > The Nitro Enclaves PCI device is used by the kernel driver as a means of
> > > communication with the
On Tue, 2020-05-26 at 12:38 -0700, James Bottomley wrote:
> On Tue, 2020-05-26 at 19:23 +, mario.limoncie...@dell.com wrote:
> > > On Tue, 2020-05-26 at 13:32 -0500, Mario Limonciello wrote:
> > > > This reverts commit d23d12484307b40eea549b8a858f5fffad913897.
> > > >
> > > > This commit has
All Intel platforms guarantee that all root complex implementations
must send transactions up to IOMMU for address translations. Hence for
RCiEP devices that are Vendor ID Intel, can claim exception for lack of
ACS support.
3.16 Root-Complex Peer to Peer Considerations
When DMA remapping is
The current codebase makes use of one-element arrays in the following
form:
struct something {
int length;
u8 data[1];
};
struct something *instance;
instance = kmalloc(sizeof(*instance) + size, GFP_KERNEL);
instance->length = size;
memcpy(instance->data, source, size);
but the
On Tue, May 26, 2020 at 09:16:38AM +0300, Mike Rapoport wrote:
> On Fri, May 22, 2020 at 03:52:14PM +0300, Kirill A. Shutemov wrote:
> > If the protected memory feature enabled, unmap guest memory from
> > kernel's direct mappings.
> >
> > Migration and KSM is disabled for protected memory as it
> On May 26, 2020, at 3:04 PM, Steven Rostedt wrote:
>
> On Tue, 26 May 2020 23:54:15 +0200
> Peter Zijlstra wrote:
>
>> On Tue, May 26, 2020 at 09:46:29PM +, Song Liu wrote:
>>>
>>>
On May 26, 2020, at 2:39 PM, Peter Zijlstra wrote:
On Tue, May 26, 2020 at 02:28:26PM
> On May 26, 2020, at 2:54 PM, Peter Zijlstra wrote:
>
> On Tue, May 26, 2020 at 09:46:29PM +, Song Liu wrote:
>>
>>
>>> On May 26, 2020, at 2:39 PM, Peter Zijlstra wrote:
>>>
>>> On Tue, May 26, 2020 at 02:28:26PM -0700, Song Liu wrote:
It is useful to trace functions in
When SYNC_STATE_ONLY support was added in commit 05ef983e0d65 ("driver
core: Add device link support for SYNC_STATE_ONLY flag"),
SYNC_STATE_ONLY links were treated similar to STATELESS links in terms
of not blocking consumer probe if the supplier hasn't probed yet.
That caused a SYNC_STATE_ONLY
On Wed, 13 May 2020 14:59:01 -0700, Douglas Anderson wrote:
> This moves the bindings over, based a lot on toshiba,tc358768.yaml.
> Unless there's someone known to be better, I've set the maintainer in
> the yaml as the first person to submit bindings.
>
> Signed-off-by: Douglas Anderson
>
Thinking about this, if the intent is to make THP usable for any
greater than PAGESIZE page size, this routine should probably go back
to taking a size or perhaps order parameter so it could be called to
align addresses accordingly rather than hard code PMD_SIZE.
> On May 15, 2020, at 7:16 AM,
On Tue, 26 May 2020 18:04:37 -0400
Steven Rostedt wrote:
>
> In the early days there was a lot of issues with recursions, but I added a
> lot of recursion protection since then. I'll give this patch a spin and see
> if I can make it crash.
I also have some patches that make both perf and the
On 5/26/2020 3:01 PM, Andrew Lunn wrote:
>>> +/* When high resolution timers aren't built-in: we can't use
>>> usleep_range() as
>>> + * we would sleep way too long. Use udelay() instead.
>>> + */
>>> +#define mscc_readl_poll_timeout(addr, val, cond, delay_us, timeout_us)
>>> \
>>> +({
On Tue, 26 May 2020 23:54:15 +0200
Peter Zijlstra wrote:
> On Tue, May 26, 2020 at 09:46:29PM +, Song Liu wrote:
> >
> >
> > > On May 26, 2020, at 2:39 PM, Peter Zijlstra wrote:
> > >
> > > On Tue, May 26, 2020 at 02:28:26PM -0700, Song Liu wrote:
> > >> It is useful to trace
On Thu, May 21, 2020 at 09:08:19PM +0530, Sandeep Maheswaram wrote:
> Add compatible for SC7180 in usb dwc3 bindings.
>
> Signed-off-by: Sandeep Maheswaram
> Reviewed-by: Douglas Anderson
> Acked-by: Rob Herring
> Reviewed-by: Stephen Boyd
> ---
>
On Mon, May 25, 2020 at 11:40:01PM -0700, John Hubbard wrote:
> On 2020-05-22 05:52, Kirill A. Shutemov wrote:
> ...
> > @@ -2773,6 +2780,7 @@ struct page *follow_page(struct vm_area_struct *vma,
> > unsigned long address,
> > #define FOLL_LONGTERM 0x1 /* mapping lifetime is indefinite:
On 5/26/20 4:27 PM, Sasha Levin wrote:
On Tue, May 26, 2020 at 08:42:09AM -0400, Don Porter wrote:
On 5/22/20 8:45 PM, Thomas Gleixner wrote:
let me clarify, that despite your intentions:
- there is not a single word in any paper, slide deck, documentation
etc. which mentions that
On Thu, 21 May 2020 21:08:18 +0530, Sandeep Maheswaram wrote:
> Convert USB DWC3 bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram
> ---
> .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -
> .../devicetree/bindings/usb/qcom,dwc3.yaml
On Tue, May 26, 2020 at 01:51:22PM -0600, Jens Axboe wrote:
> Checks if the file supports it, and initializes the values that we need.
> Caller passes in 'data' pointer, if any, and the callback function to
> be used.
>
> Signed-off-by: Jens Axboe
Acked-by: Johannes Weiner
On Tue, May 26, 2020 at 2:53 PM Michael Walle wrote:
>
> Am 2020-05-26 23:45, schrieb Saravana Kannan:
> > On Tue, May 26, 2020 at 2:13 PM Michael Walle wrote:
> >>
> >> Am 2020-05-26 21:43, schrieb Saravana Kannan:
> >> > When SYNC_STATE_ONLY support was added in commit 05ef983e0d65 ("driver
>
Hello Andy,
On Tue, May 26, 2020 at 4:54 PM Andy Shevchenko
wrote:
>
> On Tue, May 26, 2020 at 03:12:48PM -0400, Jim Quinlan wrote:
> > The new field in struct device 'dma_pfn_offset_map' is used to facilitate
> > the use of multiple pfn offsets between cpu addrs and dma addrs. It is
> >
On Tue, May 26, 2020 at 09:15:52AM +0300, Mike Rapoport wrote:
> On Fri, May 22, 2020 at 03:52:05PM +0300, Kirill A. Shutemov wrote:
> > The new VMA flag that indicate a VMA that is not accessible to userspace
> > but usable by kernel with GUP if FOLL_KVM is specified.
> >
> > The FOLL_KVM is
On 5/26/20 3:59 PM, Johannes Weiner wrote:
> On Tue, May 26, 2020 at 01:51:15PM -0600, Jens Axboe wrote:
>> Normally waiting for a page to become unlocked, or locking the page,
>> requires waiting for IO to complete. Add support for lock_page_async()
>> and wait_on_page_locked_async(), which are
> > +/* When high resolution timers aren't built-in: we can't use
> > usleep_range() as
> > + * we would sleep way too long. Use udelay() instead.
> > + */
> > +#define mscc_readl_poll_timeout(addr, val, cond, delay_us, timeout_us)
> > \
> > +({
On Tue, May 26, 2020 at 01:51:16PM -0600, Jens Axboe wrote:
> Use the async page locking infrastructure, if IOCB_WAITQ is set in the
> passed in iocb. The caller must expect an -EIOCBQUEUED return value,
> which means that IO is started but not done yet. This is similar to how
> O_DIRECT signals
On Thu, May 21, 2020 at 2:02 AM Kishon Vijay Abraham I wrote:
>
> Cadence PCIe core driver (host mode) uses "cdns,no-bar-match-nbits"
> property to configure the number of bits passed through from PCIe
> address to internal address in Inbound Address Translation register.
> This only used the NO
On Tue, May 26, 2020 at 01:51:15PM -0600, Jens Axboe wrote:
> Normally waiting for a page to become unlocked, or locking the page,
> requires waiting for IO to complete. Add support for lock_page_async()
> and wait_on_page_locked_async(), which are callback based instead. This
On Tue, May 26, 2020 at 09:16:09AM +0300, Mike Rapoport wrote:
> On Fri, May 22, 2020 at 03:52:08PM +0300, Kirill A. Shutemov wrote:
> > Wire up hypercalls for the feature and define VM_KVM_PROTECTED.
> >
> > Signed-off-by: Kirill A. Shutemov
> > ---
> > arch/x86/Kconfig | 1 +
> >
On Tue, May 26, 2020 at 10:04:57AM +0300, Andy Shevchenko wrote:
>On Mon, May 25, 2020 at 09:59:58PM +, Wei Yang wrote:
>> These two functions share the same logic.
>
>So, same comment. Please, add test first, make sure it works on current kernel,
>then after your patch applied, and send it as
Jarkko, Wolfram, the merge window is upon us, please review/merge in/whatever
the patchset.
Initially this has been a small patchset which embedded the Baikal-T1
System I2C support into the DW APB I2C driver as is by using a simplest
way. After a short discussion with Andy we decided to implement
> -Original Message-
> From: linux-hexagon-ow...@vger.kernel.org ow...@vger.kernel.org> On Behalf Of Nick Desaulniers
...
> On Tue, May 26, 2020 at 8:30 AM Guenter Roeck wrote:
> >
> > On Mon, May 11, 2020 at 09:41:37PM +0100, Will Deacon wrote:
> > > It is very rare to see versions of
dtc currently doesn't support I2C_OWN_SLAVE_ADDRESS flag set in the
i2c "reg" property. If it is the compiler will print a warning:
Warning (i2c_bus_reg): /example-2/i2c@112/eeprom@64: I2C bus unit address
format error, expected "4064"
Warning (i2c_bus_reg):
Modern device tree bindings are supposed to be created as YAML-files
in accordance with dt-schema. This commit replaces Synopsys DW I2C
legacy bare text bindings with YAML file. As before the bindings file
states that the corresponding dts node is supposed to be compatible
either with generic DW
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