Hi,
This is a subset of my bigger work for memory controller drivers [1].
Patch #1 (memory): I can take it through my tree because of dependant
work around compile testing.
Patch #2: Independent, please pick it up if it looks good.
[1]
On Fri, Jul 24, 2020 at 12:38:38PM +0200, Luka Kovacic wrote:
> MikroTik CRS305-1G-4S board has a switch chip with an integrated
> Marvell Prestera 98DX3236 CPU.
>
> This commit includes two board variants, namely the factory
> default one and a Bit variant. The Bit variant has a
> bigger
Enabling the JZ4780_NEMC driver makes sense only for specific hardware -
the Ingenic SoC architecture. Set it's dependency to MACH_INGENIC so it
will not appear on unrelated architectures (easier job for
downstream/distro kernel engineers).
When compile testing, do not enable the driver on other
On Fri, Jul 24, 2020 at 10:31:23AM -0400, qianjun.ker...@gmail.com wrote:
> From: jun qian
>
> When get the pending softirqs, it need to process all the pending
> softirqs in the while loop. If the processing time of each pending
> softirq is need more than 2 msec in this loop, or one of the
On 7/23/20 2:26 PM, Rajendra Nayak wrote:
> Post a successful pm_ops->core_get, an error in probe
> should exit by doing a pm_ops->core_put which seems
> to be missing. So fix it.
>
> Signed-off-by: Rajendra Nayak
> ---
> drivers/media/platform/qcom/venus/core.c | 15 ++-
> 1
On Fri, Jul 24, 2020 at 12:38:39PM +0200, Luka Kovacic wrote:
> MikroTik CRS328-4C-20S-4S board has a switch chip with an integrated
> Marvell Prestera 98DX3236 CPU.
>
> This commit includes two board variants, namely the factory
> default one and a Bit variant. The Bit variant has a
> bigger
Hi Linus,
Thanks for the review
> -Original Message-
> From: Linus Walleij
> Sent: Friday, July 24, 2020 2:52 PM
> To: kernel test robot
> Cc: Srinivas Neeli ; Bartosz Golaszewski
> ; Michal Simek ;
> Shubhrajyoti Datta ; Srinivas Goud
> ; kbuild-...@lists.01.org; open list:GPIO
On Fri, Jul 24, 2020 at 12:38:40PM +0200, Luka Kovacic wrote:
> An entry is added for MikroTik CRS3xx 98DX3236 based switches.
>
> Signed-off-by: Luka Kovacic
> Cc: Luka Perkov
> Cc: Jakov Petrina
Reviewed-by: Andrew Lunn
Andrew
On Fri, 24 Jul 2020 13:27:48 +0300
Mike Rapoport wrote:
> On Fri, Jul 24, 2020 at 08:05:52AM +0300, Jarkko Sakkinen wrote:
> > Use text_alloc() and text_free() instead of module_alloc() and
> > module_memfree() when an arch provides them.
> >
> > Cc: linux...@kvack.org
> > Cc: Andi Kleen
> >
On Fri, Jul 24, 2020 at 08:57:47AM +0200, Greg KH wrote:
> On Fri, Jul 24, 2020 at 10:18:07AM +0530, Madhuparna Bhowmik wrote:
> > On Thu, Jul 23, 2020 at 03:11:58PM -0700, David Miller wrote:
> > > From: madhuparnabhowmi...@gmail.com
> > > Date: Wed, 22 Jul 2020 22:53:29 +0530
> > >
> > > >
On Fri, Jul 24, 2020 at 09:48:54AM -0400, Jason Baron wrote:
>
>
> On 7/19/20 7:10 PM, Jim Cromie wrote:
> > this is v5, changes from previous:
> > - moved a chunk from patch 13 to 12, per Jason
> > - shorten logging prefix to "dyndbg", drop __func__
> > - now with more commit-log advocacy
>
Fri, Jul 24, 2020 at 04:19:51PM CEST, vadym.koc...@plvision.eu wrote:
>Marvell Prestera 98DX326x integrates up to 24 ports of 1GbE with 8
>ports of 10GbE uplinks or 2 ports of 40Gbps stacking for a largely
>wireless SMB deployment.
>
>Prestera Switchdev is a firmware based driver that operates via
Add a DT property "renesas-vin-ycbcr-8b-g" to select YCbCr422 8-bit data
input pins.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
Documentation/devicetree/bindings/media/renesas,vin.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git
Add support to read "renesas-vin-ycbcr-8b-g" DT property and select
the data pins accordingly for YCbCr422-8bit input
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/media/platform/rcar-vin/rcar-core.c | 4 +++-
drivers/media/platform/rcar-vin/rcar-dma.c | 7 +++
On Fri, Jul 24, 2020 at 07:46:32AM -0700, Andi Kleen wrote:
> > Something that seems to 'work' is:
> > '{cycles,cpu/instructions,period=5/}', so maybe you can make the
> > group modifier :S use any sampling event if there is one, and otherwise
> > designate the leader.
> >
> > Then you can
Hi All,
This patch series adds support to enable selecting data
lines via DT.
Cheers,
Prabhakar
Lad Prabhakar (2):
dt-bindings: media: renesas,vin: Document renesas-vin-ycbcr-8b-g
property
media: rcar-vin: Add support to read renesas-vin-ycbcr-8b-g property
On 07/23/20 at 11:21am, Mike Kravetz wrote:
> On 7/23/20 2:11 AM, Baoquan He wrote:
> > On 07/23/20 at 11:46am, Anshuman Khandual wrote:
> >>
> >>
> >> On 07/23/2020 08:52 AM, Baoquan He wrote:
> >>> A customer complained that no message is logged when the number of
> >>> persistent huge
On Fri, Jul 24, 2020 at 04:59:00PM +0200, Greg KH wrote:
> On Fri, Jul 24, 2020 at 09:48:54AM -0400, Jason Baron wrote:
> >
> >
> > On 7/19/20 7:10 PM, Jim Cromie wrote:
> > > this is v5, changes from previous:
> > > - moved a chunk from patch 13 to 12, per Jason
> > > - shorten logging prefix
On 7/23/20 4:15 PM, Arvind Sankar wrote:
> This #define is not used anywhere, and has the wrong value on x86_64.
Yeah, it certainly is unused.
> I tried digging into the history a bit, but it seems to have been unused
> even in the initial merge of sparsemem in v2.6.13, when it was first
>
Hi,
Gentle ping for review.
On 7/9/20 2:58 PM, Stanimir Varbanov wrote:
> This adds a new SCM memprotect command to set virtual address ranges.
>
> Signed-off-by: Stanimir Varbanov
> ---
> drivers/firmware/qcom_scm.c | 24
> drivers/firmware/qcom_scm.h | 1 +
>
I'm assuming the newly-enlarged positive error return of migrate_pages(2) won't
have adverse effects in userspace. Didn't see issues with any user in debian
codesearch, and can't imagine how it could be relied on.
This look ok. Just some nits, take them or leave them as you prefer.
On Thu, Jul 23, 2020 at 02:10:52PM -0600, Logan Gunthorpe wrote:
> On 2020-07-23 1:57 p.m., Bjorn Helgaas wrote:
> > On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:
> >> On Thu, Jul 23, 2020 at 1:43 PM Logan Gunthorpe
> >> wrote:
> >>>
> >>> The AMD Zen 2 root complex
Add support to read the bus-type and enable BT656 mode if needed.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/media/i2c/ov772x.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/drivers/media/i2c/ov772x.c
Hi All,
This patch series adds support for BT656 mode in the ov772x sensor
and also enables color bar test pattern control.
Cheers,
Prabhakar
Lad Prabhakar (2):
media: i2c: ov772x: Add support for BT656 mode
media: i2c: ov772x: Add test pattern control
drivers/media/i2c/ov772x.c | 48
Add support for test pattern control supported by the sensor.
Signed-off-by: Lad Prabhakar
Reviewed-by: Biju Das
---
drivers/media/i2c/ov772x.c | 25 -
include/media/i2c/ov772x.h | 1 +
2 files changed, 25 insertions(+), 1 deletion(-)
diff --git
On Fri, Jul 24, 2020 at 01:51:49PM +0300, Andy Shevchenko wrote:
> On Mon, Jul 20, 2020 at 7:31 PM Vaibhav Gupta
> wrote:
> >
> > Drivers using legacy PM have to manage PCI states and device's PM states
> > themselves. They also need to take care of configuration registers.
> >
> > With improved
Hi Krzysztof,
Le ven. 24 juil. 2020 à 16:54, Krzysztof Kozlowski a
écrit :
Enabling the MTD_NAND_JZ4780 driver makes sense only for specific
hardware - the Ingenic SoC architecture. Set it's dependency to
MACH_INGENIC so it will not appear on unrelated architectures (easier
job for
> -Original Message-
> From: Jonathan Cameron
> Sent: Monday, July 20, 2020 4:52 PM
> To: Lars-Peter Clausen
> Cc: Pop, Cristian ; linux-...@vger.kernel.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [RFC PATCH] one-bit-adc-dac: Add initial version of one bit ADC,
> DAC
>
>
On 07/23, Linus Torvalds wrote:
>
> But I'll walk over my patch mentally one more time. Here's the current
> version, anyway.
Both patches look correct to me, feel free to add
Reviewed-by: Oleg Nesterov
> @@ -1013,18 +1014,40 @@ static int wake_page_function(wait_queue_entry_t
> *wait,
On Fri, Jul 24, 2020 at 02:42:44PM +0300, Georgi Djakov wrote:
> Hello Greg,
>
> This is the pull request with the interconnect changes for the 5.9-rc1
> merge window. It contains some tiny core framework improvements. These
> will allow us to support new provider drivers for Samsung and Nvidia
>
Hi Thierry/Uwe,
Do you have any further comment on this patch? If not, could you please
help to pick it up?
Thanks,
Ray
On 7/17/2020 9:46 PM, Scott Branden wrote:
> From: Rayagonda Kokatanur
>
> Handle clk_get_rate() returning 0 to avoid possible division by zero.
>
> Fixes: daa5abc41c80
On Fri, Jul 24, 2020 at 03:19:06PM +0200, pet...@infradead.org wrote:
> On Thu, Jul 23, 2020 at 10:11:11AM -0700, kan.li...@linux.intel.com wrote:
> > @@ -3375,6 +3428,72 @@ static int intel_pmu_hw_config(struct perf_event
> > *event)
> > if (event->attr.type != PERF_TYPE_RAW)
> >
> -Original Message-
> From: Chi Song
> Sent: Friday, July 24, 2020 12:14 AM
> To: KY Srinivasan ; Haiyang Zhang
> ; Stephen Hemminger ;
> Wei Liu ; David S. Miller ; Jakub
> Kicinski
> Cc: linux-hyp...@vger.kernel.org; net...@vger.kernel.org; linux-
> ker...@vger.kernel.org
>
Good day,
You were recommended by a mutual associate. I write you regarding an investment
of bearer bonds I made on behalf of a client.
The investment was made in 2009 and has been under my management. The
said investor is deceased. The window is now available to assign these bonds
On 7/24/20 9:14 AM, Juri Lelli wrote:
> Hi,
>
> On 07/07/20 00:04, Peng Liu wrote:
>> 'commit 840d719604b0 ("sched/deadline: Update rq_clock of later_rq when
>> pushing a task")'
>> introduced the update_rq_clock() to fix the "used-before-update" bug.
>>
>> 'commit f4904815f97a ("sched/deadline:
\
Mrs.Lerynne West
Hallo, Sie haben eine Spende in Höhe von 2.800.000,00 €. Ich habe die
America-Lotterie in Amerika im Wert von 343 Millionen Dollar gewonnen und einen
Teil davon an fünf glückliche Menschen und Wohltätigkeitsorganisationen
gespendet, um an das Leben meines verstorbenen
On Fri, 24 Jul 2020 at 17:19, Paul Cercueil wrote:
>
> Hi Krzysztof,
>
>
> Le ven. 24 juil. 2020 à 16:54, Krzysztof Kozlowski a
> écrit :
> > Enabling the MTD_NAND_JZ4780 driver makes sense only for specific
> > hardware - the Ingenic SoC architecture. Set it's dependency to
> > MACH_INGENIC so
On Fri, Jul 24, 2020 at 04:50:53PM +0200, Joerg Roedel wrote:
> Next thing is, I can reliable reproduce it with yesterdays tip/master
> (commit 16f70beccf43), but did not see it with tip/master pulled today
> (commit c02699cd25e8) yet.
Next bisection try ended with this log:
# bad:
From: Richard Gong
Thor is moving to a new position and I will take over the maintainership.
Add myself as maintainer for 3 Altera drivers below:
1. Altera I2C driver
2. Altera System Manager driver
3. Altera System Resource driver
Signed-off-by: Richard Gong
Acked-by: Thor Thayer
---
On 24.07.20 07:31, Martin KaFai Lau wrote:
> On Thu, Jul 23, 2020 at 01:50:26PM +0200, KP Singh wrote:
>> From: KP Singh
>>
>> A purely mechanical change to split the renaming from the actual
>> generalization.
>>
>> Flags/consts:
>>
>> SK_STORAGE_CREATE_FLAG_MASK
Hi Roger,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on xen-tip/linux-next]
[also build test ERROR on linus/master v5.8-rc6 next-20200724]
[cannot apply to linux/master]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting
Le ven. 24 juil. 2020 à 17:33, Krzysztof Kozlowski a
écrit :
On Fri, 24 Jul 2020 at 17:19, Paul Cercueil
wrote:
Hi Krzysztof,
Le ven. 24 juil. 2020 à 16:54, Krzysztof Kozlowski
a
écrit :
> Enabling the MTD_NAND_JZ4780 driver makes sense only for specific
> hardware - the
Hello Rob,
Thank you for review.
On 2020/07/24 6:26, Rob Herring wrote:
On Thu, Jul 23, 2020 at 03:07:28AM +0900, Katsuhiro Suzuki wrote:
This patch converts Everest Semiconductor ES8316 low power audio
CODEC binding to DT schema.
Signed-off-by: Katsuhiro Suzuki
---
On 7/23/20 7:05 PM, Badhri Jagan Sridharan wrote:
> "tReceiverResponse 15 ms Section 6.6.2
> The receiver of a Message requiring a response Shall respond
> within tReceiverResponse in order to ensure that the
> sender’s SenderResponseTimer does not expire."
>
> When the cpu complex is busy
On Fri, Jul 24, 2020 at 05:50:06PM +0200, Paul Cercueil wrote:
>
>
> Le ven. 24 juil. 2020 à 17:33, Krzysztof Kozlowski a écrit
> :
> > On Fri, 24 Jul 2020 at 17:19, Paul Cercueil
> > wrote:
> > >
> > > Hi Krzysztof,
> > >
> > >
> > > Le ven. 24 juil. 2020 à 16:54, Krzysztof Kozlowski
> >
From: Richard Gong
When CTRL+C occurs during the process of FPGA reconfiguration, the FPGA
reconfiguration process stops and the user can't perform a new FPGA
reconfiguration properly.
Set FPGA task to be not interruptible so that the user can properly
perform FPGA reconfiguration after CTRL+C
Hi, Neal:
Neal Liu 於 2020年7月24日 週五 下午2:55寫道：
>
> Hi Chun-Kuang,
>
> On Fri, 2020-07-24 at 00:32 +0800, Chun-Kuang Hu wrote:
> > Hi, Neal:
> >
> > Neal Liu 於 2020年7月23日 週四 下午2:11寫道：
> > >
> > > Hi Chun-Kuang,
> > >
> > > On Wed, 2020-07-22 at 22:25 +0800, Chun-Kuang Hu wrote:
> > > > Hi, Neal:
>
[+cc Jonathan]
On 2020-07-24 9:06 a.m., Bjorn Helgaas wrote:
> On Thu, Jul 23, 2020 at 02:10:52PM -0600, Logan Gunthorpe wrote:
>> On 2020-07-23 1:57 p.m., Bjorn Helgaas wrote:
>>> On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:
On Thu, Jul 23, 2020 at 1:43 PM Logan Gunthorpe
The entries for JZ47xx SoCs and its drivers lacked MIPS mailing list.
Only MTD NAND driver pointed linux-mtd. Add linux-mips so the relevant
patches will get attention of MIPS developers.
Signed-off-by: Krzysztof Kozlowski
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git
This patch converts Everest Semiconductor ES8316 low power audio
CODEC binding to DT schema.
Signed-off-by: Katsuhiro Suzuki
---
Changes in v2:
- Change maintainers from Mark to Daniel and me
---
.../bindings/sound/everest,es8316.txt | 23 -
From: Joerg Roedel
The x86-64 ABI defines a red-zone on the stack:
The 128-byte area beyond the location pointed to by %rsp is considered
to be reserved and shall not be modified by signal or interrupt
handlers. Therefore, functions may use this area for temporary data
that is not
From: Joerg Roedel
Add a function to check whether an instruction has a REP prefix.
Signed-off-by: Joerg Roedel
Reviewed-by: Masami Hiramatsu
---
arch/x86/include/asm/insn-eval.h | 1 +
arch/x86/lib/insn-eval.c | 24
2 files changed, 25 insertions(+)
diff
From: Joerg Roedel
Install a page-fault handler to add an identity mapping to addresses
not yet mapped. Also do some checking whether the error code is sane.
This makes non SEV-ES machines use the exception handling
infrastructure in the pre-decompressions boot code too, making it less
likely
From: Joerg Roedel
Hi,
here is a rebased version of the latest SEV-ES patches. They are now
based on latest tip/master instead of upstream Linux and include the
necessary changes.
Changes to v4 are in particular:
- Moved early IDT setup code to idt.c, because the idt_descr
From: Joerg Roedel
Building a correct GHCB for the hypervisor requires setting valid bits
in the GHCB. Simplify that process by providing accessor functions to
set values and to update the valid bitmap.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/svm.h | 61
From: Joerg Roedel
The xgetbv() function is needed in pre-decompression boot code, but
asm/fpu/internal.h can't be included there directly. Doing so opens
the door to include-hell due to various include-magic in
boot/compressed/misc.h.
Avoid that by moving xgetbv()/xsetbv() to a separate header
From: Tom Lendacky
Add code to handle #VC exceptions on DR7 register reads and writes.
This is needed early because show_regs() reads DR7 to print it out.
Under SEV-ES there is currently no support for saving/restoring the
DRx registers, but software expects to be able to write to the DR7
From: Joerg Roedel
For SEV-ES this entry point will be used for restarting APs after they
have been offlined. Remove the '0' from the name to reflect that.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/cpu.h | 2 +-
arch/x86/kernel/head_32.S | 4 ++--
arch/x86/kernel/head_64.S | 6
From: Tom Lendacky
Implement a handler for #VC exceptions caused by RDPMC instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 22 ++
1
From: Joerg Roedel
The APs are not ready to handle exceptions when verify_cpu() is called
in secondary_startup_64.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/realmode.h | 1 +
arch/x86/kernel/head_64.S | 12
arch/x86/realmode/init.c| 6 ++
3 files
From: Tom Lendacky
As part of the GHCB specification, the booting of APs under SEV-ES
requires an AP jump table when transitioning from one layer of code to
another (e.g. when going from UEFI to the OS). As a result, each layer
that parks an AP must provide the physical address of an AP jump
From: Tom Lendacky
Calling down to EFI runtime services can result in the firmware performing
VMGEXIT calls. The firmware is likely to use the GHCB of the OS (e.g., for
setting EFI variables), so each GHCB in the system needs to be identity
mapped in the EFI page tables, as unencrypted, to avoid
From: Tom Lendacky
Implement a handler for #VC exceptions caused by MWAIT and MWAITX
instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 10 ++
1
From: Joerg Roedel
Handle #VC exceptions caused by #DB exceptions in the guest. Those
must be handled outside of instrumentation_begin()/end() so that the
handler will not be raised recursivly.
Handle them by calling the kernels debug exception handler.
Signed-off-by: Joerg Roedel
---
From: Joerg Roedel
When running under SEV-ES the kernel has to tell the hypervisor when to
open the NMI window again after an NMI was injected. This is done with
an NMI-complete message to the hypervisor.
Add code to the kernels NMI handler to send this message right at the
beginning of
From: Joerg Roedel
Set up the TSS for starting APs before they are kicked. This allows the
APs to use IST in early exception handling.
Also load the TSS early if the TSS entry in the GDT is present. This
makes sure a TSS is only loaded when it has been set up.
Signed-off-by: Joerg Roedel
---
From: Joerg Roedel
Add a play_dead handler when running under SEV-ES. This is needed
because the hypervisor can't deliver an SIPI request to restart the AP.
Instead the kernel has to issue a VMGEXIT to halt the VCPU until the
hypervisor wakes it up again.
Signed-off-by: Joerg Roedel
---
From: Tom Lendacky
Add handler for VC exceptions caused by MMIO intercepts. These
intercepts come along as nested page faults on pages with reserved
bits set.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to VC handling framework ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg
From: Joerg Roedel
Add two new paravirt callbacks to provide hypervisor specific processor
state in the GHCB and to copy state from the hypervisor back to the
processor.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/x86_init.h | 16 +++-
arch/x86/kernel/sev-es.c| 12
From: Joerg Roedel
Add the infrastructure to handle #VC exceptions when the kernel runs
on virtual addresses and has a GHCB mapped. This handler will be used
until the runtime #VC handler takes over.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/segment.h | 2 +-
From: Tom Lendacky
Implement the callbacks to copy the processor state required by KVM to
the GHCB.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: - Split out of a larger patch
- Adapt to different callback functions ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg
From: Joerg Roedel
The code at the trampoline entry point is executed in real-mode. In
real-mode #VC exceptions can't be handled, so anything that might cause
such an exception must be avoided.
In the standard trampoline entry code this is the WBINVD instruction and
the call to verify_cpu(),
From: Martin Radev
Make sure the machine supports RDRAND, otherwise there is no trusted
source of of randomness in the system.
To also check this in the pre-decompression stage, make has_cpuflag
not depend on CONFIG_RANDOMIZE_BASE anymore.
Signed-off-by: Martin Radev
Signed-off-by: Joerg
From: Doug Covelli
Add VMware specific handling for #VC faults caused by VMMCALL
instructions.
Signed-off-by: Doug Covelli
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: - Adapt to different paravirt interface ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
Hi Vitor,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on d43c7fb05765152d4d4a39a8ef957c4ea14d8847]
url:
https://github.com/0day-ci/linux/commits/Vitor-Massaru-Iha/lib-kunit-Convert-test_sort-to-KUnit-test/20200723-081244
base:
From: Joerg Roedel
Implement a handler for #VC exceptions caused by #AC exceptions. The #AC
exception is just forwarded to do_alignment_check() and not pushed down
to the hypervisor, as requested by the SEV-ES GHCB Standardization
Specification.
Signed-off-by: Joerg Roedel
---
From: Tom Lendacky
Implement a handler for #VC exceptions caused by VMMCALL instructions.
This patch is only a starting point, VMMCALL emulation under SEV-ES
needs further hypervisor-specific changes to provide additional state.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC
From: Tom Lendacky
Implement a handler for #VC exceptions caused by MONITOR and MONITORX
instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 13
From: Joerg Roedel
Allocate and map an IST stack and an additional fall-back stack for
the #VC handler. The memory for the stacks is allocated only when
SEV-ES is active.
The #VC handler needs to use an IST stack because it could be raised
from kernel space with unsafe stack, e.g. in the
From: Joerg Roedel
Make sure there is a stack once the kernel runs from virual addresses.
At this stage any secondary CPU which boots will have lost its stack
because the kernel switched to a new page-table which does not map the
real-mode stack anymore.
This is needed for handling early #VC
From: Tom Lendacky
Add the handlers for #VC exceptions invoked at runtime.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/idtentry.h | 5 +
arch/x86/kernel/idt.c | 11 +-
arch/x86/kernel/sev-es.c| 242 +++-
3
From: Tom Lendacky
Implement a handler for #VC exceptions caused by WBINVD instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling framework ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 9 +
1 file changed, 9
On Mon, 24 Feb 2020, Lee Jones wrote:
> On Mon, 27 Jan 2020, Suman Anna wrote:
>
> > The DT node full name is currently being used in regmap_config
> > which in turn is used to create the regmap debugfs directories.
> > This name however is not guaranteed to be unique and the regmap
> > debugfs
From: Joerg Roedel
Move the assembly coded dispatch between page-faults and all other
exceptions to C code to make it easier to maintain and extend.
Also change the return-type of early_make_pgtable() to bool and make it
static.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/pgtable.h
From: Joerg Roedel
When a #VC exception is triggered by user-space the instruction decoder
needs to read the instruction bytes from user addresses. Enhance
vc_decode_insn() to safely fetch kernel and user instructions.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 31
From: Tom Lendacky
Implement a handler for #VC exceptions caused by RDTSC and RDTSCP
instructions. Also make it available in the pre-decompression stage
because the KASLR code used RDTSC/RDTSCP to gather entropy and some
hypervisors intercept these instructions.
Signed-off-by: Tom Lendacky
[
From: Joerg Roedel
Early exception handling will use rd/wrgsbase in paranoid_entry/exit.
Enable the feature to avoid #UD exceptions on boot APs.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/head_64.S | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/x86/kernel/head_64.S
From: Tom Lendacky
Implement a handler for #VC exceptions caused by RDMSR/WRMSR
instructions.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 28
From: Tom Lendacky
Implement a handler for #VC exceptions caused by INVD instructions.
Since Linux should never use INVD, just mark it as unsupported.
Signed-off-by: Tom Lendacky
[ jroe...@suse.de: Adapt to #VC handling infrastructure ]
Co-developed-by: Joerg Roedel
Signed-off-by: Joerg
From: Joerg Roedel
Add handling for emulation the MOVS instruction on MMIO regions, as done
by the memcpy_toio() and memcpy_fromio() functions.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es.c | 77
1 file changed, 77 insertions(+)
diff --git
On Thu, Jul 23, 2020 at 4:18 PM Alex Deucher wrote:
>
> On Thu, Jul 23, 2020 at 4:11 PM Logan Gunthorpe wrote:
> >
> >
> >
> > On 2020-07-23 1:57 p.m., Bjorn Helgaas wrote:
> > > [+cc Andrew, Armen, hpa]
> > >
> > > On Thu, Jul 23, 2020 at 02:01:17PM -0400, Alex Deucher wrote:
> > >> On Thu, Jul
Hi Stephen,
Thanks for the review.
On 7/21/2020 1:18 PM, Stephen Boyd wrote:
Quoting Taniya Das (2020-07-14 23:36:50)
diff --git a/drivers/clk/qcom/lpasscorecc-sc7180.c
b/drivers/clk/qcom/lpasscorecc-sc7180.c
+static struct clk_alpha_pll lpass_lpaaudio_dig_pll = {
+ .offset =
From: Tom Lendacky
The runtime handler needs a GHCB per CPU. Set them up and map them
unencrypted.
Signed-off-by: Tom Lendacky
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/mem_encrypt.h | 2 ++
arch/x86/kernel/sev-es.c | 56 +-
From: Joerg Roedel
Re-use the handlers for CPUID and IOIO caused #VC exceptions in the
early boot handler.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/sev-es-shared.c | 7 +++
arch/x86/kernel/sev-es.c| 6 ++
2 files changed, 9 insertions(+), 4 deletions(-)
diff --git
From: Joerg Roedel
The get_stack_info functionality is needed in the entry code for the #VC
exception handler. Provide a version of it in the .text.noinstr
section which can be called safely from there.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/stacktrace.h | 2 ++
From: Joerg Roedel
The #VC handler needs special entry code because:
1. It runs on an IST stack
2. It needs to be able to handle nested #VC exceptions
To make this work the entry code is implemented to pretend it doesn't
use an IST stack. When entered from user-mode or early
On 7/24/2020 11:27 AM, pet...@infradead.org wrote:
On Fri, Jul 24, 2020 at 03:19:06PM +0200, pet...@infradead.org wrote:
On Thu, Jul 23, 2020 at 10:11:11AM -0700, kan.li...@linux.intel.com wrote:
@@ -3375,6 +3428,72 @@ static int intel_pmu_hw_config(struct perf_event *event)
if
From: Joerg Roedel
Also move it to a header file so that it can be used in the idt code
to setup the early IDT.
Signed-off-by: Joerg Roedel
---
arch/x86/include/asm/setup.h | 10 ++
arch/x86/kernel/head64.c | 5 -
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git
From: Joerg Roedel
Load the GDT right after switching to virtual addresses to make sure
there is a defined GDT for exception handling.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/head_64.S | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git
From: Joerg Roedel
Make sure segments are properly set up before setting up an IDT and
doing anything that might cause a #VC exception. This is later needed
for early exception handling.
Signed-off-by: Joerg Roedel
---
arch/x86/kernel/head_64.S | 52 +++
1
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