Since commit 8d7017fd621d ("blackhole_netdev: use blackhole_netdev to
invalidate dst entries"), we use blackhole_netdev to invalidate dst entries
instead of loopback device anymore. Also fix broken NETIF_F_HW_CSUM spell.
Signed-off-by: Miaohe Lin
---
include/linux/netdev_features.h | 2 +-
On Sat, Sep 5, 2020 at 10:53 AM Wang Hai wrote:
>
> BLOCK_PRIV is never used after it was introduced.
> So better to remove it.
>
> Reported-by: Hulk Robot
> Signed-off-by: Wang Hai
Acked-by: Willem de Bruijn
BLOCK_PRIV is never used after it was introduced.
So better to remove it.
Reported-by: Hulk Robot
Signed-off-by: Wang Hai
---
v1->v2:
Corrected the wrong comment
net/packet/af_packet.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/net/packet/af_packet.c b/net/packet/af_packet.c
index
tested full series on Bananapi-r64 (mt7531) running iperf3-server
[ ID] Interval Transfer Bitrate Retr
[ 5] 0.00-10.00 sec 1.09 GBytes 939 Mbits/sec0 sender
[ 5] 0.00-10.01 sec 1.09 GBytes 935 Mbits/sec receiver
reverse mode
Since commit 07d802699528 ("mm: devmap: refactor 1-based refcounting for
ZONE_DEVICE pages"), we have renamed the func put_devmap_managed_page() to
page_is_devmap_managed().
Signed-off-by: Miaohe Lin
---
mm/swap.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/mm/swap.c
Use helper macro abs() to simplify the "x > t || x < -t" cmp.
Signed-off-by: Miaohe Lin
---
mm/vmstat.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/mm/vmstat.c b/mm/vmstat.c
index 06fd13ebc2b8..648c2d6ddce2 100644
--- a/mm/vmstat.c
+++ b/mm/vmstat.c
@@ -329,7
Fix warning when compiling with W=1:
fs/read_write.c:88: warning: Function parameter or member 'maxsize' not
described in 'generic_file_llseek_size'
fs/read_write.c:88: warning: Excess function parameter 'size' description in
'generic_file_llseek_size'
Signed-off-by: Xianting Tian
---
After commit 745be2e700cd ("PCIe: portdrv: call pci_disable_device
during remove") and commit cc27b735ad3a ("PCI/portdrv: Turn off PCIe
services during shutdown"), it also calls pci_disable_device() during
shutdown, this seems unnecessary, so just remove it.
Signed-off-by: Tiezhu Yang
---
if of_find_device_by_node() succeed, mtk_ddp_comp_init() doesn't have
a corresponding put_device(). Thus add put_device() to fix the exception
handling for this function implementation.
Fixes: d0afe37f5209 ("drm/mediatek: support CMDQ interface in ddp component")
Signed-off-by: Yu Kuai
---
PAE bit of NCFGR register, when set, pauses transmission
if a non-zero 802.3 classic pause frame is received.
Fixes: 7897b071ac3b ("net: macb: convert to phylink")
Signed-off-by: Parshuram Thombare
---
drivers/net/ethernet/cadence/macb_main.c |3 +--
1 files changed, 1 insertions(+), 2
Some HW IP(ex: CCU) require the special iova range. That means the
iova got from dma_alloc_attrs for that devices must locate in his
special range. In this patch, we allocate a special iova_range for
each a special requirement and create each a iommu domain for each
a iova_range.
meanwhile we
If the iova is over 32bit, the fault status register bit is a little
different. Add a flag for the special register bits.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c
Add mt8192 smi support.
Signed-off-by: Yong Wu
---
drivers/memory/mtk-smi.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/drivers/memory/mtk-smi.c b/drivers/memory/mtk-smi.c
index e94c99ca2883..0ec3eff4d92d 100644
--- a/drivers/memory/mtk-smi.c
+++
If the iova is 34bit, the iova[32][33] is the bit0/1 in the tlb flush
register. Add a new macro for this.
there is a minor change unrelated with this patch. it also use the new
macro.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 11 +++
1 file changed, 7 insertions(+), 4
Add mt8192 iommu support.
For multi domain, Add 1M gap for the vdec domain size. That is because
vdec HW has a end address register which require (start_addr +
len) rather than (start_addr + len - 1). Take a example, if the start_addr
is 0xfff0, size is 0x10, then the end_address is
Add "struct mtk_iommu_data *" in the "struct mtk_iommu_domain",
reduce the call mtk_iommu_get_m4u_data().
No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c
In the previous SoC, the M4U HW is in the EMI power domain which is
always on. the latest M4U is in the display power domain which may be
turned on/off, thus we have to add pm_runtime interface for it.
When the engine work, the engine always enable the power and clocks for
smi-larb/smi-common,
After extending v7s, our pagetable already support iova reach
16GB(34bit). the master got the iova via dma_alloc_attrs may reach
34bits, but its HW register still is 32bit. then how to set the
bit32/bit33 iova? this depend on a SMI larb setting(bank_sel).
we separate whole 16GB iova to four
Defaultly the iova range is 0-4G. here we add a single-domain(0-4G)
for the previous SoC. this also is a preparing patch for supporting
multi-domains.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 12
1 file changed, 12 insertions(+)
diff --git a/drivers/iommu/mtk_iommu.c
For multiple iommu_domains, we need to reserve some iova regions. Take a
example, If the default iova region is 0 ~ 4G, but the 0x4000_ ~
0x43ff_ is only for the special CCU0 domain. Thus we should exclude
this region for the default iova region.
This patch adds iova reserved flow. It's a
In the lastest SoC, M4U has its special power domain. thus, If the engine
begin to work, it should help enable the power for M4U firstly.
Currently if the engine work, it always enable the power/clocks for
smi-larbs/smi-common. This patch adds device_link for smi-common and M4U.
then, if
Add "cfg" as a parameter for some macros. This is a preparing patch for
mediatek extend the lvl1 pgtable. No functional change.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 34 +++---
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git
In attach device, it will update the pagetable base address register.
Move the hw_init function also here. Then it only need call
pm_runtime_get/put one time here if m4u has power domain.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 10 ++
1 file changed, 6 insertions(+), 4
MediaTek extend the bit5 in lvl1 and lvl2 descriptor as PA34.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 9 +++--
drivers/iommu/mtk_iommu.c | 2 +-
include/linux/io-pgtable.h | 4 ++--
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git
As title.
BTW, change the ias/oas checking format in v7s_map.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/iommu/io-pgtable-arm-v7s.c
b/drivers/iommu/io-pgtable-arm-v7s.c
index
This patch adds decriptions for mt8192 IOMMU and SMI.
mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
table format. The M4U-SMI HW diagram is as below:
EMI
|
M4U
|
The standard input iova bits is 32. MediaTek quad the lvl1 pagetable
(4 * lvl1). No change for lvl2 pagetable. Then the iova bits can reach
34bit.
Signed-off-by: Yong Wu
---
drivers/iommu/io-pgtable-arm-v7s.c | 13 ++---
drivers/iommu/mtk_iommu.c | 2 +-
2 files changed, 11
Use the common larb-port header in the source code.
Signed-off-by: Yong Wu
---
drivers/iommu/mtk_iommu.c | 7 ---
drivers/iommu/mtk_iommu.h | 1 +
drivers/memory/mtk-smi.c | 1 +
include/soc/mediatek/smi.h | 2 --
4 files changed, 2 insertions(+), 9 deletions(-)
diff --git
Extend the max larb number definition as mt8192 has larb_nr over 16.
Signed-off-by: Yong Wu
Acked-by: Rob Herring
---
include/dt-bindings/memory/mtk-smi-larb-port.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/dt-bindings/memory/mtk-smi-larb-port.h
Convert MediaTek SMI to DT schema.
Signed-off-by: Yong Wu
---
.../mediatek,smi-common.txt | 49 --
.../mediatek,smi-common.yaml | 96 +++
.../memory-controllers/mediatek,smi-larb.txt | 49 --
Put all the macros about smi larb/port togethers, this is a preparing
patch for extending LARB_NR and adding new dom-id support.
Signed-off-by: Yong Wu
Acked-by: Rob Herring
---
include/dt-bindings/memory/mt2712-larb-port.h | 2 +-
include/dt-bindings/memory/mt6779-larb-port.h | 2 +-
In the latest SoC, there are several HW IP require a sepecial iova
range, mainly CCU and VPU has this requirement. Take CCU as a example,
CCU require its iova locate in the range(0x4000_ ~ 0x43ff_).
In this patch we add a domain definition for the special port. In the
example of CCU, If
Convert MediaTek IOMMU to DT schema.
Signed-off-by: Yong Wu
---
.../bindings/iommu/mediatek,iommu.txt | 103
.../bindings/iommu/mediatek,iommu.yaml| 150 ++
2 files changed, 150 insertions(+), 103 deletions(-)
delete mode 100644
This patch mainly adds support for mt8192 IOMMU and SMI.
mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
table format. The M4U-SMI HW diagram is as below:
EMI
|
M4U
On Fri, Sep 04, 2020 at 08:27:43AM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects NAND controller to be named
> "nand-controller", otherwise dtbs_check complain with a warning like:
>
> arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dt.yaml: gpmi-nand@8000c000:
>
On Thu, Sep 03, 2020 at 04:53:47PM +0200, Matthias Schiffer wrote:
> - Fix national,lm75 compatible string
> - Remove obsolete fsl,spi-num-chipselects
Two patches, please.
Shawn
>
> Fixes: cac849e9bbc8 ("ARM: dts: imx6qdl: add TQMa6{S,Q,QP} SoM")
> Signed-off-by: Matthias Schiffer
> ---
>
>
On Thu, Sep 03, 2020 at 04:53:46PM +0200, Matthias Schiffer wrote:
> Fixes: cac849e9bbc8 ("ARM: dts: imx6qdl: add TQMa6{S,Q,QP} SoM")
> Signed-off-by: Matthias Schiffer
Sorry, I do not take patch with empty commit log.
Shawn
> ---
>
> v2: no changes
>
> arch/arm/boot/dts/imx6qdl-tqma6.dtsi
On Thu, Sep 03, 2020 at 06:05:21PM +0800, fugang.d...@nxp.com wrote:
> From: Fugang Duan
>
> The pad QSPI1B_SCLK mux mode 0x1 is for function UART3_DTE_TX,
> correct the mux mode.
>
> Fixes: 743636f25f1d ("ARM: dts: imx: add pin function header for imx6sx")
> Signed-off-by: Fugang Duan
On Wed, Sep 02, 2020 at 06:32:23PM +0200, Krzysztof Kozlowski wrote:
> The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent
> allows to probe the bd718x7 clock driver fixing boot errors:
>
> bd718xx-clk bd71847-clk.1.auto: No parent clk found
> bd718xx-clk: probe of
On Wed, Sep 02, 2020 at 08:43:30PM +0530, meenakshi.aggar...@nxp.com wrote:
> From: Meenakshi Aggarwal
>
> Add device tree support for LX2162AQDS board.
> LX2162A has same die as of LX2160A with different packaging.
>
> Signed-off-by: Ioana Ciornei
> Signed-off-by: Kuldeep Singh
>
On Wed, Sep 02, 2020 at 05:02:44PM +0200, Krzysztof Kozlowski wrote:
> Fix and add missing kerneldoc to fix compile warnings like:
>
> drivers/clk/imx/clk-pfd.c:27: warning: Function parameter or member 'hw'
> not described in 'clk_pfd'
> drivers/clk/imx/clk-pllv3.c:53: warning: Function
On Wed, Sep 02, 2020 at 05:02:42PM +0200, Krzysztof Kozlowski wrote:
> Multiple files from arch/arm/mach-imx/ use clock init functions which
> are defined in the IMX clock drivers. Declare them in globally
> accessible header to fix GCC warnings:
>
> drivers/clk/imx/clk-imx21.c:122:74:
On Tue, Sep 01, 2020 at 11:37:35AM +0200, Oleksij Rempel wrote:
> Plymovent M2M is a control interface produced for the Plymovent filter
> systems.
>
> Signed-off-by: David Jander
> Signed-off-by: Oleksij Rempel
> ---
> arch/arm/boot/dts/Makefile | 1 +
>
On Tue, Sep 01, 2020 at 11:37:34AM +0200, Oleksij Rempel wrote:
> Add Plymovent Group BV M2M iMX6dl based board
>
> Signed-off-by: Oleksij Rempel
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git
On Fri, Sep 04, 2020 at 08:15:03PM +0200, Arnd Bergmann wrote:
> Is there a bigger plan for the rest? I can probably have a look at the Arm
> OABI code if nobody else working on that yet.
m68knommu seems mostly trivial and not interact much with m68k/mmu,
so that woud be my next target. All the
Le 04/09/2020 à 23:01, David Laight a écrit :
From: Alexey Dobriyan
Sent: 04 September 2020 18:58
On Fri, Sep 04, 2020 at 08:00:24AM +0200, Ingo Molnar wrote:
* Christoph Hellwig wrote:
this series removes the last set_fs() used to force a kernel address
space for the uaccess code in the
On Fri, Sep 04, 2020 at 08:04:34PM +0200, Arnd Bergmann wrote:
> > if (__builtin_constant_p(n)) {
> > switch(n) {
> > case 1:
> > - *(u8 *)to = *(u8 __force *)from;
> > + *(u8 *)to = get_unaligned((u8 __force
Add function to build prefetch iommu pages command
Signed-off-by: Wesley Sheng
---
drivers/iommu/amd/amd_iommu_types.h | 2 ++
drivers/iommu/amd/iommu.c | 19 +++
2 files changed, 21 insertions(+)
diff --git a/drivers/iommu/amd/amd_iommu_types.h
My Dear in the lord
My name is Mrs. Mina A. Brunel I am a Norway Citizen who is living in Burkina
Faso, I am married to Mr. Brunel Patrice, a politician who owns a small gold
company in Burkina Faso; He died of Leprosy and Radesyge, in the year February
2010, During his lifetime he
On Tue, Sep 01, 2020 at 06:21:49PM +0800, Robin Gong wrote:
> Correct sdma1 ahb clk, otherwise wrong 1:1 clk ratio will be chosed so
> that sdma1 function broken. sdma1 should use 1:2 clk, while sdma2/3 use
> 1:1.
>
> Fixes: 6d9b8d20431f ("arm64: dts: freescale: Add i.MX8MP dtsi support")
> Cc:
Sdw stream operation APIs can be called once per stream. Move these
operations to dailink ops. The linked series is "soundwire: Remove sdw
stream operations from Intel soundwire dai".
Reviewed-by: Vinod Koul
Changes in v3:
- s/ASOC/ASoC
Pierre-Louis Bossart (3):
ASoC: soc-dai: clarify
From: Pierre-Louis Bossart
Add trigger functionality to dailink, so far only .startup() and
.shutdown() were implemented at the machine driver level.
The companion patch for this patch is the removal of the trigger
callback at the DAI level in drivers/soundwire/intel.c
Signed-off-by:
From: Pierre-Louis Bossart
Previous changes move to use ERR_PTR(-ENOTSUPP), but it's not clear
what implementations can return in case of errors. Explicitly document
that NULL is not a possible return value, only ERR_PTR with a negative
error code is valid.
Fixes: 308811a327c38 ('ASoC: soc-dai:
From: Pierre-Louis Bossart
Add .prepare and .hw_free callback to dailink.
The companion patch for this patch is the removal of stream operations
in the .prepare and .hw_free callbacks at the DAI level in
drivers/soundwire/intel.c
Signed-off-by: Pierre-Louis Bossart
Reviewed-by: Rander Wang
On Sat, Aug 29, 2020 at 11:40:24AM +0200, Krzysztof Kozlowski wrote:
> The PCA95xx GPIO expander requires GPIO controller properties to operate
> properly.
>
> Signed-off-by: Krzysztof Kozlowski
Applied, thanks.
On Fri, Aug 28, 2020 at 06:47:40PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects pin configuration groups to end with 'grp'
> suffix, otherwise dtbs_check complain with a warning like:
>
> ... do not match any of the regexes: 'grp$', 'pinctrl-[0-9]+'
>
> Signed-off-by:
In some cases, for UDP GSO, UDPv4 and UDPv6 need to be handled
separately, for example, checksum offload, so add new GSO type
SKB_GSO_UDPV6_L4 for UDPv6, and the old SKB_GSO_UDP_L4 stands
for UDPv4.
Signed-off-by: Huazhong Tan
---
drivers/net/bonding/bond_main.c | 4
There are two updates relates to UDP GSO.
#1 adds a new GSO type for UDPv6
#2 adds check for UDP GSO when csum is disable in netdev_fix_features().
Changes since RFC V2:
- modifies the timing of setting UDP GSO type when doing UDP GRO in #1.
Changes since RFC V1:
- updates NETIF_F_GSO_LAST
When CSUM is not available, UDP GSO should be disable as well.
Signed-off-by: Huazhong Tan
---
net/core/dev.c | 12
1 file changed, 12 insertions(+)
diff --git a/net/core/dev.c b/net/core/dev.c
index d42c9ea..0c78306 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -9402,6
On Fri, Aug 28, 2020 at 06:47:37PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects pin configuration groups to end with 'grp'
> suffix. This fixes dtbs_check warnings like:
>
> pinctrl@3033: 'pcal6414-gpio', 'pmicirq', 'usdhc1grp100mhz',
> 'usdhc1grp200mhz',
On Fri, Aug 28, 2020 at 06:47:39PM +0200, Krzysztof Kozlowski wrote:
> The ROHM BD71847 PMIC has a 32.768 kHz clock. Adding necessary parent
> allows to probe the bd718x7 clock driver fixing boot errors:
>
> bd718xx-clk bd71847-clk.1.auto: No parent clk found
> bd718xx-clk: probe of
Introduce tracepoints for tasklets just like softirq does. In this case,
we can calculate tasklet latency and know what tasklet run.
Signed-off-by: Muchun Song
---
include/trace/events/irq.h | 44 ++
kernel/softirq.c | 2 ++
2 files changed, 46
On Fri, Aug 28, 2020 at 09:20:35PM +0200, Krzysztof Kozlowski wrote:
> Device tree schema expects NAND controller to be named
> "nand-controller", otherwise dtbs_check complain with a warning like:
>
> arch/arm/boot/dts/imx28-eukrea-mbmx283lc.dt.yaml: gpmi-nand@8000c000:
>
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