create_dtb() function allocates memory for the device tree blob (DTB)
and calls fdt_open_into(). If this call fails the memory allocated
for the DTB is not freed before returning from create_dtb() thereby
leaking memory.
Call vfree() to free the memory allocated for the DTB if fdt_open_into()
The functions defined in "arch/powerpc/kexec/ima.c" handle setting up
and freeing the resources required to carry over the IMA measurement
list from the current kernel to the next kernel across kexec system call.
These functions do not have architecture specific code, but are
currently limited to
Address and size of the buffer containing the IMA measurement log need
to be passed from the current kernel to the next kernel on kexec.
Any existing "linux,ima-kexec-buffer" property in the device tree
needs to be removed and its corresponding memory reservation in
the currently running kernel
On Wed, Dec 16, 2020 at 5:27 AM Adrien Grassein
wrote:
>
> nxp,phase-shift is an enum so use enum format to describe it.
> Minimum and maximum values are also wrong.
>
> Signed-off-by: Adrien Grassein
> ---
> .../bindings/regulator/nxp,pf8x00-regulator.yaml | 16
> 1 file
fdt_appendprop_addrrange() function adds a property, with the given name,
to the device tree at the given node offset, and also sets the address
and size of the property. This function should be used to add
"linux,ima-kexec-buffer" property to the device tree and set the address
and size of the
dzień dobry
Nazywam się George Mike. Z zawodu jestem prawnikiem. Chcę ci zaoferować
najbliższy krewny mojego klienta. Odziedziczysz sumę (8,5 miliona dolarów)
dolarów, które mój klient zostawił w banku przed śmiercią.
Mój klient jest obywatelem twojego kraju, który zginął wraz z żoną w
wypadku
On Wed, Dec 16, 2020 at 5:27 AM Adrien Grassein
wrote:
>
> Fix the ternary condition which is a bad coding style
> in the kernel
>
> I also remove the defering configuration of the nxp,phase-shift.
> The configuration is now done at parsing time. It save some memory
> and it's better for
On 12/17/20 6:27 PM, Joe Perches wrote:
> On Thu, 2020-12-17 at 18:11 +0100, Helge Deller wrote:
>> In most cases people use lookup_symbol_name() to resolve a kernel symbol
>> and then print it via printk().
>>
>> In such cases using the %ps, %pS, %pSR or %pB printk formats are easier
>> to use
On Wed, Dec 16, 2020 at 11:00:59PM -0500, Sven Van Asbroeck wrote:
> On Wed, Dec 16, 2020 at 7:53 AM Clemens Gruber
> wrote:
> >
> > Implements .get_state to read-out the current hardware state.
> >
>
> I am not convinced that we actually need this.
>
> Looking at the pwm core, .get_state() is
On Wed, Dec 16, 2020 at 11:02:03PM -0500, Sven Van Asbroeck wrote:
> Hi Clemens, minor nit below.
>
> On Wed, Dec 16, 2020 at 7:53 AM Clemens Gruber
> wrote:
> >
> > Reset the prescale and ON/OFF registers to their POR default state in
> > the probe function. Otherwise, the PWMs could still be
Dear xfs developer,
I was doing some testing on a Linux 5.10.1 system with two 100 TB xfs
filesystems on md raid6 raids.
The stress test was essentially `cp -a`ing a Linux source repository with two
threads in parallel on each filesystem.
After about on hour, the processes to one filesystem
On Thu, Dec 17, 2020 at 9:27 AM Linus Torvalds
wrote:
>
> So I think I'll just apply this patch instead.
Commit d652d5f1eeeb ("drm/edid: fix objtool warning in
drm_cvt_modes()") has the long and boring explanation.
Linus
From: Stefan Chulski
Issue:
Flow control frame used to pause GoP(MAC) was delivered to the CPU
and created a load on the CPU. Since XOFF/XON frames are used only
by MAC, these frames should be dropped inside MAC.
Fix:
According to 802.3-2012 - IEEE Standard for Ethernet pause frame
has unique
On Wed, Dec 16, 2020 at 11:02:57PM -0500, Sven Van Asbroeck wrote:
> Hi Clemens, see below.
>
> On Wed, Dec 16, 2020 at 7:53 AM Clemens Gruber
> wrote:
> >
> > The PCA9685 supports staggered LED output ON times to minimize current
> > surges and reduce EMI.
> > When this new option is enabled,
On Thu, Dec 17, 2020 at 9:24 AM Colin King wrote:
>
> From: Colin Ian King
>
> There is a spelling mistake in the Kconfig help text. Fix it.
>
> Signed-off-by: Colin Ian King
> ---
> arch/xtensa/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Thanks. Applied to my xtensa tree.
On Thu, Dec 17, 2020 at 12:43 PM Clemens Gruber
wrote:
> >
> > Conclusion: .get_state() will always return "pwm disabled", so why do we
> > bother reading out the h/w?
>
> If there are no plans for the PWM core to call .get_state more often in
> the future, we could just read out the period and
On Thu, 17 Dec 2020 16:05:37 +0100
Borislav Petkov wrote:
> So, that thing.
>
> I have this ontop of 5.10 along with most comments integrated.
>
> Now, I'm thinking if I start sending those pieces which belong into the
> main process documentation, the bikeshedding that is going to ensue is
>
Hi Stefan,
Quoting stef...@marvell.com (2020-12-17 18:23:11)
> From: Stefan Chulski
>
> Current PPPoE+IPv6 entry is jumping to 'next-hdr'
> field and not to 'DIP' field as done for IPv4.
>
> Fixes: db9d7d36eecc ("net: mvpp2: Split the PPv2 driver to a dedicated
> directory")
That's not the
On Thu, Dec 17, 2020 at 7:33 AM Adam Ford wrote:
>
> On Thu, Dec 17, 2020 at 5:12 AM Geert Uytterhoeven
> wrote:
> >
> > Hi Adam,
> >
> > CC alsa-devel
> >
> > On Sun, Dec 13, 2020 at 7:38 PM Adam Ford wrote:
> > > With the newly added configurable clock options, the audio CODEC can
> > >
On Thu, 17 Dec 2020 09:25:48 +0100 Ahmad Fatoum wrote:
> On 17.12.20 02:13, Jakub Kicinski wrote:
> >> + netdev_warn(priv->dev, "HW Timestamping init failed:
> >> %pe\n",
> >> + ERR_PTR(ret));
> >
> > why convert to ERR_PTR and use %pe and not
On Thu, Dec 17, 2020 at 10:53:23AM -0700, Jonathan Corbet wrote:
> Gee...a response from a two-year-old thread...
You know how we love to document stuff, right? :-)
> it's taking me a while to page all of that back in :)
Here's the gist of your concern:
> External Email
>
> --
> Hi Stefan,
>
> Quoting stef...@marvell.com (2020-12-17 18:23:11)
> > From: Stefan Chulski
> >
> > Current PPPoE+IPv6 entry is jumping to 'next-hdr'
> > field and not to 'DIP' field as done for IPv4.
>
Adds a wrapper shell script for the test_scanf module.
Signed-off-by: Richard Fitzgerald
Reviewed-by: Petr Mladek
---
tools/testing/selftests/lib/Makefile | 2 +-
tools/testing/selftests/lib/config | 1 +
tools/testing/selftests/lib/scanf.sh | 4
3 files changed, 6 insertions(+), 1
If a signed number field starts with a '-' the field width must be > 1,
or unlimited, to allow at least one digit after the '-'.
This patch adds a check for this. If a signed field starts with '-'
and field_width == 1 the scanf will quit.
It is ok for a signed number field to have a field width
Adds test_sscanf to test various number conversion cases, as
number conversion was previously broken.
This also tests the simple_strtoxxx() functions exported from
vsprintf.c.
Signed-off-by: Richard Fitzgerald
---
MAINTAINERS | 1 +
lib/Kconfig.debug | 3 +
lib/Makefile | 1 +
The existing code attempted to handle numbers by doing a strto[u]l(),
ignoring the field width, and then repeatedly dividing to extract the
field out of the full converted value. If the string contains a run of
valid digits longer than will fit in a long or long long, this would
overflow and no
Quoting stef...@marvell.com (2020-12-17 18:45:06)
> From: Stefan Chulski
>
> Issue:
> Flow control frame used to pause GoP(MAC) was delivered to the CPU
> and created a load on the CPU. Since XOFF/XON frames are used only
> by MAC, these frames should be dropped inside MAC.
>
> Fix:
> According
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet,
Hi Sven,
On Wed, Dec 16, 2020 at 11:03:39PM -0500, Sven Van Asbroeck wrote:
> Hi Clemens, see below.
>
> On Wed, Dec 16, 2020 at 7:53 AM Clemens Gruber
> wrote:
> >
> > Previously, the last used PWM channel could change the global prescale
> > setting, even if other channels were already in
Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs, which reduces
power consumption and heating of the Tegra chips. Tegra SoC has multiple
hardware units which belong to a core power domain of the SoC and share
the core voltage. The voltage must be selected in accordance to a minimum
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.
Signed-off-by: Dmitry Osipenko
---
.../display/tegra/nvidia,tegra20-host1x.txt | 49 +++
1 file changed, 49 insertions(+)
diff --git
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet,
Extend OPP API with dev_pm_opp_sync_regulators() function, which syncs
voltage state of regulators.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 42 ++
include/linux/pm_opp.h | 11 +++
2 files changed, 53 insertions(+)
diff --git
Power domain fits much better than a voltage regulator in regards to
a proper hardware description and from a software perspective as well.
Hence replace the core regulator with the power domain. Note that this
doesn't affect any existing DTBs because we haven't started to use the
regulator yet,
Hi Linus,
The following changes since commit
63e2fffa59a9dd91e443b08832656399fd80b7f0:
pNFS/flexfiles: Fix array overflow when flexfiles mirroring is
enabled (2020-11-30 10:52:22 -0500)
are available in the Git repository at:
git://git.linux-nfs.org/projects/trondmy/linux-nfs.git
Print OPP level in debug message of _opp_add_static_v2(). This helps to
chase GENPD bugs.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 1f2038a4420b..56b153ea5c56 100644
---
The debug message always prints rate=0 instead of a proper value, fix it.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/of.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/of.c b/drivers/opp/of.c
index 3b5a4c8bc62f..1f2038a4420b 100644
---
Add new Kconfig SOC_TEGRA_COMMON option which selects configuration
options that are common for all Tegra SoCs. Select PM_OPP by default
since from now on OPPs will be used by Tegra drivers which present on
all SoC generations, like display controller driver for example.
Signed-off-by: Dmitry
Add OPP and generic power domain support to the video decoder driver.
This allows us to utilize a modern GENPD API for newer device-trees and
support DVFS of the decoder hardware. Note that older DTBs will continue
to work like they did it before this patch.
Tested-by: Peter Geis
Tested-by:
Enable CPU voltage scaling and thermal throttling on Tegra30 Cardhu board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra30-cardhu.dtsi | 61 ++-
1 file changed, 60 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi
Add "performance" column to debug summary which shows performance state
of all power domains and theirs devices.
Signed-off-by: Dmitry Osipenko
---
drivers/base/power/domain.c | 22 +-
1 file changed, 17 insertions(+), 5 deletions(-)
diff --git a/drivers/base/power/domain.c
Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
1 file changed, 39 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
NVIDIA Tegra SoCs have a power domains topology such that child domains
only clamp a power rail, while parent domain controls shared performance
state of the multiple child domains. In this case child's domain doesn't
need to have OPP table. Hence we want to allow children power domains to
pass
The core voltage shall not drop until state of Core domain is synced,
i.e. all device drivers that use Core domain are loaded and ready.
Support Core domain state syncing. The Core domain driver invokes the
core-regulator voltage syncing once the state of domain is synced, at
this point the Core
The Core domain is a parent of PMC power domains, hence PMC domains
should be set up as a sub-domains of the parent (Core) domain if
"power-domains" phandle presents in a device-tree node of PMC domain.
This allows to propagate GENPD performance changes to the parent Core
domain if performance
Allow lower core voltages on Acer A500.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-acer-a500-picasso.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts
Add OPP tables and power domains to the Tegra20 device-tree.
Signed-off-by: Dmitry Osipenko
---
.../boot/dts/tegra20-acer-a500-picasso.dts| 4 +
arch/arm/boot/dts/tegra20-colibri.dtsi| 6 +-
arch/arm/boot/dts/tegra20-harmony.dts | 6 +-
Allow lower core voltages on Ventana board.
Signed-off-by: Dmitry Osipenko
---
arch/arm/boot/dts/tegra20-ventana.dts | 32 ---
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/tegra20-ventana.dts
b/arch/arm/boot/dts/tegra20-ventana.dts
Host1x channel should be idling before hardware is turned off, hence
stop the channel in the suspend callback.
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/vic.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/tegra/vic.c
Add common helper which initializes OPP table for Tegra SoC core devices.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/common.c | 137 +
include/soc/tegra/common.h | 35 ++
2 files changed, 172 insertions(+)
diff --git
On Thu, Dec 17, 2020 at 03:04:32PM +, Satya Tangirala wrote:
> This patch series adds support for metadata encryption to F2FS using
> blk-crypto.
Is there a companion patch series needed so that f2fstools can
check/repair a file system with metadata encryption enabled?
The GR3D1 hardware unit needs to pulse hardware reset after removing power
clamp, otherwise reset won't be deasserted. Hence give reset a pulse after
removing the clamp. This stayed unnoticed previously because power
management wasn't supported by the 3D driver until recently and all power
gates
Make regulator_sync_voltage() to re-balance voltage state of a coupled
regulators instead of changing the voltage directly.
Signed-off-by: Dmitry Osipenko
---
drivers/regulator/core.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
The tegra_powergate_power_up() has a typo in the error code path where it
will try to disable clocks twice, fix it. In practice that error never
happens, so this is a minor correction.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 2 +-
1 file changed, 1 insertion(+), 1
Fix voltage coupler lockup which happens when voltage-spread is out
of range due to a bug in the code. The max-spread requirement shall be
accounted when CPU regulator doesn't have consumers. This problem is
observed on Tegra30 Ouya game console once system-wide DVFS is enabled
in a device-tree.
NVIDIA Tegra SoCs have multiple power domains, each domain corresponds
to an external SoC power rail. Core power domain covers vast majority of
hardware blocks within a Tegra SoC. The voltage of a power domain should
be set to a value which satisfies all devices within a power domain. Add
driver
Add suspend/resume and generic power domain support to the Host1x driver.
This is required for enabling system-wide DVFS and supporting dynamic
power management using a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
Add OPP tables and power domains to Tegra30 device-tree.
Signed-off-by: Dmitry Osipenko
---
.../tegra30-asus-nexus7-grouper-common.dtsi |4 +
arch/arm/boot/dts/tegra30-beaver.dts |4 +
arch/arm/boot/dts/tegra30-cardhu.dtsi | 20 +-
Make set_performance_state() callback optional in order to remove the
need from power domain drivers to implement a dummy callback. If callback
isn't implemented by a GENPD driver, then the performance state is passed
to the parent domain.
Signed-off-by: Dmitry Osipenko
---
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra20-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra20-emc.c
Add OPP and PM support to the GR2D driver. This is required for enabling
system-wide DVFS and supporting dynamic power management using a generic
power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 73
Use common devm_tegra_core_dev_init_opp_table() helper for the OPP table
initialization.
Signed-off-by: Dmitry Osipenko
---
drivers/memory/tegra/tegra30-emc.c | 57 +++---
1 file changed, 4 insertions(+), 53 deletions(-)
diff --git a/drivers/memory/tegra/tegra30-emc.c
The device-tree compatibles are swapped in the code, correct them.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr2d.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/tegra/gr2d.c
Fix adding OPP entries in a wrong (opposite) order if OPP rate is
unavailable. The OPP comparison is erroneously skipped if OPP rate is
missing, thus OPPs are left unsorted.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 23 ---
drivers/opp/opp.h | 2 +-
2 files
Add OPP and add PM support to the GR3D driver. This is required for
enabling system-wide DVFS and supporting dynamic power management using
a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/gr3d.c | 264
Support set_opp() customization without requiring to use regulators. This
is needed by drivers which want to use dev_pm_opp_set_rate() for changing
rates of a multiple clocks and don't need to touch regulator.
One example is NVIDIA Tegra30/114 SoCs which have two sibling 3D hardware
units which
Print out domain name when reset fails to acquire for debugging purposes
and to make formatting of GENPD errors consistent in the driver.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/tegra/pmc.c
Add host1x_channel_stop() which waits till channel becomes idle and then
stops the channel hardware. This is needed for supporting suspend/resume
by host1x drivers since the hardware state is lost after power-gating,
thus the channel needs to be stopped before entering into suspend.
The Clock-and-Reset controller resides in a "core" power domain on
NVIDIA Tegra SoCs. In order to support voltage scaling of the core power
rail, we need to hook up some clocks (which can't operate properly on a
lower voltages above certain clock rates) to the core power domain in
order to ensure
Switch all clocks of a power domain to a safe rate which is suitable
for all possible voltages in order to ensure that hardware constraints
aren't violated when power domain state toggles.
Signed-off-by: Dmitry Osipenko
---
drivers/soc/tegra/pmc.c | 92 -
A required OPP may not be available, and thus, all OPPs which are using
this required OPP should be unavailable too.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
Add resource-managed versions of OPP API functions. This removes a need
from drivers to store and manage OPP table pointers.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 173 +
drivers/opp/of.c | 25 ++
include/linux/pm_opp.h |
Add OPP and SoC core voltage scaling support to the display controller
driver. This is required for enabling system-wide DVFS on pre-Tegra186
SoCs.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
Signed-off-by: Dmitry Osipenko
---
drivers/gpu/drm/tegra/dc.c | 66
On Thu, Dec 17, 2020 at 10:51:08AM -0600, Rob Herring wrote:
> On Fri, Dec 11, 2020 at 5:10 PM Rasmus Villemoes
> wrote:
> >
> > On 11/12/2020 23.30, Rob Herring wrote:
> > > On Fri, Dec 11, 2020 at 3:56 PM Rasmus Villemoes
> > > wrote:
> > >>
> > >> Some RTCs, e.g. the pcf2127, can be used as a
Document "clocks" sub-node which describes Tegra SoC clocks that require
a higher voltage of the core power domain in order to operate properly on
a higher rates.
Signed-off-by: Dmitry Osipenko
---
.../bindings/clock/nvidia,tegra20-car.txt | 26 +++
> Quoting stef...@marvell.com (2020-12-17 18:45:06)
> > From: Stefan Chulski
> >
> > Issue:
> > Flow control frame used to pause GoP(MAC) was delivered to the CPU and
> > created a load on the CPU. Since XOFF/XON frames are used only by MAC,
> > these frames should be dropped inside MAC.
> >
> >
This patch series fix coverity warnings for xilinx_dma driver.
No functional change. These patches are picked from xilinx
linux tree and posted for upstream.
Shravya Kumbham (3):
dmaengine: xilinx_dma: check dma_async_device_register return value
dmaengine: xilinx_dma: fix incompatible param
Add dev_pm_opp_get_required_pstate() which allows OPP users to retrieve
required performance state of a given OPP.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 22 ++
include/linux/pm_opp.h | 10 ++
2 files changed, 32 insertions(+)
diff --git
On 12/17/20 9:37 AM, Lakshmi Ramasubramanian wrote:
On kexec file load Integrity Measurement Architecture (IMA) subsystem
may verify the IMA signature of the kernel and initramfs, and measure
it. The command line parameters passed to the kernel in the kexec call
may also be measured by IMA. A
From: Shravya Kumbham
dma_async_device_register() can return non-zero error code. Add
condition to check the return value of dma_async_device_register
function and handle the error path.
Addresses-Coverity: Event check_return.
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
Add dev_pm_opp_set_voltage() which allows OPP table users to set voltage
in accordance to a given OPP. In particular this is needed for driving
voltage of a generic power domain which uses OPPs and doesn't have a
clock.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 52
Document new DVFS OPP table and power domain properties of the video
decoder engine.
Signed-off-by: Dmitry Osipenko
---
.../devicetree/bindings/media/nvidia,tegra-vde.txt | 12
1 file changed, 12 insertions(+)
diff --git
Add a ceil version of the dev_pm_opp_find_level(). It's handy to have if
levels don't start from 0 in OPP table and zero usually means a minimal
level.
Signed-off-by: Dmitry Osipenko
---
drivers/opp/core.c | 49 ++
include/linux/pm_opp.h | 8 +++
All NVIDIA Tegra SoCs have a core power domain where majority of hardware
blocks reside. Add binding for the core power domain.
Signed-off-by: Dmitry Osipenko
---
.../arm/tegra/nvidia,tegra20-core-domain.yaml | 48 +++
1 file changed, 48 insertions(+)
create mode 100644
From: Shravya Kumbham
Typecast the fls(width -1) with (enum dmaengine_alignment) in
xilinx_dma_chan_probe function to fix the coverity warning.
Addresses-Coverity: Event mixed_enum_type.
Signed-off-by: Shravya Kumbham
Signed-off-by: Radhey Shyam Pandey
---
drivers/dma/xilinx/xilinx_dma.c | 3
From: Shravya Kumbham
In xilinx_dma_child_probe function, the nr_channels variable is
passed to of_property_read_u32() which expects an u32 return value
pointer. Modify the nr_channels variable type from int to u32 to
fix the incompatible parameter coverity warning.
Addresses-Coverity: Event
On Mon, 14 Dec 2020 17:29:06 -0800 Ivan Babrou wrote:
> Without this change the driver tries to allocate too many queues,
> breaching the number of available msi-x interrupts on machines
> with many logical cpus and default adapter settings:
>
> Insufficient resources for 12 XDP event queues (24
On Thu, 2020-12-17 at 18:42 +0100, Helge Deller wrote:
> On 12/17/20 6:27 PM, Joe Perches wrote:
> > On Thu, 2020-12-17 at 18:11 +0100, Helge Deller wrote:
> > > In most cases people use lookup_symbol_name() to resolve a kernel symbol
> > > and then print it via printk().
> > >
> > > In such
On Thu, Dec 17, 2020 at 12:28 PM Guenter Roeck wrote:
>
> On Wed, Oct 14, 2020 at 12:53:08AM +, Kalesh Singh wrote:
> > Android needs to move large memory regions for garbage collection.
> > The GC requires moving physical pages of multi-gigabyte heap
> > using mremap. During this move, the
On Thu, Dec 17, 2020 at 1:07 PM Clemens Gruber
wrote:
>
> As always, great review! Thank you!
>
My pleasure, it's great to help out.
And thanks, you're the one doing all the hard work :)
On 2020-12-17 08:12, Alex Elder wrote:
On 12/15/20 4:55 PM, Bjorn Andersson wrote:
On Sat 12 Dec 14:48 CST 2020, Rishabh Bhatnagar wrote:
Create an unbound high priority workqueue for recovery tasks.
I have been looking at a different issue that is caused by
crash notification.
What
On 12/17/20 8:06 PM, Dmitry Osipenko wrote:
Add suspend/resume and generic power domain support to the Host1x driver.
This is required for enabling system-wide DVFS and supporting dynamic
power management using a generic power domain.
Tested-by: Peter Geis
Tested-by: Nicolas Chauvet
On Thu, Dec 17, 2020 at 2:54 AM Kirill A. Shutemov wrote:
>
> Also if the range doesn't have a mappable page we would setup a page
> table into the PMD entry. It means we cannot have huge page mapped there
> later. It may be a bummer: getting the page table out of page table tree
> requires
On 17/12/2020 19.12, Uwe Kleine-König wrote:
> On Thu, Dec 17, 2020 at 10:51:08AM -0600, Rob Herring wrote:
>> On Fri, Dec 11, 2020 at 5:10 PM Rasmus Villemoes
>> wrote:
>> I'm wondering how you solve which wdog to ping when there are multiple
>> without relying on numbering. I guess
> -Original Message-
> From: Denis Kirjanov
> Sent: Tuesday, November 17, 2020 6:43 PM
> To: Radhey Shyam Pandey
> Cc: da...@davemloft.net; net...@vger.kernel.org; k...@kernel.org;
> Michal Simek ; mchehab+sams...@kernel.org;
> gre...@linuxfoundation.org; nicolas.fe...@microchip.com;
On Thu, 2020-12-17 at 09:27 -0800, Linus Torvalds wrote:
> On Thu, Dec 17, 2020 at 8:25 AM Josh Poimboeuf wrote:
> >
> > Oh yeah, I forgot about that. That would be another option if my patch
> > doesn't work out.
>
> Well, one option is to just say "ok, we know gcc generates horrible
> code
On 16/12/2020 08:21, Jürgen Groß wrote:
> On 15.12.20 21:59, Andrew Cooper wrote:
>> On 15/12/2020 11:10, Juergen Gross wrote:
>>> In case a process waits for any Xenstore action in the xenbus driver
>>> it should be interruptible by signals.
>>>
>>> Signed-off-by: Juergen Gross
>>> ---
>>> V2:
On Tue, Dec 01, 2020 at 04:13:01PM +0100, Richard Weinberger wrote:
> As soon the first file is opened, ext4 samples the mountpoint
> of the filesystem in 64 bytes of the super block.
> It does so using strlcpy(), this means that the remaining bytes
> in the super block string buffer are
On 17/12/2020 19:06, Dmitry Osipenko wrote:
> Enable CPU voltage scaling and thermal throttling on Tegra20 Ventana board.
>
> Signed-off-by: Dmitry Osipenko
> ---
> arch/arm/boot/dts/tegra20-ventana.dts | 40 ++-
> 1 file changed, 39 insertions(+), 1 deletion(-)
>
>
On 17/12/2020 19:06, Dmitry Osipenko wrote:
> Enable CPU voltage scaling and thermal throttling on Tegra30 Cardhu board.
>
> Signed-off-by: Dmitry Osipenko
> ---
Same comments as 47/48
> arch/arm/boot/dts/tegra30-cardhu.dtsi | 61 ++-
> 1 file changed, 60
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