On Tue, Dec 15, 2020 at 07:28:10PM +0200, Andy Shevchenko wrote:
> On Tue, Dec 15, 2020 at 6:44 PM Calvin Johnson
> wrote:
> >
> > Extract phy_id from compatible string. This will be used by
> > fwnode_mdiobus_register_phy() to create phy device using the
> > phy_id.
>
> ...
>
> > + if
On Wed, Dec 16, 2020 at 5:16 PM Paul E. McKenney wrote:
>
> On Wed, Dec 16, 2020 at 10:52:06AM +0100, Daniel Vetter wrote:
> > On Wed, Dec 16, 2020 at 2:14 AM syzbot
> > wrote:
> > >
> > > Hello,
> > >
> > > syzbot found the following issue on:
> > >
> > > HEAD commit:94801e5c Merge tag
On 17/12/20 00:48, Sean Christopherson wrote:
c) refactor SEV-ES handling as part of this series. it's only a small change
to the SEV-ES code but it re-orders enough things around that I'm
concerned it might invalidate some of the internal testing we've done.
whereas a follow-up
On 17.12.20 09:17, Johannes Berg wrote:
> From: Johannes Berg
>
> If we store the relative path, the user might later cd to a
> different directory, and that would break the automatic symbol
> resolving that happens when a module is loaded into the target
> kernel. Fix this by storing the
On Wed, Dec 16, 2020 at 10:51 PM Palmer Dabbelt wrote:
>
> On Tue, 15 Dec 2020 22:02:54 PST (-0800), Palmer Dabbelt wrote:
> > On Wed, 04 Nov 2020 16:04:37 PST (-0800), Atish Patra wrote:
> >> In order to improve kernel text protection, we need separate .init.text/
> >> .init.data/.text in
On Wed, Dec 16, 2020 at 9:44 PM Oscar Salvador wrote:
>
> On Sun, Dec 13, 2020 at 11:45:32PM +0800, Muchun Song wrote:
> > All the infrastructure is ready, so we introduce nr_free_vmemmap_pages
> > field in the hstate to indicate how many vmemmap pages associated with
> > a HugeTLB page that we
Start all helpers with "MFD_CELL_".
Cc: Linus Walleij
Cc: Matthias Brugger
Cc: Gene Chen
Cc: linux-media...@lists.infradead.org
Signed-off-by: Lee Jones
---
drivers/mfd/ab8500-core.c | 42 +++---
drivers/mfd/db8500-prcmu.c | 6 +++---
ad539bf2480e78b
> commit: 518b466a21ad7fa1e338fa4ed9d180ef439d3bc0 pinctrl: ralink: add a
> pinctrl driver for the rt2880 family
> date: 9 days ago
> config: mips-randconfig-r025-20201217 (attached as .config)
> compiler: mipsel-linux-gcc (GCC) 9.3.0
> reproduce (this is a W=1 build):
> wget
From: zhuling
Signed-off-by: zhuling
---
samples/bpf/tracex5_user.c | 2 +-
samples/seccomp/dropper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/samples/bpf/tracex5_user.c b/samples/bpf/tracex5_user.c
index c17d3fb..417753f 100644
--- a/samples/bpf/tracex5_user.c
On 12/15/20 7:23 AM, Alex Deucher wrote:
On Mon, Dec 14, 2020 at 7:24 PM Jiaying Liang wrote:
On 12/11/20 11:39 AM, Daniel Vetter wrote:
Hi all
On Fri, Dec 11, 2020 at 8:03 PM Alex Deucher wrote:
On Mon, Nov 30, 2020 at 3:25 AM Wendy Liang wrote:
AI engine is the acceleration engine
Quoting Weiyi Lu (2020-11-13 00:29:52)
> mtk_clk_register_mux() should be a static function
>
> Fixes: a3ae549917f16 ("clk: mediatek: Add new clkmux register API")
> Signed-off-by: Weiyi Lu
> ---
Applied to clk-next
On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
>
> Hi Atish,
>
> On Thu, Dec 17, 2020 at 3:49 PM Atish Patra wrote:
> >
> > memblock_enforce_memory_limit accepts the maximum memory size not the last
> > address. Fix the function invocation correctly.
> >
> > Fixes: 1bd14a66ee52 ("RISC-V:
Hi Peng,
sorry for the inconvenience, this is most probably related to these changes:
https://lore.kernel.org/linux-arm-kernel/20201119175400.9995-1-nsaenzjulie...@suse.de/
On Thu, 2020-12-17 at 16:08 +0800, Peng Fan (OSS) wrote:
> From: Peng Fan
>
> ZONE_DMA should not be disabled, otherwise
Hi Atish,
On Thu, Dec 17, 2020 at 4:43 PM Atish Patra wrote:
>
> On Thu, Dec 17, 2020 at 12:12 AM Bin Meng wrote:
> >
> > Hi Atish,
> >
> > On Thu, Dec 17, 2020 at 3:49 PM Atish Patra wrote:
> > >
> > > memblock_enforce_memory_limit accepts the maximum memory size not the last
> > > address.
Hello,
syzbot found the following issue on:
HEAD commit:26aed0ea Add linux-next specific files for 20201216
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=16c492cb50
kernel config: https://syzkaller.appspot.com/x/.config?x=5c81cc44aa25b5b3
dashboard
On Thu, Dec 17, 2020 at 12:46 PM Ian Kent wrote:
>
> On Tue, 2020-12-15 at 20:59 +0800, Ian Kent wrote:
> > On Tue, 2020-12-15 at 16:33 +0800, Fox Chen wrote:
> > > On Mon, Dec 14, 2020 at 9:30 PM Ian Kent wrote:
> > > > On Mon, 2020-12-14 at 14:14 +0800, Fox Chen wrote:
> > > > > On Sun, Dec
Quoting Ikjoon Jang (2020-11-22 20:02:37)
> On Mon, Nov 09, 2020 at 10:03:48AM +0800, Weiyi Lu wrote:
> > Add clock controller nodes for SoC mt8192
> >
> > Signed-off-by: Weiyi Lu
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 163
> > +++
> > 1 file
Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> Adds device tree binding documentation for clocks in the
> MT7621 SOC.
>
> Signed-off-by: Sergio Paracuellos
> ---
> .../bindings/clock/mediatek,mt7621-clk.yaml | 67 +++
> 1 file changed, 67 insertions(+)
> create mode
The creation path of the NBD device respects max_part and only scans for
partitions if max_part is not 0. However, some other code paths ignore
max_part, and unconditionally scan for partitions. Add a check for
max_part on each partition scan.
Signed-off-by: Josh Triplett
---
Caught this when
syzbot has found a reproducer for the following issue on:
HEAD commit:5e60366d Merge tag 'fallthrough-fixes-clang-5.11-rc1' of g..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=17842c1350
kernel config:
On 2020/12/17 下午3:58, Michael S. Tsirkin wrote:
On Thu, Dec 17, 2020 at 11:30:18AM +0800, Jason Wang wrote:
On 2020/12/16 下午5:47, Michael S. Tsirkin wrote:
On Wed, Dec 16, 2020 at 02:47:57PM +0800, Jason Wang wrote:
Hi All:
This series tries to add the support for control virtqueue in
On Thu, Dec 10, 2020 at 9:07 AM Yongqiang Niu
wrote:
>
> This patch add support for mediatek SOC MT8183
> 1. add ovl private data
> 2. add rdma private data
> 3. add mutes private data
> 4. add main and external path module for crtc create
>
> Signed-off-by: Yongqiang Niu
> ---
>
On Thu, Dec 17, 2020 at 2:54 PM Muchun Song wrote:
>
> On Thu, Dec 17, 2020 at 6:52 AM Mike Kravetz wrote:
> >
> > On 12/16/20 2:25 PM, Oscar Salvador wrote:
> > > On Wed, Dec 16, 2020 at 02:08:30PM -0800, Mike Kravetz wrote:
> > >>> + * vmemmap_rmap_walk - walk vmemmap page table
> > >>> +
> >
On Wed, Dec 16, 2020 at 10:53 PM Quentin Monnet wrote:
>
> 2020-11-21 17:48 UTC+0800 ~ David Gow
> > On Sat, Nov 21, 2020 at 3:38 PM Andrii Nakryiko
> > wrote:
> >>
> >> On Thu, Nov 19, 2020 at 12:51 AM David Gow wrote:
> >>>
> >>> If BPF_PRELOAD is enabled, and an out-of-tree build is
Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> The documentation for this SOC only talks about two
> registers regarding to the clocks:
> * SYSC_REG_CPLL_CLKCFG0 - provides some information about
> boostrapped refclock. PLL and dividers used for CPU and some
> sort of BUS.
> *
Greg claims this bug:
https://syzkaller.appspot.com/bug?extid=e0c166ed4b16ffd653e0
was fixed by the following commit, so let's close it.
#syz fix: tun: correct header offsets in napi frags mode
On 12/16/20 10:23 AM, Matthew Wilcox (Oracle) wrote:
Implement readahead_batch_length() to determine the number of bytes in
the current batch of readahead pages and use it in btrfs.
Signed-off-by: Matthew Wilcox (Oracle)
---
fs/btrfs/extent_io.c| 6 ++
include/linux/pagemap.h | 9
Quoting Weiyi Lu (2020-11-08 18:13:15)
> This series is based on v5.10-rc1 and
> [v5,07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control[1]
> in Mediatek MT8192 clock support series
>
> [1]
>
This patch dupdates the DPDMAI interfaces to support MC firmware to
10.1x.x.
Signed-off-by: Guanhua Gao
---
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.c | 37 ++-
drivers/dma/fsl-dpaa2-qdma/dpaa2-qdma.h | 5 +-
drivers/dma/fsl-dpaa2-qdma/dpdmai.c | 174 ++--
In case of long format of qDMA command descriptor, there are one frame
descriptor, three entries in the frame list and two data entries. So the
size of dma_pool_create for these three fields should be the same with
the total size of entries respectively, or the contents may be overwritten
by the
Quoting Weiyi Lu (2020-11-08 18:03:25)
> This series is based on v5.10-rc1 and MT8192 dts v6[1].
>
> [1]
> https://patchwork.kernel.org/project/linux-mediatek/patch/20201030092207.26488-2-seiya.w...@mediatek.com/
This series doesn't apply for me to clk tree. Please resend. Also,
please remove
v1->v2:
1.Add Paul Cercueil's Reviewed-by for [1/5] & [2/5],
add Rob Herring's Acked-by for [2/5].
2.Add MACPHY and I2S for X1000, add MACPHY for X1830,
and fix bugs in MAC clock.
3.Clean up code, remove unnecessary -1 and commas and
tabs from all the -cgu.c files.
v2->v3:
Correct the
Add CIM, AIC, DMIC, I2S clocks for the X1000 SoC and the
X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
---
Notes:
v1->v2:
Add I2S clock for X1000.
v2->v3:
Correct the comment in x1000-cgu.c, change it from
"Custom (SoC-specific) OTG PHY" to "Custom
Add MACPHY, CIM, AIC, DMIC, I2S clocks bindings for the X1000 SoC
and the X1830 SoC from Ingenic.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
Acked-by: Rob Herring
---
Notes:
v1->v2:
1.Add MACPHY and I2S for X1000, and add MACPHY for X1830.
2.Add Paul Cercueil's
1.When the clock does not have "CGU_CLK_MUX", the 2/3/4 bits in
parents do not need to be filled with -1. When the clock have
a "CGU_CLK_MUX" has only one bit, the 3/4 bits of parents do
not need to be filled with -1. Clean up these unnecessary -1
from all the -cgu.c files.
2.Reformat
Hi Rafael,
On Mon, Dec 14, 2020 at 09:23:47PM +0100, Rafael J. Wysocki wrote:
> Hi,
>
> This series addresses some enumeration ordering issues by using information
> from _DEP to defer the enumeration of devices that are likely to depend on
> operation region (OpRegion) handlers supplied by the
Add "jz4780_core1_disable()" for disable the second core of JZ4780,
prepare for later commits.
Signed-off-by: 周琰杰 (Zhou Yanjie)
Reviewed-by: Paul Cercueil
---
Notes:
v1->v2:
Add Paul Cercueil's Reviewed-by.
v2->v3:
No change.
drivers/clk/ingenic/jz4780-cgu.c | 21
X1000 and X1830 have two MAC related clocks, one is MACPHY, which is
controlled by MACCDR register, the other is MAC, which is controlled
by the MAC bit in the CLKGR register (with CLK_AHB2 as the parent).
The original driver mistakenly mixed the two clocks together.
Signed-off-by: 周琰杰 (Zhou
From: zhuling
bpf/seccomp: modify hardcode 2 to SECCOMP_MODE_FILTER
while the hardcode 2 has been define in seccomp_bpf.c, we should use
the definitions(SECCOMP_MODE_FILTER) instead of hardcode 2.
Signed-off-by: zhuling
---
samples/bpf/tracex5_user.c | 2 +-
samples/seccomp/dropper.c
This is a major cleanup of the paravirt infrastructure aiming at
eliminating all custom code patching via paravirt patching.
This is achieved by using ALTERNATIVE instead, leading to the ability
to give objtool access to the patched in instructions.
In order to remove most of the 32-bit special
SWAPGS is used only for interrupts coming from user mode or for
returning to user mode. So there is no reason to use the PARAVIRT
framework, as it can easily be replaced by an ALTERNATIVE depending
on X86_FEATURE_XENPV.
There are several instances using the PV-aware SWAPGS macro in paths
which
Xen PV guests don't use IST. For double fault interrupts switch to
the same model as NMI.
Correct a typo in a comment while copying it.
Signed-off-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
Reviewed-by: Thomas Gleixner
---
V2:
- fix typo (Andy Lutomirski)
---
Xen PV guests don't use IST. For machine check interrupts switch to
the same model as debug interrupts.
Signed-off-by: Juergen Gross
Acked-by: Peter Zijlstra (Intel)
Reviewed-by: Thomas Gleixner
---
arch/x86/include/asm/idtentry.h | 3 +++
arch/x86/xen/enlighten_pv.c | 16
Instead of using paravirt patching for custom code sequences add
support for using ALTERNATIVE handling combined with paravirt call
patching.
Signed-off-by: Juergen Gross
---
V3:
- drop PVOP_ALT_VCALL() macro
---
arch/x86/include/asm/paravirt_types.h | 49 +++
1 file
Instead of only supporting to modify instructions when a specific
feature is set, support doing so for the case a feature is not set.
As today a feature is specified using a 16 bit quantity and the highest
feature number in use is around 600, using a negated feature number for
specifying the
The central pvops call macros PVOP_CALL() and PVOP_VCALL() are
looking very similar now.
The main differences are using PVOP_VCALL_ARGS or PVOP_CALL_ARGS, which
are identical, and the return value handling.
So drop PVOP_VCALL_ARGS and instead of PVOP_VCALL() just use
There is no need any longer to have different paravirt patch functions
for native and Xen. Eliminate native_patch() and rename
paravirt_patch_default() to paravirt_patch().
Signed-off-by: Juergen Gross
---
V3:
- remove paravirt_patch_insns() (kernel test robot)
---
From: Peter Zijlstra
Alternatives pose an interesting problem for unwinders because from
the unwinders PoV we're just executing instructions, it has no idea
the text is modified, nor any way of retrieving what with.
Therefore the stance has been that alternatives must not change stack
state, as
For being able to switch paravirt patching from special cased custom
code sequences to ALTERNATIVE handling some X86_FEATURE_* are needed
as new features. This enables to have the standard indirect pv call
as the default code and to patch that with the non-Xen custom code
sequence via ALTERNATIVE
USERGS_SYSRET64 is used to return from a syscall via sysret, but
a Xen PV guest will nevertheless use the iret hypercall, as there
is no sysret PV hypercall defined.
So instead of testing all the prerequisites for doing a sysret and
then mangling the stack for Xen PV again for doing an iret just
The time pvops functions are the only ones left which might be
used in 32-bit mode and which return a 64-bit value.
Switch them to use the static_call() mechanism instead of pvops, as
this allows quite some simplification of the pvops implementation.
Due to include hell this requires to split
"popf" is a rather expensive operation, so don't use it for restoring
irq flags. Instead test whether interrupts are enabled in the flags
parameter and enable interrupts via "sti" in that case.
This results in the restore_fl paravirt op to be no longer needed.
Suggested-by: Andy Lutomirski
Instead of using paravirt patching for custom code sequences use
ALTERNATIVE for the functions with custom code replacements.
Instead of patching an ud2 instruction for unpopulated vector entries
into the caller site, use a simple function just calling BUG() as a
replacement.
Signed-off-by:
PVOP_VCALL4() is only used for Xen PV, while PVOP_CALL4() isn't used
at all. Keep PVOP_CALL4() for 64 bits due to symmetry reasons.
This allows to remove the 32-bit definitions of those macros leading
to a substantial simplification of the paravirt macros, as those were
the only ones needing
The iret paravirt op is rather special as it is using a jmp instead
of a call instruction. Switch it to ALTERNATIVE.
Signed-off-by: Juergen Gross
---
V3:
- use ALTERNATIVE_TERNARY
---
arch/x86/include/asm/paravirt.h | 6 +++---
arch/x86/include/asm/paravirt_types.h | 5 +
On Thu, 17 Dec 2020 17:15:47 +0100,
Robin Gong wrote:
>
> Since mmap for userspace is based on page alignment, add page alignment
> for iram alloc from pool, otherwise, some good data located in the same
> page of dmab->area maybe touched wrongly by userspace like pulseaudio.
>
> Signed-off-by:
On Wed, 2020-12-16 at 08:53 +, Lee Jones wrote:
> On Fri, 04 Dec 2020, Matti Vaittinen wrote:
>
> > Add BD71827 driver header. For a record - Header is originally
> > based on work authored by Cong Pham although not much of original
> > work is left now.
> >
> > Signed-off-by: Matti
On Thu, Dec 17, 2020 at 3:28 AM Stephen Rothwell wrote:
>
> Hi all,
>
> On Mon, 14 Dec 2020 20:21:07 +1100 Stephen Rothwell
> wrote:
> >
> > Today's linux-next merge of the akpm-current tree got a conflict in:
> >
> > lib/Makefile
> >
> > between commit:
> >
> > 527701eda5f1 ("lib: Add a
> -Original Message-
> From: Jakub Kicinski
> Sent: Thursday, December 17, 2020 2:42 AM
> To: Stefan Chulski
> Cc: net...@vger.kernel.org; thomas.petazz...@bootlin.com;
> da...@davemloft.net; Nadav Haklai ; Yan Markman
> ; linux-kernel@vger.kernel.org;
> li...@armlinux.org.uk;
From: Stefan Chulski
During GoP port 2 Networking Complex Control mode of operation configurations,
also GoP port 3 mode of operation was wrongly set.
Patch removes these configurations.
GENCONF_CTRL0_PORTX naming also fixed.
Fixes: f84bf386f395 ("net: mvpp2: initialize the GoP")
Signed-off-by:
From: Stefan Chulski
Force link UP can be enabled by bootloader during tftpboot
and breaks NFS support.
Force link UP disabled during port init procedure.
Signed-off-by: Stefan Chulski
---
drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 14 +-
1 file changed, 13 insertions(+), 1
On Wed, 16 Dec 2020 19:29:09 +0100,
Amadej Kastelic wrote:
>
> On Wed, Dec 16, 2020 at 04:38:07PM +0100, Takashi Iwai wrote:
> > On Tue, 15 Dec 2020 19:09:05 +0100,
> > Amadej Kastelic wrote:
> > >
> > > Message-Id:
> > >
> > > Add VID to support native DSD reproduction on FiiO devices.
> > >
On 12/17/20 5:15 PM, Robin Gong wrote:
Since mmap for userspace is based on page alignment, add page alignment
for iram alloc from pool, otherwise, some good data located in the same
page of dmab->area maybe touched wrongly by userspace like pulseaudio.
I wonder, do we also have to align size
Quoting Dmitry Osipenko (2020-11-15 12:34:32)
> Add "hardware enable" column to the clk summary in order to show actual
> hardware enable-state of all clocks. The possible states are "Y/N/?",
> where question mark means that state is unknown, i.e. clock isn't a
> mux and clk-driver doesn't support
This series implements Runtime PM support for the Tegra ChipIdea USB driver.
It also squashes the older ehci-tegra driver into the ChipIdea driver, hence
the RPM is supported by both UDC and host controllers, secondly this opens
opportunity for implementing OTG support in the future.
Patchset was
The OF core adds an alias based on the OF device ID table, which is enough
to have the driver autoloaded. The legacy MODULE_ALIAS macro was relevant
to a pre-OF board files which manually created platform devices, this is
irrelevant to the modern ARM kernels since devices are created by the OF
The ehci-tegra driver was superseded by the generic ChipIdea USB driver,
update the tegra's defconfig accordingly.
Signed-off-by: Dmitry Osipenko
---
arch/arm/configs/tegra_defconfig | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/configs/tegra_defconfig
The PHY hardware needs the delay of 2ms after power up, otherwise initial
interrupt may be lost if USB controller is accessed before PHY is settled
down. Previously this issue was masked by implicit delays, but now it pops
up after squashing the older ehci-tegra driver into the ChipIdea driver.
On Thu, Dec 17, 2020 at 10:28 AM Calvin Johnson
wrote:
> On Tue, Dec 15, 2020 at 07:28:10PM +0200, Andy Shevchenko wrote:
> > On Tue, Dec 15, 2020 at 6:44 PM Calvin Johnson
> > wrote:
...
> > > + if (sscanf(cp, "ethernet-phy-id%4x.%4x", , ) == 2) {
> >*phy_id = ((upper & 0x)
Support programming of waking up from a low power mode by implementing the
generic set_wakeup() callback of the USB PHY API.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Peter Geis
Tested-by: Ion Agorria
Signed-off-by: Dmitry Osipenko
---
drivers/usb/phy/phy-tegra-usb.c |
Rename all occurrences in the code from "udc" to "usb" and change the
Kconfig entry in order to show that this driver supports USB modes other
than device-only mode. The follow up patch will add host-mode support and
it will be cleaner to perform the renaming separately, i.e. in this patch.
From: Peter Geis
Add USB host mode to the Tegra HDRC driver. This allows us to benefit from
support provided by the generic ChipIdea driver instead of duplicating the
effort in a separate ehci-tegra driver.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Ion Agorria
The ChipIdea driver now provides USB2 host mode support for NVIDIA Tegra
SoCs. The ehci-tegra driver is obsolete now, remove it and redirect the
older Kconfig entry to the CI driver.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Peter Geis
Tested-by: Ion Agorria
Signed-off-by:
Hi Alex,
On 12/2/20 7:34 AM, Alexandre Courbot wrote:
> DRC events can happen virtually at anytime, including when we are
> starting a seek. Should this happen, we must make sure to return to the
> DRC state, otherwise the firmware will expect buffers of the new
> resolution whereas userspace
Tegra PHY driver now supports waking up controller from a low power mode.
Enable runtime PM in order to put controller into the LPM during idle.
Tested-by: Matt Merhar
Tested-by: Nicolas Chauvet
Tested-by: Peter Geis
Tested-by: Ion Agorria
Signed-off-by: Dmitry Osipenko
---
Quoting Zheng Yongjun (2020-12-16 05:05:34)
> The parameter of kfree function is NULL, so kfree code is useless, delete it.
Not always though. Sometimes it is non-NULL and this code avoids a goto.
>
> Signed-off-by: Zheng Yongjun
> ---
> drivers/clk/ti/fapll.c | 1 -
> 1 file changed, 1
On 16/12/20 10:16 pm, Bean Huo wrote:
> On Wed, 2020-12-16 at 20:51 +0200, Adrian Hunter wrote:
>> ufshcd_variant_hba_exit(hba);
>> ufshcd_setup_vreg(hba, false);
>> ufshcd_suspend_clkscaling(hba);
>> @@ -9436,6 +9441,20 @@ int ufshcd_init(struct
Quoting Alexandru Ardelean (2020-12-02 23:40:36)
> Up until the these limits were global/hard-coded, since they are typically
> limits of the fabric.
>
> However, since this is an FPGA generated clock, this may run on setups
> where one clock is on a fabric, and another one synthesized on another
Quoting Alexandru Ardelean (2020-10-13 07:34:20)
> This change converts the old binding for the AXI clkgen driver to a yaml
> format.
>
> As maintainers, added:
> - Lars-Peter Clausen - as original author of driver &
>binding
> - Michael Hennerich - as supporter of
>Analog Devices
Quoting Alexandru Ardelean (2020-12-02 23:40:37)
> The change is mostly cosmetic. No functional changes.
> Since the driver now uses of_device_get_match_data() to obtain some driver
> specific info, there is no need to define the OF table before the probe
> function.
>
> Signed-off-by: Alexandru
Hi Stephen,
Thanks for the review.
On Thu, Dec 17, 2020 at 10:09 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:53)
> > The documentation for this SOC only talks about two
> > registers regarding to the clocks:
> > * SYSC_REG_CPLL_CLKCFG0 - provides some information
Le 17/12/2020 à 07:11, Alexei Starovoitov a écrit :
On Wed, Dec 16, 2020 at 10:07:37AM +, Christophe Leroy wrote:
Implement Extended Berkeley Packet Filter on Powerpc 32
Test result with test_bpf module:
test_bpf: Summary: 378 PASSED, 0 FAILED, [354/366 JIT'ed]
nice!
On Thu, 17 Dec 2020 10:43:45 +0100,
Lars-Peter Clausen wrote:
>
> On 12/17/20 5:15 PM, Robin Gong wrote:
> > Since mmap for userspace is based on page alignment, add page alignment
> > for iram alloc from pool, otherwise, some good data located in the same
> > page of dmab->area maybe touched
On Thu 17-12-20 00:49:35, Al Viro wrote:
> [Christoph added to Cc...]
> On Wed, Dec 16, 2020 at 06:31:47PM -0500, Vivek Goyal wrote:
> > Current implementation of __sync_filesystem() ignores the return code
> > from ->sync_fs(). I am not sure why that's the case. There must have
> > been some
On Mon, Dec 14, 2020 at 9:41 PM Uwe Kleine-König
wrote:
> Technically there are still some maintainers' ack missing but I'd really
> like to get this series applied. As I don't want to make people angry
> I'm asking once more for your Acks.
Acked-by: Linus Walleij
Sorry for taking so long,
Hi Stephen,
Thanks for the review!
On Thu, Dec 17, 2020 at 9:58 AM Stephen Boyd wrote:
>
> Quoting Sergio Paracuellos (2020-11-22 01:55:52)
> > Adds device tree binding documentation for clocks in the
> > MT7621 SOC.
> >
> > Signed-off-by: Sergio Paracuellos
> > ---
> >
On Wed, Dec 16, 2020 at 5:16 PM Paul E. McKenney wrote:
>
> On Wed, Dec 16, 2020 at 10:52:06AM +0100, Daniel Vetter wrote:
> > On Wed, Dec 16, 2020 at 2:14 AM syzbot
> > wrote:
> > >
> > > Hello,
> > >
> > > syzbot found the following issue on:
> > >
> > > HEAD commit:94801e5c Merge tag
Hi deee Ho Lee,
On Wed, 2020-12-02 at 15:32 +0200, Matti Vaittinen wrote:
> Hello Lee,
>
> On Wed, 2020-12-02 at 12:57 +, Lee Jones wrote:
> > On Fri, 27 Nov 2020, Vaittinen, Matti wrote:
> >
> > > Hello Lee,
> > >
> > > On Fri, 2020-11-27 at 08:32 +, Lee Jones wrote:
> > > > On Mon,
Hi Andy,
On Thu, 17 Dec 2020 11:40:51 +0200 Andy Shevchenko
wrote:
>
> Yeah, and it's slightly different. Perhaps RISC-V tree can handle this
> by moving Makefile entry somewhere else in the file.
Or just let Linus take care of it ...
--
Cheers,
Stephen Rothwell
pgprUxnfVtQtO.pgp
On Thu, Dec 17, 2020 at 9:40 AM Jiaying Liang wrote:
>
>
> On 12/15/20 7:23 AM, Alex Deucher wrote:
> > On Mon, Dec 14, 2020 at 7:24 PM Jiaying Liang
> > wrote:
> >> On 12/11/20 11:39 AM, Daniel Vetter wrote:
> >>> Hi all
> >>>
> >>> On Fri, Dec 11, 2020 at 8:03 PM Alex Deucher
> >>> wrote:
On 16.12.20 21:42, Liam R. Howlett wrote:
>
> Thank you for looking at this. I appreciate the scrutiny.
>
> * David Hildenbrand [201216 09:58]:
>> On 15.12.20 16:54, Liam R. Howlett wrote:
>>> do_mmap() will unlock the necessary VMAs. There is also a bug in the
>>> loop which will evaluate as
Hi,
This series adds some DRM bridge drivers support for i.MX8qm/qxp SoCs.
The bridges may chain one by one to form display pipes to support
LVDS displays. The relevant display controller is DPU embedded in
i.MX8qm/qxp SoCs.
The DPU KMS driver can be found at:
This patch adds RGB666_1X30_CPADLO, RGB888_1X30_CPADLO, RGB666_1X36_CPADLO
and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp pixel combiner.
The RGB pixels with padding low per component are transmitted on a 30-bit
input bus(10-bit per component) from a display controller or a 36-bit
output
This patch allows LVDS PHYs to be configured through
the generic functions and through a custom structure
added to the generic union.
The parameters added here are based on common LVDS PHY
implementation practices. The set of parameters
should cover all potential users.
Cc: Kishon Vijay Abraham
This patch adds bindings for i.MX8qm/qxp pixel combiner.
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pixel-combiner.yaml | 160 +
1 file changed, 160 insertions(+)
create mode 100644
This patch adds a drm bridge driver for i.MX8qm/qxp pixel combiner.
The pixel combiner takes two output streams from a single display
controller and manipulates the two streams to support a number
of modes(bypass, pixel combine, YUV444 to YUV422, split_RGB) configured
as either one screen, two
This patch adds documentations for RGB666_1X30_CPADLO, RGB888_1X30_CPADLO,
RGB666_1X36_CPADLO and RGB888_1X36_CPADLO bus formats used by i.MX8qm/qxp
pixel combiner. The RGB pixels with padding low per component are
transmitted on a 30-bit input bus(10-bit per component) from a display
controller
This patch adds bindings for i.MX8qxp pixel link to DPI(PXL2DPI).
Signed-off-by: Liu Ying
---
.../display/bridge/fsl,imx8qxp-pxl2dpi.yaml| 134 +
1 file changed, 134 insertions(+)
create mode 100644
This patch adds a drm bridge driver for i.MX8qxp pixel link to display
pixel interface(PXL2DPI). The PXL2DPI interfaces the pixel link 36-bit
data output and the DSI controller’s MIPI-DPI 24-bit data input, and
inputs of LVDS Display Bridge(LDB) module used in LVDS mode, to remap
the pixel color
This patch adds a drm bridge driver for i.MX8qm/qxp display pixel link.
The pixel link forms a standard asynchronous linkage between
pixel sources(display controller or camera module) and pixel
consumers(imaging or displays). It consists of two distinct
functions, a pixel transfer function and a
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