Hi,
Just to clarify things:
> > Do you see any substantial benefit of having fWriteBoosterBufferFlushEn
> > disabled?
>
> 1. The definition of fWriteBoosterBufferFlushEn is that host allows
> device to do flush in anytime after fWriteBoosterBufferFlushEn is set as
> on. This is not what we want.
From: Leonid Ravich
to remove locking from nvmet_fc_find_target_queue
which called per IO.
Signed-off-by: Leonid Ravich
---
drivers/nvme/target/fc.c | 54
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/nvme/target/fc.c
From: Leonid Ravich
to remove locking from nvmet_fc_find_target_queue
which called per IO.
Signed-off-by: Leonid Ravich
---
drivers/nvme/target/fc.c | 54
1 file changed, 32 insertions(+), 22 deletions(-)
diff --git a/drivers/nvme/target/fc.c
Roja Rani Yarubandi (3):
dt-bindings: power: Introduce 'assigned-performance-states' property
arm64: dts: sc7180: Add assigned-performance-states for i2c
i2c: i2c-qcom-geni: Add support for 'assigned-performance-states'
.../bindings/power/power-domain.yaml | 49 +++
For devices which have 'assigned-performance-states' specified in DT,
set the specified performance state during probe and drop it on remove.
Also drop/set as part of runtime suspend/resume callbacks.
Signed-off-by: Roja Rani Yarubandi
---
drivers/i2c/busses/i2c-qcom-geni.c | 49
While most devices within power-domains which support performance states,
scale the performance state dynamically, some devices might want to
set a static/default performance state while the device is active.
These devices typically would also run off a fixed clock and not support
dynamically
Hello, Mandeep, Guenter et al.
I came across the out-of-tree patch [1] that apparently is still alive
after 10 years of residing in the Chromium OS tree, and I have a couple
of questions if you don't mind spending your time answering them.
1. is this knob really necessary given there's an
qup-i2c devices on sc7180 are clocked with a fixed clock (19.2 MHz).
Though qup-i2c does not support DVFS, it still needs to vote for a
performance state on 'CX' to satisfy the 19.2 MHz clock frequency
requirement.
Use 'assigned-performance-states' to pass this information from
device tree, and
There is a deadlock in bm_register_write:
First, in the beggining of the function, a lock is taken on the
binfmt_misc root inode with inode_lock(d_inode(root))
Then, if the user used the MISC_FMT_OPEN_FILE flag, the function will
call open_exec on the user-provided interpreter.
open_exec will call
Invoke wiz_init() before configuring anything else in Sierra/Torrent
(invoked as part of of_platform_device_create()). wiz_init() resets the
SERDES device and any configuration done in the probe() of
Sierra/Torrent will be lost. In order to prevent SERDES configuration
from getting reset, invoke
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
Cadence Sierra PHY driver registers PHY using devm_phy_create()
for all sub-nodes of Sierra device tree node. However Sierra device
tree node can have sub-nodes for the various clocks in addtion to the
PHY. Use devm_phy_create() only for nodes with name "phy" (or "link"
for old device tree) which
"serdes" node (child node of WIZ) can have sub-nodes for representing links
or it can have sub-nodes for representing the various clocks within the
serdes. Instead of trying to read "reg" from every child node used for
assigning "lane_phy_type", read only if the child node's name is "phy"
or
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git
Add DT nodes for clocks within Sierra SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 --
1 file changed, 120 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as
clocks so that it's possible to select one of these two inputs from
device tree.
Signed-off-by: Kishon Vijay Abraham I
---
Patch series adds support in Sierra driver to use external clock.
v1 of the patch series can be found @ [1]
v2 of the patch series can be found @ [2]
Changes from v2:
1) Add depends on COMMON_CLK in Sierra
2) Add modelling PLL_CMNLC and PLL_CMNLC1 as clocks into a separate
patch
3) Disable
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Fixes:
Sierra has two reference recievers REFRCV and REFRCV1. REFRCV is used to
drive reference clock cmn_refclk_m/p to PLL_CMNLC1 and REFRCV1 is used to
drive reference clock cmn_refclk1_m/p to PLL_CMNLC. Model these
reference receivers as clocks in order for PLL_CMNLC and PLL_CMNLC1 to
be able to
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 55
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Rename the external refclk inputs to the SERDES from
dummy_cmn_refclk/dummy_cmn_refclk1 to cmn_refclk/cmn_refclk1
respectively. Also move the external refclk DT nodes outside the
cbass_main DT node. Since in j721e common processor board, only the
cmn_refclk1 is connected to 100MHz clock, fix the
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git
Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 45 +++
1 file
Commit 66db854b1f62d ("arm64: dts: ti: k3-j721e-common-proc-board:
Configure the PCIe instances") and
commit 02c35dca2b488 ("arm64: dts: ti: k3-j721e: Enable Super-Speed
support for USB0") added PHY DT nodes with node name as "link"
However nodes with #phy-cells should be named 'phy' as discussed
Since gpiolib requires having separate irqchips for each gpiochip, we
need to add some we definetly need a separate one for F port, and we
could combine gpiochip A and B into one - but this will break namespace
and logick.
So despite 3 irqchips is a bit beefy we need a separate irqchip for each
On Wed, Dec 23, 2020 at 02:23:15PM -0800, Tim Harvey wrote:
> Add bindings for the Gateworks Venice Development kit boards with
> IMX8MM System on Module.
>
> Signed-off-by: Tim Harvey
> ---
> Documentation/devicetree/bindings/arm/fsl.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff
As ->to_irq is redefined in gpiochip_add_irqchip, having it defined in
driver is useless, so let's drop it.
Also i think it is worth to give a gentle warning in
gpiochip_add_irqchip, to prevent people relying on to_irq.
For example
WARN_ON_ONCE(gc->to_irq,
"to_irq is redefined in
I was lucky enough to became an owner of some splendid piece's of
antiques called ts7250 based on the top of Cirrus Logic EP9302.
I don't know what fate expects this hardware (it's not EOL it's just Not
recommended for new designs) but i wanted to share fixes in ep93xx gpio area.
It seems ep93xx
On Wed, 23 Dec 2020 15:32:07 +, Lee Jones wrote:
> On Wed, 23 Dec 2020, Timon Baetz wrote:
>
> > Add of_compatible ("maxim,max8997-muic") to the mfd_cell to have a
> > of_node set in the extcon driver.
> >
> > Add of_compatible ("maxim,max8997-battery") to the mfd_cell to configure
> > the
Adds bitrate control for all coding layers for h264
same as hevc.
Signed-off-by: Dikshita Agarwal
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst | 20
drivers/media/v4l2-core/v4l2-ctrls.c | 7 +++
include/uapi/linux/v4l2-controls.h
- Adds min/max qp controls for B frame for h264.
- Adds min/max qp controls for I/P/B frames for hevc similar to h264.
- Update valid range of min/max qp for hevc to accommodate 10 bit.
Signed-off-by: Dikshita Agarwal
---
.../userspace-api/media/v4l/ext-ctrls-codec.rst| 52
Add support for frame type specific min and max qp controls
for encoder.
This is a preparation patch to support v6.
Signed-off-by: Dikshita Agarwal
---
drivers/media/platform/qcom/venus/core.h | 18
drivers/media/platform/qcom/venus/venc.c | 21 +++--
On Wed, 2020-12-23 at 17:15 +0900, Tomasz Figa wrote:
> Hi Yong,
>
> On Wed, Dec 09, 2020 at 04:00:39PM +0800, Yong Wu wrote:
> > In the latest SoC, there are several HW IP require a sepecial iova
> > range, mainly CCU and VPU has this requirement. Take CCU as a example,
> > CCU require its iova
This series adds frame specific min/max qp controls for hevc and layer
wise bitrate control for h264.
Chnages since v2:
- Rebased the changes on latest media tree
- Added driver side implementation for new controls.
Dikshita Agarwal (3):
media: v4l2-ctrl: Add frame-specific min/max qp
On Wed, 2020-12-23 at 08:51 +, Christoph Hellwig wrote:
> On Wed, Dec 16, 2020 at 06:36:01PM +0800, Yong Wu wrote:
> > In the end of __iommu_map, It alway call iotlb_sync_map.
> > This patch moves iotlb_sync_map out from __iommu_map since it is
> > unnecessary to call this for each sg segment
Port F irq's should be statically mapped to EP93XX_GPIO_F_IRQ_BASE.
So we need to specify girq->first otherwise:
"If device tree is used, then first_irq will be 0 and
irqs get mapped dynamically on the fly"
And that's not the thing we want.
Signed-off-by: Nikita Shubin
---
ALARM_EN status is retained in PMIC register after device shutdown
if poweron_alarm is enabled. Read it to make sure the driver has
consistent value with the register status.
Signed-off-by: Guixiong Wei
---
drivers/rtc/rtc-pm8xxx.c | 9 +
1 file changed, 9 insertions(+)
diff --git
I realized I didn't update fscrypt_mergeable_bio() to take metadata
encryption into account, so bios will be more fragmented than required.
I'll fix it in v3.
On Wed, 2020-12-23 at 17:18 +0900, Tomasz Figa wrote:
> On Wed, Dec 09, 2020 at 04:00:41PM +0800, Yong Wu wrote:
> > This patch adds decriptions for mt8192 IOMMU and SMI.
> >
> > mt8192 also is MTK IOMMU gen2 which uses ARM Short-Descriptor translation
> > table format. The M4U-SMI HW diagram is
On Wed, Dec 23, 2020 at 02:23:16PM -0800, Tim Harvey wrote:
> The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development
> kits comprised of a GW700x SoM and a Baseboard.
>
> The GW700x SoM contains:
> - IMX8MM SoC
It's i.MX 8M Mini.
Add bindings for AM64 SERDES Wrapper.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
cmn_refclk_ lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_ can also be configured to output the
reference clock. In order to drive the refclk out from the SERDES
(Cadence Torrent), PHY_EN_REFCLK should be set in SERDES_RST of WIZ.
Model PHY_EN_REFCLK as a
Add binding for refclk driver used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-torrent.yaml | 17 +
1 file changed, 17 insertions(+)
diff --git
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 43 +++---
1 file changed, 40 insertions(+), 3
Add DT binding for phy_en_refclk used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git
cmn_refclk_ lines in Torrent SERDES is used for connecting external
reference clock. cmn_refclk_ can also be configured to output the
reference clock. Model this derived reference clock as a "clock" so that
platforms like AM642 EVM can enable it.
This is used by PCIe to use the same refclk both in
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I
---
include/dt-bindings/mux/ti-serdes.h | 4
1 file changed, 4 insertions(+)
diff --git
AM64 uses the same SERDES as in J7200, however AM642 EVM doesn't
have a clock generator (unlike J7200 base board). Here the clock from
the SERDES has to be routed to the PCIE connector. This series adds
support to drive reference clock output from SERDES and also adds
SERDES (torrent) and SERDES
On Wed, 25 Nov 2020, Sumera Priyadarsini wrote:
> The command "make coccicheck C=1 CHECK=scripts/coccicheck" results in the
> error:
> ./scripts/coccicheck: line 65: -1: shift count out of range
>
> This happens because every time the C variable is specified,
> the shell arguments need
AM64 uses the same PCIe controller as in J7200, however AM642 EVM
doesn't have a clock generator (unlike J7200 base board). Here
the clock from the SERDES has to be routed to the PCIE connector.
This series provides an option for the pci-j721e.c driver to
drive reference clock output to the
Add binding to represent refclk to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/pci/ti,j721e-pci-host.yaml | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller/cadence/pci-j721e.c
On Thu, 2020-12-24 at 11:03 +, Avri Altman wrote:
> > > Do you see any substantial benefit of having
> > > fWriteBoosterBufferFlushEn
> > > disabled?
> >
> > 1. The definition of fWriteBoosterBufferFlushEn is that host allows
> > device to do flush in anytime after fWriteBoosterBufferFlushEn
Signed-off-by: Konrad Dybcio
---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi
b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index fd6ae5464dea..e7eb2c9f37af 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++
On Wed, Dec 23, 2020 at 02:23:16PM -0800, Tim Harvey wrote:
> The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development
> kits comprised of a GW700x SoM and a Baseboard.
>
> The GW700x SoM contains:
> - IMX8MM SoC
> - LPDDR4 DRAM
> - eMMC FLASH
> - Gateworks System Controller
On Thu, Dec 24, 2020 at 3:12 AM Daniel Scally wrote:
>
> To maintain consistency with software_node_unregister_nodes(), reverse
> the order in which the software_node_unregister_node_group() function
> unregisters nodes.
...
> - * Unregister multiple software nodes at once.
> + * Unregister
24.12.2020 09:28, Viresh Kumar пишет:
> On 23-12-20, 23:36, Dmitry Osipenko wrote:
>> 23.12.2020 07:34, Viresh Kumar пишет:
>>> On 22-12-20, 22:19, Dmitry Osipenko wrote:
22.12.2020 12:12, Viresh Kumar пишет:
> rate will be 0 for both the OPPs here if rate_not_available is true and
>
24.12.2020 09:51, Viresh Kumar пишет:
> On 23-12-20, 23:37, Dmitry Osipenko wrote:
>> 23.12.2020 08:57, Viresh Kumar пишет:
>>> What's wrong with getting the regulator in the driver as well ? Apart from
>>> the
>>> OPP core ?
>>
>> The voltage syncing should be done for each consumer regulator
>>
On Thu, Dec 24, 2020 at 11:32:55AM +0200, Amir Goldstein wrote:
> In current master, syncfs() on any file by any container user will
> result in full syncfs() of the upperfs, which is very bad for container
> isolation. This has been partly fixed by Chengguang Xu [1] and I expect
> his work will
24.12.2020 07:10, Viresh Kumar пишет:
> On 23-12-20, 23:38, Dmitry Osipenko wrote:
>> Well, there is no "same structure", the opp_table->set_opp_data is NULL
>> there.
>
> Right, I saw that yesterday. What I meant was that we need to start allocating
> the structure for this case now.
>
Okay,
On Thu, Dec 24, 2020 at 3:12 AM Daniel Scally wrote:
>
> OF, ACPI and software_nodes all implement graphs including nodes for ports
> and endpoints. These are all intended to be named with a common schema,
> as "port@n" and "endpoint@n" where n is an unsigned int representing the
> index of the
tree: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
master
head: 58cf05f597b03a8212d9ecf2c79ee046d3ee8ad9
commit: 8f28ca6bd8211214faf717677bbffe375c2a6072 iomap: constify ioreadX()
iomem argument (as in generic implementation)
date: 4 months ago
config:
On Thu, Dec 24, 2020 at 3:14 AM Daniel Scally wrote:
>
> From: Heikki Krogerus
>
> This implements the remaining .graph_* callbacks in the
.graph_* ==> ->graph_*() ?
> fwnode operations structure for the software nodes. That makes
> the fwnode_graph*() functions available in the drivers also
since commit c93e4aeed1be
("Makefile.extrawarn: remove -Wnested-externs warning")
has removed this check, so it's not needed here.
Signed-off-by: Tian Tao
---
tools/perf/Makefile.config | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/perf/Makefile.config
From: Qii Wang
With the apdma remove hand-shake signal, it requirs special
operation timing to reset i2c manually, otherwise the interrupt
will not be triggered, i2c transmission will be timeout.
Signed-off-by: Qii Wang
---
drivers/i2c/busses/i2c-mt65xx.c | 27 ++-
1
Hi YANG,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on song-md/md-next]
[also build test WARNING on v5.10 next-20201223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
mutex lock can be initialized automatically with DEFINE_MUTEX()
rather than explicitly calling mutex_init()
Signed-off-by: Zheng Yongjun
---
fs/dlm/debug_fs.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/fs/dlm/debug_fs.c b/fs/dlm/debug_fs.c
index
Em Wed, Dec 23, 2020 at 11:17:47PM +0100, Jiri Olsa escreveu:
> On Fri, Dec 04, 2020 at 11:48:36AM +, John Garry wrote:
> > On 03/12/2020 15:39, Jiri Olsa wrote:
> >
> > +
> >
> > > On Thu, Nov 26, 2020 at 04:13:16PM +0200, James Clark wrote:
> > > > Changes since v5:
> > > >* Fix test
Add a basic GPU node for mt8192.
Signed-off-by: Nick Fan
---
This patch depends on Mediatek power and regulator support.
Listed as following.
[1]https://lore.kernel.org/patchwork/patch/1336293/
[2]https://patchwork.kernel.org/project/linux-mediatek/list/?series=374013
On Thu, Dec 24, 2020 at 3:13 AM Daniel Scally wrote:
>
> V4L2 fwnode bus types are enumerated in v4l2-fwnode.c, meaning they aren't
> available to the rest of the kernel. Move the enum to the corresponding
> header so that I can use the label to refer to those values.
Reviewed-by: Andy
Convert the Arm Valhall GPU binding to DT schema format.
Define a compatible string for the Mali Valhall GPU
for Mediatek's SoC platform.
Signed-off-by: Nick Fan
---
.../bindings/gpu/arm,mali-valhall.yaml| 252 ++
1 file changed, 252 insertions(+)
create mode 100644
Hi Daniel,
Thank you for the patch.
On Thu, Dec 24, 2020 at 02:17:07PM +0200, Andy Shevchenko wrote:
> On Thu, Dec 24, 2020 at 3:12 AM Daniel Scally wrote:
> >
> > OF, ACPI and software_nodes all implement graphs including nodes for ports
> > and endpoints. These are all intended to be named
Hi YANG,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on song-md/md-next]
[also build test WARNING on v5.10 next-20201223]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as
Hi Daniel,
Thank you for the patch.
On Thu, Dec 24, 2020 at 01:09:00AM +, Daniel Scally wrote:
> From: Heikki Krogerus
>
> This implements the remaining .graph_* callbacks in the
> fwnode operations structure for the software nodes. That makes
> the fwnode_graph*() functions available in
On Thursday 24 December 2020 05:54:55 Peter Chen wrote:
> On 20-12-23 17:24:03, Pali Rohár wrote:
> > Older ATF does not provide SMC call for USB 3.0 phy power on functionality
> > and therefore initialization of xhci-hcd is failing when older version of
> > ATF is used. In this case
Hi Andy,
On Thu, Dec 24, 2020 at 02:24:12PM +0200, Andy Shevchenko wrote:
> On Thu, Dec 24, 2020 at 3:14 AM Daniel Scally wrote:
> >
> > From: Heikki Krogerus
> >
> > This implements the remaining .graph_* callbacks in the
>
> .graph_* ==> ->graph_*() ?
>
> > fwnode operations structure for
On Thu, Dec 24, 2020 at 3:12 AM Daniel Scally wrote:
>
> Currently on platforms designed for Windows, connections between CIO2 and
> sensors are not properly defined in DSDT. This patch extends the ipu3-cio2
> driver to compensate by building software_node connections, parsing the
> connection
Uncore becomes die-scope on Xeon Cascade Lake-AP and perf has supported
--per-die aggregation yet.
One issue is found in check_per_pkg() for uncore events running on
AP system. On cascade Lake-AP, we have:
S0-D0
S0-D1
S1-D0
S1-D1
But in check_per_pkg(), S0-D1 and S1-D1 are skipped because the
On Thu, 24 Dec 2020, Timon Baetz wrote:
> On Wed, 23 Dec 2020 15:32:07 +, Lee Jones wrote:
> > On Wed, 23 Dec 2020, Timon Baetz wrote:
> >
> > > Add of_compatible ("maxim,max8997-muic") to the mfd_cell to have a
> > > of_node set in the extcon driver.
> > >
> > > Add of_compatible
Hi Daniel,
Thank you for the patch.
On Thu, Dec 24, 2020 at 01:09:06AM +, Daniel Scally wrote:
> V4L2 fwnode bus types are enumerated in v4l2-fwnode.c, meaning they aren't
> available to the rest of the kernel. Move the enum to the corresponding
> header so that I can use the label to refer
On Wed, Dec 23, 2020 at 3:39 PM Ricardo Ribalda wrote:
>
> Replace all the uses of printk() and uvc_printk() with its
> equivalent dev_ alias macros.
> Modify uvc_warn_once() macro to use dev_info instead printk().
...
> +#define uvc_warn_once(_dev, warn, fmt, ...)\
24.12.2020 09:43, Viresh Kumar пишет:
> On 23-12-20, 23:37, Dmitry Osipenko wrote:
>> 23.12.2020 07:19, Viresh Kumar пишет:
>>> On 22-12-20, 22:15, Dmitry Osipenko wrote:
22.12.2020 09:42, Viresh Kumar пишет:
> On 17-12-20, 21:06, Dmitry Osipenko wrote:
>> Add a ceil version of the
On Thu, Dec 24, 2020 at 2:55 PM Laurent Pinchart
wrote:
> On Thu, Dec 24, 2020 at 02:24:12PM +0200, Andy Shevchenko wrote:
> > On Thu, Dec 24, 2020 at 3:14 AM Daniel Scally wrote:
...
> > > + if (!strncmp(to_swnode(port)->node->name, "port@",
> >
> > You may use here corresponding
On Sat, 2020-12-12 at 10:02 -0800, Tushar Sugandhi wrote:
> IMA provides capabilities to measure file data, and in-memory buffer
No need for the comma here.
Up to this patch set, all the patches refer to "buffer data", not "in-
memory buffer data". This patch introduces the concept of measuring
On Sat, 2020-12-12 at 10:02 -0800, Tushar Sugandhi wrote:
>
> diff --git a/security/integrity/ima/ima_main.c
> b/security/integrity/ima/ima_main.c
> index 68956e884403..e76ef4bfd0f4 100644
> --- a/security/integrity/ima/ima_main.c
> +++ b/security/integrity/ima/ima_main.c
> @@ -786,13 +786,13 @@
Folks,
The t1_interrupt() irq handler calls del_timer_sync() down the chain:
sge.c: t1_interrupt()
-> subr.c: t1_slow_intr_handler()
-> asic_slow_intr() || fpga_slow_intr()
-> t1_pci_intr_handler()
-> cxgb2.c: t1_fatal_err()# Cont. at [*]
->
The t1_interrupt() irq handler calls del_timer_sync() down the chain:
sge.c: t1_interrupt()
-> subr.c: t1_slow_intr_handler()
-> asic_slow_intr() || fpga_slow_intr()
-> t1_pci_intr_handler()
-> cxgb2.c: t1_fatal_err() # Cont. at [*]
->
On Thu, 24 Dec 2020 10:55:59 +0100, Krzysztof Kozlowski wrote:
> On Wed, Dec 23, 2020 at 01:43:05PM +, Timon Baetz wrote:
> > Register for extcon notification and set charging current depending on
> > the detected cable type. Current values are taken from vendor kernel,
> > where most charger
Em Thu, Dec 24, 2020 at 08:24:06PM +0800, Tian Tao escreveu:
> since commit c93e4aeed1be
> ("Makefile.extrawarn: remove -Wnested-externs warning")
> has removed this check, so it's not needed here.
But the above commit is for the kernel, scripts/Makefile.extrawarn isn't
included in tools/perf/
Since commit ac3d9dd034e5 ("netpoll: make ndo_poll_controller()
optional"), networking drivers which use NAPI for clearing their TX
completions should not provide an ndo_poll_controller(). Netpoll simply
triggers the necessary TX queues cleanup by synchronously calling the
driver's NAPI poll
cxgb's "elmer0" external interrupt handling code requires task context,
so originally a workqueue was scheduled for it from the hardirq handler.
Now that all of the external interrupt handling, elmer0 included, is run
from a threaded-irq context, just directly call the real handler.
Remove all
> > > + /* Old bindings miss the PHY handle */
> > > + phy = of_phy_get(dev->of_node, "usb3-phy");
> > > + if (IS_ERR(phy) && PTR_ERR(phy) == -EPROBE_DEFER)
> > > + return -EPROBE_DEFER;
> >
> > Doesn't need to judge IS_ERR(phy).
>
> Ok, I can remove it. I used same condition which is
-a006-20201223
x86_64 randconfig-a002-20201223
x86_64 randconfig-a004-20201223
x86_64 randconfig-a003-20201223
x86_64 randconfig-a005-20201223
i386 randconfig-a005-20201224
i386 randconfig-a002-20201224
i386
When nv50_lut_init() fails, *pwndw should be freed
just like when drm_universal_plane_init() fails.
It's the same for the subsequent error paths.
Signed-off-by: Dinghao Liu
---
drivers/gpu/drm/nouveau/dispnv50/wndw.c | 22 --
1 file changed, 12 insertions(+), 10 deletions(-)
mutex lock can be initialized automatically with DEFINE_MUTEX()
rather than explicitly calling mutex_init().
Signed-off-by: Zheng Yongjun
---
fs/dlm/lockspace.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c
index
mutex lock can be initialized automatically with DEFINE_MUTEX()
rather than explicitly calling mutex_init().
Signed-off-by: Zheng Yongjun
---
fs/btrfs/check-integrity.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/fs/btrfs/check-integrity.c b/fs/btrfs/check-integrity.c
mutex lock can be initialized automatically with DEFINE_MUTEX()
rather than explicitly calling mutex_init().
Signed-off-by: Zheng Yongjun
---
fs/ecryptfs/crypto.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/fs/ecryptfs/crypto.c b/fs/ecryptfs/crypto.c
index
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