On Thu, 2021-04-08 at 11:24 -0400, Stefan Berger wrote:
> Address a kbuild issue where a developer created an ECDSA key for signing
> kernel modules and then builds an older version of the kernel, when bi-
> secting the kernel for example, that does not support ECDSA keys.
>
> Trigger the
On Thu, Apr 8, 2021 at 3:30 AM Marco Elver wrote:
>
> On Tue, 6 Apr 2021 at 12:57, Vlastimil Babka wrote:
> >
> >
> > On 4/1/21 11:24 PM, Marco Elver wrote:
> > > On Thu, 1 Apr 2021 at 21:04, Daniel Latypov wrote:
> > >> > }
> > >> > #else
> > >> > static inline bool
On 4/7/21 2:45 PM, Ramakrishna Saripalli wrote:
> From: Ramakrishna Saripalli
>
> Expose Predictive Store Forwarding capability to guests.
> Guests enable or disable PSF via SPEC_CTRL MSR.
>
> Signed-off-by: Ramakrishna Saripalli
> ---
> arch/x86/kvm/cpuid.c | 4 +++-
> 1 file changed, 3
On Thu, 08 Apr 2021 18:56:06 +0200,
Ville Syrjälä wrote:
>
> On Thu, Apr 08, 2021 at 06:34:06PM +0200, Takashi Iwai wrote:
> > On Thu, 08 Apr 2021 09:51:18 +0200,
> > Takashi Iwai wrote:
> > >
> > > On Wed, 07 Apr 2021 23:28:48 +0200,
> > > Ville Syrjälä wrote:
> > > >
> > > > Oh, could you ask
On 4/8/21 12:10 PM, Sean Christopherson wrote:
> On Thu, Apr 08, 2021, Tom Lendacky wrote:
>> From: Tom Lendacky
>>
>> Access to the GHCB is mainly in the VMGEXIT path and it is known that the
>> GHCB will be mapped. But there are two paths where it is possible the GHCB
>> might not be mapped.
>>
On Wed, 7 Apr 2021 15:26:23 -0700
Ben Widawsky wrote:
> Support expansion of register block types that the driver will attempt
> to recognize by pulling the code up into the register block scanning
> loop. Subsequent code can easily add in new register block types with
> this.
>
>
On Fri, 2021-04-02 at 16:20 +0200, Paolo Bonzini wrote:
> On 02/04/21 13:58, Ashish Kalra wrote:
> > Hi Nathan,
> >
> > Will you be posting a corresponding Qemu patch for this ?
>
> Hi Ashish,
>
> as far as I know IBM is working on QEMU patches for guest-based
> migration helpers.
Yes, that's
On 08/04/2021 17:24:39+0200, Nicolas Ferre wrote:
> On 01/04/2021 at 12:24, Claudiu Beznea - M18063 wrote:
> > On 01.04.2021 12:38, Claudiu Beznea - M18063 wrote:
> > > On 31.03.2021 19:01, Alexandre Belloni wrote:
> > > > EXTERNAL EMAIL: Do not click links or open attachments unless you know
> >
Hi Heiner,
On Thu, Apr 8, 2021 at 1:49 PM Heiner Kallweit wrote:
>
> Can't we use frame_length - ETH_FCS_LEN direcctly here?
If the hard-coded "4" refers to ETH_FCS_LEN, then yes, good point. I'd
love to find out first why George and I need different patches to make
the driver work in our use
Clean up macros even further after removal get_fs/set_fs.
Signed-off-by: Thomas Bogendoerfer
---
arch/mips/include/asm/uaccess.h | 157 +++-
1 file changed, 71 insertions(+), 86 deletions(-)
diff --git a/arch/mips/include/asm/uaccess.h
Slot resets are bus resets with additional logic to prevent a device
from being removed during the reset. Currently slot and bus resets have
separate implementations in pci.c, complicating higher level logic. As
discussed on the mailing list, they should be combined into a generic
function which
On 4/8/2021 9:40 AM, Peter Zijlstra wrote:
@@ -4330,7 +4347,7 @@ static int intel_pmu_check_period(struct perf_event
*event, u64 value)
static int intel_pmu_aux_output_match(struct perf_event *event)
{
- if (!x86_pmu.intel_cap.pebs_output_pt_available)
+ if
On Thu, Apr 08, 2021 at 10:55:53AM +0200, Greg KH wrote:
> So to add crazy complexity to the kernel,
I agree that this can be tricky. However, driver developers are going to
open code this either way. The problem with that as well, and one of my
own reasons for striving for at least *trying* for
Quoting Jessica Yu (2021-04-08 05:05:33)
> +++ Stephen Boyd [30/03/21 20:05 -0700]:
> >+/**
> >+ * init_vmlinux_build_id - Get the running kernel's build ID
> >+ *
> >+ * Return: Running kernel's build ID
> >+ */
>
> Hm, init_vmlinux_build_id() doesn't return anything, so this comment is
> not
Hi Mel Gorman,
I may have found a problem in pfmemalloc skb handling in
net/core/dev.c. I see there are "if" conditions checking for
"sk_memalloc_socks() && skb_pfmemalloc(skb)", and when the condition
is true, the skb is handled specially as a pfmemalloc skb, otherwise
it is handled as a normal
On Fri, Apr 02, 2021 at 03:18:20PM +, Christophe Leroy wrote:
> This converts the architecture to GENERIC_CMDLINE.
>
> Signed-off-by: Christophe Leroy
> ---
> arch/x86/Kconfig| 45 ++---
> arch/x86/kernel/setup.c | 17 ++--
> 2 files
> On Apr 8, 2021, at 11:50 AM, Arnaldo Carvalho de Melo wrote:
>
> Em Thu, Apr 08, 2021 at 08:24:47PM +0200, Jiri Olsa escreveu:
>> On Thu, Apr 08, 2021 at 06:08:20PM +, Song Liu wrote:
>>>
>>>
On Apr 8, 2021, at 10:45 AM, Jiri Olsa wrote:
On Thu, Apr 08, 2021 at
Quoting Petr Mladek (2021-04-08 03:13:20)
> It helped with the vmlinux buildid. I see the following:
>
> [ 551.435942][ T1803] test_printf: loaded.
> [ 551.436667][ T1803] [ cut here ]
> [ 551.437561][ T1803] kernel BUG at lib/test_printf.c:689!
> [ 551.438352][ T1803]
On 4/8/21 12:44 PM, Nathan Chancellor wrote:
> LLVM 13 adds a new warning, -Walign-mismatch, which has an instance in
> blk_mq_complete_send_ipi():
>
> block/blk-mq.c:630:39: warning: passing 8-byte aligned argument to
> 32-byte aligned parameter 2 of 'smp_call_function_single_async' may
> result
Thus wrote Greg Kroah-Hartman (gre...@linuxfoundation.org):
> Wow, that's there for a really old kernel version and should not be
> needed anymore at all. I'll take this, but please remove the other ones
> here, they are not necessary.
Ok, I see what you mean. New patch is on the way.
Best
On Thu, Apr 08, 2021, Paolo Bonzini wrote:
> On 08/04/21 13:15, Wanpeng Li wrote:
> > I saw this splatting:
> >
> > BUG: sleeping function called from invalid context at
> > arch/x86/kvm/kvm_cache_regs.h:115
> >kvm_pdptr_read+0x20/0x60 [kvm]
> >kvm_mmu_load+0x3bd/0x540 [kvm]
> >
> >
On Wed, 07 Apr 2021 20:16:34 -0500, Zev Weiss wrote:
> This property ties SIRQ polarity to SCU register bits that don't
> necessarily have any direct relationship to it; the only use of it was
> removed in commit c82bf6e133d3 ("ARM: aspeed: g5: Do not set sirq
> polarity").
>
> Signed-off-by: Zev
On Thu, Apr 08, 2021 at 04:26:48PM +0800, Jason Wang wrote:
> This patch mandates 1.0 for vDPA devices. The goal is to have the
> semantic of normative statement in the virtio spec and eliminate the
> burden of transitional device for both vDPA bus and vDPA parent.
>
> uAPI seems fine since all
On 4/7/21 4:07 PM, Sean Christopherson wrote:
> On Wed, Apr 07, 2021, Tom Lendacky wrote:
>> On 4/7/21 3:08 PM, Sean Christopherson wrote:
>>> On Wed, Apr 07, 2021, Tom Lendacky wrote:
From: Tom Lendacky
The sev_vcpu_deliver_sipi_vector() routine will update the GHCB to inform
On Thu, Apr 8, 2021 at 5:26 PM Eric Biggers wrote:
>
> On Thu, Apr 08, 2021 at 03:32:38PM +0200, Rafael J. Wysocki wrote:
> > On Thu, Apr 8, 2021 at 3:15 PM Chris von Recklinghausen
> > wrote:
> > >
> > > Suspend fails on a system in fips mode because md5 is used for the e820
> > > integrity
On Thu, Apr 08, 2021, lihaiwei.ker...@gmail.com wrote:
> From: Haiwei Li
>
> vmcs_check32 misses the check for 64-bit and 64-bit high.
Can you clarify in the changelog that, while it is architecturally legal to
access 64-bit and 64-bit high fields with a 32-bit read/write in 32-bit mode,
KVM
On Tue, Apr 06, 2021 at 02:25:49PM -0400, Jim Quinlan wrote:
> On Tue, Apr 6, 2021 at 1:32 PM Mark Brown wrote:
> >
> > On Tue, Apr 06, 2021 at 01:26:51PM -0400, Jim Quinlan wrote:
> > > On Tue, Apr 6, 2021 at 12:47 PM Mark Brown wrote:
> >
> > > > No great problem with having these in the
On Thu, Mar 25, 2021 at 03:26:00PM +0800, Zhiqiang Liu wrote:
> From: Feilong Lin
>
> In enable_slot() in drivers/pci/hotplug/acpiphp_glue.c, if pci_get_slot()
> will return NULL, we will do not set SLOT_ENABLED flag of slot. if one
> device is found by calling pci_get_slot(), its reference
Ola Aline,
Welcome to the kernel community. Hope you enjoy some of this
Outreachy adventures.
Normally, when you submit a v2, we want to know what changed
between the first submission and v2.
If you are subscribed to linux-media, you can read some
of the series with a vN+1 and look how it's
On Tue, Apr 06, 2021 at 05:26:28PM +0800, Greentime Hu wrote:
> This patchset includes SiFive FU740 PCIe host controller driver. We also
> add pcie_aux clock and pcie_power_on_reset controller to prci driver for
> PCIe driver to use it.
>
> This is tested with e1000e: Intel(R) PRO/1000 Network
On Thu, Apr 08, 2021, Paolo Bonzini wrote:
> On 08/04/21 17:48, Sean Christopherson wrote:
> > Freaking PDPTRs. I was really hoping we could keep the lock and
> > pages_available()
> > logic outside of the helpers. What if kvm_mmu_load() reads the PDPTRs and
> > passes them into
Thanks, this looks good.
Reviewed-by: Harshad Shirwadkar
On Thu, Apr 8, 2021 at 12:00 AM Xu Yihang wrote:
>
> In case of if not ext4_fc_add_tlv branch, an error return code is missing.
>
> Fixes: aa75f4d3daae ("ext4: main fast-commit commit path")
> Reported-by: Hulk Robot
> Signed-off-by: Xu
> -Original Message-
> From: Randy Dunlap
> Sent: Thursday, April 8, 2021 12:23 PM
> To: Dexuan Cui ; da...@davemloft.net;
> k...@kernel.org; KY Srinivasan ; Haiyang Zhang
> ; Stephen Hemminger
> ; wei@kernel.org; Wei Liu
> ; net...@vger.kernel.org; l...@kernel.org;
>
> On Apr 8, 2021, at 4:47 AM, Jiri Olsa wrote:
>
> On Tue, Apr 06, 2021 at 05:36:01PM -0700, Song Liu wrote:
>> Currently, to use BPF to aggregate perf event counters, the user uses
>> --bpf-counters option. Enable "use bpf by default" events with a config
>> option, stat.bpf-counter-events.
This patch adds a check on present of PM domain and calls legacy power
domain API tegra_powergate_power_off() only when PM domain is not present.
This is a follow-up patch to Tegra186 AHCI support patch series
https://lore.kernel.org/patchwork/cover/1408752/
Signed-off-by: Sowjanya Komatineni
This includes a follow up patch to Tegra186 AHCI support patch series
https://lore.kernel.org/patchwork/cover/1408752/
Sowjanya Komatineni (1):
ata: ahci_tegra: call tegra_powergate_power_off only when PM domain is
not present
drivers/ata/ahci_tegra.c | 3 ++-
1 file changed, 2
On Thu, Apr 08, 2021 at 06:34:06PM +0200, Takashi Iwai wrote:
> On Thu, 08 Apr 2021 09:51:18 +0200,
> Takashi Iwai wrote:
> >
> > On Wed, 07 Apr 2021 23:28:48 +0200,
> > Ville Syrjälä wrote:
> > >
> > > Oh, could you ask the bug reporter to attach an acpidump to the
> > > bug? Might be good to
On Wed, 7 Apr 2021 14:56:34 +0500, Muhammad Usama Anjum wrote:
> devm_ioremap_resource() prints error message in itself. Remove the
> dev_err call to avoid redundant error message.
Applied to
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
Thanks!
[1/1] ASoC: fsl:
On Thu, 8 Apr 2021 14:27:00 +0800, Ye Bin wrote:
> The snd_soc_dai_ops structures is only stored in the ops field of a
> snd_soc_dai_driver structure, so make the snd_soc_dai_ops structure
> const to allow the compiler to put it in read-only memory.
Applied to
On Thu, 8 Apr 2021 14:27:01 +0800, Ye Bin wrote:
> The snd_soc_dai_ops structures is only stored in the ops field of a
> snd_soc_dai_driver structure, so make the snd_soc_dai_ops structure
> const to allow the compiler to put it in read-only memory.
Applied to
On Thu, 8 Apr 2021 14:40:34 +0800, Dinghao Liu wrote:
> There is a rumtime PM imbalance between the error handling path
> after devm_snd_soc_register_component() and all other error
> handling paths. Add a PM runtime increment to balance refcount.
Applied to
On Thu, 8 Apr 2021 14:26:46 +0800, Ye Bin wrote:
> The snd_soc_dai_ops structures is only stored in the ops field of a
> snd_soc_dai_driver structure, so make the snd_soc_dai_ops structure
> const to allow the compiler to put it in read-only memory.
Applied to
On Thu, 8 Apr 2021 14:26:43 +0800, Ye Bin wrote:
> The snd_soc_dai_ops structures is only stored in the ops field of a
> snd_soc_dai_driver structure, so make the snd_soc_dai_ops structure
> const to allow the compiler to put it in read-only memory.
Applied to
On Thu, 8 Apr 2021 14:26:56 +0800, Ye Bin wrote:
> The snd_soc_dai_ops structures is only stored in the ops field of a
> snd_soc_dai_driver structure, so make the snd_soc_dai_ops structure
> const to allow the compiler to put it in read-only memory.
Applied to
Hi Tom,
On 3/31/21 5:50 AM, Tom Rix wrote:
Several just for debugging items, consider adding a CONFIG_XRT_DEBUGGING
I'd like to clarify what "only for debugging" means here. It actually
means that the content of the msg/output only makes sense to a
developer, v.s. end user. It does not
On Wed, 7 Apr 2021 15:26:19 -0700
Ben Widawsky wrote:
> Trivial cleanup.
Obviously correct :)
>
> Signed-off-by: Ben Widawsky
FWIW
Acked-by: Jonathan Cameron
> ---
> drivers/cxl/mem.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/cxl/mem.c
Not all platforms are able to allocate CMA size of 256MB. One such
platform is SDX55. Hence, use the standard 64MB size for CMA.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Enable the Qualcomm Q6V5_PAS (Peripheral Authentication Service)
remoteproc driver to manage the modem co-processor in SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig
Hi Bjorn,
This series updates the qcom_defconfig by enabling the drivers required
for the SDX55 platform.
Please consider merging!
Thanks,
Mani
Manivannan Sadhasivam (7):
ARM: configs: qcom_defconfig: Enable APCS IPC mailbox driver
ARM: configs: qcom_defconfig: Enable SDX55 A7 PLL and APCS
Enable Qualcomm APCS IPC mailbox driver for IPC communication between
application processor and other masters in platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig
Enable A7 PLL driver and APCS clock driver on SDX55 platform.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index 0b9da27f923a..02f6185f31a6 100644
Enable the Qualcomm GLINK SMEM driver to support GLINK protocol over
shared memory.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index
Enable interconnect driver for SDX55 platform to manage the interconnect
providers.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig
index
Enable CPUFreq and CPUFreq DT drivers to carry out CPU Frequency scaling
duties on platforms like SDX55.
Signed-off-by: Manivannan Sadhasivam
---
arch/arm/configs/qcom_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/configs/qcom_defconfig
On Fri, Apr 2, 2021 at 8:14 AM YueHaibing wrote:
>
> commit 9a7875461fd0 ("PM: runtime: Replace pm_runtime_callbacks_present()")
> forget to change the inline version.
>
> Fixes: 9a7875461fd0 ("PM: runtime: Replace pm_runtime_callbacks_present()")
> Signed-off-by: YueHaibing
> ---
>
Hi Reinette,
On 07/04/2021 00:42, Reinette Chatre wrote:
> On 4/6/2021 10:13 AM, James Morse wrote:
>> On 31/03/2021 22:35, Reinette Chatre wrote:
>>> On 3/12/2021 9:58 AM, James Morse wrote:
resctrl is the defacto Linux ABI for SoC resource partitioning features.
To support it on
Hi Babu,
On 06/04/2021 22:37, Babu Moger wrote:
> On 4/6/21 12:19 PM, James Morse wrote:
>> On 30/03/2021 21:36, Babu Moger wrote:
>>> On 3/12/21 11:58 AM, James Morse wrote:
This series re-folds the resctrl code so the CDP resources (L3CODE et al)
behaviour is all contained in the
On Thu, Apr 08, 2021 at 04:39:33PM +, Song Liu wrote:
>
>
> > On Apr 8, 2021, at 4:47 AM, Jiri Olsa wrote:
> >
> > On Tue, Apr 06, 2021 at 05:36:01PM -0700, Song Liu wrote:
> >> Currently, to use BPF to aggregate perf event counters, the user uses
> >> --bpf-counters option. Enable "use
Hi Reinette,
On 31/03/2021 22:36, Reinette Chatre wrote:
> On 3/12/2021 9:58 AM, James Morse wrote:
>> resctrl is the defacto Linux ABI for SoC resource partitioning features.
>> To support it on another architecture, it needs to be abstracted from
>> the features provided by Intel RDT and AMD
On Thu, Apr 08, 2021 at 04:30:18PM +, Wei Liu wrote:
> On Thu, Apr 08, 2021 at 05:54:43PM +0200, Siddharth Chandrasekaran wrote:
> > On Thu, Apr 08, 2021 at 05:48:19PM +0200, Paolo Bonzini wrote:
> > > On 08/04/21 17:40, Siddharth Chandrasekaran wrote:
> > > > > > > Although the Hyper-v TLFS
On Thu, Apr 08, 2021 at 05:28:10PM +, Song Liu wrote:
>
>
> > On Apr 8, 2021, at 10:20 AM, Jiri Olsa wrote:
> >
> > On Thu, Apr 08, 2021 at 04:39:33PM +, Song Liu wrote:
> >>
> >>
> >>> On Apr 8, 2021, at 4:47 AM, Jiri Olsa wrote:
> >>>
> >>> On Tue, Apr 06, 2021 at 05:36:01PM
Wu XiangCheng writes:
> Remove Harry Wei and from
> MAINTAINERS Chinese Translation.
>
> According to git logs, Harry Wei (aka WeiWei Jia)
> * last submitted at 2012-05-07
> commit a9e73211fb0f ("Fix a mistake sentence in the file
> 'Documentation/zh_CN/magic-number.txt'")
> * last Reviewed-by
On Thu, Apr 08, 2021 at 02:51:34PM +0200, Greg Kroah-Hartman wrote:
> There are a lot of tty-core-only functions that are listed in
> include/linux/tty.h. Move them to drivers/tty/tty.h so that no one else
> can accidentally call them or think that they are public functions.
>
> Cc: Jiri Slaby
So this issue is blocking the LLVM upgrading on ChromeOS. Nathan, do
you mind sending out the smaller patch like Nick suggested just to see
what feedback we could get? I could send it for you if you are busy,
and please let me know what tags I should use in that case.
Thanks,
Jian
On Wed, Mar
On Thu, Apr 08, 2021 at 10:47:21PM +0900, Tetsuo Handa wrote:
> On 2021/04/08 21:51, Greg Kroah-Hartman wrote:
> > Remove users of tty_warn() and replace them with calls to dev_warn()
> > which provides more information about the tty that has the error and
> > uses the standard formatting logic.
>
On Thu, Apr 08, 2021 at 07:36:37PM +0200, Uwe Kleine-König wrote:
> On Thu, Apr 08, 2021 at 05:51:36PM +0200, Clemens Gruber wrote:
> > On Thu, Apr 08, 2021 at 02:50:40PM +0200, Thierry Reding wrote:
> > > Yes, I think that's basically what this is saying. I think we're perhaps
> > > getting hung
Hi Heiner,
On Thu, Apr 8, 2021 at 2:22 PM Heiner Kallweit wrote:
>
> Just an idea:
> RX_HEAD_PADDING is an alias for NET_IP_ALIGN that can have two values:
> 0 and 2
> The two systems you use may have different NET_IP_ALIGN values.
> This could explain the behavior. Then what I proposed should
On 08.04.2021 06:42, Pkshih wrote:
-Original Message-
From: Maciej S. Szmigiero [mailto:m...@maciej.szmigiero.name]
Sent: Thursday, April 08, 2021 4:53 AM
To: Larry Finger; Pkshih
Cc: linux-wirel...@vger.kernel.org; net...@vger.kernel.org;
linux-kernel@vger.kernel.org;
On Tue, Apr 06, 2021 at 10:38:36AM -0700, Daniel Walker wrote:
> On Fri, Apr 02, 2021 at 03:18:21PM +, Christophe Leroy wrote:
> > -config CMDLINE_BOOL
> > - bool "Built-in kernel command line"
> > - help
> > - For most systems, it is firmware or second stage bootloader that
> > -
Like the Intel DC P3700 NVMe, the Intel P4510 NVMe exhibits a timeout
failure when the driver tries to interact with the device to soon after
an FLR. The same reset quirk the P3700 uses also resolves the failure
for the P4510, so this change introduces the same reset quirk for the
P4510.
>
> Please provide some sort of documentation and at the least, a pointer to the
> software that uses this so that we can see how it all ties together.
>
Hi Greg, I will withdraw this review for misc and focus on MFD part review for
now. I will re-submit the misc review after mfd change is in.
> On Apr 8, 2021, at 11:24 AM, Jiri Olsa wrote:
>
> On Thu, Apr 08, 2021 at 06:08:20PM +, Song Liu wrote:
>>
>>
>>> On Apr 8, 2021, at 10:45 AM, Jiri Olsa wrote:
>>>
>>> On Thu, Apr 08, 2021 at 05:28:10PM +, Song Liu wrote:
> On Apr 8, 2021, at 10:20 AM, Jiri Olsa
Hi Arnd and all,
Here's the final version of the M1 SoC bring-up series, based on
v4 which was reviewed here:
https://lore.kernel.org/linux-arm-kernel/20210402090542.131194-1-mar...@marcan.st/T/#u
Changes since v4 as reviewed:
* Sort DT soc bus nodes by address (NFC)
* Introduce defines to
On Thu, 2021-04-08 at 11:24 -0400, Olga Kornievskaia wrote:
> On Thu, Apr 8, 2021 at 11:01 AM Trond Myklebust <
> tron...@hammerspace.com> wrote:
> >
> > On Tue, 2021-04-06 at 19:16 -0500, Aditya Pakki wrote:
> > > In gss_pipe_destroy_msg(), in case of error in msg,
> > > gss_release_msg
> > >
Use blk_mq_unique_tag() to generate requestIDs for StorVSC, avoiding
all issues with allocating enough entries in the VMbus requestor.
Suggested-by: Michael Kelley
Signed-off-by: Andrea Parri (Microsoft)
---
drivers/hv/channel.c | 14 +++---
drivers/hv/ring_buffer.c | 12
On 08/04/21 18:05, Sean Christopherson wrote:
Add compile-time assertions in vmcs_check32() to disallow accesses to
64-bit and 64-bit high fields via vmcs_{read,write}32(). Upper level
KVM code should never do partial accesses to VMCS fields. KVM handles
the split accesses
> > Thank you for noticing this. Not sure how this missmerge happened. I
> > have added the missing case, and VHE is initialized correctly during
> > boot.
> > [ 14.698175] kvm [1]: VHE mode initialized successfully
> >
> > During normal boot, kexec reboot, and kdump reboot. I will respin the
>
On Thu, Apr 08, 2021 at 09:22:52PM +0800, Yicong Yang wrote:
> On 2021/4/8 2:55, Bjorn Helgaas wrote:
> > On Tue, Apr 06, 2021 at 08:45:53PM +0800, Yicong Yang wrote:
> >> +On Kunpeng 930 SoC, the PCIe root complex is composed of several
> >> +PCIe cores.
>
> > Can you connect "Kunpeng 930" to
pci_p2pdma_map_type() will be needed by the dma-iommu map_sg
implementation because it will need to determine the mapping type
ahead of actually doing the mapping to create the actual iommu mapping.
Signed-off-by: Logan Gunthorpe
---
drivers/pci/p2pdma.c | 34
Hi,
This patchset continues my work to to add P2PDMA support to the common
dma map operations. This allows for creating SGLs that have both P2PDMA
and regular pages which is a necessary step to allowing P2PDMA pages in
userspace.
The earlier RFC[1] generated a lot of great feedback and I heard
Drop the use of pci_p2pdma_map_sg() in favour of dma_map_sg_p2pdma().
The new interface allows mapping scatterlists that mix both regular
and P2PDMA pages and will verify that the dma device can communicate
with the device the pages are on.
Signed-off-by: Logan Gunthorpe
---
In order to call upstream_bridge_distance_warn() from a dma_map function,
it must not sleep. The only reason it does sleep is to allocate the seqbuf
to print which devices are within the ACS path.
Switch the kmalloc call to use a passed in gfp_mask and don't print that
message if the buffer fails
Add pci_p2pdma_map_segment() as a helper for simple dma_map_sg()
implementations. It takes an scatterlist segment that must point to a
pci_p2pdma struct page and will map it if the mapping requires a bus
address.
The return value indicates whether the mapping required a bus address
or whether the
Convert to using dma_map_sg_p2pdma() for PCI p2pdma pages.
This should be equivalent but allows for heterogeneous scatterlists
with both P2PDMA and regular pages. However, P2PDMA support will be
slightly more restricted (only dma-direct and dma-iommu are currently
supported).
Signed-off-by:
In order to use upstream_bridge_distance_warn() from a dma_map function,
it must not sleep. However, pci_get_slot() takes the pci_bus_sem so it
might sleep.
In order to avoid this, try to get the host bridge's device from
bus->self, and if that is not set, just get the first element in the
device
Ensure the dma operations support p2pdma before using the RDMA
device for P2PDMA. This allows switching the RDMA driver from
pci_p2pdma_map_sg() to dma_map_sg_p2pdma().
Signed-off-by: Logan Gunthorpe
---
drivers/nvme/target/rdma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff
Introduce a supports_pci_p2pdma() operation in nvme_ctrl_ops to
replace the fixed NVME_F_PCI_P2PDMA flag such that the dma_map_ops
flags can be checked for PCI P2PDMA support.
Signed-off-by: Logan Gunthorpe
---
drivers/nvme/host/core.c | 3 ++-
drivers/nvme/host/nvme.h | 2 +-
When a PCI P2PDMA page is seen, set the IOVA length of the segment
to zero so that it is not mapped into the IOVA. Then, in finalise_sg(),
apply the appropriate bus address to the segment. The IOVA is not
created if the scatterlist only consists of P2PDMA pages.
Similar to dma-direct, the
This interface is superseded by the new dma_map_sg_p2pdma() interface
which supports heterogeneous scatterlists. There are no longer
any users, so remove it.
Signed-off-by: Logan Gunthorpe
---
drivers/pci/p2pdma.c | 67 --
include/linux/pci-p2pdma.h |
Add a flags member to the dma_map_ops structure with one flag to
indicate support for PCI P2PDMA.
Also, add a helper to check if a device supports PCI P2PDMA.
Signed-off-by: Logan Gunthorpe
---
include/linux/dma-map-ops.h | 3 +++
include/linux/dma-mapping.h | 5 +
kernel/dma/mapping.c
Add PCI P2PDMA support for dma_direct_map_sg() so that it can map
PCI P2PDMA pages directly without a hack in the callers. This allows
for heterogeneous SGLs that contain both P2PDMA and regular pages.
SGL segments that contain PCI bus addresses are marked with
sg_mark_pci_p2pdma() and are
Thorsten Leemhuis writes:
> +In case you performed a successful bisection, use the title of the change
> that
> +introduced the regression as the second part of your subject. Make the report
> +also mention the commit id of the culprit. For tracking purposes, add a line
> +like the following
Hi Longfang,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on usb/usb-testing]
[also build test WARNING on v5.12-rc6 next-20210408]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base
On Thu, Apr 08, 2021 at 12:52:07PM +0200, Peter Zijlstra wrote:
> > diff --git a/mm/page_alloc.c b/mm/page_alloc.c
> > index a68bacddcae0..e9e60d1a85d4 100644
> > --- a/mm/page_alloc.c
> > +++ b/mm/page_alloc.c
> > @@ -112,6 +112,13 @@ typedef int __bitwise fpi_t;
> > static
On Thu, Apr 08, 2021 at 12:58:05PM -0400, Jim Quinlan wrote:
> On Thu, Apr 8, 2021 at 12:20 PM Rob Herring wrote:
> >
> > On Tue, Apr 06, 2021 at 02:25:49PM -0400, Jim Quinlan wrote:
> > > On Tue, Apr 6, 2021 at 1:32 PM Mark Brown wrote:
> > > >
> > > > On Tue, Apr 06, 2021 at 01:26:51PM -0400,
Dear Friend,
Please I want you to read this letter very carefully and I must
apologize for berging this message into your mailbox without any
formal introduction due to the urgency and confidentiality of this
issue and I know that this message will come to you as a surprise.
Please, I urge you to
Hi Jian,
On Thu, Apr 08, 2021 at 10:57:54AM -0700, Jian Cai wrote:
> So this issue is blocking the LLVM upgrading on ChromeOS. Nathan, do
> you mind sending out the smaller patch like Nick suggested just to see
> what feedback we could get? I could send it for you if you are busy,
> and please
On Thu, Apr 08, 2021 at 06:01:05PM +, Quentin Perret wrote:
> The CRC calculation done by genksyms is triggered when the parser hits
> EXPORT_SYMBOL*() macros. At this point, genksyms recursively expands the
> types, and uses that as the input for the CRC calculation. In the case
> of
On Thu, Apr 08, 2021 at 06:08:20PM +, Song Liu wrote:
>
>
> > On Apr 8, 2021, at 10:45 AM, Jiri Olsa wrote:
> >
> > On Thu, Apr 08, 2021 at 05:28:10PM +, Song Liu wrote:
> >>
> >>
> >>> On Apr 8, 2021, at 10:20 AM, Jiri Olsa wrote:
> >>>
> >>> On Thu, Apr 08, 2021 at 04:39:33PM
On Thu, Apr 08, 2021 at 09:20:19AM +, Wu, Hao wrote:
> > On Thu, Apr 08, 2021 at 03:30:15PM +0800, Wu, Hao wrote:
> > > > > On Mon, 5 Apr 2021, Moritz Fischer wrote:
> > > > >
> > > > > > Hi Matthew,
> > > > > >
> > > > > > On Mon, Apr 05, 2021 at 04:53:00PM -0700,
> > > >
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