[PATCH v9 18/22] tracing: Add hist trigger support for stacktraces as keys

2015-07-16 Thread Tom Zanussi
It's often useful to be able to use a stacktrace as a hash key, for
keeping a count of the number of times a particular call path resulted
in a trace event, for instance.  Add a special key named 'stacktrace'
which can be used as key in a 'keys=' param for this purpose:

# echo hist:keys=stacktrace ... \
   [ if filter]  event/trigger

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c |   9 +--
 kernel/trace/trace_events_hist.c | 135 +--
 2 files changed, 106 insertions(+), 38 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 75795e3..16c64a2 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3801,10 +3801,11 @@ static const char readme_msg[] =
\tThe special string 'hitcount' can be used in place of an\n
\texplicit value field - this is simply a count of event hits.\n
\tIf 'values' is not specified, 'hitcount' will be assumed.\n
-   \tof event hits.  Keys can be any field.  Compound keys\n
-   \tconsisting of up to two fields can be specified by the 'keys'\n
-   \tkeyword.  Additionally, sort keys consisting of up to two\n
-   \tfields can be specified by the 'sort' keyword.\n\n
+   \tKeys can be any field, or the special string 'stacktrace',\n
+   \twhich will use the event's kernel stacktrace as the key.\n
+   \tCompound keys consisting of up to two fields can be specified\n
+   \tby the 'keys' keyword.  Additionally, sort keys consisting\n
+   \tof up to two fields can be specified by the 'sort' keyword.\n\n
\tReading the 'hist' file for the event will dump the hash\n
\ttable in its entirety to stdout.  Each printed hash table\n
\tentry is a simple list of the keys and values comprising the\n
diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index 28ccaa1..21ab8be 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -35,6 +35,11 @@ struct hist_field {
unsigned intoffset;
 };
 
+static u64 hist_field_none(struct hist_field *field, void *event)
+{
+   return 0;
+}
+
 static u64 hist_field_counter(struct hist_field *field, void *event)
 {
return 1;
@@ -64,9 +69,13 @@ DEFINE_HIST_FIELD_FN(u16);
 DEFINE_HIST_FIELD_FN(s8);
 DEFINE_HIST_FIELD_FN(u8);
 
+#define HIST_STACKTRACE_DEPTH  16
+#define HIST_STACKTRACE_SIZE   (HIST_STACKTRACE_DEPTH * sizeof(unsigned long))
+#define HIST_STACKTRACE_SKIP   5
+
 #define HITCOUNT_IDX   0
 #define HIST_KEY_MAX   2
-#define HIST_KEY_SIZE_MAX  (MAX_FILTER_STR_VAL + sizeof(u64))
+#define HIST_KEY_SIZE_MAX  (MAX_FILTER_STR_VAL + HIST_STACKTRACE_SIZE)
 
 enum hist_field_flags {
HIST_FIELD_HITCOUNT = 1,
@@ -77,6 +86,7 @@ enum hist_field_flags {
HIST_FIELD_SYM_OFFSET   = 32,
HIST_FIELD_EXECNAME = 64,
HIST_FIELD_SYSCALL  = 128,
+   HIST_FIELD_STACKTRACE   = 256,
 };
 
 struct hist_trigger_attrs {
@@ -314,6 +324,11 @@ static struct hist_field *create_hist_field(struct 
ftrace_event_field *field,
goto out;
}
 
+   if (flags  HIST_FIELD_STACKTRACE) {
+   hist_field-fn = hist_field_none;
+   goto out;
+   }
+
if (is_string_field(field)) {
flags |= HIST_FIELD_STRING;
hist_field-fn = hist_field_string;
@@ -437,38 +452,43 @@ static int create_key_field(struct hist_trigger_data 
*hist_data,
struct ftrace_event_field *field = NULL;
unsigned long flags = 0;
unsigned int key_size;
-   char *field_name;
int ret = 0;
 
flags |= HIST_FIELD_KEY;
 
-   field_name = strsep(field_str, .);
-   if (field_str) {
-   if (!strcmp(field_str, hex))
-   flags |= HIST_FIELD_HEX;
-   else if (!strcmp(field_str, sym))
-   flags |= HIST_FIELD_SYM;
-   else if (!strcmp(field_str, sym-offset))
-   flags |= HIST_FIELD_SYM_OFFSET;
-   else if (!strcmp(field_str, execname) 
-!strcmp(field_name, common_pid))
-   flags |= HIST_FIELD_EXECNAME;
-   else if (!strcmp(field_str, syscall))
-   flags |= HIST_FIELD_SYSCALL;
-   else {
+   if (!strcmp(field_str, stacktrace)) {
+   flags |= HIST_FIELD_STACKTRACE;
+   key_size = sizeof(unsigned long) * HIST_STACKTRACE_DEPTH;
+   } else {
+   char *field_name = strsep(field_str, .);
+
+   if (field_str) {
+   if (!strcmp(field_str, hex))
+   flags |= HIST_FIELD_HEX;
+   else if (!strcmp(field_str, sym))
+   flags |= HIST_FIELD_SYM;
+  

[PATCH v9 17/22] tracing: Add hist trigger 'syscall' modifier

2015-07-16 Thread Tom Zanussi
Allow users to have syscall id fields displayed as syscall names in
the output by appending '.syscall' to field names:

   # echo hist:keys=aaa.syscall ... \
  [ if filter]  event/trigger

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c |  1 +
 kernel/trace/trace_events_hist.c | 15 +++
 2 files changed, 16 insertions(+)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index a16ab69..75795e3 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3817,6 +3817,7 @@ static const char readme_msg[] =
\t.symdisplay an address as a symbol\n
\t.sym-offset display an address as a symbol and offset\n
\t.execname   display a common_pid as a program name\n\n
+   \t.syscalldisplay a syscall id as a syscall name\n
\tBy default, the size of the hash table is 2048 entries.  The\n
\t'size' param can be used to specify more or fewer than that.\n
\tThe units are in terms of hashtable entries - if a run uses\n
diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index af1b846..28ccaa1 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -76,6 +76,7 @@ enum hist_field_flags {
HIST_FIELD_SYM  = 16,
HIST_FIELD_SYM_OFFSET   = 32,
HIST_FIELD_EXECNAME = 64,
+   HIST_FIELD_SYSCALL  = 128,
 };
 
 struct hist_trigger_attrs {
@@ -452,6 +453,8 @@ static int create_key_field(struct hist_trigger_data 
*hist_data,
else if (!strcmp(field_str, execname) 
 !strcmp(field_name, common_pid))
flags |= HIST_FIELD_EXECNAME;
+   else if (!strcmp(field_str, syscall))
+   flags |= HIST_FIELD_SYSCALL;
else {
ret = -EINVAL;
goto out;
@@ -814,6 +817,16 @@ hist_trigger_entry_print(struct seq_file *m,
uval = *(u64 *)(key + key_field-offset);
seq_printf(m, %s: %-16s[%10llu],
   key_field-field-name, comm, uval);
+   } else if (key_field-flags  HIST_FIELD_SYSCALL) {
+   const char *syscall_name;
+
+   uval = *(u64 *)(key + key_field-offset);
+   syscall_name = get_syscall_name(uval);
+   if (!syscall_name)
+   syscall_name = unknown_syscall;
+
+   seq_printf(m, %s: %-30s[%3llu],
+  key_field-field-name, syscall_name, uval);
} else if (key_field-flags  HIST_FIELD_STRING) {
seq_printf(m, %s: %-35s, key_field-field-name,
   (char *)(key + key_field-offset));
@@ -929,6 +942,8 @@ static const char *get_hist_field_flags(struct hist_field 
*hist_field)
flags_str = sym-offset;
else if (hist_field-flags  HIST_FIELD_EXECNAME)
flags_str = execname;
+   else if (hist_field-flags  HIST_FIELD_SYSCALL)
+   flags_str = syscall;
 
return flags_str;
 }
-- 
1.9.3

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[PATCH v9 20/22] tracing: Remove restriction on string position in hist trigger keys

2015-07-16 Thread Tom Zanussi
If we assume the maximum size for a string field, we don't have to
worry about its position.  Since we only allow two keys in a compound
key and having more than one string key in a given compound key
doesn't make much sense anyway, trading a bit of extra space instead
of introducing an arbitrary restriction makes more sense.

We also need to use the event field size for static strings when
copying the contents, otherwise we get random garbage in the key.

Finally, rearrange the code without changing any functionality by
moving the compound key updating code into a separate function.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace_events_hist.c | 65 +++-
 1 file changed, 37 insertions(+), 28 deletions(-)

diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index 67fffee..4ba7645 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -508,8 +508,8 @@ static int create_key_field(struct hist_trigger_data 
*hist_data,
goto out;
}
 
-   if (is_string_field(field)) /* should be last key field */
-   key_size = HIST_KEY_SIZE_MAX - key_offset;
+   if (is_string_field(field))
+   key_size = MAX_FILTER_STR_VAL;
else
key_size = field-size;
}
@@ -781,9 +781,36 @@ static void hist_trigger_elt_update(struct 
hist_trigger_data *hist_data,
}
 }
 
+static inline void add_to_key(char *compound_key, void *key,
+ struct hist_field *key_field, void *rec)
+{
+   size_t size = key_field-size;
+
+   if (key_field-flags  HIST_FIELD_STRING) {
+   struct ftrace_event_field *field;
+
+   /* ensure NULL-termination */
+   size--;
+
+   field = key_field-field;
+   if (field-filter_type == FILTER_DYN_STRING)
+   size = *(u32 *)(rec + field-offset)  16;
+   else if (field-filter_type == FILTER_PTR_STRING)
+   size = strlen(key);
+   else if (field-filter_type == FILTER_STATIC_STRING)
+   size = field-size;
+
+   if (size  key_field-size - 1)
+   size = key_field-size - 1;
+   }
+
+   memcpy(compound_key + key_field-offset, key, size);
+}
+
 static void event_hist_trigger(struct event_trigger_data *data, void *rec)
 {
struct hist_trigger_data *hist_data = data-private_data;
+   bool use_compound_key = (hist_data-n_keys  1);
unsigned long entries[HIST_STACKTRACE_DEPTH];
char compound_key[HIST_KEY_SIZE_MAX];
struct stack_trace stacktrace;
@@ -798,8 +825,7 @@ static void event_hist_trigger(struct event_trigger_data 
*data, void *rec)
return;
}
 
-   if (hist_data-n_keys  1)
-   memset(compound_key, 0, hist_data-key_size);
+   memset(compound_key, 0, hist_data-key_size);
 
for (i = hist_data-n_vals; i  hist_data-n_fields; i++) {
key_field = hist_data-fields[i];
@@ -816,35 +842,18 @@ static void event_hist_trigger(struct event_trigger_data 
*data, void *rec)
key = entries;
} else {
field_contents = key_field-fn(key_field, rec);
-   if (key_field-flags  HIST_FIELD_STRING)
+   if (key_field-flags  HIST_FIELD_STRING) {
key = (void *)field_contents;
-   else
+   use_compound_key = true;
+   } else
key = (void *)field_contents;
-
-   if (hist_data-n_keys  1) {
-   /* ensure NULL-termination */
-   size_t size = key_field-size - 1;
-
-   if (key_field-flags  HIST_FIELD_STRING) {
-   struct ftrace_event_field *field;
-
-   field = key_field-field;
-   if (field-filter_type == 
FILTER_DYN_STRING)
-   size = *(u32 *)(rec + 
field-offset)  16;
-   else if (field-filter_type == 
FILTER_PTR_STRING)
-   size = strlen(key);
-
-   if (size  key_field-size - 1)
-   size = key_field-size - 1;
-   }
-
-   memcpy(compound_key + key_field-offset, key,
-  size);
-   }
}
+
+   if (use_compound_key)
+   add_to_key(compound_key, key, key_field, rec);
}
 
-

Re: [PATCH 0/5] arm64, pci: Add ECAM/PCIe support for Cavium ThunderX

2015-07-16 Thread Thomas Gleixner
On Wed, 15 Jul 2015, David Daney wrote:

 From: David Daney david.da...@cavium.com
 
 The subject pretty much says it all.  The first four patches tweak the
 infrastructure a little so that we can get required behavior.  The

Just that you avoid to describe what the required behaviour is.

Can you please provide a proper description how this looks like from
the HW side and how you want to map that into software?

Thanks,

tglx

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[PATCH v9 10/22] tracing: Add hist trigger support for compound keys

2015-07-16 Thread Tom Zanussi
Allow users to specify multiple trace event fields to use in keys by
allowing multiple fields in the 'keys=' keyword.  With this addition,
any unique combination of any of the fields named in the 'keys'
keyword will result in a new entry being added to the hash table.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c |  8 +---
 kernel/trace/trace_events_hist.c | 40 ++--
 2 files changed, 35 insertions(+), 13 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 8109b89..1e4801e 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3787,19 +3787,21 @@ static const char readme_msg[] =
\t   Filters can be ignored when removing a trigger.\n
 #ifdef CONFIG_HIST_TRIGGERS
  hist trigger\t- If set, event hits are aggregated into a hash 
table\n
-   \tFormat: hist:keys=field1\n
+   \tFormat: hist:keys=field1[,field2,...]\n
\t[:values=field1[,field2,...]]\n
\t[:size=#entries]\n
\t[if filter]\n\n
\tWhen a matching event is hit, an entry is added to a hash\n
-   \ttable using the key and value(s) named.  Keys and values\n
+   \ttable using the key(s) and value(s) named.  Keys and values\n
\tcorrespond to fields in the event's format description.\n
\tValues must correspond to numeric fields - on an event hit,\n
\tthe value(s) will be added to a sum kept for that field.\n
\tThe special string 'hitcount' can be used in place of an\n
\texplicit value field - this is simply a count of event hits.\n
\tIf 'values' is not specified, 'hitcount' will be assumed.\n
-   \tof event hits.  Keys can be any field.\n\n
+   \tof event hits.  Keys can be any field.  Compound keys\n
+   \tconsisting of up to two fields can be specified by the 'keys'\n
+   \tkeyword.\n\n
\tReading the 'hist' file for the event will dump the hash\n
\ttable in its entirety to stdout.  Each printed hash table\n
\tentry is a simple list of the keys and values comprising the\n
diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index 503df07..3d5433a 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -32,6 +32,7 @@ struct hist_field {
unsigned long   flags;
hist_field_fn_t fn;
unsigned intsize;
+   unsigned intoffset;
 };
 
 static u64 hist_field_counter(struct hist_field *field, void *event)
@@ -64,8 +65,8 @@ DEFINE_HIST_FIELD_FN(s8);
 DEFINE_HIST_FIELD_FN(u8);
 
 #define HITCOUNT_IDX   0
-#define HIST_KEY_MAX   1
-#define HIST_KEY_SIZE_MAX  MAX_FILTER_STR_VAL
+#define HIST_KEY_MAX   2
+#define HIST_KEY_SIZE_MAX  (MAX_FILTER_STR_VAL + sizeof(u64))
 
 enum hist_field_flags {
HIST_FIELD_HITCOUNT = 1,
@@ -327,6 +328,7 @@ static int create_val_fields(struct hist_trigger_data 
*hist_data,
 
 static int create_key_field(struct hist_trigger_data *hist_data,
unsigned int key_idx,
+   unsigned int key_offset,
struct trace_event_file *file,
char *field_str)
 {
@@ -353,7 +355,8 @@ static int create_key_field(struct hist_trigger_data 
*hist_data,
 
key_size = ALIGN(key_size, sizeof(u64));
hist_data-fields[key_idx]-size = key_size;
-   hist_data-key_size = key_size;
+   hist_data-fields[key_idx]-offset = key_offset;
+   hist_data-key_size += key_size;
if (hist_data-key_size  HIST_KEY_SIZE_MAX) {
ret = -EINVAL;
goto out;
@@ -368,7 +371,7 @@ static int create_key_field(struct hist_trigger_data 
*hist_data,
 static int create_key_fields(struct hist_trigger_data *hist_data,
 struct trace_event_file *file)
 {
-   unsigned int i, n_vals = hist_data-n_vals;
+   unsigned int i, key_offset = 0, n_vals = hist_data-n_vals;
char *fields_str, *field_str;
int ret = -EINVAL;
 
@@ -384,9 +387,11 @@ static int create_key_fields(struct hist_trigger_data 
*hist_data,
field_str = strsep(fields_str, ,);
if (!field_str)
break;
-   ret = create_key_field(hist_data, i, file, field_str);
+   ret = create_key_field(hist_data, i, key_offset,
+  file, field_str);
if (ret  0)
goto out;
+   key_offset += ret;
}
if (fields_str) {
ret = -EINVAL;
@@ -451,7 +456,10 @@ static int create_tracing_map_fields(struct 
hist_trigger_data *hist_data)
else

[PATCH v9 13/22] tracing: Add hist trigger support for clearing a trace

2015-07-16 Thread Tom Zanussi
Allow users to append 'clear' to an existing trigger in order to have
the hash table cleared.

This expands the hist trigger syntax from this:
# echo hist:keys=xxx:vals=yyy:sort=zzz.descending:pause/cont \
   [ if filter]  event/trigger

to this:

# echo hist:keys=xxx:vals=yyy:sort=zzz.descending:pause/cont/clear \
  [ if filter]  event/trigger

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c |  4 +++-
 kernel/trace/trace_events_hist.c | 25 -
 2 files changed, 27 insertions(+), 2 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 547bbc8..27daa28 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3791,7 +3791,7 @@ static const char readme_msg[] =
\t[:values=field1[,field2,...]]\n
\t[:sort=field1,field2,...]\n
\t[:size=#entries]\n
-   \t[:pause][:continue]\n
+   \t[:pause][:continue][:clear]\n
\t[if filter]\n\n
\tWhen a matching event is hit, an entry is added to a hash\n
\ttable using the key(s) and value(s) named.  Keys and values\n
@@ -3826,6 +3826,8 @@ static const char readme_msg[] =
\ttrigger or to start a hist trigger but not log any events\n
\tuntil told to do so.  'continue' can be used to start or\n
\trestart a paused hist trigger.\n\n
+   \tThe 'clear' param will clear the contents of a running hist\n
+   \ttrigger and leave its current paused/active state.\n\n
 #endif
 ;
 
diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index 3ae58e7..d8259fe 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -80,6 +80,7 @@ struct hist_trigger_attrs {
char*sort_key_str;
boolpause;
boolcont;
+   boolclear;
unsigned intmap_bits;
 };
 
@@ -188,6 +189,8 @@ static struct hist_trigger_attrs 
*parse_hist_trigger_attrs(char *trigger_str)
attrs-sort_key_str = kstrdup(str, GFP_KERNEL);
else if (!strncmp(str, pause, strlen(pause)))
attrs-pause = true;
+   else if (!strncmp(str, clear, strlen(clear)))
+   attrs-clear = true;
else if (!strncmp(str, continue, strlen(continue)) ||
 !strncmp(str, cont, strlen(cont)))
attrs-cont = true;
@@ -888,6 +891,24 @@ static struct event_trigger_ops 
*event_hist_get_trigger_ops(char *cmd,
return event_hist_trigger_ops;
 }
 
+static void hist_clear(struct event_trigger_data *data)
+{
+   struct hist_trigger_data *hist_data = data-private_data;
+   bool paused;
+
+   paused = data-paused;
+   data-paused = true;
+
+   synchronize_sched();
+
+   tracing_map_clear(hist_data-map);
+
+   atomic64_set(hist_data-total_hits, 0);
+   atomic64_set(hist_data-drops, 0);
+
+   data-paused = paused;
+}
+
 static int hist_register_trigger(char *glob, struct event_trigger_ops *ops,
 struct event_trigger_data *data,
 struct trace_event_file *file)
@@ -902,6 +923,8 @@ static int hist_register_trigger(char *glob, struct 
event_trigger_ops *ops,
test-paused = true;
else if (hist_data-attrs-cont)
test-paused = false;
+   else if (hist_data-attrs-clear)
+   hist_clear(test);
else
ret = -EEXIST;
goto out;
@@ -1003,7 +1026,7 @@ static int event_hist_trigger_func(struct event_command 
*cmd_ops,
 * triggers registered a failure too.
 */
if (!ret) {
-   if (!(attrs-pause || attrs-cont))
+   if (!(attrs-pause || attrs-cont || attrs-clear))
ret = -ENOENT;
goto out_free;
} else if (ret  0)
-- 
1.9.3

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[PATCH v9 12/22] tracing: Add hist trigger support for pausing and continuing a trace

2015-07-16 Thread Tom Zanussi
Allow users to append 'pause' or 'continue' to an existing trigger in
order to have it paused or to have a paused trace continue.

This expands the hist trigger syntax from this:
# echo hist:keys=xxx:vals=yyy:sort=zzz.descending \
  [ if filter]  event/trigger

to this:

# echo hist:keys=xxx:vals=yyy:sort=zzz.descending:pause or cont \
  [ if filter]  event/trigger

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c |  5 +
 kernel/trace/trace_events_hist.c | 26 +++---
 2 files changed, 28 insertions(+), 3 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index 5dd1fc4..547bbc8 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3791,6 +3791,7 @@ static const char readme_msg[] =
\t[:values=field1[,field2,...]]\n
\t[:sort=field1,field2,...]\n
\t[:size=#entries]\n
+   \t[:pause][:continue]\n
\t[if filter]\n\n
\tWhen a matching event is hit, an entry is added to a hash\n
\ttable using the key(s) and value(s) named.  Keys and values\n
@@ -3821,6 +3822,10 @@ static const char readme_msg[] =
\ton.  The default if unspecified is 'hitcount' and the.\n
\tdefault sort order is 'ascending'.  To sort in the opposite\n
\tdirection, append .descending' to the sort key.\n\n
+   \tThe 'pause' param can be used to pause an existing hist\n
+   \ttrigger or to start a hist trigger but not log any events\n
+   \tuntil told to do so.  'continue' can be used to start or\n
+   \trestart a paused hist trigger.\n\n
 #endif
 ;
 
diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index 6bf224f..3ae58e7 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -78,6 +78,8 @@ struct hist_trigger_attrs {
char*keys_str;
char*vals_str;
char*sort_key_str;
+   boolpause;
+   boolcont;
unsigned intmap_bits;
 };
 
@@ -184,6 +186,11 @@ static struct hist_trigger_attrs 
*parse_hist_trigger_attrs(char *trigger_str)
attrs-vals_str = kstrdup(str, GFP_KERNEL);
else if (!strncmp(str, sort, strlen(sort)))
attrs-sort_key_str = kstrdup(str, GFP_KERNEL);
+   else if (!strncmp(str, pause, strlen(pause)))
+   attrs-pause = true;
+   else if (!strncmp(str, continue, strlen(continue)) ||
+!strncmp(str, cont, strlen(cont)))
+   attrs-cont = true;
else if (!strncmp(str, size, strlen(size))) {
int map_bits = parse_map_size(str);
 
@@ -843,7 +850,10 @@ static int event_hist_trigger_print(struct seq_file *m,
if (data-filter_str)
seq_printf(m,  if %s, data-filter_str);
 
-   seq_puts(m,  [active]);
+   if (data-paused)
+   seq_puts(m,  [paused]);
+   else
+   seq_puts(m,  [active]);
 
seq_putc(m, '\n');
 
@@ -882,16 +892,25 @@ static int hist_register_trigger(char *glob, struct 
event_trigger_ops *ops,
 struct event_trigger_data *data,
 struct trace_event_file *file)
 {
+   struct hist_trigger_data *hist_data = data-private_data;
struct event_trigger_data *test;
int ret = 0;
 
list_for_each_entry_rcu(test, file-triggers, list) {
if (test-cmd_ops-trigger_type == ETT_EVENT_HIST) {
-   ret = -EEXIST;
+   if (hist_data-attrs-pause)
+   test-paused = true;
+   else if (hist_data-attrs-cont)
+   test-paused = false;
+   else
+   ret = -EEXIST;
goto out;
}
}
 
+   if (hist_data-attrs-pause)
+   data-paused = true;
+
if (data-ops-init) {
ret = data-ops-init(data-ops, data);
if (ret  0)
@@ -984,7 +1003,8 @@ static int event_hist_trigger_func(struct event_command 
*cmd_ops,
 * triggers registered a failure too.
 */
if (!ret) {
-   ret = -ENOENT;
+   if (!(attrs-pause || attrs-cont))
+   ret = -ENOENT;
goto out_free;
} else if (ret  0)
goto out_free;
-- 
1.9.3

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[PATCH v9 09/22] tracing: Add hist trigger support for multiple values ('vals=' param)

2015-07-16 Thread Tom Zanussi
Allow users to specify trace event fields to use in aggregated sums
via a new 'vals=' keyword.  Before this addition, the only aggregated
sum supported was the implied value 'hitcount'.  With this addition,
'hitcount' is also supported as an explicit value field, as is any
numeric trace event field.

This expands the hist trigger syntax from this:

  # echo hist:keys=xxx [ if filter]  event/trigger

to this:

  # echo hist:keys=xxx:vals=yyy [ if filter]  event/trigger

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c | 11 --
 kernel/trace/trace_events_hist.c | 75 +++-
 2 files changed, 82 insertions(+), 4 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index f6fdda2..8109b89 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -3788,12 +3788,17 @@ static const char readme_msg[] =
 #ifdef CONFIG_HIST_TRIGGERS
  hist trigger\t- If set, event hits are aggregated into a hash 
table\n
\tFormat: hist:keys=field1\n
+   \t[:values=field1[,field2,...]]\n
\t[:size=#entries]\n
\t[if filter]\n\n
\tWhen a matching event is hit, an entry is added to a hash\n
-   \ttable using the key named.  Keys correspond to fields in the\n
-   \tevent's format description.  On an event hit, the value of a\n
-   \tsum called 'hitcount' is incremented, which is simply a count\n
+   \ttable using the key and value(s) named.  Keys and values\n
+   \tcorrespond to fields in the event's format description.\n
+   \tValues must correspond to numeric fields - on an event hit,\n
+   \tthe value(s) will be added to a sum kept for that field.\n
+   \tThe special string 'hitcount' can be used in place of an\n
+   \texplicit value field - this is simply a count of event hits.\n
+   \tIf 'values' is not specified, 'hitcount' will be assumed.\n
\tof event hits.  Keys can be any field.\n\n
\tReading the 'hist' file for the event will dump the hash\n
\ttable in its entirety to stdout.  Each printed hash table\n
diff --git a/kernel/trace/trace_events_hist.c b/kernel/trace/trace_events_hist.c
index ded348b..503df07 100644
--- a/kernel/trace/trace_events_hist.c
+++ b/kernel/trace/trace_events_hist.c
@@ -75,6 +75,7 @@ enum hist_field_flags {
 
 struct hist_trigger_attrs {
char*keys_str;
+   char*vals_str;
unsigned intmap_bits;
 };
 
@@ -155,6 +156,7 @@ static int parse_map_size(char *str)
 static void destroy_hist_trigger_attrs(struct hist_trigger_attrs *attrs)
 {
kfree(attrs-keys_str);
+   kfree(attrs-vals_str);
kfree(attrs);
 }
 
@@ -173,6 +175,10 @@ static struct hist_trigger_attrs 
*parse_hist_trigger_attrs(char *trigger_str)
if (!strncmp(str, keys, strlen(keys)) ||
!strncmp(str, key, strlen(key)))
attrs-keys_str = kstrdup(str, GFP_KERNEL);
+   else if (!strncmp(str, values, strlen(values)) ||
+!strncmp(str, vals, strlen(vals)) ||
+!strncmp(str, val, strlen(val)))
+   attrs-vals_str = kstrdup(str, GFP_KERNEL);
else if (!strncmp(str, size, strlen(size))) {
int map_bits = parse_map_size(str);
 
@@ -256,13 +262,66 @@ static int create_hitcount_val(struct hist_trigger_data 
*hist_data)
return 0;
 }
 
+static int create_val_field(struct hist_trigger_data *hist_data,
+   unsigned int val_idx,
+   struct trace_event_file *file,
+   char *field_str)
+{
+   struct ftrace_event_field *field = NULL;
+   unsigned long flags = 0;
+   int ret = 0;
+
+   field = trace_find_event_field(file-event_call, field_str);
+   if (!field) {
+   ret = -EINVAL;
+   goto out;
+   }
+
+   hist_data-fields[val_idx] = create_hist_field(field, flags);
+   if (!hist_data-fields[val_idx]) {
+   ret = -ENOMEM;
+   goto out;
+   }
+   hist_data-n_vals++;
+ out:
+   return ret;
+}
+
 static int create_val_fields(struct hist_trigger_data *hist_data,
 struct trace_event_file *file)
 {
+   unsigned int vals_max = TRACING_MAP_FIELDS_MAX - TRACING_MAP_KEYS_MAX;
+   char *fields_str, *field_str;
+   unsigned int i, j;
int ret;
 
ret = create_hitcount_val(hist_data);
+   if (ret)
+   goto out;
 
+   fields_str = hist_data-attrs-vals_str;
+   if (!fields_str)
+   goto out;
+
+   strsep(fields_str, =);
+   if (!fields_str)
+   goto out;
+
+   vals_max = TRACING_MAP_FIELDS_MAX - TRACING_MAP_KEYS_MAX;
+
+   for (i = 0, j = 1; i  vals_max; i++) {
+  

[PATCH v9 05/22] tracing: Add get_syscall_name()

2015-07-16 Thread Tom Zanussi
Add a utility function to grab the syscall name from the syscall
metadata, given a syscall id.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.h  |  5 +
 kernel/trace/trace_syscalls.c | 11 +++
 2 files changed, 16 insertions(+)

diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 8799348..6fe5b66 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -1331,8 +1331,13 @@ int perf_ftrace_event_register(struct trace_event_call 
*call,
 
 #ifdef CONFIG_FTRACE_SYSCALLS
 void init_ftrace_syscalls(void);
+const char *get_syscall_name(int syscall);
 #else
 static inline void init_ftrace_syscalls(void) { }
+static inline const char *get_syscall_name(int syscall)
+{
+   return NULL;
+}
 #endif
 
 #ifdef CONFIG_EVENT_TRACING
diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
index 7d567a4..004c111 100644
--- a/kernel/trace/trace_syscalls.c
+++ b/kernel/trace/trace_syscalls.c
@@ -106,6 +106,17 @@ static struct syscall_metadata *syscall_nr_to_meta(int nr)
return syscalls_metadata[nr];
 }
 
+const char *get_syscall_name(int syscall)
+{
+   struct syscall_metadata *entry;
+
+   entry = syscall_nr_to_meta(syscall);
+   if (!entry)
+   return NULL;
+
+   return entry-name;
+}
+
 static enum print_line_t
 print_syscall_enter(struct trace_iterator *iter, int flags,
struct trace_event *event)
-- 
1.9.3

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[PATCH v9 07/22] tracing: Add lock-free tracing_map

2015-07-16 Thread Tom Zanussi
Add tracing_map, a special-purpose lock-free map for tracing.

tracing_map is designed to aggregate or 'sum' one or more values
associated with a specific object of type tracing_map_elt, which
is associated by the map to a given key.

It provides various hooks allowing per-tracer customization and is
separated out into a separate file in order to allow it to be shared
between multiple tracers, but isn't meant to be generally used outside
of that context.

The tracing_map implementation was inspired by lock-free map
algorithms originated by Dr. Cliff Click:

 http://www.azulsystems.com/blog/cliff/2007-03-26-non-blocking-hashtable
 http://www.azulsystems.com/events/javaone_2007/2007_LockFreeHash.pdf

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/Makefile  |   1 +
 kernel/trace/tracing_map.c | 935 +
 kernel/trace/tracing_map.h | 258 +
 3 files changed, 1194 insertions(+)
 create mode 100644 kernel/trace/tracing_map.c
 create mode 100644 kernel/trace/tracing_map.h

diff --git a/kernel/trace/Makefile b/kernel/trace/Makefile
index 9b1044e..3b26cfb 100644
--- a/kernel/trace/Makefile
+++ b/kernel/trace/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_TRACING) += trace_output.o
 obj-$(CONFIG_TRACING) += trace_seq.o
 obj-$(CONFIG_TRACING) += trace_stat.o
 obj-$(CONFIG_TRACING) += trace_printk.o
+obj-$(CONFIG_TRACING) += tracing_map.o
 obj-$(CONFIG_CONTEXT_SWITCH_TRACER) += trace_sched_switch.o
 obj-$(CONFIG_FUNCTION_TRACER) += trace_functions.o
 obj-$(CONFIG_IRQSOFF_TRACER) += trace_irqsoff.o
diff --git a/kernel/trace/tracing_map.c b/kernel/trace/tracing_map.c
new file mode 100644
index 000..a505025
--- /dev/null
+++ b/kernel/trace/tracing_map.c
@@ -0,0 +1,935 @@
+/*
+ * tracing_map - lock-free map for tracing
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Copyright (C) 2015 Tom Zanussi tom.zanu...@linux.intel.com
+ *
+ * tracing_map implementation inspired by lock-free map algorithms
+ * originated by Dr. Cliff Click:
+ *
+ * http://www.azulsystems.com/blog/cliff/2007-03-26-non-blocking-hashtable
+ * http://www.azulsystems.com/events/javaone_2007/2007_LockFreeHash.pdf
+ */
+
+#include linux/slab.h
+#include linux/jhash.h
+#include linux/sort.h
+
+#include tracing_map.h
+#include trace.h
+
+/*
+ * NOTE: For a detailed description of the data structures used by
+ * these functions (such as tracing_map_elt) please see the overview
+ * of tracing_map data structures at the beginning of tracing_map.h.
+ */
+
+/**
+ * tracing_map_update_sum - Add a value to a tracing_map_elt's sum field
+ * @elt: The tracing_map_elt
+ * @i: The index of the given sum associated with the tracing_map_elt
+ * @n: The value to add to the sum
+ *
+ * Add n to sum i associated with the specified tracing_map_elt
+ * instance.  The index i is the index returned by the call to
+ * tracing_map_add_sum_field() when the tracing map was set up.
+ */
+void tracing_map_update_sum(struct tracing_map_elt *elt, unsigned int i, u64 n)
+{
+   atomic64_add(n, elt-fields[i].sum);
+}
+
+/**
+ * tracing_map_read_sum - Return the value of a tracing_map_elt's sum field
+ * @elt: The tracing_map_elt
+ * @i: The index of the given sum associated with the tracing_map_elt
+ *
+ * Retrieve the value of the sum i associated with the specified
+ * tracing_map_elt instance.  The index i is the index returned by the
+ * call to tracing_map_add_sum_field() when the tracing map was set
+ * up.
+ *
+ * Return: The sum associated with field i for elt.
+ */
+u64 tracing_map_read_sum(struct tracing_map_elt *elt, unsigned int i)
+{
+   return (u64)atomic64_read(elt-fields[i].sum);
+}
+
+int tracing_map_cmp_string(void *val_a, void *val_b)
+{
+   char *a = val_a;
+   char *b = val_b;
+
+   return strcmp(a, b);
+}
+
+int tracing_map_cmp_none(void *val_a, void *val_b)
+{
+   return 0;
+}
+
+static int tracing_map_cmp_atomic64(void *val_a, void *val_b)
+{
+   u64 a = atomic64_read((atomic64_t *)val_a);
+   u64 b = atomic64_read((atomic64_t *)val_b);
+
+   return (a  b) ? 1 : ((a  b) ? -1 : 0);
+}
+
+#define DEFINE_TRACING_MAP_CMP_FN(type)
\
+static int tracing_map_cmp_##type(void *val_a, void *val_b)\
+{  \
+   type a = *(type *)val_a;\
+   type b = *(type *)val_b;\
+  

[GIT PULL] Block fixes for 4.2-rc2

2015-07-16 Thread Jens Axboe
Hi Linus,

A collection of fixes from the last few weeks that should go into the
current series. This pull request contains:

- Various fixes for the per-blkcg policy data, fixing regressions since
  4.1 From Arianna and Tejun.

- Code cleanup for bcache closure macros from me. Really just flushing
  this out, it's been sitting in another branch for months.

- FIELD_SIZEOF cleanup from Maninder Singh.

- bio integrity oops fix from Mike.

- Timeout regression fix for blk-mq from Ming Lei.

Please pull!


  git://git.kernel.dk/linux-block.git for-linus



Arianna Avanzini (1):
  block/blk-cgroup.c: free per-blkcg data when freeing the blkcg

Jens Axboe (1):
  bcache: don't embed 'return' statements in closure macros

Keith Busch (1):
  NVMe: Reread partitions on metadata formats

Maninder Singh (1):
  block: use FIELD_SIZEOF to calculate size of a field

Mike Snitzer (1):
  bio integrity: do not assume bio_integrity_pool exists if bioset exists

Ming Lei (1):
  blk-mq: set default timeout as 30 seconds

Tejun Heo (4):
  blkcg: allow blkcg_pol_mutex to be grabbed from cgroup [file] methods
  blkcg: blkcg_css_alloc() should grab blkcg_pol_mutex while iterating 
blkcg_policy[]
  blkcg: implement all_blkcgs list
  blkcg: fix blkcg_policy_data allocation bug

 block/bio-integrity.c   |   4 +-
 block/blk-cgroup.c  | 140 +---
 block/blk-core.c|   2 +-
 block/blk-mq.c  |   2 +-
 drivers/block/nvme-core.c   |  13 +++-
 drivers/md/bcache/closure.h |   3 -
 drivers/md/bcache/io.c  |   1 +
 drivers/md/bcache/journal.c |   2 +
 drivers/md/bcache/request.c |  14 -
 include/linux/blk-cgroup.h  |  11 +---
 10 files changed, 113 insertions(+), 79 deletions(-)

-- 
Jens Axboe

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[PATCH v9 06/22] tracing: Add a per-event-trigger 'paused' field

2015-07-16 Thread Tom Zanussi
Add a simple per-trigger 'paused' flag, allowing individual triggers
to pause.  We could leave it to individual triggers that need this
functionality to do it themselves, but we also want to allow other
events to control pausing, so add it to the trigger data.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.h| 1 +
 kernel/trace/trace_events_trigger.c | 4 
 2 files changed, 5 insertions(+)

diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 6fe5b66..5e675b2 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -1110,6 +1110,7 @@ struct event_trigger_data {
struct event_filter __rcu   *filter;
char*filter_str;
void*private_data;
+   boolpaused;
struct list_headlist;
 };
 
diff --git a/kernel/trace/trace_events_trigger.c 
b/kernel/trace/trace_events_trigger.c
index e30539c..5f632ff 100644
--- a/kernel/trace/trace_events_trigger.c
+++ b/kernel/trace/trace_events_trigger.c
@@ -72,6 +72,8 @@ event_triggers_call(struct trace_event_file *file, void *rec)
return tt;
 
list_for_each_entry_rcu(data, file-triggers, list) {
+   if (data-paused)
+   continue;
if (!rec) {
data-ops-func(data, rec);
continue;
@@ -109,6 +111,8 @@ event_triggers_post_call(struct trace_event_file *file,
struct event_trigger_data *data;
 
list_for_each_entry_rcu(data, file-triggers, list) {
+   if (data-paused)
+   continue;
if (data-cmd_ops-trigger_type  tt)
data-ops-func(data, rec);
}
-- 
1.9.3

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[PATCH v9 04/22] tracing: Add event record param to trigger_ops.func()

2015-07-16 Thread Tom Zanussi
Some triggers may need access to the trace event, so pass it in.  Also
fix up the existing trigger funcs and their callers.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 include/linux/trace_events.h|  7 ---
 kernel/trace/trace.h|  6 --
 kernel/trace/trace_events_trigger.c | 35 ++-
 3 files changed, 26 insertions(+), 22 deletions(-)

diff --git a/include/linux/trace_events.h b/include/linux/trace_events.h
index 1063c85..d9b0f89 100644
--- a/include/linux/trace_events.h
+++ b/include/linux/trace_events.h
@@ -423,7 +423,8 @@ extern int call_filter_check_discard(struct 
trace_event_call *call, void *rec,
 extern enum event_trigger_type event_triggers_call(struct trace_event_file 
*file,
   void *rec);
 extern void event_triggers_post_call(struct trace_event_file *file,
-enum event_trigger_type tt);
+enum event_trigger_type tt,
+void *rec);
 
 /**
  * trace_trigger_soft_disabled - do triggers and test if soft disabled
@@ -506,7 +507,7 @@ event_trigger_unlock_commit(struct trace_event_file *file,
trace_buffer_unlock_commit(buffer, event, irq_flags, pc);
 
if (tt)
-   event_triggers_post_call(file, tt);
+   event_triggers_post_call(file, tt, entry);
 }
 
 /**
@@ -539,7 +540,7 @@ event_trigger_unlock_commit_regs(struct trace_event_file 
*file,
irq_flags, pc, regs);
 
if (tt)
-   event_triggers_post_call(file, tt);
+   event_triggers_post_call(file, tt, entry);
 }
 
 #ifdef CONFIG_BPF_SYSCALL
diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 4ff33b7..8799348 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -1139,7 +1139,8 @@ extern int register_event_command(struct event_command 
*cmd);
  * @func: The trigger 'probe' function called when the triggering
  * event occurs.  The data passed into this callback is the data
  * that was supplied to the event_command @reg() function that
- * registered the trigger (see struct event_command).
+ * registered the trigger (see struct event_command) along with
+ * the trace record, rec.
  *
  * @init: An optional initialization function called for the trigger
  * when the trigger is registered (via the event_command reg()
@@ -1164,7 +1165,8 @@ extern int register_event_command(struct event_command 
*cmd);
  * (see trace_event_triggers.c).
  */
 struct event_trigger_ops {
-   void(*func)(struct event_trigger_data *data);
+   void(*func)(struct event_trigger_data *data,
+   void *rec);
int (*init)(struct event_trigger_ops *ops,
struct event_trigger_data *data);
void(*free)(struct event_trigger_ops *ops,
diff --git a/kernel/trace/trace_events_trigger.c 
b/kernel/trace/trace_events_trigger.c
index 6087052..e30539c 100644
--- a/kernel/trace/trace_events_trigger.c
+++ b/kernel/trace/trace_events_trigger.c
@@ -73,7 +73,7 @@ event_triggers_call(struct trace_event_file *file, void *rec)
 
list_for_each_entry_rcu(data, file-triggers, list) {
if (!rec) {
-   data-ops-func(data);
+   data-ops-func(data, rec);
continue;
}
filter = rcu_dereference_sched(data-filter);
@@ -83,7 +83,7 @@ event_triggers_call(struct trace_event_file *file, void *rec)
tt |= data-cmd_ops-trigger_type;
continue;
}
-   data-ops-func(data);
+   data-ops-func(data, rec);
}
return tt;
 }
@@ -103,13 +103,14 @@ EXPORT_SYMBOL_GPL(event_triggers_call);
  */
 void
 event_triggers_post_call(struct trace_event_file *file,
-enum event_trigger_type tt)
+enum event_trigger_type tt,
+void *rec)
 {
struct event_trigger_data *data;
 
list_for_each_entry_rcu(data, file-triggers, list) {
if (data-cmd_ops-trigger_type  tt)
-   data-ops-func(data);
+   data-ops-func(data, rec);
}
 }
 EXPORT_SYMBOL_GPL(event_triggers_post_call);
@@ -750,7 +751,7 @@ int set_trigger_filter(char *filter_str,
 }
 
 static void
-traceon_trigger(struct event_trigger_data *data)
+traceon_trigger(struct event_trigger_data *data, void *rec)
 {
if (tracing_is_on())
return;
@@ -759,7 +760,7 @@ traceon_trigger(struct event_trigger_data *data)
 }
 
 static void
-traceon_count_trigger(struct event_trigger_data *data)
+traceon_count_trigger(struct event_trigger_data *data, void *rec)
 {
  

[PATCH v9 02/22] tracing: Make ftrace_event_field checking functions available

2015-07-16 Thread Tom Zanussi
Make is_string_field() and is_function_field() accessible outside of
trace_event_filters.c for other users of ftrace_event_fields.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.h   | 12 
 kernel/trace/trace_events_filter.c | 12 
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/kernel/trace/trace.h b/kernel/trace/trace.h
index 4c41fcd..891c5b0 100644
--- a/kernel/trace/trace.h
+++ b/kernel/trace/trace.h
@@ -1050,6 +1050,18 @@ struct filter_pred {
unsigned short  right;
 };
 
+static inline bool is_string_field(struct ftrace_event_field *field)
+{
+   return field-filter_type == FILTER_DYN_STRING ||
+  field-filter_type == FILTER_STATIC_STRING ||
+  field-filter_type == FILTER_PTR_STRING;
+}
+
+static inline bool is_function_field(struct ftrace_event_field *field)
+{
+   return field-filter_type == FILTER_TRACE_FN;
+}
+
 extern enum regex_type
 filter_parse_regex(char *buff, int len, char **search, int *not);
 extern void print_event_filter(struct trace_event_file *file,
diff --git a/kernel/trace/trace_events_filter.c 
b/kernel/trace/trace_events_filter.c
index 71511eb..245ee5d 100644
--- a/kernel/trace/trace_events_filter.c
+++ b/kernel/trace/trace_events_filter.c
@@ -917,18 +917,6 @@ int filter_assign_type(const char *type)
return FILTER_OTHER;
 }
 
-static bool is_function_field(struct ftrace_event_field *field)
-{
-   return field-filter_type == FILTER_TRACE_FN;
-}
-
-static bool is_string_field(struct ftrace_event_field *field)
-{
-   return field-filter_type == FILTER_DYN_STRING ||
-  field-filter_type == FILTER_STATIC_STRING ||
-  field-filter_type == FILTER_PTR_STRING;
-}
-
 static int is_legal_op(struct ftrace_event_field *field, int op)
 {
if (is_string_field(field) 
-- 
1.9.3

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Re: [PATCH 4/5] irqchip: gic-v3: Add gic_get_irq_domain() to get the irqdomain of the GIC.

2015-07-16 Thread Marc Zyngier
On 16/07/15 18:14, David Daney wrote:
 On 07/16/2015 10:09 AM, Marc Zyngier wrote:
 On 16/07/15 17:50, David Daney wrote:
 [...]
 Patch 5 has established that you're using virtual wire SPIs, so we
 need to work on exposing that with the normal kernel abstraction, and
 not by messing with the internals of the GIC.


 Agreed.

 The MSI system has pci_enable_msix()/pci_disable_msix().

 I would propose something like:

 struct gic_spi_entry {
 int spi   /* SPI number */
 int irq;  /* kernel irq number mapped to the spi*/
 u32 msg;  /* message to be written */
 u64 assert_addr;
 u64 deassert_addr;
 };

 /* Fill in the SPI processing information */
 int gic_map_spi(int spi, struct gic_spi_entry *data);

 Neither.

 The way to do it is to make this a *separate* IRQ domain stacked onto
 the SPI domain. No funky hook on the side. If it doesn't go through the
 normal kernel API, it doesn't reach the GIC.
 
 Yes, the irqdomain does handle mapping SPI - irq, and the message can 
 be derived from the SPI.  However, the irqdomain infrastructure cannot 
 supply values for either assert_addr or deassert_addr.

This is why I suggested earlier (in my reply to patch 5) that you have a
look at the series I posted a couple of days ago to implement non-PCI
MSI support. This would allow you to compose the domains as such:

platform-MSI - message-SPI - GIC

You'd end up with a msi_msg containing the GICD_SETSPI_NSR doorbell, and
the SPI as a payload.

 Those are needed in order to use SPI.  How would you suggest that they 
 be obtained?

Two possibilities: either you derive GICD_CLRSPI_NSR by adding 8 to the
doorbell you got from the msi_msg structure (ugly, but limited to your
own code), or you extend msi_msg to cater for this case.

Thanks,

M.
-- 
Jazz is not dead. It just smells funny...
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[PATCH 00/28] arch: Provide atomic logic ops

2015-07-16 Thread Peter Zijlstra
Currently there is an incoherent mess of atomic_{set,clear}_mask() and
atomic_or() (but no atomic_{and,nand,xor}()) in the tree.

Those archs that implement atomic_{set,clear}_mask() are not even consistent on
its signature.

Implement atomic_{or,and,xor}() on all archs and deprecate
atomic_{set,clear}_mask().

The series has been compile tested by the build-bot, no known failures at this 
time.

I would like to take this through tip; I'll ask Ingo to put it in a separate
branch such that people can pull in that branch if there is conflicting work
elsewhere (Will has some for Argh64).


Changes since lst time:

 - Quite a few build fails fixed, most notable would be that each arch
   now defines CONFIG_ARCH_HAS_ATOMIC_OR for a little while -- we take it
   out again later.

 - FRV has some extra magic that allows the inline assembly to correctly
   work as inline functions.

 - TILE patch contributed by Chris -- Thanks!

 - A little extention to lib/atomic64_test.c that compile tests the new
   primitives.

 - Alpha, fixed ASM due to fallout from actually trying to compile things.

 - H8300, somehow I had overlooked it previously.

 - Added atomic_andnot() to a few archs that have that instruction to test that.

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[PATCH 09/28] ia64: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/ia64/include/asm/atomic.h |   26 ++
 1 file changed, 22 insertions(+), 4 deletions(-)

--- a/arch/ia64/include/asm/atomic.h
+++ b/arch/ia64/include/asm/atomic.h
@@ -45,8 +45,6 @@ ia64_atomic_##op (int i, atomic_t *v)
 ATOMIC_OP(add, +)
 ATOMIC_OP(sub, -)
 
-#undef ATOMIC_OP
-
 #define atomic_add_return(i,v) \
 ({ \
int __ia64_aar_i = (i); \
@@ -71,6 +69,18 @@ ATOMIC_OP(sub, -)
: ia64_atomic_sub(__ia64_asr_i, v); \
 })
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, )
+ATOMIC_OP(or, |)
+ATOMIC_OP(xor, ^)
+
+#define atomic_and(i,v)(void)ia64_atomic_and(i,v)
+#define atomic_or(i,v) (void)ia64_atomic_or(i,v)
+#define atomic_xor(i,v)(void)ia64_atomic_xor(i,v)
+
+#undef ATOMIC_OP
+
 #define ATOMIC64_OP(op, c_op)  \
 static __inline__ long \
 ia64_atomic64_##op (__s64 i, atomic64_t *v)\
@@ -89,8 +99,6 @@ ia64_atomic64_##op (__s64 i, atomic64_t
 ATOMIC64_OP(add, +)
 ATOMIC64_OP(sub, -)
 
-#undef ATOMIC64_OP
-
 #define atomic64_add_return(i,v)   \
 ({ \
long __ia64_aar_i = (i);\
@@ -115,6 +123,16 @@ ATOMIC64_OP(sub, -)
: ia64_atomic64_sub(__ia64_asr_i, v);   \
 })
 
+ATOMIC64_OP(and, )
+ATOMIC64_OP(or, |)
+ATOMIC64_OP(xor, ^)
+
+#define atomic64_and(i,v)  (void)ia64_atomic64_and(i,v)
+#define atomic64_or(i,v)   (void)ia64_atomic64_or(i,v)
+#define atomic64_xor(i,v)  (void)ia64_atomic64_xor(i,v)
+
+#undef ATOMIC64_OP
+
 #define atomic_cmpxchg(v, old, new) (cmpxchg(((v)-counter), old, new))
 #define atomic_xchg(v, new) (xchg(((v)-counter), new))
 


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Re: [mminit] [ INFO: possible recursive locking detected ]

2015-07-16 Thread Peter Zijlstra
On Thu, Jul 16, 2015 at 08:13:38PM +0300, Konstantin Khlebnikov wrote:
 Rw-sem have special non-owner mode for keeping lockdep away.


Nooo, no new ones of those please!!
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[PATCH 21/28] x86: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.


Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/x86/include/asm/atomic.h  |   35 ++-
 arch/x86/include/asm/atomic64_32.h |   14 ++
 arch/x86/include/asm/atomic64_64.h |   15 +++
 3 files changed, 55 insertions(+), 9 deletions(-)

--- a/arch/x86/include/asm/atomic.h
+++ b/arch/x86/include/asm/atomic.h
@@ -182,6 +182,23 @@ static inline int atomic_xchg(atomic_t *
return xchg(v-counter, new);
 }
 
+#define ATOMIC_OP(op)  \
+static inline void atomic_##op(int i, atomic_t *v) \
+{  \
+   asm volatile(LOCK_PREFIX #opl %1,%0   \
+   : +m (v-counter) \
+   : ir (i)  \
+   : memory);\
+}
+
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
+#undef ATOMIC_OP
+
 /**
  * __atomic_add_unless - add unless the number is already a given value
  * @v: pointer of type atomic_t
@@ -219,15 +236,15 @@ static __always_inline short int atomic_
return *v;
 }
 
-/* These are x86-specific, used by some header files */
-#define atomic_clear_mask(mask, addr)  \
-   asm volatile(LOCK_PREFIX andl %0,%1   \
-: : r (~(mask)), m (*(addr)) : memory)
-
-#define atomic_set_mask(mask, addr)\
-   asm volatile(LOCK_PREFIX orl %0,%1\
-: : r ((unsigned)(mask)), m (*(addr))  \
-: memory)
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
+{
+   atomic_and(~mask, v);
+}
+
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+   atomic_or(mask, v);
+}
 
 #ifdef CONFIG_X86_32
 # include asm/atomic64_32.h
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -313,4 +313,18 @@ static inline long long atomic64_dec_if_
 #undef alternative_atomic64
 #undef __alternative_atomic64
 
+#define ATOMIC64_OP(op, c_op)  \
+static inline void atomic64_##op(long long i, atomic64_t *v)   \
+{  \
+   long long old, c = 0;   \
+   while ((old = atomic64_cmpxchg(v, c, c c_op i)) != c)   \
+   c = old;\
+}
+
+ATOMIC64_OP(and, )
+ATOMIC64_OP(or, |)
+ATOMIC64_OP(xor, ^)
+
+#undef ATOMIC64_OP
+
 #endif /* _ASM_X86_ATOMIC64_32_H */
--- a/arch/x86/include/asm/atomic64_64.h
+++ b/arch/x86/include/asm/atomic64_64.h
@@ -220,4 +220,19 @@ static inline long atomic64_dec_if_posit
return dec;
 }
 
+#define ATOMIC64_OP(op)
\
+static inline void atomic64_##op(long i, atomic64_t *v)
\
+{  \
+   asm volatile(LOCK_PREFIX #opq %1,%0   \
+   : +m (v-counter) \
+   : er (i)  \
+   : memory);\
+}
+
+ATOMIC64_OP(and)
+ATOMIC64_OP(or)
+ATOMIC64_OP(xor)
+
+#undef ATOMIC64_OP
+
 #endif /* _ASM_X86_ATOMIC64_64_H */


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[PATCH 06/28] avr32: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/avr32/include/asm/atomic.h |   14 ++
 1 file changed, 14 insertions(+)

--- a/arch/avr32/include/asm/atomic.h
+++ b/arch/avr32/include/asm/atomic.h
@@ -44,6 +44,20 @@ static inline int __atomic_##op##_return
 ATOMIC_OP_RETURN(sub, sub, rKs21)
 ATOMIC_OP_RETURN(add, add, r)
 
+#define ATOMIC_OP(op, asm_op)  \
+ATOMIC_OP_RETURN(op, asm_op, r)
\
+static inline void atomic_##op(int i, atomic_t *v) \
+{  \
+   (void)__atomic_##op##_return(i, v); \
+}
+
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, and)
+ATOMIC_OP(or, or)
+ATOMIC_OP(xor, eor)
+
+#undef ATOMIC_OP
 #undef ATOMIC_OP_RETURN
 
 /*


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[PATCH 23/28] h8300: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Also rework the atomic implementation in terms of CPP macros to avoid
the typical repetition -- I seem to have missed this arch the last
time around when I did that.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/h8300/include/asm/atomic.h |  147 
 1 file changed, 46 insertions(+), 101 deletions(-)

--- a/arch/h8300/include/asm/atomic.h
+++ b/arch/h8300/include/asm/atomic.h
@@ -16,83 +16,54 @@
 
 #include linux/kernel.h
 
-static inline int atomic_add_return(int i, atomic_t *v)
-{
-   h8300flags flags;
-   int ret;
+#define ATOMIC_OP_RETURN(op, c_op) \
+static inline int atomic_##op##_return(int i, atomic_t *v) \
+{  \
+   h8300flags flags;   \
+   int ret;\
+   \
+   flags = arch_local_irq_save();  \
+   ret = v-counter c_op i;\
+   arch_local_irq_restore(flags);  \
+   return ret; \
+}
+
+#define ATOMIC_OP(op, c_op)\
+static inline void atomic_##op(int i, atomic_t *v) \
+{  \
+   h8300flags flags;   \
+   \
+   flags = arch_local_irq_save();  \
+   v-counter c_op i;  \
+   arch_local_irq_restore(flags);  \
+}
+
+ATOMIC_OP_RETURN(add, +=)
+ATOMIC_OP_RETURN(sub, -=)
+
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, =)
+ATOMIC_OP(or,  |=)
+ATOMIC_OP(xor, ^=)
 
-   flags = arch_local_irq_save();
-   ret = v-counter += i;
-   arch_local_irq_restore(flags);
-   return ret;
-}
+#undef ATOMIC_OP_RETURN
+#undef ATOMIC_OP
 
-#define atomic_add(i, v) atomic_add_return(i, v)
+#define atomic_add(i, v)   (void)atomic_add_return(i, v)
 #define atomic_add_negative(a, v)  (atomic_add_return((a), (v))  0)
 
-static inline int atomic_sub_return(int i, atomic_t *v)
-{
-   h8300flags flags;
-   int ret;
-
-   flags = arch_local_irq_save();
-   ret = v-counter -= i;
-   arch_local_irq_restore(flags);
-   return ret;
-}
-
-#define atomic_sub(i, v) atomic_sub_return(i, v)
-#define atomic_sub_and_test(i, v) (atomic_sub_return(i, v) == 0)
-
-static inline int atomic_inc_return(atomic_t *v)
-{
-   h8300flags flags;
-   int ret;
-
-   flags = arch_local_irq_save();
-   v-counter++;
-   ret = v-counter;
-   arch_local_irq_restore(flags);
-   return ret;
-}
-
-#define atomic_inc(v) atomic_inc_return(v)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-static inline int atomic_dec_return(atomic_t *v)
-{
-   h8300flags flags;
-   int ret;
-
-   flags = arch_local_irq_save();
-   --v-counter;
-   ret = v-counter;
-   arch_local_irq_restore(flags);
-   return ret;
-}
+#define atomic_sub(i, v)   (void)atomic_sub_return(i, v)
+#define atomic_sub_and_test(i, v)  (atomic_sub_return(i, v) == 0)
 
-#define atomic_dec(v) atomic_dec_return(v)
+#define atomic_inc_return(v)   atomic_add_return(1, v)
+#define atomic_dec_return(v)   atomic_sub_return(1, v)
 
-static inline int atomic_dec_and_test(atomic_t *v)
-{
-   h8300flags flags;
-   int ret;
+#define atomic_inc(v)  (void)atomic_inc_return(v)
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
 
-   flags = arch_local_irq_save();
-   --v-counter;
-   ret = v-counter;
-   arch_local_irq_restore(flags);
-   return ret == 0;
-}
+#define atomic_dec(v)  (void)atomic_dec_return(v)
+#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
 
 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
 {
@@ -120,40 +91,14 @@ static inline int __atomic_add_unless(at
return ret;
 }
 
-static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
 {
-   unsigned char ccr;
-   unsigned long tmp;
-
-   __asm__ __volatile__(stc ccr,%w3\n\t
-orc #0x80,ccr\n\t
-mov.l %0,%1\n\t
-

[PATCH 07/28] blackfin: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

TODO: use inline asm or at least asm macros to collapse the lot.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/blackfin/include/asm/atomic.h |   28 +---
 arch/blackfin/kernel/bfin_ksyms.c  |7 ---
 arch/blackfin/mach-bf561/atomic.S  |   30 +++---
 3 files changed, 40 insertions(+), 25 deletions(-)

--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -16,19 +16,33 @@
 #include linux/types.h
 
 asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
-asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_clear_asm(volatile int *ptr, int value);
-asmlinkage int __raw_atomic_set_asm(volatile int *ptr, int value);
+asmlinkage int __raw_atomic_add_asm(volatile int *ptr, int value);
+
+asmlinkage int __raw_atomic_and_asm(volatile int *ptr, int value);
+asmlinkage int __raw_atomic_or_asm(volatile int *ptr, int value);
 asmlinkage int __raw_atomic_xor_asm(volatile int *ptr, int value);
 asmlinkage int __raw_atomic_test_asm(const volatile int *ptr, int value);
 
 #define atomic_read(v) __raw_uncached_fetch_asm((v)-counter)
 
-#define atomic_add_return(i, v) __raw_atomic_update_asm((v)-counter, i)
-#define atomic_sub_return(i, v) __raw_atomic_update_asm((v)-counter, -(i))
+#define atomic_add_return(i, v) __raw_atomic_add_asm((v)-counter, i)
+#define atomic_sub_return(i, v) __raw_atomic_add_asm((v)-counter, -(i))
+
+#define CONFIG_ARCH_HAS_ATOMIC_OR
 
-#define atomic_clear_mask(m, v) __raw_atomic_clear_asm((v)-counter, m)
-#define atomic_set_mask(m, v)   __raw_atomic_set_asm((v)-counter, m)
+#define atomic_or(i, v)  (void)__raw_atomic_or_asm((v)-counter, i)
+#define atomic_and(i, v) (void)__raw_atomic_and_asm((v)-counter, i)
+#define atomic_xor(i, v) (void)__raw_atomic_xor_asm((v)-counter, i)
+
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
+{
+   atomic_and(~mask, v);
+}
+
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+   atomic_or(mask, v);
+}
 
 #endif
 
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -83,11 +83,12 @@ EXPORT_SYMBOL(insl);
 EXPORT_SYMBOL(insl_16);
 
 #ifdef CONFIG_SMP
-EXPORT_SYMBOL(__raw_atomic_update_asm);
-EXPORT_SYMBOL(__raw_atomic_clear_asm);
-EXPORT_SYMBOL(__raw_atomic_set_asm);
+EXPORT_SYMBOL(__raw_atomic_add_asm);
+EXPORT_SYMBOL(__raw_atomic_and_asm);
+EXPORT_SYMBOL(__raw_atomic_or_asm);
 EXPORT_SYMBOL(__raw_atomic_xor_asm);
 EXPORT_SYMBOL(__raw_atomic_test_asm);
+
 EXPORT_SYMBOL(__raw_xchg_1_asm);
 EXPORT_SYMBOL(__raw_xchg_2_asm);
 EXPORT_SYMBOL(__raw_xchg_4_asm);
--- a/arch/blackfin/mach-bf561/atomic.S
+++ b/arch/blackfin/mach-bf561/atomic.S
@@ -587,10 +587,10 @@ ENDPROC(___raw_write_unlock_asm)
  * r0 = ptr
  * r1 = value
  *
- * Add a signed value to a 32bit word and return the new value atomically.
+ * ADD a signed value to a 32bit word and return the new value atomically.
  * Clobbers: r3:0, p1:0
  */
-ENTRY(___raw_atomic_update_asm)
+ENTRY(___raw_atomic_add_asm)
p1 = r0;
r3 = r1;
[--sp] = rets;
@@ -603,19 +603,19 @@ ENTRY(___raw_atomic_update_asm)
r0 = r3;
rets = [sp++];
rts;
-ENDPROC(___raw_atomic_update_asm)
+ENDPROC(___raw_atomic_add_asm)
 
 /*
  * r0 = ptr
  * r1 = mask
  *
- * Clear the mask bits from a 32bit word and return the old 32bit value
+ * AND the mask bits from a 32bit word and return the old 32bit value
  * atomically.
  * Clobbers: r3:0, p1:0
  */
-ENTRY(___raw_atomic_clear_asm)
+ENTRY(___raw_atomic_and_asm)
p1 = r0;
-   r3 = ~r1;
+   r3 = r1;
[--sp] = rets;
call _get_core_lock;
r2 = [p1];
@@ -627,17 +627,17 @@ ENTRY(___raw_atomic_clear_asm)
r0 = r3;
rets = [sp++];
rts;
-ENDPROC(___raw_atomic_clear_asm)
+ENDPROC(___raw_atomic_and_asm)
 
 /*
  * r0 = ptr
  * r1 = mask
  *
- * Set the mask bits into a 32bit word and return the old 32bit value
+ * OR the mask bits into a 32bit word and return the old 32bit value
  * atomically.
  * Clobbers: r3:0, p1:0
  */
-ENTRY(___raw_atomic_set_asm)
+ENTRY(___raw_atomic_or_asm)
p1 = r0;
r3 = r1;
[--sp] = rets;
@@ -651,7 +651,7 @@ ENTRY(___raw_atomic_set_asm)
r0 = r3;
rets = [sp++];
rts;
-ENDPROC(___raw_atomic_set_asm)
+ENDPROC(___raw_atomic_or_asm)
 
 /*
  * r0 = ptr
@@ -787,7 +787,7 @@ ENTRY(___raw_bit_set_asm)
r2 = r1;
r1 = 1;
r1 = r2;
-   jump ___raw_atomic_set_asm
+   jump ___raw_atomic_or_asm
 ENDPROC(___raw_bit_set_asm)
 
 /*
@@ -798,10 +798,10 @@ ENDPROC(___raw_bit_set_asm)
  * Clobbers: r3:0, p1:0
  */
 ENTRY(___raw_bit_clear_asm)
-   r2 = r1;
-   r1 = 1;
-   r1 = r2;
-   jump ___raw_atomic_clear_asm

[PATCH v4 0/6] kallsyms header cleanup

2015-07-16 Thread Tom Zanussi
During review of an unrelated patchset, the question was asked why
module.h was included in code that wouldn't be a module and didn't do
anything with modules [1].

The reason is that it uses kallsyms defines, but kallsyms.h doesn't
include module.h, though it should because it uses MODULE_NAME_LEN.
The code in question also didn't include kallsyms.h but relied on
ftrace.h to pull it in.  But ftrace.h no longer contains anything that
needs kallsyms.h, and continues to include it only because other code
expects it to.

This patchset is the start of cleaning all that up.  It also adds
explicit kallsyms.h includes and removes module.h includes for obvious
cases in kernel/trace and lib/, where I happened to be working.

There are a bunch of other files that probably include module.h only
for kallsyms, but I haven't gone through them yet.  I can submit a
follow-on patchset to this one assuming this is best way to do it...

[1] https://lkml.org/lkml/2015/4/4/70

Changes from v3:
  - rebased to latest linux-next, which now includes a patch that adds
module.h to kallsyms.h [commit 5ed0a999 kernel/kallsyns.c: define
kallsyms_cmp_symbol_t as function type to simplify the code], so
patch 2 of the previous version was removed.

Changes from v2:
 - rebased to linux-next
 - trace.c now needs module.h so leave it

Changes from v1:
 - added KSYM_SYMBOL_LEN patches for fnic and slub
 - separated tracing changes into KSYM_SYMBOL_LEN-only module.h changes 
 - fixed up bogus lib change from previous patchset
 - separate patch to remove unnecessary tracing kallsyms.h and module.h usage

The following changes since commit 6593e2dcdedd0493e1b1fcb419609d2101c4d0be:

  Add linux-next specific files for 20150716 (2015-07-16 16:23:42 +1000)

are available in the git repository at:

  git://git.yoctoproject.org/linux-yocto-contrib.git 
tzanussi/kallsyms-header-cleanup-v4
  
http://git.yoctoproject.org/cgit/cgit.cgi/linux-yocto-contrib/log/?h=tzanussi/kallsyms-header-cleanup-v4

Tom Zanussi (6):
  tracing: Remove kallsyms.h include from linux/ftrace.h
  tracing: Remove redundant module.h includes
  lib: Remove redundant module.h includes
  fnic: Remove redundant module.h includes
  slub: Remove redundant module.h includes
  tracing: Remove unnecessary kallsyms.h and module.h includes

 drivers/scsi/fnic/fnic_trace.c| 1 -
 include/linux/ftrace.h| 1 -
 kernel/trace/trace.c  | 1 -
 kernel/trace/trace_branch.c   | 2 --
 kernel/trace/trace_export.c   | 2 --
 kernel/trace/trace_irqsoff.c  | 2 --
 kernel/trace/trace_kprobe.c   | 1 +
 kernel/trace/trace_output.c   | 2 +-
 kernel/trace/trace_sched_switch.c | 2 --
 kernel/trace/trace_sched_wakeup.c | 2 --
 kernel/trace/trace_stack.c| 2 --
 kernel/trace/trace_syscalls.c | 2 +-
 lib/vsprintf.c| 1 -
 mm/slub.c | 1 -
 14 files changed, 3 insertions(+), 19 deletions(-)

-- 
1.9.3

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[PATCH v4 1/6] tracing: Remove kallsyms.h include from linux/ftrace.h

2015-07-16 Thread Tom Zanussi
kallsyms.h was included by ftrace.h for KSYM_NAME_LEN, but that usage
was removed by commit 3f5ec13696f [tracing/fastboot: move boot tracer
structs and funcs into their own header].

Remove kallsyms.h and have users relying on ftrace.h to include it for
them include it explicitly.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 include/linux/ftrace.h| 1 -
 kernel/trace/trace_kprobe.c   | 1 +
 kernel/trace/trace_output.c   | 1 +
 kernel/trace/trace_syscalls.c | 1 +
 4 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/include/linux/ftrace.h b/include/linux/ftrace.h
index 1da6029..8554dd5 100644
--- a/include/linux/ftrace.h
+++ b/include/linux/ftrace.h
@@ -7,7 +7,6 @@
 #define _LINUX_FTRACE_H
 
 #include linux/trace_clock.h
-#include linux/kallsyms.h
 #include linux/linkage.h
 #include linux/bitops.h
 #include linux/ptrace.h
diff --git a/kernel/trace/trace_kprobe.c b/kernel/trace/trace_kprobe.c
index b7d0cdd..afdabd0 100644
--- a/kernel/trace/trace_kprobe.c
+++ b/kernel/trace/trace_kprobe.c
@@ -18,6 +18,7 @@
  */
 
 #include linux/module.h
+#include linux/kallsyms.h
 #include linux/uaccess.h
 
 #include trace_probe.h
diff --git a/kernel/trace/trace_output.c b/kernel/trace/trace_output.c
index dfab253..6747d85 100644
--- a/kernel/trace/trace_output.c
+++ b/kernel/trace/trace_output.c
@@ -6,6 +6,7 @@
  */
 
 #include linux/module.h
+#include linux/kallsyms.h
 #include linux/mutex.h
 #include linux/ftrace.h
 
diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
index 7d567a4..e9bf9c6 100644
--- a/kernel/trace/trace_syscalls.c
+++ b/kernel/trace/trace_syscalls.c
@@ -4,6 +4,7 @@
 #include linux/slab.h
 #include linux/kernel.h
 #include linux/module.h  /* for MODULE_NAME_LEN via KSYM_SYMBOL_LEN */
+#include linux/kallsyms.h
 #include linux/ftrace.h
 #include linux/perf_event.h
 #include asm/syscall.h
-- 
1.9.3

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[PATCH v4 3/6] lib: Remove redundant module.h includes

2015-07-16 Thread Tom Zanussi
kallsyms.h now includes module.h, so remove module.h includes that
were apparently there only to satisfy kallsyms use of MODULE_NAME_LEN
(via KSYM_SYMBOL_LEN).

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 lib/vsprintf.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 7f0cdd2..fa587aa 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -19,7 +19,6 @@
 #include stdarg.h
 #include linux/clk.h
 #include linux/clk-provider.h
-#include linux/module.h  /* for KSYM_SYMBOL_LEN */
 #include linux/types.h
 #include linux/string.h
 #include linux/ctype.h
-- 
1.9.3

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[PATCH v4 6/6] tracing: Remove unnecessary kallsyms.h and module.h includes

2015-07-16 Thread Tom Zanussi
At some point, these files made use of something from kallsyms.h
and/or module.h, but they now use nothing from either and can be
removed.

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace.c  | 1 -
 kernel/trace/trace_branch.c   | 2 --
 kernel/trace/trace_export.c   | 2 --
 kernel/trace/trace_irqsoff.c  | 2 --
 kernel/trace/trace_sched_switch.c | 2 --
 kernel/trace/trace_sched_wakeup.c | 2 --
 kernel/trace/trace_stack.c| 2 --
 7 files changed, 13 deletions(-)

diff --git a/kernel/trace/trace.c b/kernel/trace/trace.c
index abcbf7f..a164198 100644
--- a/kernel/trace/trace.c
+++ b/kernel/trace/trace.c
@@ -15,7 +15,6 @@
 #include generated/utsrelease.h
 #include linux/stacktrace.h
 #include linux/writeback.h
-#include linux/kallsyms.h
 #include linux/seq_file.h
 #include linux/notifier.h
 #include linux/irqflags.h
diff --git a/kernel/trace/trace_branch.c b/kernel/trace/trace_branch.c
index e2e12ad..eab76d8 100644
--- a/kernel/trace/trace_branch.c
+++ b/kernel/trace/trace_branch.c
@@ -3,12 +3,10 @@
  *
  * Copyright (C) 2008 Steven Rostedt srost...@redhat.com
  */
-#include linux/kallsyms.h
 #include linux/seq_file.h
 #include linux/spinlock.h
 #include linux/irqflags.h
 #include linux/uaccess.h
-#include linux/module.h
 #include linux/ftrace.h
 #include linux/hash.h
 #include linux/fs.h
diff --git a/kernel/trace/trace_export.c b/kernel/trace/trace_export.c
index adabf7d..cc48161 100644
--- a/kernel/trace/trace_export.c
+++ b/kernel/trace/trace_export.c
@@ -4,11 +4,9 @@
  * Copyright (C) 2009 Steven Rostedt srost...@redhat.com
  */
 #include linux/stringify.h
-#include linux/kallsyms.h
 #include linux/seq_file.h
 #include linux/uaccess.h
 #include linux/ftrace.h
-#include linux/module.h
 #include linux/init.h
 
 #include trace_output.h
diff --git a/kernel/trace/trace_irqsoff.c b/kernel/trace/trace_irqsoff.c
index 8523ea3..f65f596 100644
--- a/kernel/trace/trace_irqsoff.c
+++ b/kernel/trace/trace_irqsoff.c
@@ -9,9 +9,7 @@
  *  Copyright (C) 2004-2006 Ingo Molnar
  *  Copyright (C) 2004 Nadia Yvette Chambers
  */
-#include linux/kallsyms.h
 #include linux/uaccess.h
-#include linux/module.h
 #include linux/ftrace.h
 
 #include trace.h
diff --git a/kernel/trace/trace_sched_switch.c 
b/kernel/trace/trace_sched_switch.c
index 419ca37..e1793f2 100644
--- a/kernel/trace/trace_sched_switch.c
+++ b/kernel/trace/trace_sched_switch.c
@@ -4,8 +4,6 @@
  * Copyright (C) 2007 Steven Rostedt srost...@redhat.com
  *
  */
-#include linux/module.h
-#include linux/kallsyms.h
 #include linux/uaccess.h
 #include linux/ftrace.h
 #include trace/events/sched.h
diff --git a/kernel/trace/trace_sched_wakeup.c 
b/kernel/trace/trace_sched_wakeup.c
index 9b33dd1..b7692d4 100644
--- a/kernel/trace/trace_sched_wakeup.c
+++ b/kernel/trace/trace_sched_wakeup.c
@@ -9,8 +9,6 @@
  *  Copyright (C) 2004-2006 Ingo Molnar
  *  Copyright (C) 2004 Nadia Yvette Chambers
  */
-#include linux/module.h
-#include linux/kallsyms.h
 #include linux/uaccess.h
 #include linux/ftrace.h
 #include linux/sched/rt.h
diff --git a/kernel/trace/trace_stack.c b/kernel/trace/trace_stack.c
index 3f34496..06ad4c0 100644
--- a/kernel/trace/trace_stack.c
+++ b/kernel/trace/trace_stack.c
@@ -3,12 +3,10 @@
  *
  */
 #include linux/stacktrace.h
-#include linux/kallsyms.h
 #include linux/seq_file.h
 #include linux/spinlock.h
 #include linux/uaccess.h
 #include linux/ftrace.h
-#include linux/module.h
 #include linux/sysctl.h
 #include linux/init.h
 
-- 
1.9.3

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[PATCH v4 5/6] slub: Remove redundant module.h includes

2015-07-16 Thread Tom Zanussi
kallsyms.h now includes module.h, so remove module.h includes that
were apparently there only to satisfy kallsyms use of MODULE_NAME_LEN
(via KSYM_SYMBOL_LEN).

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
Acked-by: David Rientjes rient...@google.com
---
 mm/slub.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/mm/slub.c b/mm/slub.c
index 257283f..797530f 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -11,7 +11,6 @@
 
 #include linux/mm.h
 #include linux/swap.h /* struct reclaim_state */
-#include linux/module.h
 #include linux/bit_spinlock.h
 #include linux/interrupt.h
 #include linux/bitops.h
-- 
1.9.3

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[PATCH 02/28] alpha: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/alpha/include/asm/atomic.h |   43 ++--
 1 file changed, 28 insertions(+), 15 deletions(-)

--- a/arch/alpha/include/asm/atomic.h
+++ b/arch/alpha/include/asm/atomic.h
@@ -29,13 +29,13 @@
  * branch back to restart the operation.
  */
 
-#define ATOMIC_OP(op)  \
+#define ATOMIC_OP(op, asm_op)  \
 static __inline__ void atomic_##op(int i, atomic_t * v)
\
 {  \
unsigned long temp; \
__asm__ __volatile__(   \
1: ldl_l %0,%1\n  \
-   #op l %0,%2,%0\n\
+   #asm_op  %0,%2,%0\n \
   stl_c %0,%1\n  \
   beq %0,2f\n\
.subsection 2\n   \
@@ -45,15 +45,15 @@ static __inline__ void atomic_##op(int i
:Ir (i), m (v-counter));   \
 }  \
 
-#define ATOMIC_OP_RETURN(op)   \
+#define ATOMIC_OP_RETURN(op, asm_op)   \
 static inline int atomic_##op##_return(int i, atomic_t *v) \
 {  \
long temp, result;  \
smp_mb();   \
__asm__ __volatile__(   \
1: ldl_l %0,%1\n  \
-   #op l %0,%3,%2\n\
-   #op l %0,%3,%0\n\
+   #asm_op  %0,%3,%2\n \
+   #asm_op  %0,%3,%0\n \
   stl_c %0,%1\n  \
   beq %0,2f\n\
.subsection 2\n   \
@@ -65,13 +65,13 @@ static inline int atomic_##op##_return(i
return result;  \
 }
 
-#define ATOMIC64_OP(op)
\
+#define ATOMIC64_OP(op, asm_op)
\
 static __inline__ void atomic64_##op(long i, atomic64_t * v)   \
 {  \
unsigned long temp; \
__asm__ __volatile__(   \
1: ldq_l %0,%1\n  \
-   #op q %0,%2,%0\n\
+   #asm_op  %0,%2,%0\n \
   stq_c %0,%1\n  \
   beq %0,2f\n\
.subsection 2\n   \
@@ -81,15 +81,15 @@ static __inline__ void atomic64_##op(lon
:Ir (i), m (v-counter));   \
 }  \
 
-#define ATOMIC64_OP_RETURN(op) \
+#define ATOMIC64_OP_RETURN(op, asm_op) \
 static __inline__ long atomic64_##op##_return(long i, atomic64_t * v)  \
 {  \
long temp, result;  \
smp_mb();   \
__asm__ __volatile__(   \
1: ldq_l %0,%1\n  \
-   #op q %0,%3,%2\n\
-   #op q %0,%3,%0\n\
+   #asm_op  %0,%3,%2\n \
+   #asm_op  %0,%3,%0\n \
   stq_c %0,%1\n  \
   beq %0,2f\n\
.subsection 2\n   \
@@ -101,15 +101,28 

[PATCH 16/28] powerpc: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: Benjamin Herrenschmidt b...@kernel.crashing.org
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/powerpc/include/asm/atomic.h |9 +
 1 file changed, 9 insertions(+)

--- a/arch/powerpc/include/asm/atomic.h
+++ b/arch/powerpc/include/asm/atomic.h
@@ -67,6 +67,12 @@ static __inline__ int atomic_##op##_retu
 ATOMIC_OPS(add, add)
 ATOMIC_OPS(sub, subf)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, and)
+ATOMIC_OP(or, or)
+ATOMIC_OP(xor, xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -304,6 +310,9 @@ static __inline__ long atomic64_##op##_r
 
 ATOMIC64_OPS(add, add)
 ATOMIC64_OPS(sub, subf)
+ATOMIC64_OP(and, and)
+ATOMIC64_OP(or, or)
+ATOMIC64_OP(xor, xor)
 
 #undef ATOMIC64_OPS
 #undef ATOMIC64_OP_RETURN


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[PATCH v4 4/6] fnic: Remove redundant module.h includes

2015-07-16 Thread Tom Zanussi
kallsyms.h now includes module.h, so remove module.h includes that
were apparently there only to satisfy kallsyms use of MODULE_NAME_LEN
(via KSYM_SYMBOL_LEN).

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 drivers/scsi/fnic/fnic_trace.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/scsi/fnic/fnic_trace.c b/drivers/scsi/fnic/fnic_trace.c
index 4e15c4b..503f9c5 100644
--- a/drivers/scsi/fnic/fnic_trace.c
+++ b/drivers/scsi/fnic/fnic_trace.c
@@ -15,7 +15,6 @@
  * SOFTWARE.
  */
 
-#include linux/module.h
 #include linux/mempool.h
 #include linux/errno.h
 #include linux/spinlock.h
-- 
1.9.3

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[PATCH v4 2/6] tracing: Remove redundant module.h includes

2015-07-16 Thread Tom Zanussi
kallsyms.h now includes module.h, so remove module.h includes that
were apparently there only to satisfy kallsyms use of MODULE_NAME_LEN
(via KSYM_SYMBOL_LEN).

Signed-off-by: Tom Zanussi tom.zanu...@linux.intel.com
---
 kernel/trace/trace_output.c   | 1 -
 kernel/trace/trace_syscalls.c | 1 -
 2 files changed, 2 deletions(-)

diff --git a/kernel/trace/trace_output.c b/kernel/trace/trace_output.c
index 6747d85..7876c61 100644
--- a/kernel/trace/trace_output.c
+++ b/kernel/trace/trace_output.c
@@ -5,7 +5,6 @@
  *
  */
 
-#include linux/module.h
 #include linux/kallsyms.h
 #include linux/mutex.h
 #include linux/ftrace.h
diff --git a/kernel/trace/trace_syscalls.c b/kernel/trace/trace_syscalls.c
index e9bf9c6..f2bad21 100644
--- a/kernel/trace/trace_syscalls.c
+++ b/kernel/trace/trace_syscalls.c
@@ -3,7 +3,6 @@
 #include linux/syscalls.h
 #include linux/slab.h
 #include linux/kernel.h
-#include linux/module.h  /* for MODULE_NAME_LEN via KSYM_SYMBOL_LEN */
 #include linux/kallsyms.h
 #include linux/ftrace.h
 #include linux/perf_event.h
-- 
1.9.3

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Re: [PATCH 0/6] BPF JIT fixes and features for ARM

2015-07-16 Thread Alexei Starovoitov

On 7/16/15 9:46 AM, Nicolas Schichan wrote:

This serie fixes issues with the ARM BPF JIT and adds support for more
instructions to the ARM BPF JIT.

The first three patches are fixing bugs in the ARM JIT and should
probably find their way to a stable kernel.

The last three patches add support to the ARM JIT for more BPF
instructions, namely skb netdevice type retrieval, skb payload offset
retrieval, and skb packet type retrieval.

With the first three patches, all 60 test_bpf tests in Linux 4.1 release
are now passing OK (was 54 out of 60 before).

The last three patches allow 35 tests to use the JIT instead of 29
before.


looks good to me.
For the series:
Acked-by: Alexei Starovoitov a...@plumgrid.com

you might want to try the latest 4.2-rc, since it has 238 tests :)
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Re: [PATCH RFC 0/4] change sb_writers to use percpu_rw_semaphore

2015-07-16 Thread Oleg Nesterov
On 07/16, Jan Kara wrote:

 On Wed 15-07-15 20:19:20, Oleg Nesterov wrote:
 
  Perhaps it makes to merge other 2 patches from Dave first? (those which
  change __sb_start/end_write to rely on RCU). Afaics these changes are
  straightforward and correct. Although I'd suggest to use preempt_disable()
  and synchronize_sched() instead. I will be happy to (try to) make this
  conversion on top of his changes.
 
  Because I do not want to delay the performance improvements and I do not
  know when exactly I'll send the next version: I need to finish the previous
  discussion about rcu_sync first. And the necessary changes in fs/super.c
  depend on whether percpu_rw_semaphore will have rcu_sync or not (not too
  much, only destroy_super() depends, but still).
 
  And of course, I am worried that I missed something and percpu_rw_semaphore
  can't work for some reason. The code in fs/super.c looks simple, but it
  seems that filesystems do the strange things with lockdep at least.

 So Dave's patches would go in only in the next merge window anyway so we
 still have like two-three weeks to decide which patchset to take.

OK, good.

 If you
 think it will take you longer,

Hopefully not.

 then merging Dave's patches makes some sense
 although I personally don't think the issue is so important that we have to
 fix it ASAP and eventual delay of one more release would be OK for me.

OK. I will try to do this in any case, I just wanted to say that I can
equally do this on top of Dave's patches.

To remind, I need to finish the discussion about percpu_rw_semaphore
and rcu_sync, then I'll try to make v2.

And. The biggest problem is lockdep. Everything else looks really simple
although of course I could miss something. And not only because the
filesystems abuse lockdep and thus we need some cleanups first. Unless
I am totally confused fs/super.c needs some cleanups (and fixes) too,
with or without this conversion. Say, acquire_freeze_lock() logic does
do not look right:

- wait_event(.frozen  level) without rwsem_acquire_read() is
  just wrong from lockdep perspective. If we are going to deadlock
  because the caller is buggy, lockdep can't warn us.

- __sb_start_write() can race with thaw_super() + freeze_super(),
  and after goto retry the 2nd  acquire_freeze_lock() is wrong.

- The tell lockdep we are doing trylock hack doesn't look nice.

  I think this is correct, but this logic should be more explicit.
  Yes, the recursive read_lock() is fine if we hold the lock on
  higher level. But we do not need to fool lockdep. If we can not
  deadlock in this case (and I agree we can't) we should simply use
  wait == F consistently.

Something like this (not even compiled tested):

static int
do_sb_start_write(struct super_block *sb, int level, bool wait, 
unsigned long ip)
{

if (wait)
rwsem_acquire_read(sb-s_writers.lock_map[level-1], 0, 
0, ip);
retry:
if (unlikely(sb-s_writers.frozen = level)) {
if (!wait)
return 0;
wait_event(sb-s_writers.wait_unfrozen,
   sb-s_writers.frozen  level);
}

percpu_counter_inc(sb-s_writers.counter[level-1]);
/*
 * Make sure counter is updated before we check for frozen.
 * freeze_super() first sets frozen and then checks the counter.
 */
smp_mb();
if (unlikely(sb-s_writers.frozen = level)) {
__sb_end_write(sb, level);
goto retry;
}

if (!wait)
rwsem_acquire_read(sb-s_writers.lock_map[level-1], 0, 
1, ip);
return 1;
}

/*
 * This is an internal function, please use 
sb_start_{write,pagefault,intwrite}
 * instead.
 */
int __sb_start_write(struct super_block *sb, int level, bool wait)
{
bool cantbelocked = false;
int ret;

#ifdef CONFIG_LOCKDEP
/*
 * We want lockdep to tell us about possible deadlocks with 
freezing but
 * it's it bit tricky to properly instrument it. Getting a 
freeze protection
 * works as getting a read lock but there are subtle problems. 
XFS for example
 * gets freeze protection on internal level twice in some 
cases, which is OK
 * only because we already hold a freeze protection also on 
higher level. Due
 * to these cases we have to use wait == F (trylock mode) which 
must not fail.
 */
if (wait) {
int i;

for (i = 0; i  level - 1; i++)

Re: [PATCH] gpio/davinci: add interrupt support for GPIOs 16-31

2015-07-16 Thread Vitaly Andrianov



On 07/16/2015 05:04 AM, Sekhar Nori wrote:

On Tuesday 14 July 2015 07:31 PM, Linus Walleij wrote:

On Thu, Jun 18, 2015 at 7:10 PM, Vitaly Andrianov vita...@ti.com wrote:


Interrupts for GPIOs 16 through 31 are enabled by bit 1 in the
binten register (offset 8). Previous versions of GPIO only
used bit 0, which enables GPIO 0-15 interrupts.

Signed-off-by: Reece Pollack x0183...@ti.com
Signed-off-by: Vitaly Andrianov vita...@ti.com


Sekhar/Kevin: OK with this? We don't have a maintainer
listed for davinci GPIO so I assume it's you guys...


Hi Linus, I had reviewed this patch and there was a v2 send based on my
comments on July 03.


Should this be tagged for stable?


Not sure about that. It affects Keystone devices. Vitaly?

Thanks,
Sekhar


We used this patch for a long time. So, I guess it is stable.
Thanks,
Vitaly
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Re: [RFT PATCH] gpio: etraxfs: Fix devm_ioremap_resource return value check

2015-07-16 Thread Rabin Vincent
On Thu, Jul 09, 2015 at 10:19:53PM +0900, Krzysztof Kozlowski wrote:
 Value returned by devm_ioremap_resource() was checked for non-NULL but
 devm_ioremap_resource() returns IOMEM_ERR_PTR, not NULL. In case of
 error this could lead to dereference of ERR_PTR.
 
 Signed-off-by: Krzysztof Kozlowski k.kozlowsk...@gmail.com
 Fixes: d342571efea8 (gpio: add ETRAXFS GPIO driver)

Acked-by: Rabin Vincent ra...@rab.in

 Cc: sta...@vger.kernel.org

I don't think this demands a stable backport though.
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[PATCH 27/28] atomic: Replace atomic_{set,clear}_mask() usage

2015-07-16 Thread Peter Zijlstra
Replace the deprecated atomic_{set,clear}_mask() usage with the now
ubiquous atomic_{or,andnot}() functions.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/blackfin/mach-common/smp.c |2 -
 arch/m32r/kernel/smp.c  |4 +-
 arch/mn10300/mm/tlb-smp.c   |2 -
 arch/s390/kernel/time.c |4 +-
 arch/s390/kvm/interrupt.c   |   30 +--
 arch/s390/kvm/kvm-s390.c|   32 ++--
 drivers/gpu/drm/i915/i915_drv.c |2 -
 drivers/gpu/drm/i915/i915_gem.c |2 -
 drivers/gpu/drm/i915/i915_irq.c |4 +-
 drivers/s390/scsi/zfcp_aux.c|2 -
 drivers/s390/scsi/zfcp_erp.c|   62 
 drivers/s390/scsi/zfcp_fc.c |8 ++---
 drivers/s390/scsi/zfcp_fsf.c|   26 
 drivers/s390/scsi/zfcp_qdio.c   |   14 -
 14 files changed, 97 insertions(+), 97 deletions(-)

--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -195,7 +195,7 @@ void send_ipi(const struct cpumask *cpum
local_irq_save(flags);
for_each_cpu(cpu, cpumask) {
bfin_ipi_data = per_cpu(bfin_ipi, cpu);
-   atomic_set_mask((1  msg), bfin_ipi_data-bits);
+   atomic_or((1  msg), bfin_ipi_data-bits);
atomic_inc(bfin_ipi_data-count);
}
local_irq_restore(flags);
--- a/arch/m32r/kernel/smp.c
+++ b/arch/m32r/kernel/smp.c
@@ -156,7 +156,7 @@ void smp_flush_cache_all(void)
cpumask_clear_cpu(smp_processor_id(), cpumask);
spin_lock(flushcache_lock);
mask=cpumask_bits(cpumask);
-   atomic_set_mask(*mask, (atomic_t *)flushcache_cpumask);
+   atomic_or(*mask, (atomic_t *)flushcache_cpumask);
send_IPI_mask(cpumask, INVALIDATE_CACHE_IPI, 0);
_flush_cache_copyback_all();
while (flushcache_cpumask)
@@ -407,7 +407,7 @@ static void flush_tlb_others(cpumask_t c
flush_vma = vma;
flush_va = va;
mask=cpumask_bits(cpumask);
-   atomic_set_mask(*mask, (atomic_t *)flush_cpumask);
+   atomic_or(*mask, (atomic_t *)flush_cpumask);
 
/*
 * We have to send the IPI only to
--- a/arch/mn10300/mm/tlb-smp.c
+++ b/arch/mn10300/mm/tlb-smp.c
@@ -119,7 +119,7 @@ static void flush_tlb_others(cpumask_t c
flush_mm = mm;
flush_va = va;
 #if NR_CPUS = BITS_PER_LONG
-   atomic_set_mask(cpumask.bits[0], flush_cpumask.bits[0]);
+   atomic_or(cpumask.bits[0], (atomic_t *)flush_cpumask.bits[0]);
 #else
 #error Not supported.
 #endif
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -381,7 +381,7 @@ static void disable_sync_clock(void *dum
 * increase the sequence counter to avoid the race of an
 * etr event and the complete recovery against get_sync_clock.
 */
-   atomic_clear_mask(0x8000, sw_ptr);
+   atomic_andnot(0x8000, sw_ptr);
atomic_inc(sw_ptr);
 }
 
@@ -392,7 +392,7 @@ static void disable_sync_clock(void *dum
 static void enable_sync_clock(void)
 {
atomic_t *sw_ptr = this_cpu_ptr(clock_sync_word);
-   atomic_set_mask(0x8000, sw_ptr);
+   atomic_or(0x8000, sw_ptr);
 }
 
 /*
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -170,20 +170,20 @@ static unsigned long deliverable_irqs(st
 
 static void __set_cpu_idle(struct kvm_vcpu *vcpu)
 {
-   atomic_set_mask(CPUSTAT_WAIT, vcpu-arch.sie_block-cpuflags);
+   atomic_or(CPUSTAT_WAIT, vcpu-arch.sie_block-cpuflags);
set_bit(vcpu-vcpu_id, vcpu-arch.local_int.float_int-idle_mask);
 }
 
 static void __unset_cpu_idle(struct kvm_vcpu *vcpu)
 {
-   atomic_clear_mask(CPUSTAT_WAIT, vcpu-arch.sie_block-cpuflags);
+   atomic_andnot(CPUSTAT_WAIT, vcpu-arch.sie_block-cpuflags);
clear_bit(vcpu-vcpu_id, vcpu-arch.local_int.float_int-idle_mask);
 }
 
 static void __reset_intercept_indicators(struct kvm_vcpu *vcpu)
 {
-   atomic_clear_mask(CPUSTAT_IO_INT | CPUSTAT_EXT_INT | CPUSTAT_STOP_INT,
- vcpu-arch.sie_block-cpuflags);
+   atomic_andnot(CPUSTAT_IO_INT | CPUSTAT_EXT_INT | CPUSTAT_STOP_INT,
+   vcpu-arch.sie_block-cpuflags);
vcpu-arch.sie_block-lctl = 0x;
vcpu-arch.sie_block-ictl = ~(ICTL_LPSW | ICTL_STCTL | ICTL_PINT);
 
@@ -196,7 +196,7 @@ static void __reset_intercept_indicators
 
 static void __set_cpuflag(struct kvm_vcpu *vcpu, u32 flag)
 {
-   atomic_set_mask(flag, vcpu-arch.sie_block-cpuflags);
+   atomic_or(flag, vcpu-arch.sie_block-cpuflags);
 }
 
 static void set_intercept_indicators_io(struct kvm_vcpu *vcpu)
@@ -919,7 +919,7 @@ void kvm_s390_clear_local_irqs(struct kv
spin_unlock(li-lock);
 
/* clear pending external calls set by sigp interpretation facility */
-   atomic_clear_mask(CPUSTAT_ECALL_PEND, li-cpuflags);
+   atomic_andnot(CPUSTAT_ECALL_PEND, li-cpuflags);
vcpu-kvm-arch.sca-cpu[vcpu-vcpu_id].sigp_ctrl = 0;
 }
 
@@ 

[PATCH 28/28] atomic: Add simple atomic_t tests

2015-07-16 Thread Peter Zijlstra
Add a few atomic_t tests, gets some compile coverage for the new
operations.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 lib/atomic64_test.c |   69 
 1 file changed, 48 insertions(+), 21 deletions(-)

--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -16,8 +16,39 @@
 #include linux/kernel.h
 #include linux/atomic.h
 
+#define TEST(bit, op, c_op, val)   \
+do {   \
+   atomic##bit##_set(v, v0);  \
+   r = v0; \
+   atomic##bit##_##op(val, v);\
+   r c_op val; \
+   WARN(atomic##bit##_read(v) != r, %Lx != %Lx\n,   \
+   (unsigned long long)atomic##bit##_read(v), \
+   (unsigned long long)r); \
+} while (0)
+
+static __init void test_atomic(void)
+{
+   int v0 = 0xaaa31337;
+   int v1 = 0xdeadbeef;
+   int onestwos = 0x;
+   int one = 1;
+
+   atomic_t v;
+   int r;
+
+   TEST(, add, +=, onestwos);
+   TEST(, add, +=, -one);
+   TEST(, sub, -=, onestwos);
+   TEST(, sub, -=, -one);
+   TEST(, or, |=, v1);
+   TEST(, and, =, v1);
+   TEST(, xor, ^=, v1);
+   TEST(, andnot, = ~, v1);
+}
+
 #define INIT(c) do { atomic64_set(v, c); r = c; } while (0)
-static __init int test_atomic64(void)
+static __init void test_atomic64(void)
 {
long long v0 = 0xaaa31337c001d00dLL;
long long v1 = 0xdeadbeefdeafcafeLL;
@@ -34,15 +66,14 @@ static __init int test_atomic64(void)
BUG_ON(v.counter != r);
BUG_ON(atomic64_read(v) != r);
 
-   INIT(v0);
-   atomic64_add(onestwos, v);
-   r += onestwos;
-   BUG_ON(v.counter != r);
-
-   INIT(v0);
-   atomic64_add(-one, v);
-   r += -one;
-   BUG_ON(v.counter != r);
+   TEST(64, add, +=, onestwos);
+   TEST(64, add, +=, -one);
+   TEST(64, sub, -=, onestwos);
+   TEST(64, sub, -=, -one);
+   TEST(64, or, |=, v1);
+   TEST(64, and, =, v1);
+   TEST(64, xor, ^=, v1);
+   TEST(64, andnot, = ~, v1);
 
INIT(v0);
r += onestwos;
@@ -55,16 +86,6 @@ static __init int test_atomic64(void)
BUG_ON(v.counter != r);
 
INIT(v0);
-   atomic64_sub(onestwos, v);
-   r -= onestwos;
-   BUG_ON(v.counter != r);
-
-   INIT(v0);
-   atomic64_sub(-one, v);
-   r -= -one;
-   BUG_ON(v.counter != r);
-
-   INIT(v0);
r -= onestwos;
BUG_ON(atomic64_sub_return(onestwos, v) != r);
BUG_ON(v.counter != r);
@@ -147,6 +168,12 @@ static __init int test_atomic64(void)
BUG_ON(!atomic64_inc_not_zero(v));
r += one;
BUG_ON(v.counter != r);
+}
+
+static __init int test_atomics(void)
+{
+   test_atomic();
+   test_atomic64();
 
 #ifdef CONFIG_X86
pr_info(passed for %s platform %s CX8 and %s SSE\n,
@@ -166,4 +193,4 @@ static __init int test_atomic64(void)
return 0;
 }
 
-core_initcall(test_atomic64);
+core_initcall(test_atomics);


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[PATCH 03/28] arc: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: Vineet Gupta vgu...@synopsys.com
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/arc/include/asm/atomic.h |   19 +--
 1 file changed, 17 insertions(+), 2 deletions(-)

--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -143,14 +143,29 @@ static inline int atomic_##op##_return(i
 
 ATOMIC_OPS(add, +=, add)
 ATOMIC_OPS(sub, -=, sub)
-ATOMIC_OP(and, =, and)
 
-#define atomic_clear_mask(mask, v) atomic_and(~(mask), (v))
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+#define atomic_andnot atomic_andnot
+
+ATOMIC_OP(and, =, and)
+ATOMIC_OP(andnot, = ~, bic)
+ATOMIC_OP(or, |=, or)
+ATOMIC_OP(xor, ^=, xor)
 
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
+{
+   atomic_and(~mask, v);
+}
+
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+   atomic_or(mask, v);
+}
+
 /**
  * __atomic_add_unless - add unless the number is a given value
  * @v: pointer of type atomic_t


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[PATCH 15/28] parisc: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/parisc/include/asm/atomic.h |9 +
 1 file changed, 9 insertions(+)

--- a/arch/parisc/include/asm/atomic.h
+++ b/arch/parisc/include/asm/atomic.h
@@ -126,6 +126,12 @@ static __inline__ int atomic_##op##_retu
 ATOMIC_OPS(add, +=)
 ATOMIC_OPS(sub, -=)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, =)
+ATOMIC_OP(or, |=)
+ATOMIC_OP(xor, ^=)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -185,6 +191,9 @@ static __inline__ s64 atomic64_##op##_re
 
 ATOMIC64_OPS(add, +=)
 ATOMIC64_OPS(sub, -=)
+ATOMIC64_OP(and, =)
+ATOMIC64_OP(or, |=)
+ATOMIC64_OP(xor, ^=)
 
 #undef ATOMIC64_OPS
 #undef ATOMIC64_OP_RETURN


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[PATCH 10/28] m32r: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/m32r/include/asm/atomic.h |   44 +
 1 file changed, 10 insertions(+), 34 deletions(-)

--- a/arch/m32r/include/asm/atomic.h
+++ b/arch/m32r/include/asm/atomic.h
@@ -94,6 +94,12 @@ static __inline__ int atomic_##op##_retu
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -240,44 +246,14 @@ static __inline__ int __atomic_add_unles
 }
 
 
-static __inline__ void atomic_clear_mask(unsigned long  mask, atomic_t *addr)
+static __inline__ __deprecated void atomic_clear_mask(unsigned int mask, 
atomic_t *v)
 {
-   unsigned long flags;
-   unsigned long tmp;
-
-   local_irq_save(flags);
-   __asm__ __volatile__ (
-   # atomic_clear_mask\n\t
-   DCACHE_CLEAR(%0, r5, %1)
-   M32R_LOCK %0, @%1; \n\t
-   and%0, %2; \n\t
-   M32R_UNLOCK %0, @%1;   \n\t
-   : =r (tmp)
-   : r (addr), r (~mask)
-   : memory
-   __ATOMIC_CLOBBER
-   );
-   local_irq_restore(flags);
+   atomic_and(~mask, v);
 }
 
-static __inline__ void atomic_set_mask(unsigned long  mask, atomic_t *addr)
+static __inline__ __deprecated void atomic_set_mask(unsigned int mask, 
atomic_t *v)
 {
-   unsigned long flags;
-   unsigned long tmp;
-
-   local_irq_save(flags);
-   __asm__ __volatile__ (
-   # atomic_set_mask  \n\t
-   DCACHE_CLEAR(%0, r5, %1)
-   M32R_LOCK %0, @%1; \n\t
-   or %0, %2; \n\t
-   M32R_UNLOCK %0, @%1;   \n\t
-   : =r (tmp)
-   : r (addr), r (mask)
-   : memory
-   __ATOMIC_CLOBBER
-   );
-   local_irq_restore(flags);
+   atomic_or(mask, v);
 }
 
 #endif /* _ASM_M32R_ATOMIC_H */


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[PATCH 01/28] atomic: Prepare generic atomic implementation for logic ops

2015-07-16 Thread Peter Zijlstra
Clean up the #ifdef guards a bit to prepare for architectures to
supply their own logic ops.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 include/asm-generic/atomic.h |   12 ++--
 1 file changed, 10 insertions(+), 2 deletions(-)

--- a/include/asm-generic/atomic.h
+++ b/include/asm-generic/atomic.h
@@ -98,14 +98,22 @@ ATOMIC_OP_RETURN(add, +)
 ATOMIC_OP_RETURN(sub, -)
 #endif
 
-#ifndef atomic_clear_mask
+#ifndef atomic_and
 ATOMIC_OP(and, )
+#endif
+
+#ifndef atomic_clear_mask
 #define atomic_clear_mask(i, v) atomic_and(~(i), (v))
 #endif
 
-#ifndef atomic_set_mask
+#ifndef atomic_or
+#ifndef CONFIG_ARCH_HAS_ATOMIC_OR
 #define CONFIG_ARCH_HAS_ATOMIC_OR
+#endif
 ATOMIC_OP(or, |)
+#endif
+
+#ifndef atomic_set_mask
 #define atomic_set_mask(i, v)  atomic_or((i), (v))
 #endif
 


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[PATCH 19/28] xtensa: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/xtensa/include/asm/atomic.h |   85 +++
 1 file changed, 16 insertions(+), 69 deletions(-)

--- a/arch/xtensa/include/asm/atomic.h
+++ b/arch/xtensa/include/asm/atomic.h
@@ -145,10 +145,26 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+   atomic_or(mask, v);
+}
+
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
+{
+   atomic_and(~mask, v);
+}
+
 /**
  * atomic_sub_and_test - subtract value from variable and test result
  * @i: integer value to subtract
@@ -250,75 +266,6 @@ static __inline__ int __atomic_add_unles
return c;
 }
 
-
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
-{
-#if XCHAL_HAVE_S32C1I
-   unsigned long tmp;
-   int result;
-
-   __asm__ __volatile__(
-   1: l32i%1, %3, 0\n
-  wsr %1, scompare1\n
-  and %0, %1, %2\n
-  s32c1i  %0, %3, 0\n
-  bne %0, %1, 1b\n
-   : =a (result), =a (tmp)
-   : a (~mask), a (v)
-   : memory
-   );
-#else
-   unsigned int all_f = -1;
-   unsigned int vval;
-
-   __asm__ __volatile__(
-  rsila15,__stringify(LOCKLEVEL)\n
-  l32i%0, %2, 0\n
-  xor %1, %4, %3\n
-  and %0, %0, %4\n
-  s32i%0, %2, 0\n
-  wsr a15, ps\n
-  rsync\n
-   : =a (vval), =a (mask)
-   : a (v), a (all_f), 1 (mask)
-   : a15, memory
-   );
-#endif
-}
-
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-#if XCHAL_HAVE_S32C1I
-   unsigned long tmp;
-   int result;
-
-   __asm__ __volatile__(
-   1: l32i%1, %3, 0\n
-  wsr %1, scompare1\n
-  or  %0, %1, %2\n
-  s32c1i  %0, %3, 0\n
-  bne %0, %1, 1b\n
-   : =a (result), =a (tmp)
-   : a (mask), a (v)
-   : memory
-   );
-#else
-   unsigned int vval;
-
-   __asm__ __volatile__(
-  rsila15,__stringify(LOCKLEVEL)\n
-  l32i%0, %2, 0\n
-  or  %0, %0, %1\n
-  s32i%0, %2, 0\n
-  wsr a15, ps\n
-  rsync\n
-   : =a (vval)
-   : a (mask), a (v)
-   : a15, memory
-   );
-#endif
-}
-
 #endif /* __KERNEL__ */
 
 #endif /* _XTENSA_ATOMIC_H */


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Re: [PATCH] Input - elantech: force a resolution of 31 u/mm

2015-07-16 Thread Dmitry Torokhov
On Tue, Jul 14, 2015 at 07:59:47PM +0200, David Herrmann wrote:
 Hi
 
 On Fri, Jul 10, 2015 at 2:32 AM, Peter Hutterer
 peter.hutte...@who-t.net wrote:
  All Elantech touchpads pre-v4 with dynamic resolution queries have a fixed
  resolution of 800dpi - 31.49 units/mm. Set this statically, so userspace 
  does
  not have to guess.
 
  Cc: Duson Lin duson...@emc.com.tw
  Signed-off-by: Peter Hutterer peter.hutte...@who-t.net
  ---
   drivers/input/mouse/elantech.c | 13 -
   1 file changed, 8 insertions(+), 5 deletions(-)
 
 I think this is much nicer than having to work around this in
 user-space. Much appreciated!
 
 Reviewed-by: David Herrmann dh.herrm...@gmail.com

Applied, thank you.

-- 
Dmitry
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[PATCH v2 1/2] tracing: allow disabling compilation of specific trace systems

2015-07-16 Thread Tal Shorer
Allow a trace events header file to disable compilation of its
trace events by defining the preprocessor macro NOTRACE.

This could be done, for example, according to a Kconfig option.

Signed-off-by: Tal Shorer tal.sho...@gmail.com
---
 include/linux/tracepoint.h   | 17 ++---
 include/trace/define_trace.h |  2 +-
 2 files changed, 15 insertions(+), 4 deletions(-)

diff --git a/include/linux/tracepoint.h b/include/linux/tracepoint.h
index c728513..a8ddfd3 100644
--- a/include/linux/tracepoint.h
+++ b/include/linux/tracepoint.h
@@ -103,7 +103,18 @@ extern void syscall_unregfunc(void);
 #define TP_ARGS(args...)   args
 #define TP_CONDITION(args...)  args
 
-#ifdef CONFIG_TRACEPOINTS
+/*
+ * Individual subsystem my have a separate configuration to
+ * enable their tracepoints. By default, this file will create
+ * the tracepoints if CONFIG_TRACEPOINT is defined. If a subsystem
+ * wants to be able to disable its tracepoints from being created
+ * it can define NOTRACE before including the tracepoint headers.
+ */
+#if defined(CONFIG_TRACEPOINTS)  !defined(NOTRACE)
+#define TRACEPOINTS_ENABLED
+#endif
+
+#ifdef TRACEPOINTS_ENABLED
 
 /*
  * it_func[0] is never NULL because there is at least one element in the array
@@ -226,7 +237,7 @@ extern void syscall_unregfunc(void);
 #define EXPORT_TRACEPOINT_SYMBOL(name) \
EXPORT_SYMBOL(__tracepoint_##name)
 
-#else /* !CONFIG_TRACEPOINTS */
+#else /* !TRACEPOINTS_ENABLED */
 #define __DECLARE_TRACE(name, proto, args, cond, data_proto, data_args) \
static inline void trace_##name(proto)  \
{ } \
@@ -258,7 +269,7 @@ extern void syscall_unregfunc(void);
 #define EXPORT_TRACEPOINT_SYMBOL_GPL(name)
 #define EXPORT_TRACEPOINT_SYMBOL(name)
 
-#endif /* CONFIG_TRACEPOINTS */
+#endif /* TRACEPOINTS_ENABLED */
 
 #ifdef CONFIG_TRACING
 /**
diff --git a/include/trace/define_trace.h b/include/trace/define_trace.h
index 02e1003..b763d3f 100644
--- a/include/trace/define_trace.h
+++ b/include/trace/define_trace.h
@@ -86,7 +86,7 @@
 #undef DECLARE_TRACE
 #define DECLARE_TRACE(name, proto, args)
 
-#ifdef CONFIG_EVENT_TRACING
+#ifdef TRACEPOINTS_ENABLED
 #include trace/ftrace.h
 #endif
 
-- 
2.4.3

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[PATCH v2 0/2] tracing: allow disabling compilation of specific trace systems

2015-07-16 Thread Tal Shorer
Currently, enabling CONFIG_TRACING on a system comes as all-or-nothing: either
tracepoints for all subsystems are compiled (with CONFIG_TRACING) or none of
them do (without it).

This caused me an unacceptable performance penalty (obviously SOME penalty was
expected, but not one so severe) which made me revert the changes in
configuration.

The first patch in this series modifies the files that actually define the
tracepoint to look for a preprocessor macro NOTRACE and define nops (as if
CONFIG_TRACING was not set) instead of them.

The second patch provides an example of how I see this working, with the gpio
subsystem as the example for absolutely no reason.
If this idea is deemed worth the time by the community, I'll create patches for
the other subsystems.



Changelog:

v2:
- A comment in tracepoint.h explaining NOTRACE and its use
- Avoid duplication of the test for both NOTRACE and a config option by
defining TRACEPOINTS_ENABLED when both are present and using that to check
whether or not to define tracepoints

Tal Shorer (2):
  tracing: allow disabling compilation of specific trace systems
  tracing: gpio: add Kconfig option for enabling/disabling trace events

 drivers/gpio/Kconfig | 7 +++
 include/linux/tracepoint.h   | 6 +++---
 include/trace/define_trace.h | 2 +-
 include/trace/events/gpio.h  | 4 
 4 files changed, 15 insertions(+), 4 deletions(-)

-- 
2.4.3

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Re: [PATCH] arm64: KVM: Enable minimalistic support for Thunder

2015-07-16 Thread Chalamarla, Tirumalesh
the discussion on the generic cpu seems to be stuck, is there a possibility to 
take this patch. so that Thunder has a chance to run some KVM.

Thanks,
Tirumalesh.  
 On Jun 29, 2015, at 10:11 AM, Marc Zyngier marc.zyng...@arm.com wrote:
 
 On 29/06/15 18:06, Chalamarla, Tirumalesh wrote:
 
 On Jun 29, 2015, at 1:53 AM, Marc Zyngier marc.zyng...@arm.com wrote:
 
 On 26/06/15 20:51, Tirumalesh Chalamarla wrote:
 In order to allow KVM to run on Thunder implementations, add the
 minimal support required.
 
 Signed-off-by: Tirumalesh Chalamarla tchalama...@caviumnetworks.com
 
 CCing the KVM/ARM maintainers should be the first course of action.
 
 thanks. 
 
 Also, you may want to try Suzuki's patch instead:
 
 http://www.spinics.net/lists/kvm/msg117703.html
 
 will try with this.
 
 Constantly adding new CPUs without providing any insight as to how they
 should be emulated only brings churn, and not much benefit.
 
 we are not planning(at this point) to emulate Thunder with QEMU/others.   
 
 Fair enough. If cross-cpu VM migration is none of your concern, then
 Suzuki's patch should be enough.
 
 Thanks,
 
   M.
 -- 
 Jazz is not dead. It just smells funny...

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[PATCH v2 2/2] tracing: gpio: add Kconfig option for enabling/disabling trace events

2015-07-16 Thread Tal Shorer
Add a new options to gpio Kconfig, CONFIG_GPIO_TRACING, that is used
for enabling/disabling compilation of gpio function trace events.

Signed-off-by: Tal Shorer tal.sho...@gmail.com
---
 drivers/gpio/Kconfig| 7 +++
 include/trace/events/gpio.h | 4 
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c1e2ca3..2829e8e 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -88,6 +88,13 @@ config GPIO_SYSFS
 config GPIO_GENERIC
tristate
 
+config GPIO_TRACING
+   bool gpio tracing
+   depends on TRACING
+   help
+ Enable tracing for gpio subsystem
+
+
 # put drivers in the right section, in alphabetical order
 
 config GPIO_DA9052
diff --git a/include/trace/events/gpio.h b/include/trace/events/gpio.h
index 927a8ad..09af636 100644
--- a/include/trace/events/gpio.h
+++ b/include/trace/events/gpio.h
@@ -1,6 +1,10 @@
 #undef TRACE_SYSTEM
 #define TRACE_SYSTEM gpio
 
+#ifndef CONFIG_GPIO_TRACING
+#define NOTRACE
+#endif
+
 #if !defined(_TRACE_GPIO_H) || defined(TRACE_HEADER_MULTI_READ)
 #define _TRACE_GPIO_H
 
-- 
2.4.3

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[PATCH 25/28] atomic: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/alpha/include/asm/atomic.h|1 -
 arch/arc/include/asm/atomic.h  |1 -
 arch/arm/include/asm/atomic.h  |1 -
 arch/arm64/include/asm/atomic.h|1 -
 arch/avr32/include/asm/atomic.h|2 --
 arch/blackfin/include/asm/atomic.h |2 --
 arch/frv/include/asm/atomic.h  |2 --
 arch/h8300/include/asm/atomic.h|2 --
 arch/hexagon/include/asm/atomic.h  |2 --
 arch/ia64/include/asm/atomic.h |2 --
 arch/m32r/include/asm/atomic.h |2 --
 arch/m68k/include/asm/atomic.h |2 --
 arch/metag/include/asm/atomic_lnkget.h |2 --
 arch/mips/include/asm/atomic.h |2 --
 arch/mn10300/include/asm/atomic.h  |2 --
 arch/parisc/include/asm/atomic.h   |2 --
 arch/powerpc/include/asm/atomic.h  |2 --
 arch/s390/include/asm/atomic.h |2 --
 arch/sh/include/asm/atomic-grb.h   |2 --
 arch/sparc/include/asm/atomic_32.h |2 --
 arch/sparc/include/asm/atomic_64.h |2 --
 arch/tile/include/asm/atomic_32.h  |2 --
 arch/tile/include/asm/atomic_64.h  |2 --
 arch/x86/include/asm/atomic.h  |2 --
 arch/xtensa/include/asm/atomic.h   |2 --
 include/asm-generic/atomic.h   |   21 -
 include/asm-generic/atomic64.h |4 
 include/linux/atomic.h |   13 -
 lib/atomic64.c |3 +++
 29 files changed, 19 insertions(+), 68 deletions(-)

--- a/arch/alpha/include/asm/atomic.h
+++ b/arch/alpha/include/asm/atomic.h
@@ -110,7 +110,6 @@ static __inline__ long atomic64_##op##_r
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
 #define atomic_andnot atomic_andnot
 #define atomic64_andnot atomic64_andnot
 
--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -144,7 +144,6 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add, +=, add)
 ATOMIC_OPS(sub, -=, sub)
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
 #define atomic_andnot atomic_andnot
 
 ATOMIC_OP(and, =, and)
--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -194,7 +194,6 @@ static inline int __atomic_add_unless(at
 ATOMIC_OPS(add, +=, add)
 ATOMIC_OPS(sub, -=, sub)
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
 #define atomic_andnot atomic_andnot
 
 ATOMIC_OP(and, =, and)
--- a/arch/arm64/include/asm/atomic.h
+++ b/arch/arm64/include/asm/atomic.h
@@ -85,7 +85,6 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add, add)
 ATOMIC_OPS(sub, sub)
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
 #define atomic_andnot atomic_andnot
 
 ATOMIC_OP(and, and)
--- a/arch/avr32/include/asm/atomic.h
+++ b/arch/avr32/include/asm/atomic.h
@@ -51,8 +51,6 @@ static inline void atomic_##op(int i, at
(void)__atomic_##op##_return(i, v); \
 }
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
-
 ATOMIC_OP(and, and)
 ATOMIC_OP(or, or)
 ATOMIC_OP(xor, eor)
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -28,8 +28,6 @@ asmlinkage int __raw_atomic_test_asm(con
 #define atomic_add_return(i, v) __raw_atomic_add_asm((v)-counter, i)
 #define atomic_sub_return(i, v) __raw_atomic_add_asm((v)-counter, -(i))
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
-
 #define atomic_or(i, v)  (void)__raw_atomic_or_asm((v)-counter, i)
 #define atomic_and(i, v) (void)__raw_atomic_and_asm((v)-counter, i)
 #define atomic_xor(i, v) (void)__raw_atomic_xor_asm((v)-counter, i)
--- a/arch/frv/include/asm/atomic.h
+++ b/arch/frv/include/asm/atomic.h
@@ -192,8 +192,6 @@ static inline void atomic64_##op(long lo
(void)__atomic64_fetch_##op(i, v-counter);\
 }
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
-
 ATOMIC_OP(or)
 ATOMIC_OP(and)
 ATOMIC_OP(xor)
--- a/arch/h8300/include/asm/atomic.h
+++ b/arch/h8300/include/asm/atomic.h
@@ -41,8 +41,6 @@ static inline void atomic_##op(int i, at
 ATOMIC_OP_RETURN(add, +=)
 ATOMIC_OP_RETURN(sub, -=)
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
-
 ATOMIC_OP(and, =)
 ATOMIC_OP(or,  |=)
 ATOMIC_OP(xor, ^=)
--- a/arch/hexagon/include/asm/atomic.h
+++ b/arch/hexagon/include/asm/atomic.h
@@ -132,8 +132,6 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
-
 ATOMIC_OP(and)
 ATOMIC_OP(or)
 ATOMIC_OP(xor)
--- a/arch/ia64/include/asm/atomic.h
+++ b/arch/ia64/include/asm/atomic.h
@@ -69,8 +69,6 @@ ATOMIC_OP(sub, -)
: ia64_atomic_sub(__ia64_asr_i, v); \
 })
 
-#define CONFIG_ARCH_HAS_ATOMIC_OR
-
 ATOMIC_OP(and, )
 ATOMIC_OP(or, |)
 ATOMIC_OP(xor, ^)
--- a/arch/m32r/include/asm/atomic.h
+++ b/arch/m32r/include/asm/atomic.h
@@ -94,8 +94,6 @@ static __inline__ int atomic_##op##_retu
 ATOMIC_OPS(add)
 

[PATCH 18/28] sparc: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: David S. Miller da...@davemloft.net
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/sparc/include/asm/atomic_32.h |4 
 arch/sparc/include/asm/atomic_64.h |6 ++
 arch/sparc/lib/atomic32.c  |   22 +++---
 arch/sparc/lib/atomic_64.S |6 ++
 arch/sparc/lib/ksyms.c |3 +++
 5 files changed, 38 insertions(+), 3 deletions(-)

--- a/arch/sparc/include/asm/atomic_32.h
+++ b/arch/sparc/include/asm/atomic_32.h
@@ -17,10 +17,14 @@
 #include asm/barrier.h
 #include asm-generic/atomic64.h
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
 
 #define ATOMIC_INIT(i)  { (i) }
 
 int atomic_add_return(int, atomic_t *);
+void atomic_and(int, atomic_t *);
+void atomic_or(int, atomic_t *);
+void atomic_xor(int, atomic_t *);
 int atomic_cmpxchg(atomic_t *, int, int);
 int atomic_xchg(atomic_t *, int);
 int __atomic_add_unless(atomic_t *, int, int);
--- a/arch/sparc/include/asm/atomic_64.h
+++ b/arch/sparc/include/asm/atomic_64.h
@@ -33,6 +33,12 @@ long atomic64_##op##_return(long, atomic
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
--- a/arch/sparc/lib/atomic32.c
+++ b/arch/sparc/lib/atomic32.c
@@ -27,22 +27,38 @@ static DEFINE_SPINLOCK(dummy);
 
 #endif /* SMP */
 
-#define ATOMIC_OP(op, cop) \
+#define ATOMIC_OP_RETURN(op, c_op) \
 int atomic_##op##_return(int i, atomic_t *v)   \
 {  \
int ret;\
unsigned long flags;\
spin_lock_irqsave(ATOMIC_HASH(v), flags);   \
\
-   ret = (v-counter cop i);   \
+   ret = (v-counter c_op i);  \
\
spin_unlock_irqrestore(ATOMIC_HASH(v), flags);  \
return ret; \
 }  \
 EXPORT_SYMBOL(atomic_##op##_return);
 
-ATOMIC_OP(add, +=)
+#define ATOMIC_OP(op, c_op)\
+void atomic_##op(int i, atomic_t *v)   \
+{  \
+   unsigned long flags;\
+   spin_lock_irqsave(ATOMIC_HASH(v), flags);   \
+   \
+   v-counter c_op i;  \
+   \
+   spin_unlock_irqrestore(ATOMIC_HASH(v), flags);  \
+}  \
+EXPORT_SYMBOL(atomic_##op);
+
+ATOMIC_OP_RETURN(add, +=)
+ATOMIC_OP(and, =)
+ATOMIC_OP(or, |=)
+ATOMIC_OP(xor, ^=)
 
+#undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
 int atomic_xchg(atomic_t *v, int new)
--- a/arch/sparc/lib/atomic_64.S
+++ b/arch/sparc/lib/atomic_64.S
@@ -47,6 +47,9 @@ ENDPROC(atomic_##op##_return);
 
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
 
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
@@ -84,6 +87,9 @@ ENDPROC(atomic64_##op##_return);
 
 ATOMIC64_OPS(add)
 ATOMIC64_OPS(sub)
+ATOMIC64_OP(and)
+ATOMIC64_OP(or)
+ATOMIC64_OP(xor)
 
 #undef ATOMIC64_OPS
 #undef ATOMIC64_OP_RETURN
--- a/arch/sparc/lib/ksyms.c
+++ b/arch/sparc/lib/ksyms.c
@@ -111,6 +111,9 @@ EXPORT_SYMBOL(atomic64_##op##_return);
 
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
 
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN


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[PATCH 04/28] arm: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/arm/include/asm/atomic.h |   15 +++
 1 file changed, 15 insertions(+)

--- a/arch/arm/include/asm/atomic.h
+++ b/arch/arm/include/asm/atomic.h
@@ -194,6 +194,14 @@ static inline int __atomic_add_unless(at
 ATOMIC_OPS(add, +=, add)
 ATOMIC_OPS(sub, -=, sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+#define atomic_andnot atomic_andnot
+
+ATOMIC_OP(and, =, and)
+ATOMIC_OP(andnot, = ~, bic)
+ATOMIC_OP(or,  |=, orr)
+ATOMIC_OP(xor, ^=, eor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -321,6 +329,13 @@ static inline long long atomic64_##op##_
 ATOMIC64_OPS(add, adds, adc)
 ATOMIC64_OPS(sub, subs, sbc)
 
+#define atomic64_andnot atomic64_andnot
+
+ATOMIC64_OP(and, and, and)
+ATOMIC64_OP(andnot, bic, bic)
+ATOMIC64_OP(or,  orr, orr)
+ATOMIC64_OP(xor, eor, eor)
+
 #undef ATOMIC64_OPS
 #undef ATOMIC64_OP_RETURN
 #undef ATOMIC64_OP


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[PATCH 05/28] arm64: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/arm64/include/asm/atomic.h |   15 +++
 1 file changed, 15 insertions(+)

--- a/arch/arm64/include/asm/atomic.h
+++ b/arch/arm64/include/asm/atomic.h
@@ -85,6 +85,14 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add, add)
 ATOMIC_OPS(sub, sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+#define atomic_andnot atomic_andnot
+
+ATOMIC_OP(and, and)
+ATOMIC_OP(andnot, bic)
+ATOMIC_OP(or, orr)
+ATOMIC_OP(xor, eor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -183,6 +191,13 @@ static inline long atomic64_##op##_retur
 ATOMIC64_OPS(add, add)
 ATOMIC64_OPS(sub, sub)
 
+#define atomic64_andnot atomic64_andnot
+
+ATOMIC64_OP(and, and)
+ATOMIC64_OP(andnot, bic)
+ATOMIC64_OP(or, orr)
+ATOMIC64_OP(xor, eor)
+
 #undef ATOMIC64_OPS
 #undef ATOMIC64_OP_RETURN
 #undef ATOMIC64_OP


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[PATCH 17/28] sh: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/sh/include/asm/atomic-grb.h  |   45 +-
 arch/sh/include/asm/atomic-irq.h  |   21 ++---
 arch/sh/include/asm/atomic-llsc.h |   31 ++
 arch/sh/include/asm/atomic.h  |   10 
 4 files changed, 22 insertions(+), 85 deletions(-)

--- a/arch/sh/include/asm/atomic-grb.h
+++ b/arch/sh/include/asm/atomic-grb.h
@@ -48,47 +48,14 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
-{
-   int tmp;
-   unsigned int _mask = ~mask;
-
-   __asm__ __volatile__ (
-  .align 2  \n\t
-  mova1f,   r0  \n\t /* r0 = end point */
-  movr15,   r1  \n\t /* r1 = saved sp */
-  mov#-6,   r15 \n\t /* LOGIN: r15 = size */
-  mov.l  @%1,   %0  \n\t /* load  old value */
-  and %2,   %0  \n\t /* add */
-  mov.l   %0,   @%1 \n\t /* store new value */
-   1: mov r1,   r15 \n\t /* LOGOUT */
-   : =r (tmp),
- +r  (v)
-   : r   (_mask)
-   : memory , r0, r1);
-}
-
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   int tmp;
-
-   __asm__ __volatile__ (
-  .align 2  \n\t
-  mova1f,   r0  \n\t /* r0 = end point */
-  movr15,   r1  \n\t /* r1 = saved sp */
-  mov#-6,   r15 \n\t /* LOGIN: r15 = size */
-  mov.l  @%1,   %0  \n\t /* load  old value */
-  or  %2,   %0  \n\t /* or */
-  mov.l   %0,   @%1 \n\t /* store new value */
-   1: mov r1,   r15 \n\t /* LOGOUT */
-   : =r (tmp),
- +r  (v)
-   : r   (mask)
-   : memory , r0, r1);
-}
-
 #endif /* __ASM_SH_ATOMIC_GRB_H */
--- a/arch/sh/include/asm/atomic-irq.h
+++ b/arch/sh/include/asm/atomic-irq.h
@@ -37,27 +37,12 @@ static inline int atomic_##op##_return(i
 
 ATOMIC_OPS(add, +=)
 ATOMIC_OPS(sub, -=)
+ATOMIC_OP(and, =)
+ATOMIC_OP(or, |=)
+ATOMIC_OP(xor, ^=)
 
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
-{
-   unsigned long flags;
-
-   raw_local_irq_save(flags);
-   v-counter = ~mask;
-   raw_local_irq_restore(flags);
-}
-
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   unsigned long flags;
-
-   raw_local_irq_save(flags);
-   v-counter |= mask;
-   raw_local_irq_restore(flags);
-}
-
 #endif /* __ASM_SH_ATOMIC_IRQ_H */
--- a/arch/sh/include/asm/atomic-llsc.h
+++ b/arch/sh/include/asm/atomic-llsc.h
@@ -52,37 +52,12 @@ static inline int atomic_##op##_return(i
 
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
 
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
-{
-   unsigned long tmp;
-
-   __asm__ __volatile__ (
-1:movli.l @%2, %0 ! atomic_clear_mask \n
-  and %1, %0  \n
-  movco.l %0, @%2 \n
-  bf  1b  \n
-   : =z (tmp)
-   : r (~mask), r (v-counter)
-   : t);
-}
-
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   unsigned long tmp;
-
-   __asm__ __volatile__ (
-1:movli.l @%2, %0 ! atomic_set_mask   \n
-  or  %1, %0  \n
-  movco.l %0, @%2 \n
-  bf  1b  \n
-   : =z (tmp)
-   : r (mask), r (v-counter)
-   : t);
-}
-
 #endif /* __ASM_SH_ATOMIC_LLSC_H */
--- a/arch/sh/include/asm/atomic.h
+++ b/arch/sh/include/asm/atomic.h
@@ -25,6 +25,16 @@
 #include asm/atomic-irq.h
 #endif
 
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
+{
+   atomic_and(~mask, v);
+}
+
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
+{
+   atomic_or(mask, v);
+}
+
 #define atomic_add_negative(a, v)  (atomic_add_return((a), (v))  0)
 #define atomic_dec_return(v)   atomic_sub_return(1, (v))
 #define atomic_inc_return(v)   atomic_add_return(1, (v))


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[PATCH 12/28] metag: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/metag/include/asm/atomic_lnkget.h |   38 -
 arch/metag/include/asm/atomic_lock1.h  |   21 ++
 2 files changed, 17 insertions(+), 42 deletions(-)

--- a/arch/metag/include/asm/atomic_lnkget.h
+++ b/arch/metag/include/asm/atomic_lnkget.h
@@ -74,42 +74,24 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
 {
-   int temp;
-
-   asm volatile (
-   1: LNKGETD %0, [%1]\n
-  AND %0, %0, %2\n
-  LNKSETD [%1] %0\n
-  DEFR%0, TXSTAT\n
-  ANDT%0, %0, #HI(0x3f00)\n
-  CMPT%0, #HI(0x0200)\n
-  BNZ 1b\n
-   : =d (temp)
-   : da (v-counter), bd (~mask)
-   : cc);
+   atomic_and(~mask, v);
 }
 
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-   int temp;
-
-   asm volatile (
-   1: LNKGETD %0, [%1]\n
-  OR  %0, %0, %2\n
-  LNKSETD [%1], %0\n
-  DEFR%0, TXSTAT\n
-  ANDT%0, %0, #HI(0x3f00)\n
-  CMPT%0, #HI(0x0200)\n
-  BNZ 1b\n
-   : =d (temp)
-   : da (v-counter), bd (mask)
-   : cc);
+   atomic_or(mask, v);
 }
 
 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
--- a/arch/metag/include/asm/atomic_lock1.h
+++ b/arch/metag/include/asm/atomic_lock1.h
@@ -68,29 +68,22 @@ static inline int atomic_##op##_return(i
 
 ATOMIC_OPS(add, +=)
 ATOMIC_OPS(sub, -=)
+ATOMIC_OP(and, =)
+ATOMIC_OP(or, |=)
+ATOMIC_OP(xor, ^=)
 
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
 {
-   unsigned long flags;
-
-   __global_lock1(flags);
-   fence();
-   v-counter = ~mask;
-   __global_unlock1(flags);
+   atomic_and(~mask, v);
 }
 
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-   unsigned long flags;
-
-   __global_lock1(flags);
-   fence();
-   v-counter |= mask;
-   __global_unlock1(flags);
+   atomic_or(mask, v);
 }
 
 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)


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Re: [PATCH 4/7] Documentation: mtd: add a DT property to set the latency code of Spansion memory

2015-07-16 Thread Marek Vasut
On Thursday, July 16, 2015 at 05:27:51 PM, Cyrille Pitchen wrote:

Hi!

 Both the SPI controller and the NOR flash memory need to agree on the
 number of dummy cycles to use for Fast Read commands. For Spansion
 memories, this number of dummy cycles is not given directly but through a
 so called latency code.
 The latency code can be found into the memory datasheet and depends on the
 SPI clock frequency, the Fast Read op code and the Single/Dual Data Rate
 mode.

Shouldn't you be able to derive the latency code from the above information,
which you already know then ?

Best regards,
Marek Vasut
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[PATCH 26/28] atomic: Collapse all atomic_{set,clear}_mask definitions

2015-07-16 Thread Peter Zijlstra
Move the now generic definitions of atomic_{set,clear}_mask() into
linux/atomic.h to avoid endless and pointless repetition.

Also, provide an atomic_andnot() wrapper for those few archs that can
implement that.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/arc/include/asm/atomic.h  |   10 --
 arch/blackfin/include/asm/atomic.h |   10 --
 arch/frv/include/asm/atomic.h  |   10 --
 arch/h8300/include/asm/atomic.h|   10 --
 arch/m32r/include/asm/atomic.h |   11 ---
 arch/m68k/include/asm/atomic.h |   10 --
 arch/metag/include/asm/atomic_lnkget.h |   10 --
 arch/metag/include/asm/atomic_lock1.h  |   10 --
 arch/mn10300/include/asm/atomic.h  |   24 
 arch/powerpc/kernel/misc_32.S  |   19 ---
 arch/s390/include/asm/atomic.h |   10 --
 arch/sh/include/asm/atomic.h   |   10 --
 arch/x86/include/asm/atomic.h  |   10 --
 arch/xtensa/include/asm/atomic.h   |   10 --
 include/asm-generic/atomic.h   |   10 --
 include/linux/atomic.h |   25 +
 16 files changed, 25 insertions(+), 174 deletions(-)

--- a/arch/arc/include/asm/atomic.h
+++ b/arch/arc/include/asm/atomic.h
@@ -155,16 +155,6 @@ ATOMIC_OP(xor, ^=, xor)
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 /**
  * __atomic_add_unless - add unless the number is a given value
  * @v: pointer of type atomic_t
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -32,16 +32,6 @@ asmlinkage int __raw_atomic_test_asm(con
 #define atomic_and(i, v) (void)__raw_atomic_and_asm((v)-counter, i)
 #define atomic_xor(i, v) (void)__raw_atomic_xor_asm((v)-counter, i)
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 #endif
 
 #include asm-generic/atomic.h
--- a/arch/frv/include/asm/atomic.h
+++ b/arch/frv/include/asm/atomic.h
@@ -198,14 +198,4 @@ ATOMIC_OP(xor)
 
 #undef ATOMIC_OP
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 #endif /* _ASM_ATOMIC_H */
--- a/arch/h8300/include/asm/atomic.h
+++ b/arch/h8300/include/asm/atomic.h
@@ -89,14 +89,4 @@ static inline int __atomic_add_unless(at
return ret;
 }
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 #endif /* __ARCH_H8300_ATOMIC __ */
--- a/arch/m32r/include/asm/atomic.h
+++ b/arch/m32r/include/asm/atomic.h
@@ -243,15 +243,4 @@ static __inline__ int __atomic_add_unles
return c;
 }
 
-
-static __inline__ __deprecated void atomic_clear_mask(unsigned int mask, 
atomic_t *v)
-{
-   atomic_and(~mask, v);
-}
-
-static __inline__ __deprecated void atomic_set_mask(unsigned int mask, 
atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 #endif /* _ASM_M32R_ATOMIC_H */
--- a/arch/m68k/include/asm/atomic.h
+++ b/arch/m68k/include/asm/atomic.h
@@ -174,16 +174,6 @@ static inline int atomic_add_negative(in
return c != 0;
 }
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
 {
int c, old;
--- a/arch/metag/include/asm/atomic_lnkget.h
+++ b/arch/metag/include/asm/atomic_lnkget.h
@@ -82,16 +82,6 @@ ATOMIC_OP(xor)
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
-{
-   atomic_or(mask, v);
-}
-
 static inline int atomic_cmpxchg(atomic_t *v, int old, int new)
 {
int result, temp;
--- a/arch/metag/include/asm/atomic_lock1.h
+++ b/arch/metag/include/asm/atomic_lock1.h
@@ -76,16 +76,6 @@ ATOMIC_OP(xor, ^=)
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
 
-static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
-{
-   atomic_and(~mask, v);
-}
-
-static inline __deprecated void atomic_set_mask(unsigned int mask, 

[PATCH 24/28] tile: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
From: Chris Metcalf cmetc...@ezchip.com

Implement atomic logic ops -- atomic_{or,xor,and}.

For tilegx, these are relatively straightforward; the architecture
provides atomic or and and, both 32-bit and 64-bit.  To support
xor we provide a loop using cmpexch.

For the older 32-bit tilepro architecture, we have to extend
the set of low-level assembly routines to include 32-bit and,
as well as all three 64-bit routines.  Somewhat confusingly,
some 32-bit versions are already used by the bitops inlines, with
parameter types appropriate for bitops, so we have to do a bit of
casting to match int to unsigned long.

Signed-off-by: Chris Metcalf cmetc...@ezchip.com
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
Link: 
http://lkml.kernel.org/r/1436474297-32187-1-git-send-email-cmetc...@ezchip.com
---

 arch/tile/include/asm/atomic_32.h |   30 +++
 arch/tile/include/asm/atomic_64.h |   42 ++
 arch/tile/lib/atomic_32.c |   23 
 arch/tile/lib/atomic_asm_32.S |4 +++
 4 files changed, 99 insertions(+)

--- a/arch/tile/include/asm/atomic_32.h
+++ b/arch/tile/include/asm/atomic_32.h
@@ -34,6 +34,21 @@ static inline void atomic_add(int i, ato
_atomic_xchg_add(v-counter, i);
 }
 
+#define ATOMIC_OP(op)  \
+unsigned long _atomic_##op(volatile unsigned long *p, unsigned long mask); \
+static inline void atomic_##op(int i, atomic_t *v) \
+{  \
+   _atomic_##op((unsigned long *)v-counter, i);  \
+}
+
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
+#undef ATOMIC_OP
+
 /**
  * atomic_add_return - add integer and return
  * @v: pointer of type atomic_t
@@ -113,6 +128,17 @@ static inline void atomic64_add(long lon
_atomic64_xchg_add(v-counter, i);
 }
 
+#define ATOMIC64_OP(op)\
+long long _atomic64_##op(long long *v, long long n);   \
+static inline void atomic64_##op(long long i, atomic64_t *v)   \
+{  \
+   _atomic64_##op(v-counter, i); \
+}
+
+ATOMIC64_OP(and)
+ATOMIC64_OP(or)
+ATOMIC64_OP(xor)
+
 /**
  * atomic64_add_return - add integer and return
  * @v: pointer of type atomic64_t
@@ -225,6 +251,7 @@ extern struct __get_user __atomic_xchg_a
 extern struct __get_user __atomic_xchg_add_unless(volatile int *p,
  int *lock, int o, int n);
 extern struct __get_user __atomic_or(volatile int *p, int *lock, int n);
+extern struct __get_user __atomic_and(volatile int *p, int *lock, int n);
 extern struct __get_user __atomic_andn(volatile int *p, int *lock, int n);
 extern struct __get_user __atomic_xor(volatile int *p, int *lock, int n);
 extern long long __atomic64_cmpxchg(volatile long long *p, int *lock,
@@ -234,6 +261,9 @@ extern long long __atomic64_xchg_add(vol
long long n);
 extern long long __atomic64_xchg_add_unless(volatile long long *p,
int *lock, long long o, long long n);
+extern long long __atomic64_and(volatile long long *p, int *lock, long long n);
+extern long long __atomic64_or(volatile long long *p, int *lock, long long n);
+extern long long __atomic64_xor(volatile long long *p, int *lock, long long n);
 
 /* Return failure from the atomic wrappers. */
 struct __get_user __atomic_bad_address(int __user *addr);
--- a/arch/tile/include/asm/atomic_64.h
+++ b/arch/tile/include/asm/atomic_64.h
@@ -58,6 +58,28 @@ static inline int __atomic_add_unless(at
return oldval;
 }
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+static inline void atomic_and(int i, atomic_t *v)
+{
+   __insn_fetchand4((void *)v-counter, i);
+}
+
+static inline void atomic_or(int i, atomic_t *v)
+{
+   __insn_fetchor4((void *)v-counter, i);
+}
+
+static inline void atomic_xor(int i, atomic_t *v)
+{
+   int guess, oldval = v-counter;
+   do {
+   guess = oldval;
+   __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
+   oldval = __insn_cmpexch4(v-counter, guess ^ i);
+   } while (guess != oldval);
+}
+
 /* Now the true 64-bit operations. */
 
 #define ATOMIC64_INIT(i)   { (i) }
@@ -91,6 +113,26 @@ static inline long atomic64_add_unless(a
return oldval != u;
 }
 
+static inline void atomic64_and(long i, atomic64_t *v)
+{
+   __insn_fetchand((void *)v-counter, i);
+}
+
+static inline void atomic64_or(long i, atomic64_t *v)
+{
+   __insn_fetchor((void *)v-counter, i);
+}
+
+static inline void atomic64_xor(long i, atomic64_t *v)
+{
+   long guess, oldval = v-counter;
+   do {
+   guess = oldval;
+   __insn_mtspr(SPR_CMPEXCH_VALUE, guess);
+   oldval = 

[PATCH 20/28] s390: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: Heiko Carstens heiko.carst...@de.ibm.com
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/s390/include/asm/atomic.h |   47 -
 1 file changed, 33 insertions(+), 14 deletions(-)

--- a/arch/s390/include/asm/atomic.h
+++ b/arch/s390/include/asm/atomic.h
@@ -27,6 +27,7 @@
 #define __ATOMIC_ORlao
 #define __ATOMIC_AND   lan
 #define __ATOMIC_ADD   laa
+#define __ATOMIC_XOR   lax
 #define __ATOMIC_BARRIER bcr  14,0\n
 
 #define __ATOMIC_LOOP(ptr, op_val, op_string, __barrier)   \
@@ -49,6 +50,7 @@
 #define __ATOMIC_ORor
 #define __ATOMIC_AND   nr
 #define __ATOMIC_ADD   ar
+#define __ATOMIC_XOR   xr
 #define __ATOMIC_BARRIER \n
 
 #define __ATOMIC_LOOP(ptr, op_val, op_string, __barrier)   \
@@ -118,14 +120,26 @@ static inline void atomic_add(int i, ato
 #define atomic_dec_return(_v)  atomic_sub_return(1, _v)
 #define atomic_dec_and_test(_v)(atomic_sub_return(1, _v) == 0)
 
-static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
+#define ATOMIC_OP(op, OP)  \
+static inline void atomic_##op(int i, atomic_t *v) \
+{  \
+   __ATOMIC_LOOP(v, i, __ATOMIC_##OP, __ATOMIC_NO_BARRIER);\
+}
+
+ATOMIC_OP(and, AND)
+ATOMIC_OP(or, OR)
+ATOMIC_OP(xor, XOR)
+
+#undef ATOMIC_OP
+
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
 {
-   __ATOMIC_LOOP(v, ~mask, __ATOMIC_AND, __ATOMIC_NO_BARRIER);
+   atomic_and(~mask, v);
 }
 
-static inline void atomic_set_mask(unsigned int mask, atomic_t *v)
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-   __ATOMIC_LOOP(v, mask, __ATOMIC_OR, __ATOMIC_NO_BARRIER);
+   atomic_or(mask, v);
 }
 
 #define atomic_xchg(v, new) (xchg(((v)-counter), new))
@@ -167,6 +181,7 @@ static inline int __atomic_add_unless(at
 #define __ATOMIC64_OR  laog
 #define __ATOMIC64_AND lang
 #define __ATOMIC64_ADD laag
+#define __ATOMIC64_XOR laxg
 #define __ATOMIC64_BARRIER bcr14,0\n
 
 #define __ATOMIC64_LOOP(ptr, op_val, op_string, __barrier) \
@@ -189,6 +204,7 @@ static inline int __atomic_add_unless(at
 #define __ATOMIC64_OR  ogr
 #define __ATOMIC64_AND ngr
 #define __ATOMIC64_ADD agr
+#define __ATOMIC64_XOR xgr
 #define __ATOMIC64_BARRIER \n
 
 #define __ATOMIC64_LOOP(ptr, op_val, op_string, __barrier) \
@@ -247,16 +263,6 @@ static inline void atomic64_add(long lon
__ATOMIC64_LOOP(v, i, __ATOMIC64_ADD, __ATOMIC64_NO_BARRIER);
 }
 
-static inline void atomic64_clear_mask(unsigned long mask, atomic64_t *v)
-{
-   __ATOMIC64_LOOP(v, ~mask, __ATOMIC64_AND, __ATOMIC64_NO_BARRIER);
-}
-
-static inline void atomic64_set_mask(unsigned long mask, atomic64_t *v)
-{
-   __ATOMIC64_LOOP(v, mask, __ATOMIC64_OR, __ATOMIC64_NO_BARRIER);
-}
-
 #define atomic64_xchg(v, new) (xchg(((v)-counter), new))
 
 static inline long long atomic64_cmpxchg(atomic64_t *v,
@@ -270,6 +276,19 @@ static inline long long atomic64_cmpxchg
return old;
 }
 
+#define ATOMIC64_OP(op, OP)\
+static inline void atomic64_##op(long i, atomic64_t *v)
\
+{  \
+   __ATOMIC64_LOOP(v, i, __ATOMIC64_##OP, __ATOMIC64_NO_BARRIER);  \
+}
+
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC64_OP(and, AND)
+ATOMIC64_OP(or, OR)
+ATOMIC64_OP(xor, XOR)
+
+#undef ATOMIC64_OP
 #undef __ATOMIC64_LOOP
 
 static inline int atomic64_add_unless(atomic64_t *v, long long i, long long u)


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[PATCH 13/28] mips: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: Ralf Baechle r...@linux-mips.org
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/mips/include/asm/atomic.h |9 +
 1 file changed, 9 insertions(+)

--- a/arch/mips/include/asm/atomic.h
+++ b/arch/mips/include/asm/atomic.h
@@ -137,6 +137,12 @@ static __inline__ int atomic_##op##_retu
 ATOMIC_OPS(add, +=, addu)
 ATOMIC_OPS(sub, -=, subu)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, =, and)
+ATOMIC_OP(or, |=, or)
+ATOMIC_OP(xor, ^=, xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -416,6 +422,9 @@ static __inline__ long atomic64_##op##_r
 
 ATOMIC64_OPS(add, +=, daddu)
 ATOMIC64_OPS(sub, -=, dsubu)
+ATOMIC64_OP(and, =, and)
+ATOMIC64_OP(or, |=, or)
+ATOMIC64_OP(xor, ^=, xor)
 
 #undef ATOMIC64_OPS
 #undef ATOMIC64_OP_RETURN


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[PATCH 14/28] mn10300: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/mn10300/include/asm/atomic.h |   57 ++
 1 file changed, 10 insertions(+), 47 deletions(-)

--- a/arch/mn10300/include/asm/atomic.h
+++ b/arch/mn10300/include/asm/atomic.h
@@ -89,6 +89,12 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -134,31 +140,9 @@ static inline void atomic_dec(atomic_t *
  *
  * Atomically clears the bits set in mask from the memory word specified.
  */
-static inline void atomic_clear_mask(unsigned long mask, unsigned long *addr)
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
 {
-#ifdef CONFIG_SMP
-   int status;
-
-   asm volatile(
-   1: mov %3,(_AAR,%2)\n
-  mov (_ADR,%2),%0\n
-  and %4,%0   \n
-  mov %0,(_ADR,%2)\n
-  mov (_ADR,%2),%0\n /* flush */
-  mov (_ASR,%2),%0\n
-  or  %0,%0   \n
-  bne 1b  \n
-   : =r(status), =m(*addr)
-   : a(ATOMIC_OPS_BASE_ADDR), r(addr), r(~mask)
-   : memory, cc);
-#else
-   unsigned long flags;
-
-   mask = ~mask;
-   flags = arch_local_cli_save();
-   *addr = mask;
-   arch_local_irq_restore(flags);
-#endif
+   atomic_and(~mask, v);
 }
 
 /**
@@ -168,30 +152,9 @@ static inline void atomic_clear_mask(uns
  *
  * Atomically sets the bits set in mask from the memory word specified.
  */
-static inline void atomic_set_mask(unsigned long mask, unsigned long *addr)
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-#ifdef CONFIG_SMP
-   int status;
-
-   asm volatile(
-   1: mov %3,(_AAR,%2)\n
-  mov (_ADR,%2),%0\n
-  or  %4,%0   \n
-  mov %0,(_ADR,%2)\n
-  mov (_ADR,%2),%0\n /* flush */
-  mov (_ASR,%2),%0\n
-  or  %0,%0   \n
-  bne 1b  \n
-   : =r(status), =m(*addr)
-   : a(ATOMIC_OPS_BASE_ADDR), r(addr), r(mask)
-   : memory, cc);
-#else
-   unsigned long flags;
-
-   flags = arch_local_cli_save();
-   *addr |= mask;
-   arch_local_irq_restore(flags);
-#endif
+   atomic_or(mask, v);
 }
 
 #endif /* __KERNEL__ */


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[PATCH 22/28] frv: Rewrite atomic implementation

2015-07-16 Thread Peter Zijlstra
Mostly complete rewrite of the FRV atomic implementation, instead of
using assembly files, use inline assembler.

The out-of-line CONFIG option makes a bit of a mess of things, but a
little CPP trickery gets that done too.

FRV already had the atomic logic ops but under a non standard name,
the reimplementation provides the generic names and provides the
intermediate form required for the bitops implementation.

The slightly inconsistent __atomic32_fetch_##op naming is because
__atomic_fetch_##op conlicts with GCC builtin functions.

The 64bit atomic ops use the inline assembly %Ln construct to access
the low word register (r+1), afaik this construct was not previously
used in the kernel and is completely undocumented, but I found it in
the FRV GCC code and it seems to work.

FRV had a non-standard definition of atomic_{clear,set}_mask() which
would work types other than atomic_t, the one user relying on that
(arch/frv/kernel/dma.c) got converted to use the new intermediate
form.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/frv/include/asm/atomic.h  |  119 ++---
 arch/frv/include/asm/atomic_defs.h |  172 +
 arch/frv/include/asm/bitops.h  |   99 ++---
 arch/frv/kernel/dma.c  |6 -
 arch/frv/kernel/frv_ksyms.c|5 -
 arch/frv/lib/Makefile  |2 
 arch/frv/lib/atomic-lib.c  |7 +
 arch/frv/lib/atomic-ops.S  |  110 ---
 arch/frv/lib/atomic64-ops.S|   94 
 9 files changed, 259 insertions(+), 355 deletions(-)

--- a/arch/frv/include/asm/atomic.h
+++ b/arch/frv/include/asm/atomic.h
@@ -15,7 +15,6 @@
 #define _ASM_ATOMIC_H
 
 #include linux/types.h
-#include asm/spr-regs.h
 #include asm/cmpxchg.h
 #include asm/barrier.h
 
@@ -23,6 +22,8 @@
 #error not SMP safe
 #endif
 
+#include asm/atomic_defs.h
+
 /*
  * Atomic operations that C can't guarantee us.  Useful for
  * resource counting etc..
@@ -34,56 +35,26 @@
 #define atomic_read(v) ACCESS_ONCE((v)-counter)
 #define atomic_set(v, i)   (((v)-counter) = (i))
 
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-static inline int atomic_add_return(int i, atomic_t *v)
+static inline int atomic_inc_return(atomic_t *v)
 {
-   unsigned long val;
+   return __atomic_add_return(1, v-counter);
+}
 
-   asm(0: \n
-  orccgr0,gr0,gr0,icc3\n /* set ICC3.Z */
-  ckeqicc3,cc7\n
-  ld.p%M0,%1  \n /* LD.P/ORCR 
must be atomic */
-  orcrcc7,cc7,cc3 \n /* set CC3 to 
true */
-  add%I2  %1,%2,%1\n
-  cst.p   %1,%M0  ,cc3,#1 \n
-  corcc   gr29,gr29,gr0   ,cc3,#1 \n /* clear ICC3.Z 
if store happens */
-  beq icc3,#0,0b  \n
-   : +U(v-counter), =r(val)
-   : NPr(i)
-   : memory, cc7, cc3, icc3
-   );
+static inline int atomic_dec_return(atomic_t *v)
+{
+   return __atomic_sub_return(1, v-counter);
+}
 
-   return val;
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+   return __atomic_add_return(i, v-counter);
 }
 
 static inline int atomic_sub_return(int i, atomic_t *v)
 {
-   unsigned long val;
-
-   asm(0: \n
-  orccgr0,gr0,gr0,icc3\n /* set ICC3.Z */
-  ckeqicc3,cc7\n
-  ld.p%M0,%1  \n /* LD.P/ORCR 
must be atomic */
-  orcrcc7,cc7,cc3 \n /* set CC3 to 
true */
-  sub%I2  %1,%2,%1\n
-  cst.p   %1,%M0  ,cc3,#1 \n
-  corcc   gr29,gr29,gr0   ,cc3,#1 \n /* clear ICC3.Z 
if store happens */
-  beq icc3,#0,0b  \n
-   : +U(v-counter), =r(val)
-   : NPr(i)
-   : memory, cc7, cc3, icc3
-   );
-
-   return val;
+   return __atomic_sub_return(i, v-counter);
 }
 
-#else
-
-extern int atomic_add_return(int i, atomic_t *v);
-extern int atomic_sub_return(int i, atomic_t *v);
-
-#endif
-
 static inline int atomic_add_negative(int i, atomic_t *v)
 {
return atomic_add_return(i, v)  0;
@@ -101,17 +72,14 @@ static inline void atomic_sub(int i, ato
 
 static inline void atomic_inc(atomic_t *v)
 {
-   atomic_add_return(1, v);
+   atomic_inc_return(v);
 }
 
 static inline void atomic_dec(atomic_t *v)
 {
-   atomic_sub_return(1, v);
+   atomic_dec_return(v);
 }
 
-#define atomic_dec_return(v)   atomic_sub_return(1, (v))
-#define atomic_inc_return(v)   atomic_add_return(1, (v))
-
 #define 

[PATCH 11/28] m68k: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Acked-by: Geert Uytterhoeven ge...@linux-m68k.org
Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/m68k/include/asm/atomic.h |   14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

--- a/arch/m68k/include/asm/atomic.h
+++ b/arch/m68k/include/asm/atomic.h
@@ -77,6 +77,12 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add, +=, add)
 ATOMIC_OPS(sub, -=, sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and, =, and)
+ATOMIC_OP(or, |=, or)
+ATOMIC_OP(xor, ^=, eor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP
@@ -170,14 +176,14 @@ static inline int atomic_add_negative(in
return c != 0;
 }
 
-static inline void atomic_clear_mask(unsigned long mask, unsigned long *v)
+static inline __deprecated void atomic_clear_mask(unsigned int mask, atomic_t 
*v)
 {
-   __asm__ __volatile__(andl %1,%0 : +m (*v) : ASM_DI (~(mask)));
+   atomic_and(~mask, v);
 }
 
-static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
+static inline __deprecated void atomic_set_mask(unsigned int mask, atomic_t *v)
 {
-   __asm__ __volatile__(orl %1,%0 : +m (*v) : ASM_DI (mask));
+   atomic_or(mask, v);
 }
 
 static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)


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[PATCH 08/28] hexagon: Provide atomic_{or,xor,and}

2015-07-16 Thread Peter Zijlstra
Implement atomic logic ops -- atomic_{or,xor,and}.

These will replace the atomic_{set,clear}_mask functions that are
available on some archs.

Signed-off-by: Peter Zijlstra (Intel) pet...@infradead.org
---
 arch/hexagon/include/asm/atomic.h |6 ++
 1 file changed, 6 insertions(+)

--- a/arch/hexagon/include/asm/atomic.h
+++ b/arch/hexagon/include/asm/atomic.h
@@ -132,6 +132,12 @@ static inline int atomic_##op##_return(i
 ATOMIC_OPS(add)
 ATOMIC_OPS(sub)
 
+#define CONFIG_ARCH_HAS_ATOMIC_OR
+
+ATOMIC_OP(and)
+ATOMIC_OP(or)
+ATOMIC_OP(xor)
+
 #undef ATOMIC_OPS
 #undef ATOMIC_OP_RETURN
 #undef ATOMIC_OP


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Re: [PATCH 10/13] arm64: Add support for running Linux in EL2 mode

2015-07-16 Thread Will Deacon
On Wed, Jul 08, 2015 at 05:19:13PM +0100, Marc Zyngier wrote:
 With the ARMv8.1 VHE, the architecture is able to (almost) transparently
 run the kernel at EL2, despite being written for EL1.
 
 This patch takes care of the almost part, mostly preventing the kernel
 from dropping from EL2 to EL1, and setting up the HYP configuration.
 
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 ---
  arch/arm64/kernel/head.S | 23 ++-
  1 file changed, 22 insertions(+), 1 deletion(-)
 
 diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
 index c0ff3ce..a179747 100644
 --- a/arch/arm64/kernel/head.S
 +++ b/arch/arm64/kernel/head.S
 @@ -29,6 +29,7 @@
  #include asm/asm-offsets.h
  #include asm/cache.h
  #include asm/cputype.h
 +#include asm/kvm_mmu.h
  #include asm/memory.h
  #include asm/thread_info.h
  #include asm/pgtable-hwdef.h
 @@ -481,8 +482,16 @@ CPU_LE(  bic x0, x0, #(3  24)  )   // 
 Clear the EE and E0E bits for EL1
   isb
   ret
  
 + /* Check for VHE being present */
 +2:   mrs x2, id_aa64mmfr1_el1
 + ubfxx2, x2, #8, #4
 +
   /* Hyp configuration. */
 -2:   mov x0, #(1  31)  // 64-bit EL1
 + mov x0, #HCR_RW // 64-bit EL1
 + cbz x2, set_hcr
 + orr x0, x0, #HCR_TGE// Enable Host Extensions
 + orr x0, x0, #HCR_E2H
 +set_hcr:
   msr hcr_el2, x0
  
   /* Generic timers. */
 @@ -522,6 +531,9 @@ CPU_LE(   movkx0, #0x30d0, lsl #16)   // 
 Clear EE and E0E on LE systems
  
   /* Coprocessor traps. */
   mov x0, #0x33ff

These bits are RES0 with VHE enabled, afaict.

 + cbz x2, set_cptr
 + orr x0, x0, #(3  20)  // Don't trap FP
 +set_cptr:
   msr cptr_el2, x0// Disable copro. traps to EL2
  
  #ifdef CONFIG_COMPAT
 @@ -531,6 +543,15 @@ CPU_LE(  movkx0, #0x30d0, lsl #16)   // 
 Clear EE and E0E on LE systems
   /* Stage-2 translation */
   msr vttbr_el2, xzr
  
 + cbz x2, install_el2_stub
 +
 + setup_vtcr x4, x5
 +
 + mov w20, #BOOT_CPU_MODE_EL2 // This CPU booted in EL2

You do this in install_el2_stub as well -- can you move it above the cbz?

Will
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Re: [PATCH v9 07/22] tracing: Add lock-free tracing_map

2015-07-16 Thread Peter Zijlstra
On Thu, Jul 16, 2015 at 12:22:40PM -0500, Tom Zanussi wrote:
 + for (i = 0; i  elt-map-n_fields; i++) {
 + atomic64_set(dup_elt-fields[i].sum,
 +  atomic64_read(elt-fields[i].sum));
 + dup_elt-fields[i].cmp_fn = elt-fields[i].cmp_fn;
 + }
 +
 + return dup_elt;
 +}

So there is a lot of atomic64_{set,read}() in this patch set, what kind
of magic properties do you assume they have?

Note that atomic*_{set,read}() are weaker than {WRITE,READ}_ONCE(), so
if you're assuming they do that, you're mistaken -- although it is on a
TODO list someplace to go fix that.
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Re: [mminit] [ INFO: possible recursive locking detected ]

2015-07-16 Thread Mel Gorman
On Thu, Jul 16, 2015 at 08:13:38PM +0300, Konstantin Khlebnikov wrote:
  @@ -1187,14 +1195,14 @@ void __init page_alloc_init_late(void)
   {pgdat_init_rwsempgdat_init_rwsempgdat_init_rwsem
  int nid;
 
  +   /* There will be num_node_state(N_MEMORY) threads */
  +   atomic_set(pgdat_init_n_undone, num_node_state(N_MEMORY));
  for_each_node_state(nid, N_MEMORY) {
  -   down_read(pgdat_init_rwsem);
 
 Rw-sem have special non-owner mode for keeping lockdep away.
 This should be enough:
 

I think in this case that the completions look nicer though so I think
I'll keep them.

-- 
Mel Gorman
SUSE Labs
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[PATCH-v3 0/2] mfd: 88pm800: Add 88pm860 device support

2015-07-16 Thread Vaibhav Hiremath
88PM860 falls under 88pm800 family of devices, with some feature
additions, for example, support for dual phase on BUCK1.

This patch series, enabled chip ID support for 88pm860 in the driver
and adds Init time configuration support based on chip ID

V2 = V3
===
Link to V2: 
https://www.mail-archive.com/linux-kernel@vger.kernel.org/msg931170.html

  - Mistakenly introduced warning in V2, unused variable 'val'
Fixed it.
Note that no other code change compared to V2.

V1 = V2

 - Dropped PATCH [03/06 to 06/06]
PATCH [03  04]: New clock provider driver is under development for
32KHz clock output enable/disable

PATCH [05  06]: Moved to regulator driver and will be part of regulator
changes patch-series, as dual-phase configuration belongs to regulator.

  - Added Acked-by of Krzysztof Kozlowski

  - Added comment into the code for missing init configuration for
88pm800  88pm805 device.

TODO:
  - Some of init time configurations are common to both 88pm800 and 88pm860
devices, but since I can not validate it, decided to move it to
88pm860 block only.
But if someone is willing to help me in validation, we can move it to
common code later. No issues there.
  - Sleep/low-power-mode related configuration is also part of init time,
but since we are too far from sleep mode support and without testing
I do not want add anything, decided to take it later when we actually
start looking at sleep support.
  - Init time configuration also includes pinmux setting for the device.
I am working on using pinctrl-single driver to have standard and generic
interface, hopefully it will get handled through pinctrl subsystem.
  Link to RFC - https://patches.linaro.org/50604/

Vaibhav Hiremath (2):
  mfd: 88pm80x: Add 88pm860 chip type support
  mfd: 88pm800: Add init time initial configuration support

 drivers/mfd/88pm800.c   | 70 +
 drivers/mfd/88pm80x.c   |  2 ++
 include/linux/mfd/88pm80x.h | 14 +
 3 files changed, 86 insertions(+)

-- 
1.9.1

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[PATCH-v3 1/2] mfd: 88pm80x: Add 88pm860 chip type support

2015-07-16 Thread Vaibhav Hiremath
Add chip identification support for 88PM860 device
to the pm80x_chip_mapping table.

Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
 drivers/mfd/88pm80x.c   | 2 ++
 include/linux/mfd/88pm80x.h | 1 +
 2 files changed, 3 insertions(+)

diff --git a/drivers/mfd/88pm80x.c b/drivers/mfd/88pm80x.c
index 5e72f65..63445ea 100644
--- a/drivers/mfd/88pm80x.c
+++ b/drivers/mfd/88pm80x.c
@@ -33,6 +33,8 @@ static struct pm80x_chip_mapping chip_mapping[] = {
{0x3,   CHIP_PM800},
/* 88PM805 chip id number */
{0x0,   CHIP_PM805},
+   /* 88PM860 chip id number */
+   {0x4,   CHIP_PM860},
 };
 
 /*
diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
index 9c5773b..2e25fb1 100644
--- a/include/linux/mfd/88pm80x.h
+++ b/include/linux/mfd/88pm80x.h
@@ -21,6 +21,7 @@ enum {
CHIP_INVALID = 0,
CHIP_PM800,
CHIP_PM805,
+   CHIP_PM860,
CHIP_MAX,
 };
 
-- 
1.9.1

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[PATCH-v3 2/2] mfd: 88pm800: Add init time initial configuration support

2015-07-16 Thread Vaibhav Hiremath
This patch adds init time configuration of 88PM800/805 and
88PM860. It includes,

  - Enable BUCK clock gating in low power mode
  - Full mode support for BUCK2 and 4
  - Enable voltage change (LPF, DVC) in PMIC

Note that both 88PM800 and 88PM860 do share common configurations,
but since I can not validate the configuration on 88PM800,
restricting myself only to 88PM860.
If anyone can validate on 88PM800, we can move common code accordingly.

Signed-off-by: Vaibhav Hiremath vaibhav.hirem...@linaro.org
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com
---
 drivers/mfd/88pm800.c   | 70 +
 include/linux/mfd/88pm80x.h | 13 +
 2 files changed, 83 insertions(+)

diff --git a/drivers/mfd/88pm800.c b/drivers/mfd/88pm800.c
index 95c8ad4..f104a32 100644
--- a/drivers/mfd/88pm800.c
+++ b/drivers/mfd/88pm800.c
@@ -521,6 +521,69 @@ out:
return ret;
 }
 
+static int pm800_init_config(struct pm80x_chip *chip, struct device_node *np)
+{
+   int ret;
+
+   /*
+* Although both 88PM800  88PM860 do share some common configurations,
+* and should have common code wherever possible. But due to lack of
+* testing on 88pm800/88pm805 device, common code is avoided as of now.
+*
+* Once it is tested on 88PM800, it can be moved to common code.
+*/
+   switch (chip-type) {
+   case CHIP_PM800:
+   case CHIP_PM805:
+   break;
+   case CHIP_PM860:
+   /* Enable LDO and BUCK clock gating in low power mode */
+   ret = regmap_update_bits(chip-regmap, PM800_LOW_POWER_CONFIG3,
+   PM800_LDOBK_FREEZE, PM800_LDOBK_FREEZE);
+   if (ret)
+   goto error;
+
+   /* Enable voltage change in pmic, POWER_HOLD = 1 */
+   ret = regmap_update_bits(chip-regmap, PM800_WAKEUP1,
+   PM800_PWR_HOLD_EN, PM800_PWR_HOLD_EN);
+   if (ret)
+   goto error;
+
+   /*
+* Set buck2 and buck4 driver selection to be full.
+* The default value is 0, for full drive support
+* it should be set to 1.
+* In A1 version it will be set to 1 by default.
+* To be on safer side, set it explicitly
+*/
+   ret = regmap_update_bits(chip-subchip-regmap_power,
+   PM860_BUCK2_MISC2,
+   PM860_BUCK2_FULL_DRV,
+   PM860_BUCK2_FULL_DRV);
+   if (ret)
+   goto error;
+
+   ret = regmap_update_bits(chip-subchip-regmap_power,
+   PM860_BUCK4_MISC2,
+   PM860_BUCK4_FULL_DRV,
+   PM860_BUCK4_FULL_DRV);
+   if (ret)
+   goto error;
+
+
+   break;
+   default:
+   dev_err(chip-dev, Unknown device type: %d\n, chip-type);
+   break;
+   }
+
+   return 0;
+
+error:
+   dev_err(chip-dev, failed to access registers\n);
+   return ret;
+}
+
 static int pm800_probe(struct i2c_client *client,
 const struct i2c_device_id *id)
 {
@@ -585,6 +648,13 @@ static int pm800_probe(struct i2c_client *client,
if (pdata-plat_config)
pdata-plat_config(chip, pdata);
 
+   /* common register configurations , init time only */
+   ret = pm800_init_config(chip, np);
+   if (ret) {
+   dev_err(chip-dev, Failed to configure 88pm800 devices\n);
+   goto err_device_init;
+   }
+
return 0;
 
 err_device_init:
diff --git a/include/linux/mfd/88pm80x.h b/include/linux/mfd/88pm80x.h
index 2e25fb1..2ef62af 100644
--- a/include/linux/mfd/88pm80x.h
+++ b/include/linux/mfd/88pm80x.h
@@ -74,6 +74,7 @@ enum {
 
 /* Wakeup Registers */
 #define PM800_WAKEUP1  (0x0D)
+#define PM800_PWR_HOLD_EN  BIT(7)
 
 #define PM800_WAKEUP2  (0x0E)
 #define PM800_WAKEUP2_INV_INT  BIT(0)
@@ -87,7 +88,10 @@ enum {
 /* Referance and low power registers */
 #define PM800_LOW_POWER1   (0x20)
 #define PM800_LOW_POWER2   (0x21)
+
 #define PM800_LOW_POWER_CONFIG3(0x22)
+#define PM800_LDOBK_FREEZE BIT(7)
+
 #define PM800_LOW_POWER_CONFIG4(0x23)
 
 /* GPIO register */
@@ -279,6 +283,15 @@ enum {
 #define PM805_EARPHONE_SETTING (0x29)
 #define PM805_AUTO_SEQ_SETTING (0x2A)
 
+
+/* 88PM860 Registers */
+
+#define PM860_BUCK2_MISC2  (0x7C)
+#define PM860_BUCK2_FULL_DRV   BIT(2)
+
+#define PM860_BUCK4_MISC2  (0x82)
+#define PM860_BUCK4_FULL_DRV   BIT(2)
+
 struct pm80x_rtc_pdata {
int  

[PATCH] arm64: remove dead code

2015-07-16 Thread Mark Salter
Commit 68234df4ea79 (arm64: kill flush_cache_all()) removed
soft_reset() from the kernel. This was the only caller of
setup_mm_for_reboot(), so remove that also.

Signed-off-by: Mark Salter msal...@redhat.com
---
 arch/arm64/include/asm/mmu.h |  1 -
 arch/arm64/mm/mmu.c  | 11 ---
 2 files changed, 12 deletions(-)

diff --git a/arch/arm64/include/asm/mmu.h b/arch/arm64/include/asm/mmu.h
index 79fcfb0..0302087 100644
--- a/arch/arm64/include/asm/mmu.h
+++ b/arch/arm64/include/asm/mmu.h
@@ -28,7 +28,6 @@ typedef struct {
 #define ASID(mm)   ((mm)-context.id  0x)
 
 extern void paging_init(void);
-extern void setup_mm_for_reboot(void);
 extern void __iomem *early_io_map(phys_addr_t phys, unsigned long virt);
 extern void init_mem_pgprot(void);
 extern void create_pgd_mapping(struct mm_struct *mm, phys_addr_t phys,
diff --git a/arch/arm64/mm/mmu.c b/arch/arm64/mm/mmu.c
index a4ede4e..63012fe 100644
--- a/arch/arm64/mm/mmu.c
+++ b/arch/arm64/mm/mmu.c
@@ -461,17 +461,6 @@ void __init paging_init(void)
 }
 
 /*
- * Enable the identity mapping to allow the MMU disabling.
- */
-void setup_mm_for_reboot(void)
-{
-   cpu_set_reserved_ttbr0();
-   flush_tlb_all();
-   cpu_set_idmap_tcr_t0sz();
-   cpu_switch_mm(idmap_pg_dir, init_mm);
-}
-
-/*
  * Check whether a kernel address is valid (derived from arch/x86/).
  */
 int kern_addr_valid(unsigned long addr)
-- 
2.4.3

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[PATCH net-next 1/1] hv_netvsc: Wait for sub-channels to be processed during probe

2015-07-16 Thread K. Y. Srinivasan
The current code returns from probe without waiting for the proper handling
of subchannels that may be requested. If the netvsc driver were to be rapidly
loaded/unloaded, we can  trigger a panic as the unload will be tearing
down state that may not have been fully setup yet. We fix this issue by making
sure that we return from the probe call only after ensuring that the
sub-channel offers in flight are properly handled.

Signed-off-by: K. Y. Srinivasan k...@microsoft.com
Reviewed-and-tested-by: Haiyang Zhang haiya...@microsoft.com
---
 drivers/net/hyperv/hyperv_net.h   |2 ++
 drivers/net/hyperv/rndis_filter.c |   25 +
 2 files changed, 27 insertions(+), 0 deletions(-)

diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h
index 26cd14c..925b75d 100644
--- a/drivers/net/hyperv/hyperv_net.h
+++ b/drivers/net/hyperv/hyperv_net.h
@@ -671,6 +671,8 @@ struct netvsc_device {
u32 send_table[VRSS_SEND_TAB_SIZE];
u32 max_chn;
u32 num_chn;
+   spinlock_t sc_lock; /* Protects num_sc_offered variable */
+   u32 num_sc_offered;
atomic_t queue_sends[NR_CPUS];
 
/* Holds rndis device info */
diff --git a/drivers/net/hyperv/rndis_filter.c 
b/drivers/net/hyperv/rndis_filter.c
index 2e40417..2e09f3f 100644
--- a/drivers/net/hyperv/rndis_filter.c
+++ b/drivers/net/hyperv/rndis_filter.c
@@ -984,9 +984,16 @@ static void netvsc_sc_open(struct vmbus_channel *new_sc)
struct netvsc_device *nvscdev;
u16 chn_index = new_sc-offermsg.offer.sub_channel_index;
int ret;
+   unsigned long flags;
 
nvscdev = hv_get_drvdata(new_sc-primary_channel-device_obj);
 
+   spin_lock_irqsave(nvscdev-sc_lock, flags);
+   nvscdev-num_sc_offered--;
+   spin_unlock_irqrestore(nvscdev-sc_lock, flags);
+   if (nvscdev-num_sc_offered == 0)
+   complete(nvscdev-channel_init_wait);
+
if (chn_index = nvscdev-num_chn)
return;
 
@@ -1015,8 +1022,10 @@ int rndis_filter_device_add(struct hv_device *dev,
u32 rsscap_size = sizeof(struct ndis_recv_scale_cap);
u32 mtu, size;
u32 num_rss_qs;
+   u32 sc_delta;
const struct cpumask *node_cpu_mask;
u32 num_possible_rss_qs;
+   unsigned long flags;
 
rndis_device = get_rndis_device();
if (!rndis_device)
@@ -1039,6 +1048,8 @@ int rndis_filter_device_add(struct hv_device *dev,
net_device-max_chn = 1;
net_device-num_chn = 1;
 
+   spin_lock_init(net_device-sc_lock);
+
net_device-extension = rndis_device;
rndis_device-net_dev = net_device;
 
@@ -1116,6 +1127,9 @@ int rndis_filter_device_add(struct hv_device *dev,
num_possible_rss_qs = cpumask_weight(node_cpu_mask);
net_device-num_chn = min(num_possible_rss_qs, num_rss_qs);
 
+   num_rss_qs = net_device-num_chn - 1;
+   net_device-num_sc_offered = num_rss_qs;
+
if (net_device-num_chn == 1)
goto out;
 
@@ -1157,11 +1171,22 @@ int rndis_filter_device_add(struct hv_device *dev,
 
ret = rndis_filter_set_rss_param(rndis_device, net_device-num_chn);
 
+   /*
+* Wait for the host to send us the sub-channel offers.
+*/
+   spin_lock_irqsave(net_device-sc_lock, flags);
+   sc_delta = net_device-num_chn - 1 - num_rss_qs;
+   net_device-num_sc_offered -= sc_delta;
+   spin_unlock_irqrestore(net_device-sc_lock, flags);
+
+   if (net_device-num_sc_offered != 0)
+   wait_for_completion(net_device-channel_init_wait);
 out:
if (ret) {
net_device-max_chn = 1;
net_device-num_chn = 1;
}
+
return 0; /* return 0 because primary channel can be used alone */
 
 err_dev_remv:
-- 
1.7.4.1

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Re: [PATCH v4 1/2] vTPM: support little endian guests

2015-07-16 Thread Hon Ching(Vicky) Lo
Hi Peter,


On Mon, 2015-07-13 at 23:08 +0200, Peter Hüwe wrote:
 Hi Vicky,
 
 sorry for the late reply
 
 
  This patch makes the code endianness independent. We defined a
  macro do_endian_conversion to apply endianness to raw integers
  in the event entries so that they will be displayed properly.
  tpm_binary_bios_measurements_show() is modified for the display.
  
  Signed-off-by: Hon Ching(Vicky) Lo hon...@linux.vnet.ibm.com
  Signed-off-by: Joy Latten jmlat...@linux.vnet.ibm.com
 
  b/drivers/char/tpm/tpm_eventlog.h index e7da086..267bfbd 100644
  --- a/drivers/char/tpm/tpm_eventlog.h
  +++ b/drivers/char/tpm/tpm_eventlog.h
  @@ -6,6 +6,12 @@
   #define MAX_TEXT_EVENT 1000/* Max event string length */
   #define ACPI_TCPA_SIG  TCPA  /* 0x41504354 /'TCPA' */
  
  +#ifdef CONFIG_PPC64
  +#define do_endian_conversion(x) be32_to_cpu(x)
  +#else
  +#define do_endian_conversion(x) x
  +#endif
 
 
 Why is this macro needed?
 shouldn't the be32_to_cpu macro already do correct thing?
 Or am I missing something here?
 
 
 Thanks,
 Peter
 
The macro is defined to not do the conversion in the architecture
that does not need it.


Regards,
Vicky

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Re: [PATCH] Staging: drivers: dgnc

2015-07-16 Thread Joe Perches
On Fri, 2015-07-17 at 00:20 +, Craig Inches wrote:
 Hi Joe,

Rehi Craig.

 On Thu, Jul 16, 2015 at 08:30:53AM -0700, Joe Perches wrote:
  On Thu, 2015-07-16 at 23:11 +, Craig Inches wrote:
   Fixed up some checkpatch.pl style issues.
   Line greater than 80 Chars in multiple locations.
  
  I think most all of these are not improvements.
   Ok, can you be a little more specific? I did see some that where
   not worth modifying due to only being 1 or 2 chars over, and
   breaking the line seemed pointless.

Precisely.

Please don't do things you recognize as pointless
just to satisfy some brainless script.

  Please use --strict when verifying your patches.
   Not sure where the --strict should be set? I cant see the option
   in  the checklist.pl script 

$ ./scripts/checkpatch.pl --help
[...]
  --subjective, --strict enable more subjective tests
[...]
$


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[PATCH] staging: fsl-mc: update TODO list

2015-07-16 Thread Stuart Yoder
update TODO list to provide more detail on remaining work

Signed-off-by: Stuart Yoder stuart.yo...@freescale.com
---
 drivers/staging/fsl-mc/TODO | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/drivers/staging/fsl-mc/TODO b/drivers/staging/fsl-mc/TODO
index d78288b..c29516b 100644
--- a/drivers/staging/fsl-mc/TODO
+++ b/drivers/staging/fsl-mc/TODO
@@ -6,8 +6,30 @@
   and if so add support for this.
 
 * Add at least one device driver for a DPAA2 object (child device of the
-  fsl-mc bus).
+  fsl-mc bus).  Most likely candidate for this is adding DPAA2 Ethernet
+  driver support, which depends on drivers for several objects: DPNI,
+  DPIO, DPMAC.  Other pre-requisites include:
+
+ * interrupt support. for meaningful driver support we need
+   interrupts, and thus need message interrupt support by the bus
+   driver.
+  -Note: this has dependencies on generic MSI support work
+   in process upstream, see [1] and [2].
+
+ * Management Complex (MC) command serialization. locking mechanisms
+   are needed by drivers to serialize commands sent to the MC, including
+   from atomic context.
+
+ * MC firmware uprev.  The MC firmware upon which the fsl-mc
+   bus driver and DPAA2 object drivers are based is continuing
+   to evolve, so minor updates are needed to keep in sync with binary
+   interface changes to the MC.
+
+* Cleanup
 
 Please send any patches to Greg Kroah-Hartman gre...@linuxfoundation.org,
 german.riv...@freescale.com, de...@driverdev.osuosl.org,
 linux-kernel@vger.kernel.org
+
+[1] https://lkml.org/lkml/2015/7/9/93
+[2] https://lkml.org/lkml/2015/7/7/712
-- 
2.3.3

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Re: [PATCH 11/13] arm64: Panic when VHE and non VHE CPUs coexist

2015-07-16 Thread Will Deacon
On Wed, Jul 08, 2015 at 05:19:14PM +0100, Marc Zyngier wrote:
 Having both VHE and non-VHE capable CPUs in the same system
 is likely to be a recipe for disaster.
 
 If the boot CPU has VHE, but a secondary is not, we won't be
 able to downgrade and run the kernel at EL1. Add CPU hotplug
 to the mix, and this produces a terrifying mess.
 
 Let's solve the problem once and for all. If you mix VHE and
 non-VHE CPUs in the same system, you deserve to loose, and this
 patch makes sure you don't get a chance.
 
 This is implemented by storing the kernel execution level in
 a global variable. Secondaries will park themselves in a
 WFI loop if they observe a mismatch. Also, the primary CPU
 will detect that the secondary CPU has died on a mismatched
 execution level. Panic will follow.
 
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com
 ---
  arch/arm64/include/asm/virt.h | 15 +++
  arch/arm64/kernel/head.S  | 15 +++
  arch/arm64/kernel/smp.c   |  4 
  3 files changed, 34 insertions(+)
 
 diff --git a/arch/arm64/include/asm/virt.h b/arch/arm64/include/asm/virt.h
 index 9f22dd6..8e246f7 100644
 --- a/arch/arm64/include/asm/virt.h
 +++ b/arch/arm64/include/asm/virt.h
 @@ -36,6 +36,11 @@
   */
  extern u32 __boot_cpu_mode[2];
  
 +/*
 + * __run_cpu_mode records the mode the boot CPU uses for the kernel.
 + */
 +extern u32 __run_cpu_mode;
 +
  void __hyp_set_vectors(phys_addr_t phys_vector_base);
  phys_addr_t __hyp_get_vectors(void);
  
 @@ -60,6 +65,16 @@ static inline bool is_kernel_in_hyp_mode(void)
   return el == CurrentEL_EL2;
  }
  
 +static inline bool is_kernel_mode_mismatched(void)
 +{
 + u64 el;
 + u32 mode;
 +
 + asm(mrs %0, CurrentEL : =r (el));
 + mode = ACCESS_ONCE(__run_cpu_mode);
 + return el != mode;

Why the temporary 'mode' variable?

 +}
 +
  /* The section containing the hypervisor text */
  extern char __hyp_text_start[];
  extern char __hyp_text_end[];
 diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
 index a179747..318e69f 100644
 --- a/arch/arm64/kernel/head.S
 +++ b/arch/arm64/kernel/head.S
 @@ -578,7 +578,20 @@ ENTRY(set_cpu_boot_mode_flag)
  1:   str w20, [x1]   // This CPU has booted in EL1
   dmb sy
   dc  ivac, x1// Invalidate potentially stale 
 cache line
 + adr_l   x1, __run_cpu_mode
 + ldr w0, [x1]
 + mrs x20, CurrentEL

Why x20?

 + str w20, [x1]
 + dmb sy
 + dc  ivac, x1// Invalidate potentially stale 
 cache line

Can we stick __run_cpu_mode and __boot_cpu_mode into a struct in the same
cacheline and avoid the extra maintenance?

 + cbz x0, skip_el_check

w0?

 + cmp x0, x20

w0, w20?

 + bne mismatched_el
 +skip_el_check:
   ret
 +mismatched_el:
 + wfi
 + b   mismatched_el
  ENDPROC(set_cpu_boot_mode_flag)
  
  /*
 @@ -593,6 +606,8 @@ ENDPROC(set_cpu_boot_mode_flag)
  ENTRY(__boot_cpu_mode)
   .long   BOOT_CPU_MODE_EL2
   .long   BOOT_CPU_MODE_EL1
 +ENTRY(__run_cpu_mode)
 + .long   0
   .popsection
  
  #ifdef CONFIG_SMP
 diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c
 index 695801a..b467f51 100644
 --- a/arch/arm64/kernel/smp.c
 +++ b/arch/arm64/kernel/smp.c
 @@ -52,6 +52,7 @@
  #include asm/sections.h
  #include asm/tlbflush.h
  #include asm/ptrace.h
 +#include asm/virt.h
  
  #define CREATE_TRACE_POINTS
  #include trace/events/ipi.h
 @@ -112,6 +113,9 @@ int __cpu_up(unsigned int cpu, struct task_struct *idle)
   pr_crit(CPU%u: failed to come online\n, cpu);
   ret = -EIO;
   }
 +
 + if (is_kernel_mode_mismatched())
 + panic(CPU%u: incompatible execution level, cpu);

Might be useful to print the incompatible values, if possible.

Will
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Re: [PATCH v9 07/22] tracing: Add lock-free tracing_map

2015-07-16 Thread Tom Zanussi
On Thu, 2015-07-16 at 20:03 +0200, Peter Zijlstra wrote:
 On Thu, Jul 16, 2015 at 12:22:40PM -0500, Tom Zanussi wrote:
  +   map-map = kcalloc(map-map_size, sizeof(struct tracing_map_entry),
  +  GFP_KERNEL);
 
 In a later email you state the max map size to be 128k, with a 16 byte
 struct, that is 2m of memory for this allocation.
 
 Isn't that a tad big for a kmalloc() ?

Yeah, that is a bit big for kmalloc (actually it's double that), though
I never ran into problems in my testing (of course that would depend on
the state of the system, and I mainly tested on a newly booted system).

It would probably make sense to make it page-based, which means a bit
more complicated mapping for the array (can't use vmalloc here) but that
shouldn't be too big a deal.

Tom

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Re: [PATCH 1/5] memcg: export struct mem_cgroup

2015-07-16 Thread Andrew Morton
On Thu, 16 Jul 2015 09:19:49 +0200 Michal Hocko mho...@kernel.org wrote:

 On Wed 15-07-15 13:57:11, Andrew Morton wrote:
  On Wed, 15 Jul 2015 13:14:41 +0200 Michal Hocko mho...@kernel.org wrote:
  
   mem_cgroup structure is defined in mm/memcontrol.c currently which
   means that the code outside of this file has to use external API even
   for trivial access stuff.
   
   This patch exports mm_struct with its dependencies and makes some of the
   exported functions inlines. This even helps to reduce the code size a bit
   (make defconfig + CONFIG_MEMCG=y)
   
   text  databss dec  hexfilename
   123553461823792 1089536 15268674 e8fb42 vmlinux.before
   123549701823792 1089536 15268298 e8f9ca vmlinux.after
   
   This is not much (370B) but better than nothing. We also save a function
   call in some hot paths like callers of mem_cgroup_count_vm_event which is
   used for accounting.
   
   The patch doesn't introduce any functional changes.
   
   ...
  
include/linux/memcontrol.h | 369 
   +
  
  Boy, that's a ton of new stuff into the header file.  Do we actually
  *need* to expose all this?
 
 I am exporting struct mem_cgroup with its dependencies + some small
 functions which allow to inline some really trivial code and helps to
 generate a better code.
 
  Is some other patch dependent on it? 
 
 Without mem_cgroup visible outside of memcontrol.c we couldn't inline
 and now we can also use some fields from mem_cgroup directly and get rid
 of some really trivial access functions.
 
  If
  not then perhaps we shouldn't do this - if the code was already this
  way, I'd be attracted to a patch which was the reverse of this one!
 
 I agree with Johannes who originally suggested to expose mem_cgroup that
 it will allow for a better code later.

Sure, but how *much* better?  Are there a significant number of
fastpath functions involved?

From a maintainability/readability point of view, this is quite a bad
patch.  It exposes a *lot* of stuff to the whole world.  We need to get
a pretty good runtime benefit from doing this to ourselves.  I don't
think that saving 376 bytes on a fatconfig build is sufficient
justification?


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Re: [PATCH 4/5] regulator: 88pm800: Add 88pm860 regulator support

2015-07-16 Thread Mark Brown
On Thu, Jul 16, 2015 at 11:46:57PM +0530, Vaibhav Hiremath wrote:
 88PM860 falls under 88pm800 family of devices, with
 additional feature enhancements, like,
   - 88pm860 had additional BUCK regulator (BUCK6 and BUCK1B)
   - Additional LDO (LDO20)
   - different voltage and current capability

...and reverted since this doesn't build as the kbuild test robot
reported.  :(


signature.asc
Description: Digital signature


Re: [PATCH 2/2] cpufreq: Properly handle errors from cpufreq_init_policy()

2015-07-16 Thread Rafael J. Wysocki
On Thursday, July 16, 2015 10:16:14 AM Jon Medhurst wrote:
 On Thu, 2015-07-16 at 02:32 +0200, Rafael J. Wysocki wrote:
  On Wednesday, July 08, 2015 04:50:23 PM Viresh Kumar wrote:
   On 08-07-15, 12:17, Jon Medhurst (Tixy) wrote:
I tried these patches without the earlier cpufreq: Initialize the
governor again while restoring policy patch.

The result is that the error when bringing a cpu online is with flagged
up with a kernel message:

  cpufreq: cpufreq_add_dev: Failed to initialize policy for cpu: 1 (-16)

and afterwards, the sysfs entries that I was poking and causing the
crash aren't present. So looks like this patch has done what we want,
and cleaned things up after an error. So...

Tested-by: Jon Medhurst t...@linaro.org

Thanks for the prompt fix.
   
   And thanks for your help in getting these tested :)
  
  Both queued up for 4.3, thanks!
 
 The crash I was getting was a regression caused by changes that went
 into 4.2-rc1.
 
 Indeed, the first patch from Viresh is marked:
 
 Fixes: 18bf3a124ef8 (cpufreq: Mark policy-governor = NULL for inactive 
 policies)
 For 4.2-rc
 
 And I am having to carry that first patch to keep two ARM big.LITTLE
 platforms working.

That one is going into 4.2-rc, I'm about to send a pull request with it.


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I speak only for myself.
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Re: [RFC][PATCH] x86, fpu: dynamically allocate 'struct fpu'

2015-07-16 Thread Andy Lutomirski
On Thu, Jul 16, 2015 at 3:42 PM, H. Peter Anvin h...@zytor.com wrote:
 On 07/16/2015 12:14 PM, Dave Hansen wrote:
 The FPU rewrite removed the dynamic allocations of 'struct fpu'.
 But, this potentially wastes massive amounts of memory (2k per
 task on systems that do not have AVX-512 for instance).

 Instead of having a separate slab, this patch just appends the
 space that we need to the 'task_struct' which we dynamically
 allocate already.  This saves from doing an extra slab allocation
 at fork().  The only real downside here is that we have to stick
 everything and the end of the task_struct.  But, I think the
 BUILD_BUG_ON()s I stuck in there should keep that from being too
 fragile.

 This survives a quick build and boot in a VM.  Does anyone see any
 real downsides to this?


 No.  I have also long advocated for merging task_struct and thread_info
 into a common structure and get it off the stack; it would improve
 security and avoid weird corner cases in the irqstack handling.


In tip/x86/asm, entry_64.S only references thread_info in two places,
both in the syscall code.  I'm hoping that we can move that code into
C soon and that we can do the same thing to the 32-bit code.  If we do
that, then we could just move ti-flags into thread_struct.
Everything else should be easy, and then thread_info would be empty.

--Andy
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Re: [PATCH 03/13] arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature

2015-07-16 Thread Will Deacon
On Wed, Jul 08, 2015 at 05:19:06PM +0100, Marc Zyngier wrote:
 Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the
 CPU has the ARMv8,1 VHE capability.
 
 This will be used to trigger kernel patching in KVM.
 
 Signed-off-by: Marc Zyngier marc.zyng...@arm.com

Acked-by: Will Deacon will.dea...@arm.com

Will
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[PATCH] pagemap: update documentation

2015-07-16 Thread Konstantin Khlebnikov
Notes about recent changes.

Signed-off-by: Konstantin Khlebnikov khlebni...@yandex-team.ru
---
 Documentation/vm/pagemap.txt |   14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/Documentation/vm/pagemap.txt b/Documentation/vm/pagemap.txt
index 3cfbbb333ea1..aab39aa7dd8f 100644
--- a/Documentation/vm/pagemap.txt
+++ b/Documentation/vm/pagemap.txt
@@ -16,12 +16,17 @@ There are three components to pagemap:
 * Bits 0-4   swap type if swapped
 * Bits 5-54  swap offset if swapped
 * Bit  55pte is soft-dirty (see Documentation/vm/soft-dirty.txt)
-* Bit  56page exlusively mapped
+* Bit  56page exclusively mapped (since 4.2)
 * Bits 57-60 zero
-* Bit  61page is file-page or shared-anon
+* Bit  61page is file-page or shared-anon (since 3.5)
 * Bit  62page swapped
 * Bit  63page present
 
+   Since Linux 4.0 only users with the CAP_SYS_ADMIN capability can get PFNs:
+   for unprivileged users from 4.0 till 4.2 open fails with -EPERM, starting
+   from from 4.2 PFN field is zeroed if user has no CAP_SYS_ADMIN capability.
+   Reason: information about PFNs helps in exploiting Rowhammer vulnerability.
+
If the page is not present but in swap, then the PFN contains an
encoding of the swap file number and the page's offset into the
swap. Unmapped pages return a null PFN. This allows determining
@@ -160,3 +165,8 @@ Other notes:
 Reading from any of the files will return -EINVAL if you are not starting
 the read on an 8-byte boundary (e.g., if you sought an odd number of bytes
 into the file), or if the size of the read is not a multiple of 8 bytes.
+
+Before Linux 3.11 pagemap bits 55-60 were used for page-shift (which is
+always 12 at most architectures). Since Linux 3.11 their meaning changes
+after first clear of soft-dirty bits. Since Linux 4.2 they are used for
+flags unconditionally.

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[PATCH] drm: atmel-hlcdc: fix vblank initial state

2015-07-16 Thread Sylvain Rochet
From: Boris Brezillon boris.brezil...@free-electrons.com

drm_vblank_on() now warns on nested use or if vblank is not properly
initialized. This patch fixes Atmel HLCDC vblank initial state.

Signed-off-by: Boris Brezillon boris.brezil...@free-electrons.com
Reported-by: Sylvain Rochet sylvain.roc...@finsecur.com
---
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c |  1 +
 drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c   | 12 ++--
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index f69b925..5ae5c69 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -355,6 +355,7 @@ int atmel_hlcdc_crtc_create(struct drm_device *dev)
planes-overlays[i]-base.possible_crtcs = 1  crtc-id;
 
drm_crtc_helper_add(crtc-base, lcdc_crtc_helper_funcs);
+   drm_crtc_vblank_reset(crtc-base);
 
dc-crtc = crtc-base;
 
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c 
b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index 60b0c13..6fad1f9 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
@@ -313,20 +313,20 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
 
pm_runtime_enable(dev-dev);
 
-   ret = atmel_hlcdc_dc_modeset_init(dev);
+   ret = drm_vblank_init(dev, 1);
if (ret  0) {
-   dev_err(dev-dev, failed to initialize mode setting\n);
+   dev_err(dev-dev, failed to initialize vblank\n);
goto err_periph_clk_disable;
}
 
-   drm_mode_config_reset(dev);
-
-   ret = drm_vblank_init(dev, 1);
+   ret = atmel_hlcdc_dc_modeset_init(dev);
if (ret  0) {
-   dev_err(dev-dev, failed to initialize vblank\n);
+   dev_err(dev-dev, failed to initialize mode setting\n);
goto err_periph_clk_disable;
}
 
+   drm_mode_config_reset(dev);
+
pm_runtime_get_sync(dev-dev);
ret = drm_irq_install(dev, dc-hlcdc-irq);
pm_runtime_put_sync(dev-dev);
-- 
2.1.4

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Re: [PATCH] ibmvscsi:Remove no longer required comment for the function send_mad_adapter_info

2015-07-16 Thread Tyrel Datwyler
On 07/09/2015 10:24 AM, Nicholas Krause wrote:
 This removes the no longer required comment for the function
 send_mad_adapter_info stating that it always return zero due
 to this function being declared as void and thus never returning
 any useful value.
 
 Signed-off-by: Nicholas Krause xerofo...@gmail.com

Acked-by: Tyrel Datwyler tyr...@linux.vnet.ibm.com

 ---
  drivers/scsi/ibmvscsi/ibmvscsi.c | 1 -
  1 file changed, 1 deletion(-)
 
 diff --git a/drivers/scsi/ibmvscsi/ibmvscsi.c 
 b/drivers/scsi/ibmvscsi/ibmvscsi.c
 index 6a41c36..70ea976 100644
 --- a/drivers/scsi/ibmvscsi/ibmvscsi.c
 +++ b/drivers/scsi/ibmvscsi/ibmvscsi.c
 @@ -1423,7 +1423,6 @@ static void adapter_info_rsp(struct srp_event_struct 
 *evt_struct)
   *  returned SRP version doesn't match ours.
   * @hostdata:ibmvscsi_host_data of host
   * 
 - * Returns zero if successful.
  */
  static void send_mad_adapter_info(struct ibmvscsi_host_data *hostdata)
  {
 

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Re: cpu_hotplug vs oom_notify_list: possible circular locking dependency detected

2015-07-16 Thread David Rientjes
On Wed, 15 Jul 2015, Paul E. McKenney wrote:

 On Tue, Jul 14, 2015 at 04:48:24PM -0700, David Rientjes wrote:
  On Tue, 14 Jul 2015, Paul E. McKenney wrote:
  
   commit a1992f2f3b8e174d740a8f764d0d51344bed2eed
   Author: Paul E. McKenney paul...@linux.vnet.ibm.com
   Date:   Tue Jul 14 16:24:14 2015 -0700
   
   rcu: Don't disable CPU hotplug during OOM notifiers
   
   RCU's rcu_oom_notify() disables CPU hotplug in order to stabilize the
   list of online CPUs, which it traverses.  However, this is completely
   pointless because smp_call_function_single() will quietly fail if 
   invoked
   on an offline CPU.  Because the count of requests is incremented in 
   the
   rcu_oom_notify_cpu() function that is remotely invoked, everything 
   works
   nicely even in the face of concurrent CPU-hotplug operations.
   
   Furthermore, in recent kernels, invoking get_online_cpus() from an OOM
   notifier can result in deadlock.  This commit therefore removes the
   call to get_online_cpus() and put_online_cpus() from rcu_oom_notify().
   
   Reported-by: Marcin Ślusarz marcin.slus...@gmail.com
   Reported-by: David Rientjes rient...@google.com
   Signed-off-by: Paul E. McKenney paul...@linux.vnet.ibm.com
  
  Acked-by: David Rientjes rient...@google.com
 
 Thank you!
 
 Any news on whether or not it solves the problem?
 

Marcin, is your lockdep violation reproducible?  If so, does this patch 
fix it?

Re: [PATCH] asm-generic: {get,put}_user ptr argument evaluate only 1 time

2015-07-16 Thread Geert Uytterhoeven
Hi Sato-san,

On Thu, Jul 16, 2015 at 7:15 AM, Yoshinori Sato
ys...@users.sourceforge.jp wrote:
 Current implemantation ptr argument evaluate 2 times.
 It'll be an unexpected result.

 Signed-off-by: Yoshinori Sato ys...@users.sourceforge.jp

Acked-by: Geert Uytterhoeven ge...@linux-m68k.org

 ---
  include/asm-generic/uaccess.h | 10 ++
  1 file changed, 6 insertions(+), 4 deletions(-)

 diff --git a/include/asm-generic/uaccess.h b/include/asm-generic/uaccess.h
 index 72d8803..1b813fb 100644
 --- a/include/asm-generic/uaccess.h
 +++ b/include/asm-generic/uaccess.h
 @@ -163,9 +163,10 @@ static inline __must_check long __copy_to_user(void 
 __user *to,

  #define put_user(x, ptr)   \
  ({ \
 +   __typeof__((ptr)) __p = (ptr);  \
 might_fault();  \
 -   access_ok(VERIFY_WRITE, ptr, sizeof(*ptr)) ?\
 -   __put_user(x, ptr) :\
 +   access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ?\
 +   __put_user(x, __p) :\

For safety, you may want to change x to (x) while at it.

 -EFAULT;\
  })

 @@ -225,9 +226,10 @@ extern int __put_user_bad(void) 
 __attribute__((noreturn));

  #define get_user(x, ptr)   \
  ({ \
 +   __typeof__((ptr)) __p = (ptr);  \
 might_fault();  \
 -   access_ok(VERIFY_READ, ptr, sizeof(*ptr)) ? \
 -   __get_user(x, ptr) :\
 +   access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \
 +   __get_user(x, __p) :\

Likewise.

Gr{oetje,eeting}s,

Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- ge...@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say programmer or something like that.
-- Linus Torvalds
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Re: ARM: OMAP2: Delete unnecessary checks before three function calls

2015-07-16 Thread SF Markus Elfring
 I have to say, I am a bit leery about applying the omap_device.c and
 omap_hwmod.c changes, since the called functions -- omap_device_delete()
 and clk_disable() -- don't explicitly document that NULLs are allowed
 to be passed in.

How are the chances to improve documentation around such implementation details?


 So there's no explicit contract that callers can rely upon, to (at least
 in theory) prevent those internal NULL pointer checks from being removed.

Are there any additional variations to consider for source files from different
processor architectures?


 So I would suggest that those two functions' kerneldoc be patched first to 
 explicitly state that passing in a NULL pointer is allowed.

Should my static source code analysis approach help you any more to clarify
further open issues?


 So I'll apply that change now for v4.3, touching up the commit message 
 accordingly.

Thanks for your constructive feedback.


  arch/arm/mach-omap2/omap_device.c | 3 +--
  arch/arm/mach-omap2/omap_hwmod.c  | 5 +
  arch/arm/mach-omap2/timer.c   | 3 +--

Did Tony Lindgren pick a similar update suggestion up, too?
https://lkml.org/lkml/2015/7/15/112

Regards,
Markus
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Re: [BUG] mellanox IB driver fails to load on large config

2015-07-16 Thread Or Gerlitz

On 7/14/2015 11:28 PM, Alex Thorlton wrote:


We see the same exact messages on 4.1-rc8.




does this solves the problem?


diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index ad31e47..c8ae3b9 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -45,7 +45,7 @@
 #include linux/timecounter.h

 #define MAX_MSIX_P_PORT17
-#define MAX_MSIX   64
+#define MAX_MSIX   1024
 #define MIN_MSIX_P_PORT5
 #define MLX4_IS_LEGACY_EQ_MODE(dev_cap) ((dev_cap).num_comp_vectors  \
(dev_cap).num_ports * MIN_MSIX_P_PORT)
--

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[PATCH v2 1/3] ARM: multi_v7_defconfig: Enable max77802 regulator

2015-07-16 Thread Javier Martinez Canillas
The Exynos5420 based Peach Pit and Exynos5800 based Peach Pi Chromebooks
use the Maxim max77802 Power Management IC (PMIC). This PMIC has besides
other devices, a set of regulators that can be controller over I2C.

Commit f3caa529c6f5 (ARM: multi_v7_defconfig: Enable max77802 regulator,
rtc and clock drivers) was supposed to enable the config option for the
regulator driver as a module but the final version that landed did not
include this. The commit was modified and the REGULATOR_MAX77802 removed
since it was thought to be useless.

Unfortunately that's not the case for the mentioned reason above so this
patch enables the needed Kconfig option.

Signed-off-by: Javier Martinez Canillas jav...@osg.samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

---

Changes in v2:
- Better explanation why the max77802 regulator config option is needed.
- Add Krzysztof Kozlowski Reviewed-by tag in patch #1

 arch/arm/configs/multi_v7_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index 4b93761d58d2..b07493997993 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -402,6 +402,7 @@ CONFIG_REGULATOR_MAX14577=m
 CONFIG_REGULATOR_MAX8907=y
 CONFIG_REGULATOR_MAX8973=y
 CONFIG_REGULATOR_MAX77686=y
+CONFIG_REGULATOR_MAX77802=m
 CONFIG_REGULATOR_MAX77693=m
 CONFIG_REGULATOR_PALMAS=y
 CONFIG_REGULATOR_S2MPS11=y
-- 
2.4.3

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[PATCH v2 3/3] ARM: exynos_defconfig: Enable NTC Thermistors support

2015-07-16 Thread Javier Martinez Canillas
The Exynos5420 Peach Pit and Exynos5800 Peach Pi Chromebooks have
IIO based ADC thermistors. Enable built-in support for its driver.

Signed-off-by: Javier Martinez Canillas jav...@osg.samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

---

Changes in v2:
- Add Krzysztof Kozlowski Reviewed-by tag in patch #3.

 arch/arm/configs/exynos_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/configs/exynos_defconfig 
b/arch/arm/configs/exynos_defconfig
index 9504e7790288..e5d7d4476a80 100644
--- a/arch/arm/configs/exynos_defconfig
+++ b/arch/arm/configs/exynos_defconfig
@@ -94,6 +94,7 @@ CONFIG_CHARGER_MAX14577=y
 CONFIG_CHARGER_MAX77693=y
 CONFIG_CHARGER_TPS65090=y
 CONFIG_SENSORS_LM90=y
+CONFIG_SENSORS_NTC_THERMISTOR=y
 CONFIG_SENSORS_PWM_FAN=y
 CONFIG_SENSORS_INA2XX=y
 CONFIG_THERMAL=y
-- 
2.4.3

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linux-next: Tree for Jul 16

2015-07-16 Thread Stephen Rothwell
Hi all,

For those that care:  I have stopped signing these messages because
vger's mailing list software destroys the signatures and then Google
(at least) assumes that they are spam.  I could clear sign them instead
(if anyone thinks that is worth while).

Changes since 20150715:

Removed tree: init (it has all been merged)

The tip tree lost its build failure.

The rcu tree gained a conflict against the tip tree and a build failure
for which I applied a merge fix patch.

The akpm-current tree gained a conflict against the arm tree and 2 build
failures for which I applied fix patches.

Non-merge commits (relative to Linus' tree): 2446
 2485 files changed, 100730 insertions(+), 34595 deletions(-)



I have created today's linux-next tree at
git://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git
(patches at http://www.kernel.org/pub/linux/kernel/next/ ).  If you
are tracking the linux-next tree using git, you should not use git pull
to do so as that will try to merge the new linux-next release with the
old one.  You should use git fetch and checkout or reset to the new
master.

You can see which trees have been included by looking in the Next/Trees
file in the source.  There are also quilt-import.log and merge.log
files in the Next directory.  Between each merge, the tree was built
with a ppc64_defconfig for powerpc and an allmodconfig for x86_64,
a multi_v7_defconfig for arm and a native build of tools/perf. After
the final fixups (if any), it is also built with powerpc allnoconfig
(32 and 64 bit), ppc44x_defconfig and allyesconfig (this fails its final
link) and i386, sparc, sparc64 and arm defconfig.

Below is a summary of the state of the merge.

I am currently merging 223 trees (counting Linus' and 33 trees of patches
pending for Linus' tree).

Stats about the size of the tree over time can be seen at
http://neuling.org/linux-next-size.html .

Status of my local build tests will be at
http://kisskb.ellerman.id.au/linux-next .  If maintainers want to give
advice about cross compilers/configs that work, we are always open to add
more builds.

Thanks to Randy Dunlap for doing many randconfig builds.  And to Paul
Gortmaker for triage and bug fixes.

-- 
Cheers,
Stephen Rothwells...@canb.auug.org.au

$ git checkout master
$ git reset --hard stable
Merging origin/master (97d6e2b636c6 Merge tag 'module-final-v4.2-rc1' of 
git://git.kernel.org/pub/scm/linux/kernel/git/paulg/linux)
Merging fixes/master (c7e9ad7da219 Merge branch 'perf-urgent-for-linus' of 
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip)
Merging kbuild-current/rc-fixes (c517d838eb7d Linux 4.0-rc1)
Merging arc-current/for-curr (e4140819dadc ARC: signal handling robustify)
Merging arm-current/fixes (ab525b473c96 ARM: invalidate L1 before enabling 
coherency)
Merging m68k-current/for-linus (1214c525484c m68k: Use for_each_sg())
Merging metag-fixes/fixes (0164a711c97b metag: Fix ioremap_wc/ioremap_cached 
build errors)
Merging mips-fixes/mips-fixes (1795cd9b3a91 Linux 3.16-rc5)
Merging powerpc-fixes/fixes (bc0195aad0da Linux 4.2-rc2)
Merging powerpc-merge-mpe/fixes (bc0195aad0da Linux 4.2-rc2)
Merging powerpc-merge-benh/merge (c517d838eb7d Linux 4.0-rc1)
Merging sparc/master (4a10a91756ef Merge branch 'upstream' of 
git://git.infradead.org/users/pcmoore/audit)
Merging net/master (bc8c20acaea1 bridge: multicast: treat igmpv3 report with 
INCLUDE and no sources as a leave)
Merging ipsec/master (31a418986a58 xen: netback: read hotplug script once at 
start of day.)
Merging sound-current/for-linus (4d0e677523a9 ALSA: line6: Fix -EBUSY error 
during active monitoring)
Merging pci-current/for-linus (c9ddbac9c891 PCI: Restore PCI_MSIX_FLAGS_BIRMASK 
definition)
Merging wireless-drivers/master (7865598ec24a ath9k_hw: fix device ID check for 
AR956x)
Merging driver-core.current/driver-core-linus (bc0195aad0da Linux 4.2-rc2)
Merging tty.current/tty-linus (bc0195aad0da Linux 4.2-rc2)
Merging usb.current/usb-linus (51f007e1a1f1 Merge tag 'usb-serial-4.2-rc2' of 
git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial into usb-linus)
Merging usb-gadget-fixes/fixes (b2e2c94b878b usb: gadget: f_midi: fix error 
recovery path)
Merging usb-serial-fixes/usb-linus (d23f47d4927f USB: serial: Destroy 
serial_minors IDR on module exit)
Merging staging.current/staging-linus (d309509f8472 staging: vt6656: check 
ieee80211_bss_conf bssid not NULL)
Merging char-misc.current/char-misc-linus (bc0195aad0da Linux 4.2-rc2)
Merging input-current/for-linus (dbf3c370862d Revert Input: synaptics - 
allocate 3 slots to keep stability in image sensors)
Merging crypto-current/master (030f4e968741 crypto: nx - Fix reentrancy bugs)
Merging ide/master (d681f1166919 ide: remove deprecated use of pci api)
Merging devicetree-current/devicetree/merge (f76502aa9140 of/dynamic: Fix test 
for PPC_PSERIES)
Merging rr-fixes/fixes (758556bdc1c8 module: Fix load_module() error 

Re: [PATCH 1/1] add pwm capability to dm816x

2015-07-16 Thread Paul Walmsley
Hello Brian,

On Mon, 15 Jun 2015, Brian Hutchinson wrote:

 Clocks 4-7 are capable of PWM output on dm816x.
 
 This adds the pwm capability to those timers.
 
 Cc: Paul Walmsley p...@pwsan.com
 Cc: Tero Kristo t-kri...@ti.com
 Cc: Tony Lindgren t...@atomide.com
 Signed-off-by: Brian Hutchinson b.hutch...@gmail.com t...@atomide.com

This patch seems to be corrupted.  The above line doesn't look right; 
there are some spurious newlines in the patch header, and tabs seem to 
have been converted to whitespace.  Some of these issues may be due to 
mailer problems.  Could you please fix and try again?


- Paul

 
 --- arch/arm/mach-omap2/omap_hwmod_81xx_data.c_orig 2015-06-15
 13:20:43.174343431 -0400
 +++ arch/arm/mach-omap2/omap_hwmod_81xx_data.c  2015-06-15
 13:34:51.770551392 -0400
 @@ -546,6 +546,14 @@ static struct omap_timer_capability_dev_
 .timer_capability   = OMAP_TIMER_ALWON,
  };
 
 +/* pwm timers dev attribute.
 + * timers 4-7 may be used for PWM output - see datasheet timer terminal
 + * functions table
 + */
 +static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
 +   .timer_capability   = OMAP_TIMER_ALWON | OMAP_TIMER_HAS_PWM,
 +};
 +
  static struct omap_hwmod dm816x_timer1_hwmod = {
 .name   = timer1,
 .clkdm_name = alwon_l3s_clkdm,
 @@ -619,7 +627,7 @@ static struct omap_hwmod dm816x_timer4_h
 .modulemode = MODULEMODE_SWCTRL,
 },
 },
 -   .dev_attr   = capability_alwon_dev_attr,
 +   .dev_attr   = capability_pwm_dev_attr,
 .class  = dm816x_timer_hwmod_class,
  };
 
 @@ -640,7 +648,7 @@ static struct omap_hwmod dm816x_timer5_h
 .modulemode = MODULEMODE_SWCTRL,
 },
 },
 -   .dev_attr   = capability_alwon_dev_attr,
 +   .dev_attr   = capability_pwm_dev_attr,
 .class  = dm816x_timer_hwmod_class,
  };
 
 @@ -661,7 +669,7 @@ static struct omap_hwmod dm816x_timer6_h
 .modulemode = MODULEMODE_SWCTRL,
 },
 },
 -   .dev_attr   = capability_alwon_dev_attr,
 +   .dev_attr   = capability_pwm_dev_attr,
 .class  = dm816x_timer_hwmod_class,
  };
 
 @@ -682,7 +690,7 @@ static struct omap_hwmod dm816x_timer7_h
 .modulemode = MODULEMODE_SWCTRL,
 },
 },
 -   .dev_attr   = capability_alwon_dev_attr,
 +   .dev_attr   = capability_pwm_dev_attr,
 .class  = dm816x_timer_hwmod_class,
  };
 


- Paul
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Re: perf: fuzzer triggered warning in intel_pmu_drain_pebs_nhm()

2015-07-16 Thread Stephane Eranian
On Wed, Jul 15, 2015 at 2:35 PM, Peter Zijlstra pet...@infradead.org wrote:
 On Wed, Jul 15, 2015 at 08:42:50AM +0200, Stephane Eranian wrote:
 On Fri, Jul 3, 2015 at 9:49 PM, Vince Weaver vincent.wea...@maine.edu 
 wrote:
  On Fri, 3 Jul 2015, Peter Zijlstra wrote:
 
  That said, its far too warm and I might just not be making sense.
 
  you need to come visit Maine!  Although I am not sure the cooler weather
  necessarily improves my kernel debugging skills.
 
  I managed to lock the machine (again this is with the patch applied).
 
 I can reproduce the problem on my HSW running the fuzzer.

 I can see why this could be happening if you are mixing PEBS and non PEBS 
 events
 in the bottom 4 counters. I suspect:
 for (bit = 0; bit  x86_pmu.max_pebs_events; bit++) {
 if ((counts[bit] == 0)  (error[bit] == 0))
 continue;

 This test is not correct when you have non-PEBS events mixed with PEBS
 events and
 they overflow at the same time. They will have counts[i] != 0 but
 error[i] == 0, and thus
 you fall thru the loop and hit the assert. Or it is something along those 
 lines.


 The only way I can make this work is if -status only has !PEBS events
 set, because if it has both set we'll take that slow path which masks
 out the !PEBS bits.

 After masking there are 3 options:

  - there is one bit set, and its @bit, we increment counts[bit].
  - there are multiple bits set, we increment error[] for each set bit,
we do not increment counts[].
  - there are no bits set, we do nothing.

 The intent was to never increment counts[] for !PEBS events.

 Now if we start out with only a single !PEBS event set, we'll pass the
 test and increment counts[] for a !PEBS and hit the warn.

 The below patch modifies the code such that it can deal with that
 particular issue. Can you try?

Been running it for a couple of hours, so far so good. I will let it
run all night.
Testing it on HSW and NHM, my SNB is broken at the moment.

Don't know if the fuzzer has already reproduced the test case.
Thanks.

 ---
  arch/x86/kernel/cpu/perf_event_intel_ds.c | 29 +
  1 file changed, 13 insertions(+), 16 deletions(-)

 diff --git a/arch/x86/kernel/cpu/perf_event_intel_ds.c 
 b/arch/x86/kernel/cpu/perf_event_intel_ds.c
 index 71fc40238843..68d0ced1d229 100644
 --- a/arch/x86/kernel/cpu/perf_event_intel_ds.c
 +++ b/arch/x86/kernel/cpu/perf_event_intel_ds.c
 @@ -1142,6 +1142,7 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs 
 *iregs)

 for (at = base; at  top; at += x86_pmu.pebs_record_size) {
 struct pebs_record_nhm *p = at;
 +   u64 pebs_status;

 /* PEBS v3 has accurate status bits */
 if (x86_pmu.intel_cap.pebs_format = 3) {
 @@ -1152,12 +1153,14 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs 
 *iregs)
 continue;
 }

 -   bit = find_first_bit((unsigned long *)p-status,
 +   pebs_status = p-status  cpuc-pebs_enabled;
 +   pebs_status = (1ULL  x86_pmu.max_pebs_events) - 1;
 +
 +   bit = find_first_bit((unsigned long *)pebs_status,
 x86_pmu.max_pebs_events);
 if (bit = x86_pmu.max_pebs_events)
 continue;
 -   if (!test_bit(bit, cpuc-active_mask))
 -   continue;
 +
 /*
  * The PEBS hardware does not deal well with the situation
  * when events happen near to each other and multiple bits
 @@ -1172,27 +1175,21 @@ static void intel_pmu_drain_pebs_nhm(struct pt_regs 
 *iregs)
  * one, and it's not possible to reconstruct all events
  * that caused the PEBS record. It's called collision.
  * If collision happened, the record will be dropped.
 -*
  */
 -   if (p-status != (1  bit)) {
 -   u64 pebs_status;
 -
 -   /* slow path */
 -   pebs_status = p-status  cpuc-pebs_enabled;
 -   pebs_status = (1ULL  MAX_PEBS_EVENTS) - 1;
 -   if (pebs_status != (1  bit)) {
 -   for_each_set_bit(i, (unsigned long 
 *)pebs_status,
 -MAX_PEBS_EVENTS)
 -   error[i]++;
 -   continue;
 -   }
 +   if (p-status != (1ULL  bit)) {
 +   for_each_set_bit(i, (unsigned long *)pebs_status,
 +x86_pmu.max_pebs_events)
 +   error[i]++;
 +   continue;
 }
 +
 counts[bit]++;
 }

 for (bit = 0; bit  x86_pmu.max_pebs_events; bit++) {
 if ((counts[bit] 

Re: [RFC v4 17/25] powerpc, fbdev: Use arch_nvram_ops methods instead of nvram_read_byte() and nvram_write_byte()

2015-07-16 Thread Finn Thain

On Wed, 15 Jul 2015, I wrote:

 On Tue, 14 Jul 2015, Benjamin Herrenschmidt wrote:
 
  Maybe we should have a dedicated accessor for mac_xpram ...
 
 ... I can see how to implement XPRAM for matroxfb and imsttfb 

I'll have to retract that. The video mode and color mode settings used by 
the PowerMac framebuffer drivers don't exist in the PRAM portion of NVRAM.

Addresses 0x140F and 0x1410 are found in the partition reserved by Apple 
for Name Registry properties, according to Designing PCI Cards and 
Drivers for Power Macintosh Computers. There is no equivalent on m68k 
Macs, AFAIK.

This is NVRAM partition 2 on my beige g3, which begins at 0x1400. I'm not 
sure that this is true on New World PowerMacs, and I suspect that the 
framebuffer drivers should be calling pmac_get_partition() to determine 
the offset of the beginning of the Name Registry partition.

The arch_nvram_ops methods don't deal with structures like partitions. 
They treat the entire 8 KiB as unstructured, because that's how /dev/nvram 
treats it.

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Re: [PATCH 1/3] ARM: multi_v7_defconfig: Enable max77802 regulator

2015-07-16 Thread Krzysztof Kozlowski
On 16.07.2015 14:44, Javier Martinez Canillas wrote:
 Hello Krzysztof,
 
 Thanks for the feedback.
 
 On 07/16/2015 02:45 AM, Krzysztof Kozlowski wrote:
 On 16.07.2015 01:32, Javier Martinez Canillas wrote:
 The Maxim max77802 Power Management IC has besides other devices, a set of
 regulators. Commit f3caa529c6f5 (ARM: multi_v7_defconfig: Enable max77802
 regulator, rtc and clock drivers) was supposed to enable the config option
 for the regulator driver as a module but the final version that landed did
 not include this. So this patch enables the needed Kconfig option.

 Signed-off-by: Javier Martinez Canillas jav...@osg.samsung.com

 Please describe why do you want to enable it (IOW who will benefit from
 enabling it?). This symbol was removed by Kukjin from your commit:
  [kg...@kernel.org: removing useless REGULATOR_MAX77802 config]
 so justification would be welcomed.

 
 You are right, sorry for not making the commit message clear. This PMIC
 is used by a couple of Exynos5 based boars such as the Peach Pit and Pi
 Chromebooks. I expect it to be found in other designs too just like the
 max77686 is found in many Exynos5 based boards.
 
 I'll add this to the commit message on v2.
  
 Beside the commit description I agree with the patch.

 
 Does this mean I can add your Reviewed-by to this patch as well?

With extended description (something similar to explanation in your
other patches) yes, go ahead:

Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

Best regards,
Krzysztof

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Re: [PATCH] kprobes: Use debugfs_remove_recursive instead debugfs_remove

2015-07-16 Thread Masami Hiramatsu
On 2015/07/16 11:16, Wang Long wrote:
 In debugfs_kprobe_init, we create a directory 'kprobes' and three
 files 'list', 'enabled' and 'blacklist'. When any one of the three
 files creation fails, we should remove all of them. But debugfs_remove
 function can not complete this work. So use debugfs_remove_recursive
 instead.
 

OK, it should be fixed.

Acked-by: Masami Hiramatsu masami.hiramatsu...@hitachi.com

Thank you!

 Signed-off-by: Wang Long long.wangl...@huawei.com
 ---
  kernel/kprobes.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
 
 diff --git a/kernel/kprobes.c b/kernel/kprobes.c
 index c90e417..8cd82a5 100644
 --- a/kernel/kprobes.c
 +++ b/kernel/kprobes.c
 @@ -2459,7 +2459,7 @@ static int __init debugfs_kprobe_init(void)
   return 0;
  
  error:
 - debugfs_remove(dir);
 + debugfs_remove_recursive(dir);
   return -ENOMEM;
  }
  
 


-- 
Masami HIRAMATSU
Linux Technology Research Center, System Productivity Research Dept.
Center for Technology Innovation - Systems Engineering
Hitachi, Ltd., Research  Development Group
E-mail: masami.hiramatsu...@hitachi.com
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Re: [PATCH] ARM: OMAP2: Delete unnecessary checks before three function calls

2015-07-16 Thread Tony Lindgren
* Paul Walmsley p...@pwsan.com [150715 22:58]:
 Hello Markus
 
 On Tue, 30 Jun 2015, SF Markus Elfring wrote:
 
  From: Markus Elfring elfr...@users.sourceforge.net
  Date: Tue, 30 Jun 2015 14:00:16 +0200
  
  The functions clk_disable(), of_node_put() and omap_device_delete() test
  whether their argument is NULL and then return immediately.
  Thus the test around the call is not needed.
  
  This issue was detected by using the Coccinelle software.
  
  Signed-off-by: Markus Elfring elfr...@users.sourceforge.net
 
 Thanks for the patch.  I have to say, I am a bit leery about applying the 
 omap_device.c and omap_hwmod.c changes, since the called functions -- 
 omap_device_delete() and clk_disable() -- don't explicitly document that 
 NULLs are allowed to be passed in.  So there's no explicit contract that 
 callers can rely upon, to (at least in theory) prevent those internal NULL 
 pointer checks from being removed.
 
 So I would suggest that those two functions' kerneldoc be patched first to 
 explicitly state that passing in a NULL pointer is allowed.  Then I would 
 feel a bit more comfortable applying the omap_device.c and omap_hwmod.c 
 changes.
 
 The kerneldoc for of_node_put() does explicitly allow NULLs to be passed 
 in.  So I'll apply that change now for v4.3, touching up the commit 
 message accordingly.

I have them applied from a later thread already, but will drop both in
my branch as I have not pushed them out yet.

Regards,

Tony
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Re: [PATCH 2/4] Input: tsc2005 - convert to regmap

2015-07-16 Thread Dmitry Torokhov
On Wed, Jul 15, 2015 at 02:13:26PM +0200, Sebastian Reichel wrote:
 -static int tsc2005_write(struct tsc2005 *ts, u8 reg, u16 value)
 -{
 - u32 tx = ((reg | TSC2005_REG_PND0)  16) | value;
 - struct spi_transfer xfer = {
 - .tx_buf = tx,
 - .len= 4,
 - .bits_per_word  = 24,
 - };

I wonder why the original code used 24 bit-sized-words for transfers...

-- 
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Re: [Ksummit-discuss] [TECH TOPIC] IRQ affinity

2015-07-16 Thread Michael S. Tsirkin
On Wed, Jul 15, 2015 at 02:48:00PM -0400, Matthew Wilcox wrote:
 On Wed, Jul 15, 2015 at 11:25:55AM -0600, Jens Axboe wrote:
  On 07/15/2015 11:19 AM, Keith Busch wrote:
  On Wed, 15 Jul 2015, Bart Van Assche wrote:
  * With blk-mq and scsi-mq optimal performance can only be achieved if
   the relationship between MSI-X vector and NUMA node does not change
   over time. This is necessary to allow a blk-mq/scsi-mq driver to
   ensure that interrupts are processed on the same NUMA node as the
   node on which the data structures for a communication channel have
   been allocated. However, today there is no API that allows
   blk-mq/scsi-mq drivers and irqbalanced to exchange information
   about the relationship between MSI-X vector ranges and NUMA nodes.
  
  We could have low-level drivers provide blk-mq the controller's irq
  associated with a particular h/w context, and the block layer can provide
  the context's cpumask to irqbalance with the smp affinity hint.
  
  The nvme driver already uses the hwctx cpumask to set hints, but this
  doesn't seems like it should be a driver responsibility. It currently
  doesn't work correctly anyway with hot-cpu since blk-mq could rebalance
  the h/w contexts without syncing with the low-level driver.
  
  If we can add this to blk-mq, one additional case to consider is if the
  same interrupt vector is used with multiple h/w contexts. Blk-mq's cpu
  assignment needs to be aware of this to prevent sharing a vector across
  NUMA nodes.
  
  Exactly. I may have promised to do just that at the last LSF/MM conference,
  just haven't done it yet. The point is to share the mask, I'd ideally like
  to take it all the way where the driver just asks for a number of vecs
  through a nice API that takes care of all this. Lots of duplicated code in
  drivers for this these days, and it's a mess.
 
 Yes.  I think the fundamental problem is that our MSI-X API is so funky.
 We have this incredibly flexible scheme where each MSI-X vector could
 have its own interrupt handler, but that's not what drivers want.
 They want to say Give me eight MSI-X vectors spread across the CPUs,
 and use this interrupt handler for all of them.  That is, instead of
 the current scheme where each MSI-X vector gets its own Linux interrupt,
 we should have one interrupt handler (of the per-cpu interrupt type),
 which shows up with N bits set in its CPU mask.

It would definitely be nice to have a way to express that.  But it's
also pretty common for drivers to have e.g. RX and TX use separate
vectors, and these need separate handlers.

 ___
 Ksummit-discuss mailing list
 ksummit-disc...@lists.linuxfoundation.org
 https://lists.linuxfoundation.org/mailman/listinfo/ksummit-discuss
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[PATCH] Documentation: Update filesystems/debugfs.txt

2015-07-16 Thread Wang Long
This patch update the Documentation/filesystems/debugfs.txt
file. The main work is to add the description of the following
functions:
debugfs_create_atomic_t
debugfs_create_u32_array
debugfs_create_devm_seqfile
debugfs_create_file_size

Signed-off-by: Wang Long long.wangl...@huawei.com
---
 Documentation/filesystems/debugfs.txt | 41 +++
 1 file changed, 41 insertions(+)

diff --git a/Documentation/filesystems/debugfs.txt 
b/Documentation/filesystems/debugfs.txt
index 88ab81c..b1ba8df 100644
--- a/Documentation/filesystems/debugfs.txt
+++ b/Documentation/filesystems/debugfs.txt
@@ -1,4 +1,5 @@
 Copyright 2009 Jonathan Corbet cor...@lwn.net
+Updated by Wang Long long.wangl...@huawei.com on 2015/07/16
 
 Debugfs exists as a simple way for kernel developers to make information
 available to user space.  Unlike /proc, which is only meant for information
@@ -51,6 +52,17 @@ operations should be provided; others can be included as 
needed.  Again,
 the return value will be a dentry pointer to the created file, NULL for
 error, or ERR_PTR(-ENODEV) if debugfs support is missing.
 
+Create a file with an initial size, the following function can be used
+instead:
+
+struct dentry *debugfs_create_file_size(const char *name, umode_t mode,
+   struct dentry *parent, void *data,
+   const struct file_operations *fops,
+   loff_t file_size);
+
+file_size is the initial file size. The other parameters are the same
+as the function debugfs_create_file.
+
 In a number of cases, the creation of a set of file operations is not
 actually necessary; the debugfs code provides a number of helper functions
 for simple situations.  Files containing a single integer value can be
@@ -100,6 +112,14 @@ A read on the resulting file will yield either Y (for 
non-zero values) or
 N, followed by a newline.  If written to, it will accept either upper- or
 lower-case values, or 1 or 0.  Any other input will be silently ignored.
 
+Also, atomic_t values can be placed in debugfs with:
+
+struct dentry *debugfs_create_atomic_t(const char *name, umode_t mode,
+   struct dentry *parent, atomic_t *value)
+
+A read of this file will get atomic_t values, and a write of this file
+will set atomic_t values.
+
 Another option is exporting a block of arbitrary binary data, with
 this structure and function:
 
@@ -147,6 +167,27 @@ The base argument may be 0, but you may want to build 
the reg32 array
 using __stringify, and a number of register names (macros) are actually
 byte offsets over a base for the register block.
 
+If you want to dump an u32 array in debugfs, you can create file with:
+
+struct dentry *debugfs_create_u32_array(const char *name, umode_t mode,
+   struct dentry *parent,
+   u32 *array, u32 elements);
+
+The array argument provides data, and the elements argument is
+the number of elements in the array. Note: Once array is created its
+size can not be changed.
+
+There is a helper function to create device related seq_file:
+
+   struct dentry *debugfs_create_devm_seqfile(struct device *dev,
+   const char *name,
+   struct dentry *parent,
+   int (*read_fn)(struct seq_file *s,
+   void *data));
+
+The dev argument is the device related to this debugfs file, and
+the read_fn is a function pointer which to be called to print the
+seq_file content.
 
 There are a couple of other directory-oriented helper functions:
 
-- 
1.8.3.4

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[PATCH v2 2/3] ARM: multi_v7_defconfig: Enable NTC Thermistors support

2015-07-16 Thread Javier Martinez Canillas
The Exynos5420 Peach Pit and Exynos5800 Peach Pi Chromebooks have
IIO based ADC thermistors. Enable module support for its driver
and also for the needed Exynos ADC driver.

Signed-off-by: Javier Martinez Canillas jav...@osg.samsung.com
Reviewed-by: Krzysztof Kozlowski k.kozlow...@samsung.com

---

Changes in v2:
- Add Krzysztof Kozlowski Reviewed-by tag in patch #2.

 arch/arm/configs/multi_v7_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm/configs/multi_v7_defconfig 
b/arch/arm/configs/multi_v7_defconfig
index b07493997993..0a8aa724c5a0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -357,6 +357,7 @@ CONFIG_POWER_RESET_KEYSTONE=y
 CONFIG_POWER_RESET_RMOBILE=y
 CONFIG_SENSORS_LM90=y
 CONFIG_SENSORS_LM95245=y
+CONFIG_SENSORS_NTC_THERMISTOR=m
 CONFIG_THERMAL=y
 CONFIG_CPU_THERMAL=y
 CONFIG_RCAR_THERMAL=y
@@ -617,6 +618,7 @@ CONFIG_MEMORY=y
 CONFIG_TI_AEMIF=y
 CONFIG_IIO=y
 CONFIG_AT91_ADC=m
+CONFIG_EXYNOS_ADC=m
 CONFIG_XILINX_XADC=y
 CONFIG_AK8975=y
 CONFIG_PWM=y
-- 
2.4.3

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