Ping
On 10.01.2016 19:46, Ivaylo Dimitrov wrote:
Add linux,can-disable; to all gpios exported from gpio-keys driver, so
userspace can disable them
Signed-off-by: Ivaylo Dimitrov
---
arch/arm/boot/dts/omap3-n900.dts | 6 ++
1 file changed, 6 insertions(+)
On Thu, Jan 21, 2016 at 03:41:27PM +0900, Michel Dänzer wrote:
> On 21.01.2016 15:38, Michel Dänzer wrote:
> > On 21.01.2016 14:31, Mario Kleiner wrote:
> >> On 01/21/2016 04:43 AM, Michel Dänzer wrote:
> >>> On 21.01.2016 05:32, Mario Kleiner wrote:
>
> So the problem is that AMDs hardwa
num_slots comes from pdata if existing, otherwise from
dw_mci_parse_dt which make it at least one slot. If
num_slots is less than 1 for the existing pdata case,
current code return -ENODEV. But dw_mci_probe seems to
treat this a optional case as it will call SDMMC_GET_SLOT_NUM
if no slot assigned.
On 01/21/2016 08:44 AM, Wenwei Tao wrote:
> 2016-01-20 21:19 GMT+08:00 Matias Bjørling :
>> On 01/15/2016 12:44 PM, Wenwei Tao wrote:
>>> When create a target, we specify the begin lunid and
>>> the end lunid, and get the corresponding continuous
>>> luns from media manager, if one of the luns is n
As per the documentation of the devfreq_dev_profile.target callback, set
the freq argument to the new frequency before returning.
This caused endless messages like this after recent changes in the core:
devfreq 6000c800.actmon: Couldn't update frequency transition information.
Signed-off-by: Tom
Signed-off-by: Yuan Yao
---
Changed in v3:
No changes.
Changed in v2:
Update my email to
---
arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts | 9 -
arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi| 4 ++--
2 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/bo
Hi, all
According to the suggestions from Thomas Gleixner, I made a new patch
to fix this problem.
Changes:
The commit 71f64340fc0e will not be reverted. And action test is
inserted.
Best Regards!
Zhu Yanjun
From: Zhu Yanjun
After this commit 71f64340fc0e ("genirq: Remove the second parameter
from handle_irq_event_percpu()") is applied, the variable desc->action is
not protected by raw_spin_lock. The following calltrace will pop up.
BUG: unable to handle kernel NULL pointer dereference at 00
2016-01-20 21:19 GMT+08:00 Matias Bjørling :
> On 01/15/2016 12:44 PM, Wenwei Tao wrote:
>> When create a target, we specify the begin lunid and
>> the end lunid, and get the corresponding continuous
>> luns from media manager, if one of the luns is not free,
>> we failed to create the target, even
On 01/21/2016 07:35 AM, Alexander Duyck wrote:
> This patch is meant to fix the RCU handling for VPD pages. The original
> code had a number of issues including the fact that the local variables
> were being declared as __rcu, the RCU variable being directly accessed
> outside of the RCU locked re
On 01/21/2016 07:35 AM, Alexander Duyck wrote:
> The patch "scsi: rescan VPD attributes" introduced a regression in which
> devices that don't support VPD were being scanned for VPD attributes
> anyway. This could cause issues for this parts and should be avoided so
> the check for scsi_level has
This makes vmalloc_to_phys() public as there will be another user
(in-kernel VFIO acceleration) for it soon.
As a part of future little optimization, this changes the helper to call
vmalloc_to_pfn() instead of vmalloc_to_page() as the size of the
struct page may not be power-of-two aligned which w
Cc:-ed other gents who touched the mutex code recently. Mail quoted below.
Thanks,
Ingo
* Ding Tianhong wrote:
> I build a script to create several process for ioctl loop calling,
> the ioctl will calling the kernel function just like:
> xx_ioctl {
> ...
> rtnl_lock();
> function();
>
Hi Simon, Linus, everyone,
On Thu, Jan 21, 2016 at 3:21 PM, Simon Horman
wrote:
> Update the mailing list used for development of support for
> ARM64 Renesas SoCs.
>
> This is a follow-up for a similar change for other Renesas SoCs and
> drivers uses by Renesas SoCs. The ARM64 SoC entry was not u
> From: Xiangliang Yu
>
> > Signed-off-by: Xiangliang Yu
>
> Yes.
>
> > Reviewed-by: Jon Mason
>
> Maybe, but that's for Jon to decide. If he accepts it, he will add
> signed-off-by,
> but again, that's for Jon to decide.
Jon also spend a lot of time to review the code, I think should sho
There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.
Therefore, this patch add support a provider as the parameter
handler when we call the clock register functions for per CRU.
Signed-off-by: Xing Zheng
---
Changes in v3:
Hi everyone,
Due to lack of time in the next few months, I've asked Bjorn Andersson for
help with the remoteproc/rpmsg/hwspinlock maintainership.
Bjorn has kindly agreed to step up and co-maintain
remoteproc/rpmsg/hwspinlock with me, and we expect that Bjorn will start
picking up patches as soon
new compatible string: "fsl,ls2080a-qspi".
Signed-off-by: Yuan Yao
---
Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-qspi" followed by "fsl,ls1021a-qspi"
Changed in v2:
Update my email to
---
Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 4 +++-
1 file
Add optional properties for QSPI:
big-endian
if the register is big endian on this platform.
Signed-off-by: Yuan Yao
---
Changed in v3:
No changes.
Changed in v2:
Update my email to
---
Documentation/devicetree/bindings/mtd/fsl-quadspi.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Do
new compatible string: "fsl,ls2080a-qspi".
Signed-off-by: Yuan Yao
---
Changed in v3:
Add the modifier for new compatible string like:
"fsl,ls2080a-dspi" followed by "fsl,ls2085a-dspi"
Changed in v2:
Update my email to
---
Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt | 5 -
1 fil
Ok, here's what I found after several hours of debugging and reviewing
this subsystem:
This subsystem plays is pretty loose in doing its math on 64 bit
registers. I traced through ktime_get_ts64 hundreds of times and
sampled data running through it and from what I saw, just normal
operations come
On Wed, Jan 20, 2016 at 04:14:51PM -0700, Shuah Khan wrote:
> On 01/20/2016 03:00 PM, Greg Kroah-Hartman wrote:
> > This is the start of the stable review cycle for the 3.10.95 release.
> > There are 35 patches in this series, all will be posted as a response
> > to this one. If anyone has any iss
Hi,
> On Wed, Jan 20, 2016 at 01:29:51PM +0100, Lothar Waßmann wrote:
>
> > This pin is used as IRQ pin for the LTC3589 PMIC on the Ka-Ro
> > electronics TX48 module. Make the IRQ optional in the driver and use a
> > polling routine instead if no IRQ is specified in DT.
> > Otherwise the driver w
2016-01-20 21:03 GMT+08:00 Matias Bjørling :
> On 01/15/2016 12:44 PM, Wenwei Tao wrote:
>> We can create more than one target on a lightnvm
>> device by specifying its begin lun and end lun.
>>
>> But only specify the physical address area is not
>> enough, we need to get the corresponding non-
>>
On Wed, Jan 20, 2016 at 10:22:44AM +0100, Peter Zijlstra wrote:
> On Wed, Jan 20, 2016 at 12:48:24PM +0800, Huang Rui wrote:
> > Hi Peter,
> >
> > Thanks so much to your comments.
> >
> > On Tue, Jan 19, 2016 at 01:12:50PM +0100, Peter Zijlstra wrote:
> > > On Thu, Jan 14, 2016 at 10:50:08AM +080
From: Xiangliang Yu
> Signed-off-by: Xiangliang Yu
Yes.
> Reviewed-by: Jon Mason
Maybe, but that's for Jon to decide. If he accepts it, he will add
signed-off-by, but again, that's for Jon to decide.
> Reviewed-by: Allen Hubbe
Adding my reviewed-by is hardly a reason to resend the whole
dw_mmc already use mmc_of_parse to get "broken-cd" property,
but it considered "broken-cd" to be a quirk in its driver. We
don't need this quirk here, and just take what we need from
mmc->caps.
Signed-off-by: Shawn Lin
---
Changes in v2:
- fix wrong using of cur_slot
drivers/mmc/host/dw_mmc.c
I build a script to create several process for ioctl loop calling,
the ioctl will calling the kernel function just like:
xx_ioctl {
...
rtnl_lock();
function();
rtnl_unlock();
...
}
The function may sleep several ms, but will not halt, at the same time
another user service may calling ifconfig to c
Resend V5 for more convenient pick up.
Main changes in V5
Only change Signed-off-by to Reviewed-by.
Xiangliang Yu (1):
[Resend patch V5] NTB: Add support for AMD PCI-Express Non-Transparent Bridge
MAINTAINERS |6 +
drivers/ntb/hw/Kconfig |1 +
drivers/ntb/h
On 2016/1/20 10:20, Alexei Starovoitov wrote:
On Wed, Jan 20, 2016 at 09:37:42AM +0800, Wangnan (F) wrote:
On 2016/1/20 1:42, Alexei Starovoitov wrote:
On Tue, Jan 19, 2016 at 11:16:44AM +, Wang Nan wrote:
This patchset introduces two methods to support reading from overwrite.
1) Tai
On 2016/1/21 9:43, Jaehoon Chung wrote:
Hi, Shawn.
After applied this patch at my dw-mmc git, i found some problem.
So I will revert this until fixing problem.
Oops this patch was based on some un-submmited ones which simplify
the probe flow. Although I did remember to only pick this one
Hi, Heiko,
Thank you for your reply.
On 2016年01月21日 07:38, Heiko Stuebner wrote:
Hi,
Am Mittwoch, 20. Januar 2016, 17:06:49 schrieb Xing Zheng:
There are need to support Multi-CRUs probability in future, but
it is not supported on the current Rockchip Clock Framework.
Therefore, this patc
This adds support for AMD's PCI-Express Non-Transparent Bridge
(NTB) device on the Zeppelin platform. The driver connnects to the
standard NTB sub-system interface, with modification to add hooks
for power management in a separate patch. The AMD NTB device has 3
memory windows, 16 doorbell, 16 scra
Heiko Carstens writes:
> On Wed, Jan 06, 2016 at 11:20:55AM +0800, kernel test robot wrote:
>> FYI, we noticed the below changes on
>>
>> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
>> commit 6cdb18ad98a49f7e9b95d538a0614cde827404b8 ("mm/vmstat: fix overflow in
>>
On 21 January 2016 at 06:10, Rusty Russell wrote:
> Ard Biesheuvel writes:
>> This implements text-relative kallsyms address tables. This was developed
>> as part of my series to implement KASLR/CONFIG_RELOCATABLE for arm64, but
>> I think it may be beneficial to other architectures as well, so I
On 21.01.2016 15:38, Michel Dänzer wrote:
> On 21.01.2016 14:31, Mario Kleiner wrote:
>> On 01/21/2016 04:43 AM, Michel Dänzer wrote:
>>> On 21.01.2016 05:32, Mario Kleiner wrote:
So the problem is that AMDs hardware frame counters reset to
zero during a modeset. The old DRM code dea
On 2016/1/21 13:13, Michael S. Tsirkin wrote:
On Thu, Jan 21, 2016 at 10:11:35AM +0800, Yang Zhang wrote:
On 2016/1/20 22:35, Michael S. Tsirkin wrote:
On Tue, Dec 01, 2015 at 02:39:45PM +0800, Jason Wang wrote:
This patch tries to poll for new added tx buffer or socket receive
queue for a whi
On 21.01.2016 14:31, Mario Kleiner wrote:
> On 01/21/2016 04:43 AM, Michel Dänzer wrote:
>> On 21.01.2016 05:32, Mario Kleiner wrote:
>>>
>>> So the problem is that AMDs hardware frame counters reset to
>>> zero during a modeset. The old DRM code dealt with drivers doing that by
>>> keeping vblank
The patch "scsi: rescan VPD attributes" introduced a regression in which
devices that don't support VPD were being scanned for VPD attributes
anyway. This could cause issues for this parts and should be avoided so
the check for scsi_level has been moved out of scsi_add_lun and into
scsi_attach_vpd
This patch is meant to fix the RCU handling for VPD pages. The original
code had a number of issues including the fact that the local variables
were being declared as __rcu, the RCU variable being directly accessed
outside of the RCU locked region, and the fact that length was not
associated with
Recent changes to the kernel pulled in during the merge window have
resulted in my system generating an endless loop of the following type of
errors:
[ 318.965756] ata14: SATA link up 1.5 Gbps (SStatus 113 SControl 300)
[ 318.968457] ata14.00: configured for UDMA/66
[ 318.970656] ata14: EH comp
From: Gu Zheng
[Problem]
cpuid <-> nodeid mapping is firstly established at boot time. And workqueue
caches
the mapping in wq_numa_possible_cpumask in wq_numa_init() at boot time.
When doing node online/offline, cpuid <-> nodeid mapping is
established/destroyed,
which means, cpuid <-> nodeid
> From: Yu, Xiangliang [mailto:xiangliang...@amd.com]
> > > > Signed-off-by: Jon Mason
> > > > Signed-off-by: Allen Hubbe
> > >
> > > NO.
> >
> > Ok, I'll change it if you doesn't want to change it.
>
> Nah, just remember it for next time...
>
> I'm satisfied with this v5.
>
> Reviewed-by: All
From: Gu Zheng
The whole patch-set aims at making cpuid <-> nodeid mapping persistent. So that,
when node online/offline happens, cache based on cpuid <-> nodeid mapping such
as
wq_numa_possible_cpumask will not cause any problem.
It contains 4 steps:
1. Enable apic registeration flow to handle
From: Gu Zheng
The whole patch-set aims at making cpuid <-> nodeid mapping persistent. So that,
when node online/offline happens, cache based on cpuid <-> nodeid mapping such
as
wq_numa_possible_cpumask will not cause any problem.
It contains 4 steps:
1. Enable apic registeration flow to handle
From: Gu Zheng
The whole patch-set aims at making cpuid <-> nodeid mapping persistent. So that,
when node online/offline happens, cache based on cpuid <-> nodeid mapping such
as
wq_numa_possible_cpumask will not cause any problem.
It contains 4 steps:
1. Enable apic registeration flow to handle
[Problem]
cpuid <-> nodeid mapping is firstly established at boot time. And workqueue
caches
the mapping in wq_numa_possible_cpumask in wq_numa_init() at boot time.
When doing node online/offline, cpuid <-> nodeid mapping is
established/destroyed,
which means, cpuid <-> nodeid mapping will chan
For now, x86 does not support memory-less node. A node without memory
will not be onlined, and the cpus on it will be mapped to the other
online nodes with memory in init_cpu_to_node(). The reason of doing this
is to ensure each cpu has mapped to a node with memory, so that it will
be able to alloc
Signed-off-by: Huaitong Han
---
arch/x86/include/asm/elf.h | 2 +-
arch/x86/kernel/mpparse.c | 2 +-
arch/x86/lguest/boot.c | 2 +-
arch/x86/xen/enlighten.c | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/x86/include/asm/elf.h b/arch/x86/include/asm/elf.h
index
Hi Rob:
thanks for your review.
On 2016年01月21日 02:28, Rob Herring wrote:
On Tue, Jan 12, 2016 at 07:29:49PM +0800, Andy Yan wrote:
add device tree binding document for reboot-mode driver
Signed-off-by: Andy Yan
---
Changes in v2: None
Changes in v1: None
.../bindings/power/reset/reboot
On Wed, Jan 20, 2016 at 8:42 PM, Christoph Lameter wrote:
> On Wed, 20 Jan 2016, Shiraz Hashim wrote:
>
>> The patch makes vmstat_shepherd deferable which if is quiesed
>> would not schedule vmstat update on other cpus. Wouldn't this
>> aggravate the problem of vmstat for rest cpus not gettng upda
Update the mailing list used for development of support for
ARM64 Renesas SoCs.
This is a follow-up for a similar change for other Renesas SoCs and
drivers uses by Renesas SoCs. The ARM64 SoC entry was not updated in
that patch as it was not yet present in mainline.
The motivation for the mailing
From: Yu, Xiangliang [mailto:xiangliang...@amd.com]
> > > Signed-off-by: Jon Mason
> > > Signed-off-by: Allen Hubbe
> >
> > NO.
>
> Ok, I'll change it if you doesn't want to change it.
Nah, just remember it for next time...
I'm satisfied with this v5.
Reviewed-by: Allen Hubbe
> I don’t thin
On 2016/1/21 14:02, Wu, Feng wrote:
-Original Message-
From: Yang Zhang [mailto:yang.zhang...@gmail.com]
Sent: Thursday, January 21, 2016 1:58 PM
To: Wu, Feng ; pbonz...@redhat.com;
rkrc...@redhat.com
Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
Subject: Re: [PATCH v3 2/4] KV
On Thu, Jan 21, 2016 at 01:47:10PM +0800, Huang, Ying wrote:
> Sudip Mukherjee writes:
>
> > On Wed, Jan 20, 2016 at 01:00:40PM +0800, Huang, Ying wrote:
> >> Sudip Mukherjee writes:
> >>
> >> > On Wed, Jan 20, 2016 at 08:44:37AM +0800, kernel test robot wrote:
> >
> > I am not able to reprodu
> -Original Message-
> From: Yang Zhang [mailto:yang.zhang...@gmail.com]
> Sent: Thursday, January 21, 2016 1:58 PM
> To: Wu, Feng ; pbonz...@redhat.com;
> rkrc...@redhat.com
> Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
> Subject: Re: [PATCH v3 2/4] KVM: x86: Use vector-hashin
> From: Xiangliang Yu
> > This adds support for AMD's PCI-Express Non-Transparent Bridge
> > (NTB) device on the Zeppelin platform. The driver connnects to the
> > standard NTB sub-system interface, with modification to add hooks for
> > power management in a separate patch. The AMD NTB device h
On 2016/1/21 13:46, Wu, Feng wrote:
-Original Message-
From: Yang Zhang [mailto:yang.zhang...@gmail.com]
Sent: Thursday, January 21, 2016 1:43 PM
To: Wu, Feng ; pbonz...@redhat.com;
rkrc...@redhat.com
Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
Subject: Re: [PATCH v3 2/4] KV
Recent changes (4.4.0+) in module loader triggered oops on ARM :
The module in question is in-tree module :
drivers/misc/ti-st/st_drv.ko
The BUG is here :
[ 53.638335] [ cut here ]
[ 53.642967] kernel BUG at mm/memory.c:1878!
[ 53.647153] Internal error: Oops - BUG: 0 [#
Hi Yingjoe,
On Thu, 2016-01-21 at 10:45 +0800, Yingjoe Chen wrote:
> On Thu, 2016-01-21 at 10:28 +0800, Yingjoe Chen wrote:
> > On Tue, 2016-01-12 at 16:31 +0800, James Liao wrote:
> > > Add a Kconfig to define clock configuration for each SoC, and
> > > modify the Makefile to build drivers that o
Hi Douglas,
[auto build test ERROR on next-20160120]
[cannot apply to v4.4-rc8 v4.4-rc7 v4.4-rc6 v4.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Douglas-Anderson/usb-dwc2-host-Fix-and
On (01/21/16 10:25), Sergey Senozhatsky wrote:
[..]
> > First, the message "This stops the holder of console_sem just where we
> > want him" is suspitious.
>
> this comment is irrelevant, as of today. it was, a long time ago, because
> the entire thing was a bit different (linux-2.4.21 kernel/prin
Hi Yingjoe,
On Thu, 2016-01-21 at 10:28 +0800, Yingjoe Chen wrote:
> On Tue, 2016-01-12 at 16:31 +0800, James Liao wrote:
> > Add a Kconfig to define clock configuration for each SoC, and
> > modify the Makefile to build drivers that only selected in config.
> >
> > Signed-off-by: Shunli Wang
>
Hi Stephen,
On Thu, Jan 21, 2016 at 04:25:45PM +1100, Stephen Rothwell wrote:
> Hi Sudip,
>
> On Thu, 21 Jan 2016 10:47:09 +0530 Sudip Mukherjee
> wrote:
> >
> > On Thu, Jan 21, 2016 at 04:11:56PM +1100, Stephen Rothwell wrote:
> > > Hi Andrew,
> > >
> > > After merging the akpm-current tree,
Sudip Mukherjee writes:
> On Wed, Jan 20, 2016 at 01:00:40PM +0800, Huang, Ying wrote:
>> Sudip Mukherjee writes:
>>
>> > On Wed, Jan 20, 2016 at 08:44:37AM +0800, kernel test robot wrote:
>> >> FYI, we noticed the below changes on
>> >>
>> >> https://git.kernel.org/pub/scm/linux/kernel/git/to
> -Original Message-
> From: Yang Zhang [mailto:yang.zhang...@gmail.com]
> Sent: Thursday, January 21, 2016 1:43 PM
> To: Wu, Feng ; pbonz...@redhat.com;
> rkrc...@redhat.com
> Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
> Subject: Re: [PATCH v3 2/4] KVM: x86: Use vector-hashin
On 2016/1/21 13:41, Wu, Feng wrote:
-Original Message-
From: Yang Zhang [mailto:yang.zhang...@gmail.com]
Sent: Thursday, January 21, 2016 1:36 PM
To: Wu, Feng ; pbonz...@redhat.com;
rkrc...@redhat.com
Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
Subject: Re: [PATCH v3 1/4] KV
On 2016/1/21 13:33, Wu, Feng wrote:
-Original Message-
From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
ow...@vger.kernel.org] On Behalf Of Yang Zhang
Sent: Thursday, January 21, 2016 1:24 PM
To: Wu, Feng ; pbonz...@redhat.com;
rkrc...@redhat.com
Cc: linux-kernel@vger.ker
> -Original Message-
> From: Yang Zhang [mailto:yang.zhang...@gmail.com]
> Sent: Thursday, January 21, 2016 1:36 PM
> To: Wu, Feng ; pbonz...@redhat.com;
> rkrc...@redhat.com
> Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
> Subject: Re: [PATCH v3 1/4] KVM: Recover IRTE to remapp
Hi everyone,
This series adds support for vqmmc regulator and eMMC DDR modes for
sunxi-mmc. Allwinner's MMC controller supports eMMC 4.41 on earlier
SoCs, and up to 5.0 on latest ones. UHS-1 modes are also supported
by the hardware, but these are not covered in this series, as no
boards have dedic
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun9i-a80.dt
mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.
Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.
Sig
mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.
Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.
Sig
eMMC chips require 2 power supplies, vmmc for internal logic, and vqmmc
for driving output buffers. vqmmc also controls signaling voltage. Most
boards we've seen use the same regulator for both, nevertheless the 2
have different usages, and should be set separately.
This patch adds support for vqm
sun9i/A80 MMC controllers have a larger FIFO, and the FIFO DMA
trigger levels can be increased. Also, the mmc module clock parent
has a higher clock rate, and the sample and output delay phases
are different.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun9i-a80.dtsi | 8
1 file c
Allwinner's MMC controller needs to run at double the card clock rate
for 8 bit DDR transfer modes. Interestingly, this is not needed for
4 bit DDR transfers.
Different clock delays are needed for 8 bit eMMC DDR, due to the
increased module clock rate. For the A80 though, the same values for
4 bit
mmc2 has a special pin for eMMC hardware reset, which is controllable
from the controller. Add the "mmc-cap-hw-reset" property to denote that
this controller supports this function, and the pins are actually used.
Also increase the signal drive strength for mmc2 pins, for HS-DDR mode
support.
Sig
According to Allwinner, only mmc3 supports 8 bit DDR transfers for eMMC.
Switch to mmc3 for the onboard eMMC, and also assign vqmmc for signal
voltage sensing/switching, and "cap-mmc-hw-reset" to denote this
instance can use eMMC hardware reset.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/
mmc2_8bit_pins is used with eMMC chips, which also have a reset pin.
The MMC controller also has a reset output that is supported.
Signed-off-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-a23-
Remove unnecessory "if" statement and club it with previos "if" block.
Signed-off-by: Sunil Shahu
---
net/mac80211/mesh_plink.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/net/mac80211/mesh_plink.c b/net/mac80211/mesh_plink.c
index bd3d55e..e5851ae 100644
--- a/n
mmc2 and mmc3 are available on the same pins, with different mux values.
However, only mmc3 supports 8 bit DDR transfer modes.
Since preference for mmc3 over mmc2 is due to DDR transfer modes, just
set the drive strength to 40mA, which is needed for DDR.
This pinmux setting also includes the hard
On 2016/1/21 13:07, Wu, Feng wrote:
-Original Message-
From: Yang Zhang [mailto:yang.zhang...@gmail.com]
Sent: Thursday, January 21, 2016 1:00 PM
To: Wu, Feng ; pbonz...@redhat.com;
rkrc...@redhat.com
Cc: linux-kernel@vger.kernel.org; k...@vger.kernel.org
Subject: Re: [PATCH v3 1/4] KV
Allwinner's mmc controller supports signal voltage switching. This is
supported in code in Allwinner's kernel. However, publicly available
boards all tie it to a fixed 3.0/3.3V regulator, with options to tie
it to 1.8V for eMMC on some.
Since Allwinner's kernel is an ancient 3.4, it is hard to say
sunxi_mmc_init_host() originated from Allwinner kernel sources. The
magic numbers written to various registers was never documented.
Add comments for values found in Allwinner user manuals.
Signed-off-by: Chen-Yu Tsai
---
drivers/mmc/host/sunxi-mmc.c | 12
1 file changed, 12 insert
> -Original Message-
> From: linux-kernel-ow...@vger.kernel.org [mailto:linux-kernel-
> ow...@vger.kernel.org] On Behalf Of Yang Zhang
> Sent: Thursday, January 21, 2016 1:24 PM
> To: Wu, Feng ; pbonz...@redhat.com;
> rkrc...@redhat.com
> Cc: linux-kernel@vger.kernel.org; k...@vger.kernel
DDR transfer modes include UHS-1 DDR50 and MMC HS-DDR (or MMC_DDR52).
Consider MMC_DDR52 when setting clock delays.
Signed-off-by: Chen-Yu Tsai
---
drivers/mmc/host/sunxi-mmc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/ho
Let .set_ios() fail if mmc_regulator_set_ocr() fails to enable and set a
proper voltage for vmmc.
Signed-off-by: Chen-Yu Tsai
---
drivers/mmc/host/sunxi-mmc.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/sunxi-mmc.c b/drivers/mmc/host/sunxi-mmc.c
index
On Mon, 2016-18-01 at 00:44:27 UTC, Michael Ellerman wrote:
> From: Alan Modra
>
> PowerPC64 uses the symbol .TOC. much as other targets use
> _GLOBAL_OFFSET_TABLE_. It identifies the value of the GOT pointer (or in
> powerpc parlance, the TOC pointer). Global offset tables are generally
> local
Now that clock delay settings for 8 bit DDR are correct, and vqmmc
support is available, we can enable MMC_CAP_1_8V_DDR support. This
enables MMC HS-DDR at up to 52 MHz, even if signal voltage switching
is not available.
Signed-off-by: Chen-Yu Tsai
---
drivers/mmc/host/sunxi-mmc.c | 1 +
1 file
On Wed, Jan 20, 2016 at 01:00:40PM +0800, Huang, Ying wrote:
> Sudip Mukherjee writes:
>
> > On Wed, Jan 20, 2016 at 08:44:37AM +0800, kernel test robot wrote:
> >> FYI, we noticed the below changes on
> >>
> >> https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
> >> commi
On 01/21/2016 04:43 AM, Michel Dänzer wrote:
On 21.01.2016 05:32, Mario Kleiner wrote:
So the problem is that AMDs hardware frame counters reset to
zero during a modeset. The old DRM code dealt with drivers doing that by
keeping vblank irqs enabled during modesets and incrementing vblank
count
On Wed, 2016-01-20 at 17:14 +0800, Yingjoe Chen wrote:
> On Wed, 2016-01-20 at 14:08 +0800, James Liao wrote:
> > Refine scpsys driver common code to support multiple SoC / platform.
> >
> > Signed-off-by: James Liao
> <...>
> > diff --git a/drivers/soc/mediatek/mtk-scpsys.h
> > b/drivers/soc/me
Hi Douglas,
[auto build test ERROR on next-20160120]
[cannot apply to v4.4-rc8 v4.4-rc7 v4.4-rc6 v4.4]
[if your patch is applied to the wrong git tree, please drop us a note to help
improving the system]
url:
https://github.com/0day-ci/linux/commits/Douglas-Anderson/usb-dwc2-host-Fix-and
Hi Sudip,
On Thu, 21 Jan 2016 10:47:09 +0530 Sudip Mukherjee
wrote:
>
> On Thu, Jan 21, 2016 at 04:11:56PM +1100, Stephen Rothwell wrote:
> > Hi Andrew,
> >
> > After merging the akpm-current tree, today's linux-next build (arm
> > efm32_defconfig) failed like this:
> >
> > fs/proc/task_nommu.
On 2016/1/20 9:42, Feng Wu wrote:
Use vector-hashing to deliver lowest-priority interrupts, As an
example, modern Intel CPUs in server platform use this method to
handle lowest-priority interrupts.
Signed-off-by: Feng Wu
---
v3:
- Fix a bug for sparse topologies, in that case, vcpu_id is not eq
On Wed, Jan 20, 2016 at 06:22:04PM +, Linux Kernel wrote:
> Web:
> https://git.kernel.org/torvalds/c/93209d65c1d38f86ffb3f61a1214130b581a9709
> Commit: 93209d65c1d38f86ffb3f61a1214130b581a9709
> Parent: a1ccdb63b5535dc3446b0a9efc6d97aca82c72ef
> Refname:refs/heads/maste
Hi Yingjoe, Rob,
On Wed, 2016-01-20 at 10:35 -0600, Rob Herring wrote:
> On Wed, Jan 20, 2016 at 05:29:21PM +0800, Yingjoe Chen wrote:
> > On Wed, 2016-01-20 at 14:08 +0800, James Liao wrote:
> > > From: Shunli Wang
> > >
> > > Add power dt-bindings for MT2701.
> > >
> > > Signed-off-by: Shunli
FYI, we noticed the below changes on
https://github.com/0day-ci/linux
Zhaoyang-Huang/rpm-refining-the-rpm_suspend-function/20160120-160501
commit 1b018e07564eb530a5f19f1acab2a926f84b ("rpm: refining the rpm_suspend
fun
FYI, we noticed the below changes on
https://git.kernel.org/pub/scm/linux/kernel/git/mel/linux-balancenuma
mm-vmscan-node-lru-v2r16
commit ab543c4e6ce43e2225a598e2d96f5b0ec04dbd73 ("mm, vmscan: Move LRU lists to
node")
[7.976872] Loading compiled-in X.509 certificates
[8.057169] Unregi
Hi Rob,
On Wed, 2016-01-20 at 10:32 -0600, Rob Herring wrote:
> On Wed, Jan 20, 2016 at 02:35:43PM +0800, James Liao wrote:
> > This patch adds the binding documentation for apmixedsys, bdpsys,
> > ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
> > vdecsys for Mediatek MT2701.
> >
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