On Mon, 16 May 2016, Vignesh R wrote:
> From: Grygorii Strashko
>
> It is seen that just enabling the TSC module triggers a HW_PEN IRQ
> without any interaction with touchscreen by user. This results in first
> suspend/resume sequence to fail as system immediately
On Mon, 16 May 2016, Vignesh R wrote:
> From: Grygorii Strashko
>
> It is seen that just enabling the TSC module triggers a HW_PEN IRQ
> without any interaction with touchscreen by user. This results in first
> suspend/resume sequence to fail as system immediately wakes up from
> suspend as
On 20 August 2015 at 16:56, Maxime Ripard
wrote:
>> + /* Enable Dedicated DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + reg |= SUN4I_CTL_DMAMC_DEDICATED;
>> + sun4i_spi_write(sspi,
On 20 August 2015 at 16:56, Maxime Ripard
wrote:
>> + /* Enable Dedicated DMA requests */
>> + reg = sun4i_spi_read(sspi, SUN4I_CTL_REG);
>> + reg |= SUN4I_CTL_DMAMC_DEDICATED;
>> + sun4i_spi_write(sspi, SUN4I_CTL_REG, reg);
>> +
Hi Linus,
we're not talking about a driver here - we're talking about a new API
lifted from a driver to generic code because it's commonly useful.
It's also in entirely new files and not a modification of existing code,
and it's always been clear how it is. Some of the code has been in
since
Hi Linus,
we're not talking about a driver here - we're talking about a new API
lifted from a driver to generic code because it's commonly useful.
It's also in entirely new files and not a modification of existing code,
and it's always been clear how it is. Some of the code has been in
since
Hi,
[auto build test ERROR on next-20160511]
[cannot apply to v4.6-rc7 v4.6-rc6 v4.6-rc5 v4.6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
Hi,
[auto build test ERROR on next-20160511]
[cannot apply to v4.6-rc7 v4.6-rc6 v4.6-rc5 v4.6]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
On 05/17/2016 03:06 AM, Wang Xiaoqiang wrote:
>>yes it would. Why that would matter. The checks should be in an order
>>which could give us a more specific reason with later checks. bad_page()
>
> I see, you mean the later "bad_reason" is the superset of the previous one.
Not exactly. It's not
On 05/17/2016 03:06 AM, Wang Xiaoqiang wrote:
>>yes it would. Why that would matter. The checks should be in an order
>>which could give us a more specific reason with later checks. bad_page()
>
> I see, you mean the later "bad_reason" is the superset of the previous one.
Not exactly. It's not
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +-
1 file changed, 1
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
1 file changed, 2
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/serial/microchip,pic32-uart.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-dmt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: James Liao
This patch fixed wrong state of parent clocks if they are registered
after critical clocks.
Signed-off-by: James Liao
---
drivers/clk/clk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git
From: Shunli Wang
Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
From: James Liao
This patch fixed wrong state of parent clocks if they are registered
after critical clocks.
Signed-off-by: James Liao
---
drivers/clk/clk.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index ce39add..bf80e39
From: Shunli Wang
Dt-binding file about reset controller is used to provide
kinds of definition, which is referenced by dts file and
IC-specified reset controller driver code.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
Acked-by: Philipp Zabel
---
From: James Liao
Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by:
From: James Liao
Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
Reviewed-by: Matthias Brugger
---
drivers/clk/Kconfig |
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
1 file changed, 1 insertion(+),
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
1 file changed, 2
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/gpio/microchip,pic32-gpio.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/watchdog/microchip,pic32-wdt.txt | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
From: Shunli Wang
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
From: Shunli Wang
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
---
drivers/clk/mediatek/Kconfig | 50 ++
drivers/clk/mediatek/Makefile |7
From: Shunli Wang
Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
From: Shunli Wang
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.
Signed-off-by: Shunli Wang
From: James Liao
Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and
bdpsys. This patch also add two oscillators that provide clocks for
MT2701.
Signed-off-by: James Liao
From: James Liao
This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.
Signed-off-by: James Liao
Tested-by: John Crispin
We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.
Signed-off-by: Erin Lo
---
arch/arm/boot/dts/mt2701.dtsi | 18 --
1 file changed, 8
From: Shunli Wang
Add MT2701 clock dt-bindings, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
Reviewed-by: Matthias Brugger
---
include/dt-bindings/clock/mt2701-clk.h | 486
From: Shunli Wang
In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.
Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Tested-by: John Crispin
From: James Liao
Add clock controller nodes for MT2701, include topckgen, infracfg,
pericfg, apmixedsys, mmsys, imgsys, vdecsys, hifsys, ethsys and
bdpsys. This patch also add two oscillators that provide clocks for
MT2701.
Signed-off-by: James Liao
---
arch/arm/boot/dts/mt2701.dtsi | 42
From: James Liao
This patch adds the binding documentation for apmixedsys, bdpsys,
ethsys, hifsys, imgsys, infracfg, mmsys, pericfg, topckgen and
vdecsys for Mediatek MT2701.
Signed-off-by: James Liao
Tested-by: John Crispin
Acked-by: Rob Herring
---
We used to use a fixed rate clock for the UARTs. Now that we have clock
support we can associate the correct clocks to the UARTs and drop the
26MHz fixed rate UART clock.
Signed-off-by: Erin Lo
---
arch/arm/boot/dts/mt2701.dtsi | 18 --
1 file changed, 8 insertions(+), 10
Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +-
1 file changed, 1
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
1 file changed, 1
Update binding example based on new clock binding documentation.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/mmc/microchip,sdhci-pic32.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Update binding example based on new clock binding scheme.
[1] Documentation/devicetree/bindings/clock/microchip,pic32.txt
Signed-off-by: Purna Chandra Mandal
---
Documentation/devicetree/bindings/pinctrl/microchip,pic32-pinctrl.txt | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.
To fix this use PIC32 specific
From: Joshua Henderson
The wrong external interrupt bits are being set, offset by 1.
Signed-off-by: Joshua Henderson
Signed-off-by: Purna Chandra Mandal
---
drivers/irqchip/irq-pic32-evic.c | 2 +-
1 file
From: James Liao
Remove __init from functions that will be used by init functions
that support probe deferral.
Signed-off-by: James Liao
---
drivers/clk/mediatek/clk-gate.c | 2 +-
drivers/clk/mediatek/clk-mtk.c | 12 ++--
Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.
Signed-off-by: Purna Chandra Mandal
---
drivers/tty/serial/pic32_uart.c | 1 -
1 file changed, 1 deletion(-)
diff --git
PIC32 clock driver is now implemented as platform driver instead of
as part of of_clk_init(). It meants all the clock modules are available
quite late in the boot sequence. So request for CPU clock by clk_get_sys()
and clk_get_rate() to find c0_timer rate fails.
To fix this use PIC32 specific
From: Joshua Henderson
The wrong external interrupt bits are being set, offset by 1.
Signed-off-by: Joshua Henderson
Signed-off-by: Purna Chandra Mandal
---
drivers/irqchip/irq-pic32-evic.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-pic32-evic.c
From: James Liao
Remove __init from functions that will be used by init functions
that support probe deferral.
Signed-off-by: James Liao
---
drivers/clk/mediatek/clk-gate.c | 2 +-
drivers/clk/mediatek/clk-mtk.c | 12 ++--
drivers/clk/mediatek/clk-pll.c | 2 +-
3 files changed, 8
Allocated memory for 'sport->irq_fault_name' is freed twice, first
in error check of 'if(!sport->irq_rx_name)' and other in fallback
handler.
Signed-off-by: Purna Chandra Mandal
---
drivers/tty/serial/pic32_uart.c | 1 -
1 file changed, 1 deletion(-)
diff --git
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda.c | 1 +
pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
Optional SOSC is an external fixed clock running at 32768HZ.
So Initialize SOSC rate as per PIC32MZDA datasheet.
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-pic32mzda.c | 1 +
1 file changed, 1
pbclk_set_rate() is using readl_poll_timeout_atomic() even
though spinlock is released. Fix it by replacing with
readl_poll_timeout().
Signed-off-by: Purna Chandra Mandal
---
Note: Please pull this complete series through the MIPS tree.
---
drivers/clk/microchip/clk-core.c | 6 +++---
1 file
This series is based on clk-next, add clock and reset controller support
for Mediatek MT2701.
This series also refined makefile and Kconfig to support configurable
multiple SoC clock support.
There some code borrowed from [2] in clk-mtk.h, and may need to resolve
conflicts while merging these
This series is based on clk-next, add clock and reset controller support
for Mediatek MT2701.
This series also refined makefile and Kconfig to support configurable
multiple SoC clock support.
There some code borrowed from [2] in clk-mtk.h, and may need to resolve
conflicts while merging these
Hi all,
Please do not add any v4.8 destined material to your linux-next included
branches until after v4.7-rc1 has been released.
Changes since 20160516:
The vfs tree gained a conflict against the ext4 tree.
The net-next tree gained a conflict against the arm64 tree.
The spi tree lost its
Hi all,
Please do not add any v4.8 destined material to your linux-next included
branches until after v4.7-rc1 has been released.
Changes since 20160516:
The vfs tree gained a conflict against the ext4 tree.
The net-next tree gained a conflict against the arm64 tree.
The spi tree lost its
3047a96d7cfcfca1a6d026ecaec526ea4803e9e/linux-headers.cgz"
repeat_to: 2
kernel:
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/vmlinuz-4.5.0-00570-g23047a9"
dequeue_time: 2016-05-17 00:25:26.281743408 +08:00
job_state: finished
loadavg: 39.10 58.24 29.31 1/548
3047a96d7cfcfca1a6d026ecaec526ea4803e9e/linux-headers.cgz"
repeat_to: 2
kernel:
"/pkg/linux/x86_64-rhel/gcc-4.9/23047a96d7cfcfca1a6d026ecaec526ea4803e9e/vmlinuz-4.5.0-00570-g23047a9"
dequeue_time: 2016-05-17 00:25:26.281743408 +08:00
job_state: finished
loadavg: 39.10 58.24 29.31 1/548
On Mon, May 16, 2016 at 12:25:47PM -0600, Jason Gunthorpe wrote:
> Provide some flags in tpm_class_ops to allow drivers to opt-in to the
> common startup sequence. This is the sequence used by tpm_tis and
> tpm_crb.
>
> All drivers should set this flag.
The commit message should be a much much
On Mon, May 16, 2016 at 12:25:47PM -0600, Jason Gunthorpe wrote:
> Provide some flags in tpm_class_ops to allow drivers to opt-in to the
> common startup sequence. This is the sequence used by tpm_tis and
> tpm_crb.
>
> All drivers should set this flag.
The commit message should be a much much
On 05/16/2016 06:14 PM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 3.14.70 release.
There are 17 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
On 05/16/2016 06:14 PM, Greg Kroah-Hartman wrote:
This is the start of the stable review cycle for the 3.14.70 release.
There are 17 patches in this series, all will be posted as a response
to this one. If anyone has any issues with these being applied, please
let me know.
Responses should be
Hello Greg KH,
I make patch same like other, I'm new and I nerver see changelog in other
patches.
Where to add changelog? I followed you are tutorial.
Thanks,
Amit Ghadge
On Mon, May 16, 2016 at 08:34:55PM -0700, Greg KH wrote:
>
> A: No.
> Q: Should I include quotations after my reply?
>
>
Hello Greg KH,
I make patch same like other, I'm new and I nerver see changelog in other
patches.
Where to add changelog? I followed you are tutorial.
Thanks,
Amit Ghadge
On Mon, May 16, 2016 at 08:34:55PM -0700, Greg KH wrote:
>
> A: No.
> Q: Should I include quotations after my reply?
>
>
commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to
commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to
this patch set contains the following changes
1. fix issues in cyclic dma
2. add support to SYNC DMA termination
3. avoid system hang, when SDMA channel 0 timeouts
4. add lock to prevent race condition
Jiada Wang (10):
dma: imx-sdma: use chn_real_count to report residue for UART
dma:
Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.
This patch updates sdmac status to the status of current
Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful,
On Mon, May 16, 2016 at 10:46:38AM +0100, Matt Fleming wrote:
> > >
> > > - rq->clock_skip_update = 0;
> > > + /* Clear ACT, preserve everything else */
> > > + rq->clock_update_flags ^= RQCF_ACT_SKIP;
> >
> > The comment says "Clear ACT", but this is really xor, and I am not sure
> > this is
Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.
This patch updates sdmac status to the status of current
Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful,
On Mon, May 16, 2016 at 10:46:38AM +0100, Matt Fleming wrote:
> > >
> > > - rq->clock_skip_update = 0;
> > > + /* Clear ACT, preserve everything else */
> > > + rq->clock_update_flags ^= RQCF_ACT_SKIP;
> >
> > The comment says "Clear ACT", but this is really xor, and I am not sure
> > this is
this patch set contains the following changes
1. fix issues in cyclic dma
2. add support to SYNC DMA termination
3. avoid system hang, when SDMA channel 0 timeouts
4. add lock to prevent race condition
Jiada Wang (10):
dma: imx-sdma: use chn_real_count to report residue for UART
dma:
Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c
Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c | 43
Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
---
For uart rx dma data may not receive fully, so the number
of data read by sdma script once isn't always equal to period_len,
thus residue returned from sdma_tx_status() isn't valid for uart rx
dma. The old way to use chn_real_count to report residue should be
used for uart rx dma.
Signed-off-by:
For uart rx dma data may not receive fully, so the number
of data read by sdma script once isn't always equal to period_len,
thus residue returned from sdma_tx_status() isn't valid for uart rx
dma. The old way to use chn_real_count to report residue should be
used for uart rx dma.
Signed-off-by:
Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.
This patch updates sdmac status to the status of current
There is race between STOP of SDMA channel and finish of
SDMA transfer, so some times, even after sdma_disable_channel()
is called, the bit of 'terminated channel' in INTR may still get
asserted, thus cause an extra sdma tasklet be called.
Add flag 'enabled' to each sdma channel to indicate its
Previously for cyclic dma mode, once sdma fails sdma channel status will
be set to DMA_ERROR, unless the transfer is prepared again, sdmac status
will always be kept to DMA_ERROR, even the transfer for following buffers
is successful.
This patch updates sdmac status to the status of current
There is race between STOP of SDMA channel and finish of
SDMA transfer, so some times, even after sdma_disable_channel()
is called, the bit of 'terminated channel' in INTR may still get
asserted, thus cause an extra sdma tasklet be called.
Add flag 'enabled' to each sdma channel to indicate its
Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful,
commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to
Previously in cyclic dma mode when sdma transfer fails for one buffer,
it will mask BD_RROR flag for that buffer descriptor (BD). This flag
won't be cleared unless a new cyclic dma transfer is prepared, so if
sdma script next time iterates to the same BD, even this time the
transfer is successful,
commit d1a792f3b407 ("Update imx-sdma cyclic handling to report residue")
moves updating of BD to isr routine, to avoid stop
of cyclic dma, but there is chance 'new' isr comes before the 'old'
tasklet can be fired, thus cause data loss due to missing of one
tasklet. So move updating of BD back to
In case the corresponding channel has already been terminated,
then instead of go on updating channel status, driver should abort from
sdma_handle_channel_loop(), otherwise channel status will be updated
incorrecly.
This patch also adds lock to avoid race between terminate of channel,
and updaing
Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c
In case the corresponding channel has already been terminated,
then instead of go on updating channel status, driver should abort from
sdma_handle_channel_loop(), otherwise channel status will be updated
incorrecly.
This patch also adds lock to avoid race between terminate of channel,
and updaing
Previously when channel0 timeouts to finish its task,
sdma_run_channel0() just returns without disable channel0,
this will cause continuous interrupt later when channel0
finishs its task and set channel0 interrupt bit.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c | 43
When SDMA channel0 timeouts, even it's disabled in error path,
but sometimes we still see its interrupt bit be asserted,
which causes irq routine be triggered continuously because
no one else clears this bit.
This commit clears channel0 interrupt as well in irq routine,
so that even channel0
When SDMA channel0 timeouts, even it's disabled in error path,
but sometimes we still see its interrupt bit be asserted,
which causes irq routine be triggered continuously because
no one else clears this bit.
This commit clears channel0 interrupt as well in irq routine,
so that even channel0
Implement the new device_synchronize() callback to allow proper
synchronization when stopping a channel. Since the driver already makes
sure that no new complete callbacks are scheduled after the
device_terminate_all() has been called, all left to do in the
device_synchronize() callback is to wait
Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
Implement the new device_synchronize() callback to allow proper
synchronization when stopping a channel. Since the driver already makes
sure that no new complete callbacks are scheduled after the
device_terminate_all() has been called, all left to do in the
device_synchronize() callback is to wait
Implement device_terminate_all(), so that dmaengine_terminate_async()
can work.
Signed-off-by: Jiada Wang
---
drivers/dma/imx-sdma.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index ef5d37c..040cbf2 100644
---
this patch set contains the following changes
1. fix issues in cyclic dma
2. add support to SYNC DMA termination
3. avoid system hang, when SDMA channel 0 timeouts
4. add lock to prevent race condition
Jiada Wang (10):
dma: imx-sdma: use chn_real_count to report residue for UART
dma:
Implement the new device_synchronize() callback to allow proper
synchronization when stopping a channel. Since the driver already makes
sure that no new complete callbacks are scheduled after the
device_terminate_all() has been called, all left to do in the
device_synchronize() callback is to wait
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