No functional change, just prepare for the next patch.
Signed-off-by: Zhen Lei
---
drivers/iommu/arm-smmu-v3.c | 44 ++--
1 file changed, 22 insertions(+), 22 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index
Invalidate the caching of the intermediate L1ST descriptor after it has
been updated.
Signed-off-by: Zhen Lei
---
drivers/iommu/arm-smmu-v3.c | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git a/drivers/iommu/arm-smmu-v3.c b/drivers/iommu/arm-smmu-v3.c
index
This patch series include two parts:
1. Patch1-2 use dummy STE tables with "ste abort" hardware feature to abort
unexpected
devices accessing. For more details, see the description in patch 2.
2. If the "ste abort" feature is not support, force the unexpected devices in
the
secondary
To reduce the risk of further crash, the device_shutdown() was not called
by the first kernel. That means some devices may still working in the
secondary kernel. For example, a netcard may still using ring buffer to
receive the broadcast messages in the kdump kernel. No events are reported
utill
The (STRTAB_L1_DESC_DWORDS << 3) appears more than 1 times, replace it
with STRTAB_L1_DESC_SIZE to eliminate the duplication. And the latter
seems more clear when it's used to calculate memory size. And the same is
true for STRTAB_STE_DWORDS and CTXDESC_CD_DWORDS.
Signed-off-by: Zhen Lei
---
Some boards may not implement the STE.config=0b000 correctly, it also
reports event C_BAD_STE when a transaction incoming. To make kdump kernel
can be worked well in this situation, backup the strtab_base which is used
in the first kernel, to make the unexpected devices can reuse the old
mapping
On 19/02/2019 04:20, Michael Ellerman wrote:
Hi Michael,
> Mark Cave-Ayland writes:
>> On 08/02/2019 14:45, Christophe Leroy wrote:
>>
>>> Le 08/02/2019 à 15:33, Mark Cave-Ayland a écrit :
Commit 8792468da5e1 "powerpc: Add the ability to save FPU without giving
it up"
>>>
>>>
Hi all,
topic/mei-hdcp-2019-02-19:
Prep patches + headers for the mei-hdcp/i915 component interfaces
Also contains the prep work in the component helpers plus adjustements
for the snd-hda/i915 component interface.
Plus one small static inline in the drm_hdcp.h header that both i915
and mei_hdcp
On 19.02.19 01:01, Alexander Duyck wrote:
> On Mon, Feb 18, 2019 at 1:04 PM David Hildenbrand wrote:
>>
>> On 18.02.19 21:40, Nitesh Narayan Lal wrote:
>>> On 2/18/19 3:31 PM, Michael S. Tsirkin wrote:
On Mon, Feb 18, 2019 at 09:04:57PM +0100, David Hildenbrand wrote:
>> So I'm fine
Sorry for resurrecting an old discussion, but since someone posted patches
for H5 and H6, I thought we should resolve this. I'm working on patches to
fix / replace the big-endian issue.
On Thu, Sep 6, 2018 at 7:51 PM Maxime Ripard wrote:
>
> On Thu, Sep 06, 2018 at 01:47:47PM +0200, Philipp
EFI systems may not provide legacy ROM. The memory may not be mapped
at all.
Trying to dereference values in legacy ROM leads to crash on Macbook
Pro.
Only look for values in the legacy ROM for non-EFI system.
Signed-off-by: Kirill A. Shutemov
Bugzilla:
This patch registers 3 VFIO device state regiones of type
VFIO_REGION_TYPE_DEVICE_STATE, and subtype
VFIO_REGION_SUBTYPE_DEVICE_STATE_CTL,
VFIO_REGION_SUBTYPE_DEVICE_STATE_DATA_CONFIG,
VFIO_REGION_SUBTYPE_DEVICE_STATE_DATA_DIRTYBITMAP.
userspace VFIO will check the existence of those regions to
+Sergei and Mason who recently worked on an HyperFlash controller.
On Tue, 19 Feb 2019 12:06:02 +0530
Vignesh R wrote:
> Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
> interface between a host system master and one or more slave interfaces.
> HyperBus is used to
The patch implments the gvt interface intel_gvt_save_restore to
save/restore vGPU's device config data for live migration.
vGPU device config data includes vreg, vggtt, vcfg space, workloads, ppgtt,
execlist.
It does not include dirty pages in system memory produced by vGPU.
Signed-off-by: Yulei
From: Yulei Zhang
Adjust the buffer start gma in dmabuf for display in host domain.
Signed-off-by: Yulei Zhang
---
drivers/gpu/drm/i915/gvt/dmabuf.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpu/drm/i915/gvt/dmabuf.c
b/drivers/gpu/drm/i915/gvt/dmabuf.c
index
From: Yulei Zhang
As guest gm aperture region start offset is initialized when vGPU created,
in order to make sure that start offset is remain the same after migration,
align the aperture start offset to 0 for guest.
Signed-off-by: Yulei Zhang
Signed-off-by: Zhenyu Wang
---
From: Yulei Zhang
As after migration the host gm base address will be changed due
to resource re-allocation, in order to make sure the guest gm
address doesn't change with that to retrieve the guest gm base
address from PVINFO.
Signed-off-by: Yulei Zhang
Signed-off-by: Zhenyu Wang
---
From: Yulei Zhang
Apply the guest to host gma conversion while guest config the
fence mmio registers due to the host gma change after the migration.
Signed-off-by: Yulei Zhang
---
drivers/gpu/drm/i915/gvt/aperture_gm.c | 6 --
drivers/gpu/drm/i915/gvt/gvt.h | 14 ++
2
From: Yulei Zhang
Adjust the graphics memory address in gpu commands according to
the shift offset in guests' aperture and hidden gm address, and patch
the commands before submit to execute.
Signed-off-by: Yulei Zhang
---
drivers/gpu/drm/i915/gvt/cmd_parser.c | 31 ---
From: Yulei Zhang
Apply guest to host gma conversion while guest try to access the
GTT mmio registers, as after enable live migration the host gma
will be changed due to the resourece re-allocation, but guest
gma should be remaining unchanged, thus g2h conversion is request
for it.
This patchset provides GVT vGPU with device states control and
interfaces to get/set device data.
Desgin of device state control and interfaces to get/set device data
CODE STRUCTURES
---
/* Device State region type
On Tue, Feb 19, 2019 at 02:57:50PM +0800, YueHaibing wrote:
> The return from the call to fwnode_property_read_u16_array is int,
> it can be a negative error code however this is being assigned to
> an size_t variable 'nval', hence the check is always false.
> Fix this by making 'nval' an int.
>
The __reserved_mem_init_node will call region specific reserved memory
init codes, but once all compatibled init codes failed, the memory region
will left in memory.reserved and cause leakage.
Take cma reserve memory DTS for example, if user declare 1MB size,
which is not align to (PAGE_SIZE <<
On Fri, Feb 15, 2019 at 2:07 PM Erin Lo wrote:
> Subject: [PATCH v7 5/6] arm64: dts: mt8183: add pintcrl file
minor spelling mistake in the commit title: pinctrl
>
> This patch adds pinctrl file for mt8183.
>
> Signed-off-by: Zhiyong Tao
> Signed-off-by: Erin Lo
> ---
Hi Stephen, Arnd,
> After merging the asm-generic tree, today's linux-next build (powerpc
> allnoconfig) failed like this:
> ...
> Caused by commit
>
> 8e074c243ed3 ("iomap: add missing const to ioread*/iowrite addr arg")
I have prepared a patch addressing this issue, and am currently
On 2/15/19 8:49 PM, Pavel Machek wrote:
On Fri 2019-02-15 13:50:10, Stefan Mavrodiev wrote:
Teres-I and A64-OLinuXino commes with populated LED connected
to AXP803. So to be used as battery indication, pass the LED control
to the charger itself in mode 0 ( FULL while charging, OFF no battery
On 2/15/19 8:32 PM, Pavel Machek wrote:
Hi!
On Fri, Feb 15, 2019 at 01:50:06PM +0200, Stefan Mavrodiev wrote:
+static ssize_t control_store(struct device *dev, struct device_attribute *attr,
+const char *buf, size_t size)
+{
+ struct led_classdev *cdev =
Hello Claudiu,
On Mon, Jan 21, 2019 at 12:30:53PM +, claudiu.bez...@microchip.com wrote:
> From: Claudiu Beznea
>
> New SAM9X60's PWM controller use 32 bits counters thus it could generate
> signals with higher period and duty cycles. Update the current driver
> to work with old controller
Hi,
On 2019/02/19 4:53, Rob Herring wrote:
On Fri, 8 Feb 2019 21:26:30 +0900, Sugaya Taichi wrote:
Add DT bindings document for Milbeaut M10V timer.
Signed-off-by: Sugaya Taichi
---
.../bindings/timer/socionext,milbeaut-timer.txt | 17 +
1 file changed, 17
On 02/18/2019 11:29 PM, Zi Yan wrote:
> On 18 Feb 2019, at 9:52, Matthew Wilcox wrote:
>
>> On Mon, Feb 18, 2019 at 09:51:33AM -0800, Zi Yan wrote:
>>> On 18 Feb 2019, at 9:42, Vlastimil Babka wrote:
On 2/18/19 6:31 PM, Zi Yan wrote:
> The purpose of proposing exchange_pages() is to
Hi,
On 2019/02/19 4:52, Rob Herring wrote:
On Fri, Feb 08, 2019 at 09:26:04PM +0900, Sugaya Taichi wrote:
This adds a DT binding documentation for the M10V and its evaluation
board.
Most boards/soc bindings are using DT schema (yaml) now. We're not
requiring that just yet, but I'd like to
Hi,
On 2019/02/19 4:49, Rob Herring wrote:
On Fri, 8 Feb 2019 21:25:33 +0900, Sugaya Taichi wrote:
The Milbeaut M10V SoC needs a part of sram for smp, so this adds the
M10V sram compatible and binding.
Signed-off-by: Sugaya Taichi
---
.../devicetree/bindings/sram/milbeaut-smp-sram.txt |
Hi,
Thank you for your comments.
On 2019/02/18 21:20, Arnd Bergmann wrote:
On Fri, Feb 8, 2019 at 1:24 PM Sugaya Taichi
wrote:
Hi,
Here is the series of patches the initial support for SC2000(M10V) of
Milbeaut SoCs. "M10V" is the internal name of SC2000, so commonly used in
source code.
On Wed, Feb 13, 2019 at 04:05:08PM +0100, Mathieu Othacehe wrote:
> Add support for hi3559v100-shub-pwm and hisilicon,hi3559v100-pwm
> platforms. They require a special quirk: pwm has to be enabled again
> to force duty_cycle refresh.
>
> Signed-off-by: Mathieu Othacehe
> ---
>
From: Min Guo
Add musb nodes and usb2 phy nodes for MT2701
Signed-off-by: Min Guo
---
changes in v5:
1. Add usb connector child node
changes in v4:
1. no changes
changes in v3:
1. no changes
changes in v2:
1. Remove phy-names
---
arch/arm/boot/dts/mt2701-evb.dts | 26
From: Min Guo
Add get/set toggle hooks in struct musb_io and struct musb_platform_ops
for special platform; remove function musb_save_toggle, use the set/get
callback to handle toggle.
Signed-off-by: Min Guo
---
changes in v5:
1. no changes
new patch based on v4:
---
From: Min Guo
Delete the const attribute of addr parameter in readb/w/l hooks, these
changes are for implementing clearing W1C registers.
Replace musb_readb/w with musb_clearb/w to clear the interrupt status.
Signed-off-by: Min Guo
---
changes in v5:
1. Replace musb_readb() with musb_clearb()
From: Min Guo
Add noirq type of dma create interface for platform which do not
have dedicated DMA interrupt line, move musbhsdma macro definition
to musb_dma.h
Signed-off-by: Min Guo
---
changes in v5:
1. no changes
new patch based on v4:
---
drivers/usb/musb/musb_dma.h | 9
From: Min Guo
This adds support for MediaTek musb controller in
host, peripheral and otg mode.
There are some quirk of MediaTek musb controller, such as:
-W1C interrupt status registers
-Private data toggle registers
-No dedicated DMA interrupt line
Signed-off-by: Min Guo
Signed-off-by:
From: Min Guo
These patches introduce the MediaTek MUSB controller driver.
The driver can be configured as Dual-Role Device (DRD),
Peripheral Only and Host Only modes. This has beed tested on
MT2701 with a variety of devices in host mode and with the
f_mass gadget driver in peripheral mode,
From: Min Guo
This adds support for MediaTek musb controller in
host, peripheral and otg mode.
Signed-off-by: Min Guo
---
changes in v5:
suggested by Rob:
1. Modify compatible as
- compatible : should be one of:
"mediatek,mt-2701"
...
followed by
From: Lanqing Liu
This patch adds dmas and dma-names properties for the UART DMA mode.
Signed-off-by: Lanqing Liu
Signed-off-by: Baolin Wang
---
.../devicetree/bindings/serial/sprd-uart.txt |6 ++
1 file changed, 6 insertions(+)
diff --git
From: Lanqing Liu
This patch adds power management for the Spreadtrum serial controller.
Signed-off-by: Lanqing Liu
Signed-off-by: Baolin Wang
---
drivers/tty/serial/sprd_serial.c | 61 +++---
1 file changed, 57 insertions(+), 4 deletions(-)
diff --git
From: Lanqing Liu
Add DMA mode support for the Spreadtrum serial controller.
Signed-off-by: Lanqing Liu
Signed-off-by: Baolin Wang
---
drivers/tty/serial/sprd_serial.c | 440 --
1 file changed, 426 insertions(+), 14 deletions(-)
diff --git
From: Lanqing Liu
This patch adds clocks and clocks-names properties, which are used to do
power management for our UART driver.
Signed-off-by: Lanqing Liu
Signed-off-by: Baolin Wang
---
.../devicetree/bindings/serial/sprd-uart.txt | 11 +--
1 file changed, 9 insertions(+), 2
This patch set fixes the baud rate calculation formula issue, as well as
adding power management support and DMA mode support for the Spreadtrum
serial controller.
Lanqing Liu (5):
serial: sprd: Modify the baud rate calculation formula
dt-bindings: serial: sprd: Add clocks and clocks-names
From: Lanqing Liu
When the source clock is not divisible by the expected baud rate and
the remainder is not less than half of the expected baud rate, the old
formular will round up the frequency division coefficient. This will
make the actual baud rate less than the expected value and can not
On Mon, Feb 18, 2019 at 02:36:58PM -0600, Rob Herring wrote:
> On Fri, Jan 18, 2019 at 09:44:49AM +0100, Matthias Brugger wrote:
> >
> >
> > On 18/01/2019 04:24, Ryder Lee wrote:
> > > This adds a property "mediatek,num-pwms" in example so that we could
> > > set the number of PWM channels via
If we remove the scsi disk when running io with fio, oops occured with
the following condition.
[scsi_eh_0] [fio]
scsi_end_request
->blk_update_request
->end_bio(io returned to userspace)
close
calc_tpm2_event_size return size of the event which type is
size_t, If it is an invalid event, returns 0. And all the
caller use a size_t variable to check the return value, so
no need to convert to the return value type to int.
Signed-off-by: YueHaibing
---
drivers/char/tpm/eventlog/tpm2.c | 4
There is no need to create the inner domain as a parent for MSI domian,
some feature has been implemented by MSI framework.
Remove the inner domain and its irq chip, it will be more closer to the
hardware implementation.
Signed-off-by: Jianjun Wang
---
drivers/pci/controller/pcie-mediatek.c |
On 19/02/19 12:06 PM, Vignesh R wrote:
[...]
>
> Tested on modified TI AM654 EVM with Cypress Hyperflash S26KS512 by
> creating a UBIFS partition and writing and reading files to it.
> Stress tested by writing/reading 16MB flash repeatedly at different
> offsets using dd commmand.
>
Here is
When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will turn on immediately on related Root Hub
ports. Then the VBUS will be de-asserted for a little while during xhci
reset (conducted by xhci driver) for a little while and back to normal.
This VBUS
On Tue, 19 Feb 2019, Al Viro wrote:
> On Mon, Feb 18, 2019 at 09:37:52PM -0800, Hugh Dickins wrote:
> > From: "Darrick J. Wong"
> >
> > tmpfs has a peculiarity of accounting hard links as if they were separate
> > inodes: so that when the number of inodes is limited, as it is by default,
> > a
When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
(or its control signal) will be turned on immediately on related Root Hub
ports. Then, the VBUS is turned off for a little while(15us) when do xhci
reset (conducted by xhci driver) and back to normal finally, we can
observe a
Ping...
Best Regards!
Anson Huang
> -Original Message-
> From: Anson Huang
> Sent: 2019年2月13日 13:36
> To: robh...@kernel.org; mark.rutl...@arm.com; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; feste...@gmail.com;
> catalin.mari...@arm.com; will.dea...@arm.com;
> @@ -1826,7 +1830,9 @@ _random_read(int nonblock, char __user *buf, size_t
> nbytes)
>
> nbytes = min_t(size_t, nbytes, SEC_XFER_SIZE);
> while (1) {
> - n = extract_entropy_user(_pool, buf, nbytes);
> + n = input_pool.initialized
> +
Hi,
Thank you for your comments.
On 2019/02/18 21:15, Arnd Bergmann wrote:
On Fri, Feb 8, 2019 at 1:26 PM Sugaya Taichi
wrote:
+static int m10v_pm_enter(suspend_state_t state)
+{
+ switch (state) {
+ case PM_SUSPEND_STANDBY:
+ pr_err("STANDBY\n");
+
On Tue, 19 Feb 2019, wen.yan...@zte.com.cn wrote:
> > > I would have a hard time saying which one is more reasonable to test,
> > I suggest to reconsider the interpretation of this software situation once
> > more.
> > > since both are extremely unlikely.
> > I disagree to this view because
The return from the call to tee_client_invoke_func can be a
negative error code however this is being assigned to an
unsigned variable 'ret' hence the check is always false.
Fix this by making 'ret' an int.
Detected by Coccinelle ("Unsigned expression compared with zero:
ret < 0")
Fixes:
On Tue, Feb 19, 2019 at 12:46:08AM +0100, Andrew Lunn wrote:
> On Mon, Feb 18, 2019 at 07:21:59PM +0100, Michal Kubecek wrote:
> > Three types of netlink notifications are introduced:
> >
> > - ETHA_EVENT_NEWDEV to notify about newly registered network devices
> > - ETHA_EVENT_DELDEV to
On Wed, 2019-01-23 at 15:40 +, Lorenzo Pieralisi wrote:
> On Mon, Dec 24, 2018 at 07:40:28PM +0800, Jianjun Wang wrote:
> > On Thu, 2018-12-20 at 12:20 -0600, Bjorn Helgaas wrote:
> > > On Tue, Dec 18, 2018 at 05:19:24PM +0800, Jianjun Wang wrote:
> > > > On Mon, 2018-12-17 at 15:46 +,
The return from the call to fwnode_property_read_u16_array is int,
it can be a negative error code however this is being assigned to
an size_t variable 'nval', hence the check is always false.
Fix this by making 'nval' an int.
Detected by Coccinelle ("Unsigned expression compared with
zero: nval
-Original Message-
From: Lorenzo Pieralisi
Sent: 2019年2月6日 2:03
To: Xiaowei Bao
Cc: bhelg...@google.com; robh...@kernel.org; mark.rutl...@arm.com;
shawn...@kernel.org; Leo Li ; kis...@ti.com; a...@arndb.de;
gre...@linuxfoundation.org; M.h. Lian ; Mingkai Hu
; Roy Zang ;
On 2/13/2019 4:49 PM, Philipp Puschmann wrote:
> When quality is set to 0 this driver is not used as randomness source by
> HWRNG framework at all. So set the quality and finally make this driver
> work. The value of the quality was discussed before
> ( see see
On Tue, 19 Feb 2019 at 12:04, YueHaibing wrote:
>
> The return from the call to tee_client_invoke_func can be a
> negative error code however this is being assigned to an
> unsigned variable 'ret' hence the check is always false.
> Fix this by making 'ret' an int.
>
> Detected by Coccinelle
When fail, translate_desc() returns negative value, otherwise the
number of iovs. So we should fail when the return value is negative
instead of a blindly check against zero.
Detected by CoverityScan, CID# 1442593: Control flow issues (DEADCODE)
Fixes: cc5e71075947 ("vhost: log dirty page
On 2019/2/16 上午12:45, Stephen Hemminger wrote:
On Fri, 15 Feb 2019 15:53:24 +0800
Jason Wang wrote:
When fail, translate_desc() returns negative value, otherwise the
number of iovs. So we should fail when the return value is negative
instead of a blindly check against zero.
Reported-by:
On 2019/2/16 上午2:03, David Miller wrote:
From: Jason Wang
Date: Fri, 15 Feb 2019 15:53:24 +0800
When fail, translate_desc() returns negative value, otherwise the
number of iovs. So we should fail when the return value is negative
instead of a blindly check against zero.
Reported-by: Stephen
On Tue 05 Feb 06:58 PST 2019, Ulf Hansson wrote:
> On Thu, 31 Jan 2019 at 03:01, Bjorn Andersson
> wrote:
> >
> > On the Qualcomm SDM845 platform the apb_pclk is controlled as part of
> > the QDSS power/clock domain. Handle this by allowing amba to operate
> > without direct apb_pclk control,
On Mon 2019-02-18 17:22, Petr wrote:
> On Mon 2019-02-18 13:29:11, chengjian (D) wrote:
> > Hi，Jiri
> >
> >
> > This patch should be merged into 4.4 stable,
> >
> > which still use klp_write_module_reloc.
> >
> >
> > https://elixir.bootlin.com/linux/v4.4.174/source/arch/x86/kernel/livep
> >
On 2019/1/29 1:43, Anton Kuchin wrote:
Win10 attempts to save these registers during KiSaveDebugRegisterState
if LBR or BTF bits are set in MSR_IA32_DEBUGCTLMSR. It uses DR7 GE and LE
flags for per-thread switching of these these features so zero value that
is returned for MSR_IA32_DEBUGCTLMSR
Hi Arnd,
After merging the asm-generic tree, today's linux-next build (powerpc
allnoconfig) failed like this:
arch/powerpc/kernel/iomap.c:18:14: error: conflicting types for 'ioread8'
unsigned int ioread8(void __iomem *addr)
^~~
In file included from
HyperFlash devices are compliant with CFI AMD/Fujitsu Extended Command
Set(0x0002) for flash operations, therefore drivers/mtd/chips/cfi_cmdset_0002.c
can be use as is. But these devices do not support DQ polling method of
determining chip ready/good status. These flashes provide Status
Register
Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
interface between a host system master and one or more slave interfaces.
HyperBus is used to connect microprocessor, microcontroller, or ASIC
devices with random access NOR flash memory(called HyperFlash) or
self refresh
There are some complaints about bad commit description in 'Fixes' tag.
Most cases are SHA1 should be at least 12 digits long. Let's extend
the existing check in checkpatch.pl to include commit description of
'Fixes' tag.
Reference: https://lkml.org/lkml/2019/2/18/1477
Signed-off-by: Changbin Du
Cypress HyperBus is Low Signal Count, High Performance Double Data Rate Bus
interface between a host system master and one or more slave interfaces.
HyperBus is used to connect microprocessor, microcontroller, or ASIC
devices with random access NOR flash memory(called HyperFlash) or
self refresh
Add driver for Hyperbus memory controller on TI's AM654 SoC. Programming
IP is pretty simple and provides direct memory mapped access to
connected Flash devices.
Add basic support for the IP without DMA. Second ChipSelect is not
supported for now.
Signed-off-by: Vignesh R
---
Add binding documentation for TI's Hyperbus memory controller present on
AM654 SoC.
Signed-off-by: Vignesh R
---
.../devicetree/bindings/mtd/ti,am654-hbmc.txt | 27 +++
MAINTAINERS | 1 +
2 files changed, 28 insertions(+)
create mode 100644
Add DT binding documentation for Hyperbus memory devices. For now only
Hyperflash is supported.
Signed-off-by: Vignesh R
---
Documentation/devicetree/bindings/mtd/cypress,hyperbus.txt | 6 ++
1 file changed, 6 insertions(+)
create mode 100644
The return from the call to tee_client_invoke_func can be a
negative error code however this is being assigned to an
unsigned variable 'ret' hence the check is always false.
Fix this by making 'ret' an int.
Detected by Coccinelle ("Unsigned expression compared with zero:
ret < 0")
Fixes:
On 19/2/2019 4:33 AM, Rob Herring wrote:
> On Tue, Dec 18, 2018 at 03:34:36PM +0800, Wei Ni wrote:
>> Add "nvidia,gpu-throt-level" property to set gpu hw
>> throttle level.
>>
>> Signed-off-by: Wei Ni
>> ---
>> .../bindings/thermal/nvidia,tegra124-soctherm.txt | 17 +++--
>>
PMS405 L3 is outside the acceptable range, causing PCIe to fail. Fix
this.
Fixes: 0b363f5b871c ("arm64: dts: qcom: qcs404: Add PMS405 RPM regulators")
Signed-off-by: Bjorn Andersson
---
Changes since v1:
- Rebased upon
On 19/2/2019 4:32 AM, Rob Herring wrote:
> On Tue, Dec 18, 2018 at 03:34:43PM +0800, Wei Ni wrote:
>> Add OC HW throttle configuration for soctherm in DT.
>> It is used to describe the OCx throttle events.
>>
>> Signed-off-by: Wei Ni
>> ---
>> .../bindings/thermal/nvidia,tegra124-soctherm.txt
On 13. 02. 19, 19:38, Greg Kroah-Hartman wrote:
> 4.20-stable review patch. If anyone has any objections, please let me know.
>
> --
>
> From: Eric W. Biederman
>
> commit 35634ffa1751b6efd8cf75010b509dcb0263e29b upstream.
>
> Recently syzkaller was able to create unkillablle
From: Guo Ren
This fixup is continue to commit 35ff802af1c4 (csky: fixup remove
vdsp implement for kernel.) and in that patch I didn't finish the
job. We must forbid gcc to generate any vdsp & fpu instructions
and remove vdsp asm in memmove.S.
eg: For GCC it's -mcpu=ck860 and For AS it's
uprobe_profile has filename and number of probe hits information for
each uprobe event. The documentation erroneously talks about probe
mis-hits. Update the documentation to the correct information.
Cc: Masami Hiramatsu
Cc: Steven Rostedt
Reported-by: KAUSTUBH RAJENDRA WELANKAR
Signed-off-by:
On Tue, 19 Feb 2019, 陈华才 wrote:
>
> I've tested, this patch can fix the nvme problem, but it can't be applied
> to 4.19 because of different context. And, I still think my original solution
> (genirq/affinity: Assign default affinity to pre/post vectors) is correct.
> There may be similar
+ Matthew Wilcox
On 02/19/2019 11:02 AM, Yu Zhao wrote:
> On Tue, Feb 19, 2019 at 09:51:01AM +0530, Anshuman Khandual wrote:
>>
>>
>> On 02/19/2019 04:43 AM, Yu Zhao wrote:
>>> For pte page, use pgtable_page_ctor(); for pmd page, use
>>> pgtable_pmd_page_ctor() if not folded; and for the rest
On 19/2/2019 4:29 AM, Rob Herring wrote:
> On Tue, Dec 18, 2018 at 03:34:36PM +0800, Wei Ni wrote:
>> Add "nvidia,gpu-throt-level" property to set gpu hw
>> throttle level.
>>
>> Signed-off-by: Wei Ni
>> ---
>> .../bindings/thermal/nvidia,tegra124-soctherm.txt | 17 +++--
>>
> /proc/kheaders.txz
This is gross.
> The feature is also buildable as a module just in case the user desires
> it not being part of the kernel image. This makes it possible to load
> and unload the headers on demand. A tracing program, or a kernel module
> builder can load the module, do its
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.
Reviewed-by: Niklas Cassel
Acked-by: Stephen Boyd
Signed-off-by: Bjorn Andersson
---
drivers/clk/qcom/gcc-qcs404.c | 7 +++
include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++
2 files
The Qualcomm PCIe2 PHY is based on design from Synopsys and found in
several different platforms where the QMP PHY isn't used.
Reviewed-by: Niklas Cassel
Signed-off-by: Bjorn Andersson
---
drivers/phy/qualcomm/Kconfig | 8 +
drivers/phy/qualcomm/Makefile | 1 +
The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of
Qualcomm platforms, add a binding to describe this.
Signed-off-by: Bjorn Andersson
---
.../bindings/phy/qcom-pcie2-phy.txt | 40 +++
1 file changed, 40 insertions(+)
create mode 100644
Before introducing the QCS404 platform, which uses the same PCIe
controller as IPQ4019, migrate this to use the bulk clock API, in order
to make the error paths slighly cleaner.
Reviewed-by: Niklas Cassel
Signed-off-by: Bjorn Andersson
---
drivers/pci/controller/dwc/pcie-qcom.c | 48
The QCS404 has a PCIe2 PHY and a Qualcomm PCIe controller, add these to
the platform dtsi and enable them for the EVB with the perst gpio
and analog supplies defined.
Reviewed-by: Niklas Cassel
Signed-off-by: Bjorn Andersson
---
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi | 25 +
This series adds support for the PCIe controller and PHY found in the Qualcomm
platform QCS404.
Bjorn Andersson (7):
clk: gcc-qcs404: Add PCIe resets
dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY
phy: qcom: Add Qualcomm PCIe2 PHY driver
PCI: qcom: Use clk_bulk API for 2.4.0
The Qualcomm QCS404 platform contains a PCIe controller, add this to the
Qualcomm PCI binding document. The controller is the same version as the
one used in IPQ4019, but the PHY part is described separately, hence the
difference in clocks and resets.
Signed-off-by: Bjorn Andersson
---
The QCS404 platform contains a PCIe controller of version 2.4.0 and a
Qualcomm PCIe2 PHY. The driver already supports version 2.4.0, for the
IPQ4019, but this support touches clocks and resets related to the PHY
as well, and there's no upstream driver for the PHY.
On QCS404 we must initialize the
> On Feb 17, 2019, at 3:05 PM, Jiri Olsa wrote:
>
> On Fri, Feb 15, 2019 at 01:53:48PM -0800, Song Liu wrote:
>
> SNIP
>
>> info_linear = bpf_program__get_prog_info_linear(fd, arrays);
>> if (IS_ERR_OR_NULL(info_linear)) {
>> @@ -151,8 +165,8 @@ static int
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