This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
Signed-off-by: Alison Wang
---
Changes in v3:
- Sort EDMA node in unit-address.
Changes in v2:
- Modify some nodes' names.
- Use GIC_SPI and IRQ_TYPE_LEVEL_HIGH.
arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dts | 62
On 28.02.2019 17:55, Halil Pasic wrote:
> On Thu, 28 Feb 2019 09:48:39 +0100
> Pierre Morel wrote:
>
>> On 28/02/2019 09:23, Christian Borntraeger wrote:
>>> On 22.02.2019 16:29, Pierre Morel wrote:
To be able to use the VFIO interface to facilitate the
mediated device memory
On 01/03/2019 04.36, Qiang Zhao wrote:
> On 2019年2月28日 18:31，Rasmus Villemoes wrote:
>
>> -Original Message-
>> From: Rasmus Villemoes
>> Sent: 2019年2月28日 18:31
>> To: Qiang Zhao ; Leo Li
>> Cc: Scott Wood ; linux-kernel@vger.kernel.org; Timur Tabi
>> ; Rasmus Villemoes
>> Subject:
On 2019/3/1 15:29, Naoya Horiguchi wrote:
> On Tue, Feb 26, 2019 at 10:34:32PM +0800, zhong jiang wrote:
>> On 2019/2/26 21:51, Kirill A. Shutemov wrote:
>>> On Tue, Feb 26, 2019 at 07:18:00PM +0800, zhong jiang wrote:
From: zhongjiang
When soft_offline_in_use_page() runs on a thp
On Fri, Mar 01, 2019 at 06:56:14AM +, Ardelean, Alexandru wrote:
> On Thu, 2019-02-28 at 11:23 -0300, Renato Lui Geh wrote:
> >
> >
> > Previously, the AD7780 driver only supported gpio for the 'powerdown'
> > pin. This commit adds suppport for the 'gain' and 'filter' pin.
> >
> >
On Thu, 2019-02-28 at 11:25 -0300, Renato Lui Geh wrote:
>
>
> To maintain consistency between ad7780_probe and ad7780_remove orders,
> regulator initialization has been moved to after GPIO initializations.
>
> Signed-off-by: Renato Lui Geh
> ---
> drivers/staging/iio/adc/ad7780.c | 26
If we want to know the zone type, we have to check whether
CONFIG_ZONE_DMA, CONFIG_ZONE_DMA32 and CONFIG_HIGHMEM are set or not,
that's not so convenient.
We'd better show the zone type directly.
Signed-off-by: Yafang Shao
---
include/trace/events/vmscan.h | 9 ++---
1 file changed, 6
As Paul Bandha reported in bugzilla:
https://bugzilla.kernel.org/show_bug.cgi?id=202709
When I run the poc on the mounted f2fs img I get a buffer overflow in
read_inline_xattr due to there being no sanity check on the value of
i_inline_xattr_size.
I created the img by just modifying the value
> On Wed, Feb 20, 2019 at 04:44:57PM +0800, Alison Wang wrote:
> > This patch adds Audio DT nodes for LS1028ARDB and LS1028AQDS boards.
> >
> > Signed-off-by: Alison Wang
> > ---
> > Changes in v2:
> > - Modify some nodes' names.
> > - Use GIC_SPI and IRQ_TYPE_LEVEL_HIGH.
> >
> >
Hi Wanglai,
On Thu, Feb 28, 2019 at 02:33:23PM +0800, Wanglai Shi wrote:
> This patch adds devicetree entries for the CoreSight trace
> components on hi3660.
>
> Signed-off-by: Wanglai Shi
> ---
> .../arm64/boot/dts/hisilicon/hi3660-coresight.dtsi | 429
> +
>
On Tue, Feb 26, 2019 at 10:34:32PM +0800, zhong jiang wrote:
> On 2019/2/26 21:51, Kirill A. Shutemov wrote:
> > On Tue, Feb 26, 2019 at 07:18:00PM +0800, zhong jiang wrote:
> >> From: zhongjiang
> >>
> >> When soft_offline_in_use_page() runs on a thp tail page after pmd is plit,
> >
On Wed, 2019-02-27 at 18:31 +0300, Dmitry V. Levin wrote:
> syscall_get_arch() is required to be implemented on all architectures
> in addition to already implemented syscall_get_nr(),
> syscall_get_arguments(), syscall_get_error(), and
> syscall_get_return_value() functions in order to extend the
On Fri, Mar 01, 2019 at 09:36:11AM +0530, Rushikesh S Kadam wrote:
> Integrated Sensor Hub (ISH) is also a MCU running EC
> having feature bit EC_FEATURE_ISH. Instantiate it as
> a special CrOS EC device with device name 'cros_ish'.
> v2
> - Addressed review comments to term the CrOS EC device as
Use rgmii-id phy mode for the CPU port (MAC0) of the QCA8334 switch
to add delays to both Tx and Rx clock.
It worked with the rgmii mode before because the qca8k driver
(incorrectly) enabled delays in that mode and rgmii-id was not
implemented at all.
Commit 5ecdd77c61c8 ("net: dsa: qca8k:
Hi Faiz,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on ulf.hansson-mmc/next]
[also build test ERROR on v5.0-rc8 next-20190228]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system]
url:
https://github.com/0day-ci
On Thu, Feb 28, 2019 at 11:37:52PM -0600, Parav Pandit wrote:
> Add a subdev driver to probe the subdev devices and create fake
> netdevice for it.
So I'm guessing here is the "meat" of the whole goal here?
You just want multiple netdevices per PCI device? Why can't you do that
today in your
On Thu, 2019-02-28 at 11:24 -0300, Renato Lui Geh wrote:
>
>
> The ad7780 supports both the ad778x and ad717x families. Each chip has
> a corresponding ID. This patch provides a mask for extracting ID values
> from the status bits and also macros for the correct values for the
> ad7170, ad7171,
On Thu, Feb 28, 2019 at 11:37:51PM -0600, Parav Pandit wrote:
> --- /dev/null
> +++ b/drivers/net/ethernet/mellanox/mlx5/core/subdev.c
> @@ -0,0 +1,55 @@
> +// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
For new stuff, just use GPL-2.0, no need to keep the mistake of the
Linux-OpenIB license
On Thu, 2019-02-28 at 11:24 -0300, Renato Lui Geh wrote:
>
>
> The AD7780 driver contains status pattern bits designed for checking
> whether serial transfers have been correctly performed. Pattern macros
> were previously generated through bit fields. This patch sets good
> pattern values
On Thu, Feb 28, 2019 at 11:37:45PM -0600, Parav Pandit wrote:
> Introduce a new subdev bus which holds sub devices created from a
> primary device. These devices are named as 'subdev'.
> A subdev is identified similarly to pci device using 16-bit vendor id
> and device id.
> Unlike PCI devices,
> -Original Message-
> From: Kacper Kołodziej [mailto:kac...@kolodziej.it]
> Sent: Tuesday, February 05, 2019 9:38 PM
> To: Yamada, Masahiro/山田 真弘 ;
> michal.l...@markovi.net
> Cc: linux-kbu...@vger.kernel.org; linux-kernel@vger.kernel.org;
> kac...@kolodziej.it
> Subject: [PATCH]
Now that the Kconfig is the only user of this script, we can drop
unneeded code.
Remove the -p option, and stop prepending the output with zero,
so that Kconfig can directly use the output from this script.
Signed-off-by: Masahiro Yamada
---
init/Kconfig| 2 +-
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
Display the mitigation status if active, otherwise
assume the cpu is safe unless it doesn't have CSV3
and isn't in our whitelist.
Signed-off-by: Jeremy Linton
---
arch/arm64/kernel/cpufeature.c | 47 ++
1 file
There is no more direct user of this macro; it is only used by
cc-ifversion.
Calling this macro is not efficient since it invokes the compiler to
get the compiler version. CONFIG_GCC_VERSION is already calculated in
the Kconfig stage, so Makefile can reuse it.
Here is a note about the slight
Commit 469cb7376c06 ("kconfig: add CC_IS_CLANG and CLANG_VERSION")
changed the code, but missed to update the comment block.
The -p option was gone, and the output is 5-digit (or 6-digit when
Clang 10 is released).
Update the comment now.
Signed-off-by: Masahiro Yamada
---
On 2/28/19 9:52 PM, Jiri Olsa wrote:
> how about attached change (untested)?
LGTM. Would you mind sending a patch.
>
> but I wonder there are some other hidden
> bugs wrt empty node
>
> jirka
>
>
> ---
> diff --git a/tools/perf/builtin-c2c.c b/tools/perf/builtin-c2c.c
> index
Hi,
On Sat, 23 Feb 2019 10:23:23 -0800
Tony Lindgren wrote:
> * Andreas Kemnade [190223 11:48]:
> > Since commit
> > 6e2bd956936 ("i2c: omap: Use noirq system sleep pm ops to idle device for
> > suspend")
> > on gta04 we have handle_twl4030_pih() called in situations where
> >
Remove the duplicate implementation of cpumask_to_vpset() and use the
shared implementation. Export hv_max_vp_index, which is required by
cpumask_to_vpset().
Signed-off-by: Maya Nakamura
Reviewed-by: Michael Kelley
Reviewed-by: Vitaly Kuznetsov
Tested-by: Vitaly Kuznetsov
---
Changes in v5:
Hi Joel,
On Thu, 28 Feb 2019 22:26:11 -0500
Joel Fernandes wrote:
> On Fri, Mar 01, 2019 at 11:28:26AM +0900, Masami Hiramatsu wrote:
> > Hi Joel,
>
> Hi Masami,
>
> > On Thu, 28 Feb 2019 10:00:54 -0500
> > Joel Fernandes wrote:
> >
> > > > Hmm, isn't it easier to add kernel-headers package
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
From: Mian Yousaf Kaukab
Enable CPU vulnerabilty show functions for spectre_v1, spectre_v2,
meltdown and store-bypass.
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Jeremy Linton
Reviewed-by: Andre Przywara
Thanks,
Andre.
---
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
Return status based on ssbd_state and the arm64 SSBS feature. If
the mitigation is disabled, or the firmware isn't responding then
return the expected machine state based on a new blacklist of known
vulnerable cores.
Signed-off-by: Jeremy Linton
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
The ssb detection logic is necessary regardless of whether
the vulnerability mitigation code is built into the kernel.
Break it out so that the CONFIG option only controls the
mitigation logic and not the vulnerability detection.
Signed-off-by:
On Thu, 2019-02-28 at 11:24 -0300, Renato Lui Geh wrote:
>
>
> This patch adds the new feature of reading the filter odr value for
> ad778x chips. This value is stored in the chip's state struct whenever a
> read or write call is performed on the chip's driver.
>
> This feature requires sharing
Remove a duplicate definition of VP set (hv_vp_set) and use the common
definition (hv_vpset) that is used in other places.
Change the order of the members in struct hv_pcibus_device so that the
declaration of retarget_msi_interrupt_params is the last member. Struct
hv_vpset, which contains a
In some places, the code prints a human-readable USB endpoint
transfer type (e.g. "bulk"). This involves a switch statement
sometimes wrapped around in ({ ... }) block leading to code
repetition.
To make this scenario easier, here introduces usb_ep_type_string()
function, which returns a
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
Add code to track whether all the cores in the machine are
vulnerable, and whether all the vulnerable cores have been
mitigated.
Once we have that information we can add the sysfs stub and
provide an accurate view of what is known about the machine.
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
The sysfs patches need to display machine vulnerability
status regardless of kernel config. Prepare for that
by breaking out the vulnerability/mitigation detection
code from the logic which implements the mitigation.
Signed-off-by: Jeremy Linton
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
From: Marc Zyngier
The SMCCC ARCH_WORKAROUND_1 service can indicate that although the
firmware knows about the Spectre-v2 mitigation, this particular
CPU is not vulnerable, and it is thus not necessary to call
the firmware on this CPU.
Let's use
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
From: Marc Zyngier
We currently have a list of CPUs affected by Spectre-v2, for which
we check that the firmware implements ARCH_WORKAROUND_1. It turns
out that not all firmwares do implement the required mitigation,
and that we fail to let the
On Fri, Mar 01, 2019 at 09:13:27AM +0900, Masahiro Yamada wrote:
> On Fri, Mar 1, 2019 at 7:08 AM Alexey Dobriyan wrote:
> >
> > On Thu, Feb 28, 2019 at 09:41:09AM -0800, a...@linux-foundation.org wrote:
> > > ---
> > >
Because Hyper-V requires that hypercall arguments be aligned on an 8
byte boundary, add __aligned(8) to struct retarget_msi_interrupt.
Link: https://lore.kernel.org/lkml/87k1hlqlby@vitty.brq.redhat.com/
Signed-off-by: Maya Nakamura
---
drivers/pci/controller/pci-hyperv.c | 2 +-
1 file
On Thu, 2019-02-28 at 11:23 -0300, Renato Lui Geh wrote:
>
>
> Previously, the AD7780 driver only supported gpio for the 'powerdown'
> pin. This commit adds suppport for the 'gain' and 'filter' pin.
>
> Signed-off-by: Renato Lui Geh
> Signed-off-by: Giuliano Belinassi
> Co-developed-by:
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
From: Mian Yousaf Kaukab
spectre v1, has been mitigated, and the mitigation is
always active.
Signed-off-by: Mian Yousaf Kaukab
Signed-off-by: Jeremy Linton
---
arch/arm64/kernel/cpu_errata.c | 6 ++
1 file changed, 6 insertions(+)
diff
This patchset removes a duplicate definition of VP set (hv_vp_set) and
uses the common definition (hv_vpset) that is used in other places. It
changes the order of the members in struct hv_pcibus_device due to
flexible array in hv_vpset.
It also removes the duplicate implementation of
Hi,
On 2/26/19 7:05 PM, Jeremy Linton wrote:
There are various reasons, including bencmarking, to disable spectrev2
mitigation on a machine. Provide a command-line to do so.
Signed-off-by: Jeremy Linton
Reviewed-by: Andre Przywara
Cheers,
Andre.
Cc: Jonathan Corbet
Cc:
On 28.02.2019 23:11, Alexey Budankov wrote:
>
> On 28.02.2019 21:46, Arnaldo Carvalho de Melo wrote:
>> Em Thu, Feb 28, 2019 at 11:59:01AM +0300, Alexey Budankov escreveu:
>>> +++ b/tools/build/Makefile.feature
>>> @@ -66,7 +66,8 @@ FEATURE_TESTS_BASIC := \
>>>
i.MX8QXP is an ARMv8 SoC which has a Cortex-M4 system controller
inside, the system controller is in charge of controlling power,
clock and watchdog etc..
This patch adds i.MX system controller watchdog driver support,
watchdog operation needs to be done in secure EL3 mode via
Enable CONFIG_IMX_SC_WDT as module to support i.MX system
controller watchdog.
Signed-off-by: Anson Huang
---
No changes.
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 2d9c390..690f4ba
On 2/28/19 6:29 PM, Masami Hiramatsu wrote:
> Hi Yonghong,
>
> On Thu, 28 Feb 2019 22:49:43 +
> Yonghong Song wrote:
>
>>
>>
>> On 2/28/19 8:03 AM, Masami Hiramatsu wrote:
>>> Add probe_user_read(), strncpy_from_unsafe_user() and
>>> strnlen_unsafe_user() which allows caller to access
On 01. 03. 19 3:13, Shawn Guo wrote:
On Tue, Feb 19, 2019 at 02:37:00PM +0100, Michal Vokáč wrote:
The PHY must add delays to both Tx and Rx clock on the cpu port
to work propperly.
It worked with the rgmii mode before beacause the qca8k driver
(incorrecly) enabled delays in that mode.
Zdravstvujte Vas interesuet parsing kontaktov?
On Fri, Mar 1, 2019 at 12:06 AM Joel Fernandes wrote:
>
> On Thu, Feb 28, 2019 at 11:17:51AM +0900, Masahiro Yamada wrote:
> > Hi Joel,
> >
> >
> > On Thu, Feb 28, 2019 at 4:40 AM Joel Fernandes (Google)
> > wrote:
> > >
> > > Introduce in-kernel headers and other artifacts which are made
In POWER9, OCC(On-Chip-Controller) provides for hard and soft system
powercapping range. The hard powercap range is guaranteed while soft
powercap may or may not be enforced by OCC due to various power-thermal
reasons based on system configuration and workloads. This patch adds
a sysfs file to
Use regulator_set/get_current_limit_regmap helpers to save some code.
Signed-off-by: Axel Lin
---
drivers/regulator/lp87565-regulator.c | 47 ---
1 file changed, 7 insertions(+), 40 deletions(-)
diff --git a/drivers/regulator/lp87565-regulator.c
In the page alloc fast path, it may do node reclaim, which may cause
latency spike.
We should add tracepoint for this event, and also measure the latency
it causes.
So bellow two tracepoints are introduced,
mm_vmscan_node_reclaim_begin
mm_vmscan_node_reclaim_end
Signed-off-by:
There are three tracepoints using this template, which are
mm_vmscan_direct_reclaim_begin,
mm_vmscan_memcg_reclaim_begin,
mm_vmscan_memcg_softlimit_reclaim_begin.
Regarding mm_vmscan_direct_reclaim_begin,
sc.may_writepage is !laptop_mode, that's a static setting, and
reclaim_idx is derived from
On 2/21/19 9:21 PM, Dave Martin wrote:
On Thu, Feb 21, 2019 at 12:29:42PM +, Mark Rutland wrote:
On Tue, Feb 19, 2019 at 02:54:28PM +0530, Amit Daniel Kachhap wrote:
From: Mark Rutland
When pointer authentication is supported, a guest may wish to use it.
This patch adds the necessary
LP87565_BUCK_0 is missed, fix it.
Fixes: f0168a9bf ("regulator: lp87565: Add support for lp87565 PMIC regulators")
Signed-off-by: Axel Lin
---
Hi J Keerthy,
While reading the code, it seems strange that LP87565_BUCK_0 is never used.
So current code only register 3 BUCKs for lp87565-regulator.
On 01.03.2019 00:49, Florian Fainelli wrote:
> Because we skip the prepare phase, we would not get a chance to have the
> port_vlan_prepare() callback return -EOPNOTSUPP and tell us about that.
> This causes problems with mv88e6xxx which specifically checks for VLAN
> ID = 0. Turns out we do not
Hi,
On 2/21/19 9:21 PM, Dave Martin wrote:
On Tue, Feb 19, 2019 at 02:54:27PM +0530, Amit Daniel Kachhap wrote:
Save host MDCR_EL2 value during kvm HYP initialisation and restore
after every switch from host to guest. There should not be any
change in functionality due to this.
The value of
Hi Chao,
I am back porting this commit to our distrols from tip.
3a63f70bf4c3 x86/boot: Early parse RSDP and save it in boot_params
Findind out those SRAT handling related declarations are out of
BOOT_COMPRESSED_MISC_H ifdeffery. Is this made on purpose?
Saw "misc.h" is included in several
Hi all,
[Thanks, Dan for the heads up and resolution.]
Today's linux-next merge of the nvdimm tree got a conflict in:
mm/memory_hotplug.c
between commit:
357b4da50a62 ("x86: respect memory size limiting via mem= parameter")
from the xen-tip tree and commit:
2794129e902d
From: Su Yanjun
Because nf_conntrack_helper_unregister maybe used in an unloadable module,
it uses 'synchronize_rcu' which may cause kernel panic.
According to the artical:
RCU and Unloadable Modules
https://lwn.net/Articles/217484/
When we have a heavy rcu callback load, then some of the
Hi,
On 2/21/19 9:19 PM, Dave Martin wrote:
On Tue, Feb 19, 2019 at 02:54:26PM +0530, Amit Daniel Kachhap wrote:
From: Mark Rutland
When restoring HCR_EL2 for the host, KVM uses HCR_HOST_VHE_FLAGS, which
is a constant value. This works today, as the host HCR_EL2 value is
always the same, but
On Thu, Feb 28, 2019 at 11:29:37PM -0600, Samuel Holland wrote:
> This series adds support for the "hardware message box" in sun8i, sun9i,
> and sun50i SoCs, used for communication with the ARISC management
> processor (the platform's equivalent of the ARM SCP). The end goal is to
> use the
On Thu, Feb 28, 2019 at 10:47:41AM -0600, Joshua Watt wrote:
> Reports the size of the virtgpu framebuffer to userspace and installs
> the deferred I/O handlers so that userspace can mmap() and write to it.
Fixed already, as side effect of switching virtio to the generic fbdev
emulation. Patches
Hi Linus,
Three final fixes, one for a feature that is new in this kernel, one
bochs fix for qemu riscv and one atomic modesetting fix.
I've left a few of the other late fixes until next as I didn't want to
throw in anything that wasn't really necessary.
Dave.
drm-fixes-2019-03-01:
drm amdgfx,
On Tue, Feb 26, 2019 at 05:35:04PM +0100, Jan Kara wrote:
> On Wed 27-02-19 00:07:27, Liu Song wrote:
> > In jbd2_get_transaction, a new transaction is initialized,
> > and set to the j_running_transaction. No need for a return
> > value, so remove it.
> > Also, adjust some comments to match the
> -Original Message-
> From: Parav Pandit
> Sent: Thursday, February 28, 2019 11:36 PM
> To: net...@vger.kernel.org; linux-kernel@vger.kernel.org;
> michal.l...@markovi.net; da...@davemloft.net;
> gre...@linuxfoundation.org; Jiri Pirko
> Cc: Parav Pandit
> Subject: [PATCH net-next
Keep power management callbacks in place to optionally notify drivers
who register them.
Signed-off-by: Parav Pandit
---
drivers/subdev/subdev_main.c | 59
1 file changed, 59 insertions(+)
diff --git a/drivers/subdev/subdev_main.c
Add support to parse subdev module device id table.
Signed-off-by: Parav Pandit
---
scripts/mod/devicetable-offsets.c | 4
scripts/mod/file2alias.c | 15 +++
2 files changed, 19 insertions(+)
diff --git a/scripts/mod/devicetable-offsets.c
Add variants of devlink_register and devlink_unregister which doesn't
explicitly acquire/release devlink_mutex lock, but requires that caller
hold the devlink_mutex lock.
This is required to create child devlink devices while working on
parent devlink device.
Change-Id:
Introduce a new subdev bus which holds sub devices created from a
primary device. These devices are named as 'subdev'.
A subdev is identified similarly to pci device using 16-bit vendor id
and device id.
Unlike PCI devices, scope of subdev is limited to Linux kernel.
A central entry that assigns
Add support for creating and deleting devlink subdevices.
For every subdev created on subdev bus, has corresponding devlink device.
This devlink device serves the control point for any internal device
configuration which is usually required before setting up the protocol
specific devices such as
Implement devlink device add/del command which cretes dummy subdev
devices that actual driver can bind to using standard device driver
model.
Signed-off-by: Parav Pandit
---
drivers/net/ethernet/mellanox/mlx5/core/Makefile | 1 +
drivers/net/ethernet/mellanox/mlx5/core/main.c | 4 ++
Add a subdev driver to probe the subdev devices and create fake
netdevice for it.
Signed-off-by: Parav Pandit
---
drivers/net/ethernet/mellanox/mlx5/core/Makefile | 2 +-
drivers/net/ethernet/mellanox/mlx5/core/main.c | 8 +-
.../net/ethernet/mellanox/mlx5/core/mlx5_core.h| 3 +
There is usecase to allocate devlink instance along with other structure
instance.
This is case when struct devlink and struct device are desired to be
part of single structure instance whose life cycle is driven by the life
cycle of the core device.
To support it, have more grandular init/cleanup
Use case:
-
A user wants to create/delete hardware linked sub devices without
using SR-IOV.
These devices for a pci device can be netdev (optional rdma device)
or other devices. Such sub devices share some of the PCI device
resources and also have their own dedicated resources.
Few
Use case:
-
A user wants to create/delete hardware linked sub devices without
using SR-IOV.
These devices for a pci device can be netdev (optional rdma device)
or other devices. Such sub devices share some of the PCI device
resources and also have their own dedicated resources.
Few
This mailbox hardware is present in Allwinner sun8i, sun9i, and sun50i
SoCs. Add a device tree binding for it.
Signed-off-by: Samuel Holland
---
.../bindings/mailbox/sunxi-msgbox.txt | 44 +++
1 file changed, 44 insertions(+)
create mode 100644
The msgbox clock is critical because the hardware is shared between
Linux and system firmware. The message box may be used by the EL3 secure
monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
uses the
The msgbox clock is critical because the hardware is shared between
Linux and system firmware. The message box may be used by the EL3 secure
monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
uses the
The H6 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file
The msgbox clock is critical because the hardware is shared between
Linux and system firmware. The message box may be used by the EL3 secure
monitor's PSCI implementation. On 64-bit sunxi SoCs, this is provided by
ARM TF-A; 32-bit SoCs use a different implementation. The secure monitor
uses the
The A64 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++
1 file
This series adds support for the "hardware message box" in sun8i, sun9i,
and sun50i SoCs, used for communication with the ARISC management
processor (the platform's equivalent of the ARM SCP). The end goal is to
use the arm_scpi driver as a client, communicating with firmware running
on the ARISC
The A83T SoC contains a message box that can be used to send messages
and interrupts back and forth between the ARM application CPUs and the
ARISC coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10
Allwinner sun8i, sun9i, and sun50i SoCs contain a hardware message box
used for communication between the ARM CPUs and the ARISC management
coprocessor. The hardware contains 8 unidirectional 4-message FIFOs.
Add a driver for it, so it can be used for SCPI or other communication
protocols.
The A80 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++
1 file changed, 10
The H3 and H5 SoCs contain a message box that can be used to send
messages and interrupts back and forth between the ARM application CPUs
and the ARISC coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 ++
1 file
Currently dwc host doesn't support the remove, but nothing prevent us
from supporting it. Save the root bus for clean up work in driver
remove code path.
After this patch, the dwc host users could implement its remove as:
static int foo_pcie_remove(struct platform_device *pdev)
{
...
Use devm_pci_alloc_host_bridge() to simplify the error code path.
Signed-off-by: Jisheng Zhang
---
.../pci/controller/dwc/pcie-designware-host.c | 21 +++
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
If we ever did some msi related initializations, we need to call
dw_pcie_free_msi() in the error code path.
Signed-off-by: Jisheng Zhang
---
drivers/pci/controller/dwc/pcie-designware-host.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git
To avoid memory leak, we need to free the page for MSI in
dw_pcie_free_msi().
Signed-off-by: Jisheng Zhang
---
drivers/pci/controller/dwc/pcie-designware-host.c | 3 +++
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 4 insertions(+)
diff --git
We should check msi_irq before calling irq_set_chained_handler() and
irq_set_handler_data().
Signed-off-by: Jisheng Zhang
---
drivers/pci/controller/dwc/pcie-designware-host.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
Currently, the PCI dwc host users don't support the remove, but nothing
prevent us from supporting it. To achieve this goal, we need to ensure
we can do necessary clean up work.
Changes since v1:
- address Bjorn's comments, I.E Capitalize, s/irq/IRQ/, s/msi/MSI/
Jisheng Zhang (5):
PCI: dwc:
In the present driver outbound window configuration is done to map above
32-bit address I/O regions with corresponding PCI memory range given in
ranges DT property.
This patch add outbound window configuration to map below 32-bit I/O range
with corresponding PCI memory, which helps to access I/O
This patch set extends support of new IPROC PCIe host controller features
- Add CRS check using controller register status flags
- Add outbound window mapping configuration for 32-bit I/O region
This patch set is based on Linux-5.0-rc2.
Changes from v3:
- Addressed Lorenzo Pieralisi
In the current implementation, config read output data 0x0001 is
assumed as CRS completion. But sometimes 0x0001 can be a valid data.
IPROC PCIe host controller PAXB v2 has a register to show config read
status flags like SC, UR, CRS and CA. So that extra check is added to
confirm the CRS
Hi, Guenter
Best Regards!
Anson Huang
> -Original Message-
> From: Guenter Roeck [mailto:groe...@gmail.com] On Behalf Of Guenter
> Roeck
> Sent: 2019年3月1日 12:21
> To: Anson Huang ; catalin.mari...@arm.com;
> will.dea...@arm.com; w...@linux-watchdog.org; shawn...@kernel.org;
>
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