On Fri, Mar 01, 2019 at 03:06:06PM -0800, Todd Kjos wrote:
> An munmap() on a binder device causes binder_vma_close() to be called
> which clears the alloc->vma pointer.
>
> If direct reclaim causes binder_alloc_free_page() to be called, there
> is a race where alloc->vma is read into a local vma
From: Antoine Tenart
Date: Fri, 1 Mar 2019 11:52:02 +0100
> This series aims to improve the Marvell PPv2 driver and to fix various
> issues we encountered while testing the ports in many different
> configurations. The series is based on top of Russell PPv2 phylink
> rework and improvement.
From: Flavio Suligoi
Date: Thu, 28 Feb 2019 10:20:35 +0100
> Sometimes, in some embedded systems boards (i.e. ARM boards),
> the NVM eeprom is not mounted, to save cost and space.
>
> In this case it is necessary to bypass the NVM management
> and directly force the MAC address using a kernel
Hello,
syzbot found the following crash on:
HEAD commit:c63e9e91a254 Add linux-next specific files for 20190301
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=160f18ecc0
kernel config: https://syzkaller.appspot.com/x/.config?x=f5875f9dc6e009b2
Hello,
syzbot found the following crash on:
HEAD commit:c63e9e91a254 Add linux-next specific files for 20190301
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=16a559b2c0
kernel config: https://syzkaller.appspot.com/x/.config?x=f5875f9dc6e009b2
Hello,
syzbot found the following crash on:
HEAD commit:42fd8df9d1d9 Add linux-next specific files for 20190228
git tree: linux-next
console output: https://syzkaller.appspot.com/x/log.txt?x=16c3cd5cc0
kernel config: https://syzkaller.appspot.com/x/.config?x=c0f38652d28b522f
Hello,
syzbot found the following crash on:
HEAD commit:7d762d69145a afs: Fix manually set volume location server ..
git tree: upstream
console output: https://syzkaller.appspot.com/x/log.txt?x=13044284c0
kernel config: https://syzkaller.appspot.com/x/.config?x=b76ec970784287c
On 2019/3/1 19:07, Jean-Philippe Brucker wrote:
> Hi Leizhen,
>
> On 01/03/2019 04:44, Leizhen (ThunderTown) wrote:
>>
>>
>> On 2019/2/26 20:36, Hanjun Guo wrote:
>>> Hi Jean,
>>>
>>> On 2019/1/31 22:55, Jean-Philippe Brucker wrote:
Hi,
On 31/01/2019 13:52, Zhen Lei wrote:
>
I tested this vs. Samba a few minutes ago with test 208 - looks like
it works. Thank you!
Now just need some additional reviews as this can be a complex area of code.
On Fri, Mar 1, 2019 at 9:04 PM Long Li wrote:
>
> From: Long Li
>
> When sending a wdata, transport may return -EAGAIN. In
From: Florian Fainelli
Date: Wed, 27 Feb 2019 16:29:16 -0800
> There are no more in tree users of the
> switchdev_trans_item_{dequeue,enqueue} or switchdev_trans_item structure
> in the kernel since commit 00fc0c51e35b ("rocker: Change world_ops API
> and implementation to be switchdev
Tegra CQHCI/SDHCI design prevents write access to SDHCI block size
register when CQE is enabled and unhalted.
CQHCI driver enabled CQE prior to invoking sdhci_cqe_enable which
violates this Tegra specific host requirement.
This patch fixes this by configuring sdhci block registers prior
to CQE
This patch enables command queue support for Tegra186 SDMMC4.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index
Tegra186 design has a known bug where CQE does not generated task
complete interrupt for data transfer tasks issued after DCMD task
with R1b response type and results in timeout.
SW WAR is to set CMD_TIMING to 1 in task descriptor for DCMDs with
R1b response type. This bug and SW WAR is
This patch adds define for CBC field mask of the register
CQHCI_SSC1.
Signed-off-by: Sowjanya Komatineni
---
drivers/mmc/host/cqhci.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/host/cqhci.h b/drivers/mmc/host/cqhci.h
index f96d8565cc07..f1dc48c7436f 100644
---
This patch includes below HW tuning related fixes.
- configures tuning parameters as per Tegra TRM
- WAR fix for manual tap change
- HW auto-tuning post process
As per Tegra TRM, SDR50 mode tuning execution takes upto maximum
of 256 tuning iterations and SDR104/HS200/HS400 modes tuning
execution
This patch adds a quirk for setting CMD_TIMING to 1 in descriptor
for DCMD with R1B response type to allow the command to be sent to
device during data activity or busy time.
Tegra186 CQHCI host has bug where it selects DATA_PRESENT_SELECT
to 1 by CQHCI controller for DCMDs with R1B response type
SDHCI controller of Tegra194 is similar to SDHCI controller in Tegra186.
This patch documents Tegra194 sdhci compatible string.
Signed-off-by: Sowjanya Komatineni
---
Documentation/devicetree/bindings/mmc/nvidia,tegra20-sdhci.txt | 1 +
1 file changed, 1 insertion(+)
diff --git
As per the Host Controller Standard Specification Version 4.20,
limitation of tuning iteration count is removed as PLL locking
time can be longer than UHS-1 tuning due to larger PVT fluctuation
and it will result in increase of tuning iteration to complete the
tuning.
This patch creates a hook
This patch adds support for post tuning process needed for some hosts
to perform after successful completion of HW tuning.
Signed-off-by: Sowjanya Komatineni
---
drivers/mmc/host/sdhci.c | 6 +-
drivers/mmc/host/sdhci.h | 1 +
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git
Default tap and trim values are incorrect for Tegra186 SDMMC4.
This patch fixes it.
Signed-off-by: Sowjanya Komatineni
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
ddr_signaling is set to true for DDR50 and DDR52 modes but is
not set back to false for other modes. This programs incorrect
host clock when mode change happens from DDR52/DDR50 to other
SDR or HS modes like incase of mmc_retune where it switches
from HS400 to HS DDR and then from HS DDR to HS
Only mm_compaction_isolate_{free, migrate}pages may be used when
CONFIG_COMPACTION is not set.
All others are used only when CONFIG_COMPACTION is set.
Signed-off-by: Yafang Shao
---
include/trace/events/compaction.h | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git
show the gfp flag names instead of the gfp_mask could make the trace
more convenient.
Signed-off-by: Yafang Shao
---
include/trace/events/compaction.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/trace/events/compaction.h
b/include/trace/events/compaction.h
The msgbox clock is critical because the hardware it controls is shared
between Linux and system firmware. The message box may be used by the
EL3 secure monitor's PSCI implementation. On 64-bit sunxi SoCs, this is
provided by ARM TF-A; 32-bit SoCs use a different implementation. The
secure monitor
On sun8i, sun9i, and sun50i SoCs, system suspend/resume support requires
firmware running on the AR100 coprocessor (the "SCP"). Such firmware can
provide additional features, such as thermal monitoring and poweron/off
support for boards without a PMIC.
Since the AR100 may be running critical
The H3 and H5 SoCs contain a message box that can be used to send
messages and interrupts back and forth between the ARM application CPUs
and the ARISC coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 10 ++
1 file
The A80 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun9i-a80.dtsi | 10 ++
1 file changed, 10
In order to give firmware full access to r_intc, Linux needs to avoid
using it in the device tree. Most IRQ lines attached to r_intc are also
attached to the GIC. Unfortunately, the NMI is not. For it to be used in
Linux, we have to forward it in firmware over the mailbox.
Add a node representing
The A64 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 10 ++
1 file
This mailbox hardware is present in Allwinner sun8i, sun9i, and sun50i
SoCs. Add a device tree binding for it.
Signed-off-by: Samuel Holland
---
.../mailbox/allwinner,sunxi-msgbox.yaml | 79 +++
1 file changed, 79 insertions(+)
create mode 100644
The A83T SoC contains a message box that can be used to send messages
and interrupts back and forth between the ARM application CPUs and the
ARISC coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm/boot/dts/sun8i-a83t.dtsi | 10 ++
1 file changed, 10
Hardware attached to AHB0/APB0 and controlled in the PRCM is designed to
be used by firmware running on the ARISC core. However, some devices in
this block (specifically the I2C, RSB, PIO, and CIR-RX) have native
Linux drivers and are already in the device tree. In particular, the RSB
and I2C
This is a somewhat generic binding for an interrupt controller/forwarder
implemented in firmware and communicated with using a mailbox.
Signed-off-by: Samuel Holland
---
.../interrupt-controller/mbox-intc.txt| 33 +++
1 file changed, 33 insertions(+)
create mode 100644
This series adds support for the "hardware message box" in sun8i, sun9i,
and sun50i SoCs, used for communication with the ARISC management
processor (the platform's equivalent of the ARM SCP). The end goal is to
use the arm_scpi driver as a client, communicating with firmware running
on the AR100
Now that there is an alternate way for Linux to receive NMIs from the
PMIC, replace references to r_intc with references to the new interrupt
controller.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64-amarula-relic.dts | 4 ++--
Allwinner sun8i, sun9i, and sun50i SoCs contain a hardware message box
used for communication between the ARM CPUs and the ARISC management
coprocessor. The hardware contains 8 unidirectional 4-message FIFOs.
Add a driver for it, so it can be used for SCPI or other communication
protocols.
The H6 SoC contains a message box that can be used to send messages and
interrupts back and forth between the ARM application CPUs and the ARISC
coprocessor. Add a device tree node for it.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file
This driver implements a simple interrupt controller using message
passing over a mailbox channel. The intention is for the other end of
the channel to be implemented in firmware. This allows filtering and
forwarding interrupts from one processor to another.
Signed-off-by: Samuel Holland
---
Now that r_intc is no longer used directly by Linux, it can be removed
from the SoC device tree.
Signed-off-by: Samuel Holland
---
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 9 -
1 file changed, 9 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
Larry,
Sorry about all these extra replies. Shortly after I sent my last
message my access point started recognizing the connection as 802.11ac
with PHY Rate / Modulation Rate of 866.6 Mbps. What is somewhat
misleading is the information reported by iwconfig (see bit rate below).
$ iwconfig
On Fri, Mar 01, 2019 at 09:08:35PM +0100, Jann Horn wrote:
> get_ds() is a legacy name for KERNEL_DS; all architectures #define it to
> KERNEL_DS,
not quite - h8300 and m68k have it as (equivalent) static inline.
> and almost every user of set_fs() uses the name KERNEL_DS.
>
> Let the VFS also
The idea behind this is: we don't want to keep tracking of huge pages when
logging_active is true, which will result in performance degradation. We
still need to set vma_pagesize to PAGE_SIZE, so that we can make use of it
to force a PTE mapping.
Cc: Suzuki K Poulose
Cc: Punit Agrawal
On 3/1/2019 5:11 AM, Ivan Khoronzhuk wrote:
> On Wed, Feb 27, 2019 at 08:29:20PM -0800, Florian Fainelli wrote:
>>
>>
>> On 2/26/2019 10:45 AM, Ivan Khoronzhuk wrote:
>>> IVDF - individual virtual device filtering. Allows to set per vlan
>>> l2 address filters on end real network device (for
From: John Hubbard
1. Bug fix: the error handling release pages starting
at the first page that experienced an error.
2. Refinement: release_pages() is better than put_page()
in a loop.
3. Dead code removal: the check for (user_virt & ~page_mask)
is checking for a condition that can never
From: John Hubbard
Hi,
Ira Weiny alerted me to a couple of places where I'd missed a change from
put_page() to put_user_page(), in my pending patchsets. But when I
attempted to dive more deeply into that code, I ran into things that I
*think* should be fixed up a bit.
I hope I didn't
On 3/1/2019 4:28 AM, Ivan Khoronzhuk wrote:
> On Wed, Feb 27, 2019 at 08:13:34PM -0800, Florian Fainelli wrote:
>>
>>
>> On 2/26/2019 10:45 AM, Ivan Khoronzhuk wrote:
>>> The vlan device address is held separately from uc/mc lists and
>>> handled differently. The vlan dev address is bound with
On 3/1/2019 4:24 AM, Ivan Khoronzhuk wrote:
> On Wed, Feb 27, 2019 at 08:09:44PM -0800, Florian Fainelli wrote:
>>
>>
>> On 2/26/2019 10:45 AM, Ivan Khoronzhuk wrote:
>>> Update vlan mc and uc addresses with VID tag while propagating
>>> addresses to lower devices, do this only if address is
Larry,
Please disregard my last message. The firmware is now installed and the
rtw88 module is working with my wireless router. The next hurdle
appears to be setting the speed to 802.11ac as it is currently
connecting as an 802.11n client.
Sincerely,
David R. Bergstein
On 3/1/19 9:55 PM,
The addresses within a single page are always contiguous, so it's
not so necessary to always allocate one single page from CMA area.
Since the CMA area has a limited predefined size of space, it may
run out of space in heavy use cases, where there might be quite a
lot CMA pages being allocated for
On 3/1/2019 2:54 AM, Jose Abreu wrote:
> Currently phy_read_status() considers that either the PHY driver has the
> read_status() callback or uses the generic callback.
>
> For C45 PHYs we need to use the gen10g_read_status() callback.
Right, so we could expect your C45 PHY driver to assign
On 3/1/2019 7:07 AM, Antoine Tenart wrote:
> Hi Andrew,
>
> On Fri, Mar 01, 2019 at 03:19:53PM +0100, Andrew Lunn wrote:
>> On Fri, Mar 01, 2019 at 12:00:47PM +0100, Antoine Tenart wrote:
>>> When the Marvell 10G PHYs are set out of reset, the LPOWER bit is set
>>> depending on an hardware
On 3/1/19 3:56 PM, Jiri Olsa wrote:
> Ravi Bangoria reported that we fail with empty
> numa node with following message:
>
> $ lscpu
> NUMA node0 CPU(s):
> NUMA node1 CPU(s): 0-4
>
> $ sudo ./perf c2c report
> node/cpu topology bugFailed setup nodes
>
> Fixing this by detecting
From: Long Li
When sending a wdata, transport may return -EAGAIN. In this case
we should re-obtain credits because the session may have been
reconnected.
Signed-off-by: Long Li
---
fs/cifs/file.c | 61 +-
1 file changed, 31 insertions(+), 30
From: Long Li
When sending a rdata, transport may return -EAGAIN. In this case
we should re-obtain credits because the session may have been
reconnected.
Signed-off-by: Long Li
---
fs/cifs/file.c | 51 +-
1 file changed, 26 insertions(+), 25
Larry,
Following up to your last reply, I blacklisted the r8822be module,
rebooted and was unable to bring up the wireless interface via rtw88.
Below are some errors recorded in my system log:
[ 267.509818] rtw_pci :3d:00.0: Direct firmware load for
rtw88/rtw8822b_fw.bin failed with
A bit in reg_ch_conf_pending in wl271 and tmp_ch_bitmap is set atomically
by set_bit(). set_bit() sets the bit in a single unsigned long location. If
the variables are not aligned to unsigned long, set_bit() accesses two
cache lines and thus causes slower performance. On x86, this scenario is
Some CPU feature bits are forced set and stored in cpuinfo_x86 before
handling clearcpuid options. To clear those bits from cpuinfo_x86,
apply_forced_cap() is called after handling the options.
Please note, apply_forced_cap() is called twice on boot CPU. But this code
is simple and there is no
The kernel option clearcpuid currently only takes feature bit which
can be changed from kernel to kernel.
Extend clearcpuid to use cap flag string, which is defined in
x86_cap_flags[] and won't be changed from kernel to kernel.
And user can easily get the cap flag string from /proc/cpuinfo.
Currently only one kernel option "clearcpuid=" can be picked up by
kernel during boot time.
In some cases, user may want to clear a few cpu caps. This may be
useful to replace endless (new) kernel options like nosmep, nosmap,
etc.
We add support of multiple clearcpuid options to allow user to
From: Peter Zijlstra
After kernel clears a CPUID bit through clearcpuid or other kernel options,
CPUID instruction executed from user space should see the same value for
the bit. The CPUID faulting handler returns the cleared bit to user.
Signed-off-by: Peter Zijlstra
Signed-off-by: Fenghua Yu
Bits in MSR IA32_CORE_CAPABILITY enumerate features that are not
enumerated through CPUID. Currently bit 5 is defined to enumerate
feature of #AC for split lock accesses. All other bits are reserved now.
When the bit 5 is 1, the feature is supported and feature bit
X86_FEATURE_SPLIT_LOCK_DETECT
set_cpu_cap() calls locked BTS and clear_cpu_cap() calls locked BTR to
operate on bitmap defined in x86_capability.
Locked BTS/BTR accesses a single unsigned long location. In 64-bit mode,
the location is at:
base address of x86_capability + (bit offset in x86_capability % 64) * 8
Since base
A bit in pwol_mask is set in b44_magic_pattern automatically by set_bit.
set_bit sets the bit in a single unsigned long location. Since pwol_mask
may not be aligned to unsigned long, the location may cross two cache
lines and accessing the location degradates performance. On x86, accessing
two
MSR register IA32_CORE_CAPABILITIES (0xCF) contains bits that enumerate
some model specific features.
The MSR 0xCF itself is enumerated by CPUID.(EAX=0x7,ECX=0):EDX[30].
When this bit is 1, the MSR 0xCF exists.
Detailed information for the CPUID bit and the MSR can be found in the
latest Intel
cpu_caps_cleared and cpu_caps_set may not be aligned to unsigned long.
Atomic operations (i.e. set_bit and clear_bit) on the bitmaps may access
two cache lines (a.k.a. split lock) and lock bus to block all memory
accesses from other processors to ensure atomicity.
To avoid the overall performance
Since kernel option clearcpuid now supports multiple options and CPU
capability flags, the document needs to be changed.
Signed-off-by: Fenghua Yu
---
Documentation/admin-guide/kernel-parameters.txt | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git
From: Xiaoyao Li
MSR IA32_CORE_CAPABILITY is a feature-enumerating MSR, bit 5 of which
reports the capability of enabling detection of split locks (will be
supported on future processors based on Tremont microarchitecture and
later).
Please check the latest Intel Architecture Instruction Set
From: Xiaoyao Li
A control bit (bit 29) in TEST_CTL MSR 0x33 will be introduced in
future x86 processors. When bit 29 is set, the processor causes #AC
exception for split locked accesses at all CPL.
Please check the latest Intel Software Developer's Manual
for more detailed information on the
The interface /sys/device/system/cpu/split_lock_detect is added
to allow user to control split lock detection and show current split
lock detection setting.
Writing 1 to the file enables split lock detection and writing 0
disables split lock detection. Split lock detection is enabled or
disabled
From: Xiaoyao Li
In the latest Intel SDM, CPUID.(EAX=7H,ECX=0):EDX[30] will enumerate
the presence of the IA32_CORE_CAPABILITY MSR.
Update GET_SUPPORTED_CPUID to expose this feature bit to user space, so
that user space know this bit can be enabled in CPUID.
Signed-off-by: Xiaoyao Li
---
There may be different considerations on how to handle #AC for split lock,
e.g. how to handle system hang caused by split lock issue in firmware,
how to emulate faulting instruction, etc. We use a simple method to
handle user and kernel split lock and may extend the method in the future.
When #AC
A new IA32_CORE_CAPABILITY MSR (0xCF) is defined. Each bit in
the MSR enumerates a model specific feature. Currently bit 5 enumerates
#AC exception for split locked accesses. When bit 5 is 1, split locked
accesses will generate #AC exception. When bit 5 is 0, split locked
accesses will not
==Introduction==
A split lock is any atomic operation whose operand crosses two cache
lines. Since the operand spans two cache lines and the operation must
be atomic, the system locks the bus while the CPU accesses the two cache
lines.
During bus locking, request from other CPUs or bus agents
Hi Linus:
This push fixes a couple of issues in arm64/chacha that was
introduced in 5.0.
Please pull from
git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git linus
Eric Biggers (2):
crypto: arm64/chacha - fix chacha_4block_xor_neon() for big endian
crypto:
On Sat, Mar 02, 2019 at 11:13:07AM +0900, Masahiro Yamada wrote:
> On Sat, Mar 2, 2019 at 3:03 AM Joel Fernandes wrote:
> >
> > On Fri, Mar 01, 2019 at 03:25:05PM +0900, Masahiro Yamada wrote:
> > [...]
> > > > > I am guessing the user will run these commands
> > > > > on the target system.
> > >
From: YueHaibing
syzkaller report this:
BUG: memory leak
unreferenced object 0x88837a71a500 (size 256):
comm "syz-executor.2", pid 9770, jiffies 4297825125 (age 17.843s)
hex dump (first 32 bytes):
00 00 00 00 ad 4e ad de ff ff ff ff 00 00 00 00 .N..
ff ff ff ff ff ff
Hi Nick,
On Sat, 2 Mar 2019 13:27:50 +1100 Stephen Rothwell
wrote:
>
> On Fri, 1 Mar 2019 16:07:14 -0800 Nick Desaulniers
> wrote:
> >
> > It turns out that arch/x86/boot/string.c doesn't actually need
> > linux/kernel.h, simply linux/limits.h and linux/compiler.h. Include them,
> > and sort
Hi Nick,
On Fri, 1 Mar 2019 16:07:14 -0800 Nick Desaulniers
wrote:
>
> It turns out that arch/x86/boot/string.c doesn't actually need
> linux/kernel.h, simply linux/limits.h and linux/compiler.h. Include them,
> and sort the headers alphabetically.
One small nit: please do not do the sort in
On Sat, Mar 2, 2019 at 3:03 AM Joel Fernandes wrote:
>
> On Fri, Mar 01, 2019 at 03:25:05PM +0900, Masahiro Yamada wrote:
> [...]
> > > > I am guessing the user will run these commands
> > > > on the target system.
> > > > In other words, external modules are native-compiled.
> > > > So,
> > > >
On 3/1/19 4:26 PM, David R. Bergstein wrote:
Larry,
Thanks for the response and detailed instructions, which allowed me to
build and install the rtw88 kernel module. I cannot however seem to get
my system to actually use the module. Just to recap this is an HP Omen
laptop with secure boot
On Thu, Feb 28, 2019 at 12:14 PM Toshi Kani wrote:
>
> ACPI NFIT flags field reports major errors on NVDIMM, which need
> user's attention.
>
> Update the current log to a proper error message with dev_err().
> The current message string is kept for grep-compatibility.
>
Looks good, applied.
On 2019/3/1 22:50, Bartlomiej Zolnierkiewicz wrote:
>
> Hi,
>
> On 03/01/2019 02:53 AM, Yue Haibing wrote:
>> From: YueHaibing
>>
>> After commit 60d2fa0dad06 ("fbdev: omap2: no need to check
>> return value of debugfs_create functions"), there are corner
>> code need to be cleaned.
>>
>>
Support both Python2 and Python3 in the exported-sql-viewer.py,
export-to-postgresql.py and export-to-sqlite.py scripts
There may be differences in the ordering of output lines due to
differences in dictionary ordering etc. However the format within lines
should be unchanged.
The use of 'from
Support both Python2 and Python3 in the intel-pt-events.py script
There may be differences in the ordering of output lines due to
differences in dictionary ordering etc. However the format within lines
should be unchanged.
The use of 'from __future__' implies the minimum supported Python2
Support both Python2 and Python3 in the event_analyzing_sample.py script
There may be differences in the ordering of output lines due to
differences in dictionary ordering etc. However the format within lines
should be unchanged.
The use of 'from __future__' implies the minimum supported
Introduce a printdate function to eliminate the repetitive use of
datetime.datetime.today() in the SQL exporting scripts.
Signed-off-by: Tony Jones
Cc: Adrian Hunter
---
tools/perf/scripts/python/export-to-postgresql.py | 19 +++
tools/perf/scripts/python/export-to-sqlite.py
Support both Python 2 and Python 3 in the check-perf-trace.py script.
There may be differences in the ordering of output lines due to
differences in dictionary ordering etc. However the format within lines
should be unchanged.
The use of from __future__ implies the minimum supported version of
This is v2 of my version of the patchset. Incorporating the
previous feedback. Some changes from v1 were already merged.
Patch 1/7 deals with the existing inconsistent indentation.
Indentation is now consistent per file but varying styles (tabs,
4 spaces and 8 spaces).
I will followup at a
Support both Python2 and Python3 in the futex-contention.py script
There may be differences in the ordering of output lines due to
differences in dictionary ordering etc. However the format within lines
should be unchanged.
The use of 'from __future__' implies the minimum supported Python2
Remove mixed indentation in Python scripts. Revert to either all
tabs (most common form) or all spaces (4 or 8) depending on what
was the intent of the original commit. This is necessary to
complete Python3 support as it will flag an error if it encounters
mixed indentation.
Signed-off-by:
On Wed, 2019-02-27 at 15:57 +1100, Alastair D'Silva wrote:
> From: Alastair D'Silva
>
> Use %# instead of using a literal '0x'
I think it's better not to change this unless
the compilation unit already uses a mix of styles.
Overall, the kernel uses "0x%" over "%#"
by ~8:1
$ git grep -P
Hi Chunfeng Yun,
On 2019/2/22 15:32, Chunfeng Yun wrote:
> On Tue, 2019-02-19 at 11:20 +0800, Chen Yu wrote:
>> Hi,
>>
>> On 2019/2/19 10:50, Chunfeng Yun wrote:
+ if (ret)
+ hisi_hikey_usb->typec_vbus_enable_val = 1;
+
+ hisi_hikey_usb->typec_vbus =
On Thu, 2019-02-28 at 11:55 +0200, Oded Gabbay wrote:
> Don't cast pointer to u64 to print it. Instead, print the pointer using
> %p.
You might want to use %px here if you _really_
want the actual address and not the hashed output
%p normally produces.
> diff --git
On Fri, 2019-03-01 at 13:48 +0100, Petr Mladek wrote:
> I want to double check what was the history of KERN_DEFAULT defined
> as "d". It existed since ages...
There less than 100 uses of KERN_DEFAULT.
Relatively speaking, KERN_DEFAULT hasn't existed all
that long actually.
commit
This extends the "console=" interface to allow setting the per-console
loglevel by adding "/N" to the string, where N is the desired loglevel
expressed as a base 10 integer. Invalid values are silently ignored.
Signed-off-by: Calvin Owens
---
.../admin-guide/kernel-parameters.txt | 6
Not all consoles are created equal: depending on the actual hardware,
the latency of a printk() call can vary dramatically. The worst examples
are serial consoles, where it can spin for tens of milliseconds banging
the UART to emit a message, which can cause application-level problems
when the
Signed-off-by: Calvin Owens
---
kernel/printk/printk.c | 40
1 file changed, 40 insertions(+)
diff --git a/kernel/printk/printk.c b/kernel/printk/printk.c
index 67e1e993ab80..e7e602fa2d0b 100644
--- a/kernel/printk/printk.c
+++ b/kernel/printk/printk.c
Hello all,
This is an extremely overdue refresh of this series:
https://lkml.org/lkml/2017/9/28/770
The big change here is the 3rd patch, which actually wires up the console
drivers to support embedding a device structure, so we can place them on
a "console" bus and expose attributes in
On 2019/3/2 0:43, Christoph Muellner wrote:
When using direct commands (DCMDs) on an RK3399, we get spurious
CQE completion interrupts for the DCMD transaction slot (#31):
I didn't see it. Do you try any newer code, for instance, linux-next?
[ 931.196520] [ cut here
Quoting Stephen Boyd (2019-02-26 14:34:21)
>
> I plan to at least merge the early patches in this series into clk-next
> so we can clear the way for the later patches. I don't think anything is
> too controversial until we get to the new way of specifying parents
> at the end and of course, the
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