Re: linux-next: build failure after merge of the sound tree
On Fri, 09 Aug 2019 04:54:58 +0200,
Stephen Rothwell wrote:
>
> Hi all,
>
> After merging the sound tree, today's linux-next build (arm
> multi_v7_defconfig) failed like this:
>
> sound/hda/hdac_bus.c: In function 'snd_hdac_aligned_read':
> sound/hda/hdac_bus.c:228:6: error: implicit declaration of function 'readl';
> did you mean 'd_real'? [-Werror=implicit-function-declaration]
> v = readl(aligned_addr);
> ^
> d_real
> sound/hda/hdac_bus.c: In function 'snd_hdac_aligned_write':
> sound/hda/hdac_bus.c:244:2: error: implicit declaration of function 'writel'
> [-Werror=implicit-function-declaration]
> writel(v, aligned_addr);
> ^~
>
> Caused by commit
>
> 19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
>
> I have applied the following patch for today:
>
> From: Stephen Rothwell
> Date: Fri, 9 Aug 2019 12:50:25 +1000
> Subject: [PATCH] ALSA: hda: readl/writel need linux/io.h
>
> Fixes: 19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
> Signed-off-by: Stephen Rothwell
> ---
> sound/hda/hdac_bus.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/sound/hda/hdac_bus.c b/sound/hda/hdac_bus.c
> index dc2523ef7d98..cd25e2b3f7f2 100644
> --- a/sound/hda/hdac_bus.c
> +++ b/sound/hda/hdac_bus.c
> @@ -4,6 +4,7 @@
> */
>
> #include
> +#include
> #include
> #include
> #include
Thanks, it's obviously a right fix.
I applied it on top of topic/hda-bus-ops-cleanup branch branch.
Mark, feel free to pull it into yours again.
Takashi
[PATCH V5 4/9] vhost: reset invalidate_count in vhost_set_vring_num_addr()
The vhost_set_vring_num_addr() could be called in the middle of
invalidate_range_start() and invalidate_range_end(). If we don't reset
invalidate_count after the un-registering of MMU notifier, the
invalidate_cont will run out of sync (e.g never reach zero). This will
in fact disable the fast accessor path. Fixing by reset the count to
zero.
Reported-by: Michael S. Tsirkin
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 2a3154976277..2a7217c33668 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -2073,6 +2073,10 @@ static long vhost_vring_set_num_addr(struct vhost_dev *d,
d->has_notifier = false;
}
+ /* reset invalidate_count in case we are in the middle of
+* invalidate_start() and invalidate_end().
+*/
+ vq->invalidate_count = 0;
vhost_uninit_vq_maps(vq);
#endif
--
2.18.1
[PATCH V5 3/9] vhost: fix vhost map leak
We don't free map during vhost_map_unprefetch(). This means it could
be leaked. Fixing by free the map.
Reported-by: Michael S. Tsirkin
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 17f6abea192e..2a3154976277 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -302,9 +302,7 @@ static void vhost_vq_meta_reset(struct vhost_dev *d)
static void vhost_map_unprefetch(struct vhost_map *map)
{
kfree(map->pages);
- map->pages = NULL;
- map->npages = 0;
- map->addr = NULL;
+ kfree(map);
}
static void vhost_uninit_vq_maps(struct vhost_virtqueue *vq)
--
2.18.1
[PATCH V5 6/9] vhost: don't do synchronize_rcu() in vhost_uninit_vq_maps()
There's no need for RCU synchronization in vhost_uninit_vq_maps()
since we've already serialized with readers (memory accessors). This
also avoid the possible userspace DOS through ioctl() because of the
possible high latency caused by synchronize_rcu().
Reported-by: Michael S. Tsirkin
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index c12cdadb0855..cfc11f9ed9c9 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -333,7 +333,9 @@ static void vhost_uninit_vq_maps(struct vhost_virtqueue *vq)
}
spin_unlock(>mmu_lock);
- synchronize_rcu();
+ /* No need for synchronize_rcu() or kfree_rcu() since we are
+* serialized with memory accessors (e.g vq mutex held).
+*/
for (i = 0; i < VHOST_NUM_ADDRS; i++)
if (map[i])
--
2.18.1
[PATCH V5 7/9] vhost: do not use RCU to synchronize MMU notifier with worker
We used to use RCU to synchronize MMU notifier with worker. This leads
calling synchronize_rcu() in invalidate_range_start(). But on a busy
system, there would be many factors that may slow down the
synchronize_rcu() which makes it unsuitable to be called in MMU
notifier. This path switch to use a simple spinlock to do the
synchronization.
Benchmark was done through testpmd + vhost_net + XDP_DROP on
tap. Compare to copy_{to|from}_user() path, on Sandy Bridge (without
SMAP support), 1.5% PPS improvement was measured; on Broadwell (with
SMAP and enabled), 14% PPS improvement was measured.
This means we are not as fast as what 7f466032dc9e did because the
spinlock overhead in the datapath. This needs to be addressed in the
future.
Reported-by: Michael S. Tsirkin
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 115 ++
drivers/vhost/vhost.h | 5 +-
2 files changed, 62 insertions(+), 58 deletions(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index cfc11f9ed9c9..29e8abe694f7 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -324,17 +324,16 @@ static void vhost_uninit_vq_maps(struct vhost_virtqueue
*vq)
spin_lock(>mmu_lock);
for (i = 0; i < VHOST_NUM_ADDRS; i++) {
- map[i] = rcu_dereference_protected(vq->maps[i],
- lockdep_is_held(>mmu_lock));
+ map[i] = vq->maps[i];
if (map[i]) {
vhost_set_map_dirty(vq, map[i], i);
- rcu_assign_pointer(vq->maps[i], NULL);
+ vq->maps[i] = NULL;
}
}
spin_unlock(>mmu_lock);
- /* No need for synchronize_rcu() or kfree_rcu() since we are
-* serialized with memory accessors (e.g vq mutex held).
+ /* No need for synchronization since we are serialized with
+* memory accessors (e.g vq mutex held).
*/
for (i = 0; i < VHOST_NUM_ADDRS; i++)
@@ -362,6 +361,16 @@ static bool vhost_map_range_overlap(struct vhost_uaddr
*uaddr,
return !(end < uaddr->uaddr || start > uaddr->uaddr - 1 + uaddr->size);
}
+static void inline vhost_vq_access_map_begin(struct vhost_virtqueue *vq)
+{
+ spin_lock(>mmu_lock);
+}
+
+static void inline vhost_vq_access_map_end(struct vhost_virtqueue *vq)
+{
+ spin_unlock(>mmu_lock);
+}
+
static void vhost_invalidate_vq_start(struct vhost_virtqueue *vq,
int index,
unsigned long start,
@@ -376,16 +385,14 @@ static void vhost_invalidate_vq_start(struct
vhost_virtqueue *vq,
spin_lock(>mmu_lock);
++vq->invalidate_count;
- map = rcu_dereference_protected(vq->maps[index],
- lockdep_is_held(>mmu_lock));
+ map = vq->maps[index];
if (map) {
+ vq->maps[index] = NULL;
vhost_set_map_dirty(vq, map, index);
- rcu_assign_pointer(vq->maps[index], NULL);
}
spin_unlock(>mmu_lock);
if (map) {
- synchronize_rcu();
vhost_map_unprefetch(map);
}
}
@@ -457,7 +464,7 @@ static void vhost_init_maps(struct vhost_dev *dev)
for (i = 0; i < dev->nvqs; ++i) {
vq = dev->vqs[i];
for (j = 0; j < VHOST_NUM_ADDRS; j++)
- RCU_INIT_POINTER(vq->maps[j], NULL);
+ vq->maps[j] = NULL;
}
}
#endif
@@ -921,7 +928,7 @@ static int vhost_map_prefetch(struct vhost_virtqueue *vq,
map->npages = npages;
map->pages = pages;
- rcu_assign_pointer(vq->maps[index], map);
+ vq->maps[index] = map;
/* No need for a synchronize_rcu(). This function should be
* called by dev->worker so we are serialized with all
* readers.
@@ -1216,18 +1223,18 @@ static inline int vhost_put_avail_event(struct
vhost_virtqueue *vq)
struct vring_used *used;
if (!vq->iotlb) {
- rcu_read_lock();
+ vhost_vq_access_map_begin(vq);
- map = rcu_dereference(vq->maps[VHOST_ADDR_USED]);
+ map = vq->maps[VHOST_ADDR_USED];
if (likely(map)) {
used = map->addr;
*((__virtio16 *)>ring[vq->num]) =
cpu_to_vhost16(vq, vq->avail_idx);
- rcu_read_unlock();
+ vhost_vq_access_map_end(vq);
return 0;
}
- rcu_read_unlock();
+ vhost_vq_access_map_end(vq);
}
#endif
@@ -1245,18 +1252,18 @@ static inline int vhost_put_used(struct vhost_virtqueue
*vq,
size_t size;
if (!vq->iotlb) {
- rcu_read_lock();
+
[PATCH V5 2/9] vhost: validate MMU notifier registration
The return value of mmu_notifier_register() is not checked in
vhost_vring_set_num_addr(). This will cause an out of sync between mm
and MMU notifier thus a double free. To solve this, introduce a
boolean flag to track whether MMU notifier is registered and only do
unregistering when it was true.
Reported-and-tested-by:
syzbot+e58112d71f77113dd...@syzkaller.appspotmail.com
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 19 +++
drivers/vhost/vhost.h | 1 +
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 488380a581dc..17f6abea192e 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -629,6 +629,7 @@ void vhost_dev_init(struct vhost_dev *dev,
dev->iov_limit = iov_limit;
dev->weight = weight;
dev->byte_weight = byte_weight;
+ dev->has_notifier = false;
init_llist_head(>work_list);
init_waitqueue_head(>wait);
INIT_LIST_HEAD(>read_list);
@@ -730,6 +731,7 @@ long vhost_dev_set_owner(struct vhost_dev *dev)
if (err)
goto err_mmu_notifier;
#endif
+ dev->has_notifier = true;
return 0;
@@ -959,7 +961,11 @@ void vhost_dev_cleanup(struct vhost_dev *dev)
}
if (dev->mm) {
#if VHOST_ARCH_CAN_ACCEL_UACCESS
- mmu_notifier_unregister(>mmu_notifier, dev->mm);
+ if (dev->has_notifier) {
+ mmu_notifier_unregister(>mmu_notifier,
+ dev->mm);
+ dev->has_notifier = false;
+ }
#endif
mmput(dev->mm);
}
@@ -2064,8 +2070,10 @@ static long vhost_vring_set_num_addr(struct vhost_dev *d,
/* Unregister MMU notifer to allow invalidation callback
* can access vq->uaddrs[] without holding a lock.
*/
- if (d->mm)
+ if (d->has_notifier) {
mmu_notifier_unregister(>mmu_notifier, d->mm);
+ d->has_notifier = false;
+ }
vhost_uninit_vq_maps(vq);
#endif
@@ -2085,8 +2093,11 @@ static long vhost_vring_set_num_addr(struct vhost_dev *d,
if (r == 0)
vhost_setup_vq_uaddr(vq);
- if (d->mm)
- mmu_notifier_register(>mmu_notifier, d->mm);
+ if (d->mm) {
+ r = mmu_notifier_register(>mmu_notifier, d->mm);
+ if (!r)
+ d->has_notifier = true;
+ }
#endif
mutex_unlock(>mutex);
diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
index 42a8c2a13ab1..a9a2a93857d2 100644
--- a/drivers/vhost/vhost.h
+++ b/drivers/vhost/vhost.h
@@ -214,6 +214,7 @@ struct vhost_dev {
int iov_limit;
int weight;
int byte_weight;
+ bool has_notifier;
};
bool vhost_exceeds_weight(struct vhost_virtqueue *vq, int pkts, int total_len);
--
2.18.1
[PATCH V5 1/9] vhost: don't set uaddr for invalid address
We should not setup uaddr for the invalid address, otherwise we may
try to pin or prefetch mapping of wrong pages.
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 0536f8526359..488380a581dc 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -2082,7 +2082,8 @@ static long vhost_vring_set_num_addr(struct vhost_dev *d,
}
#if VHOST_ARCH_CAN_ACCEL_UACCESS
- vhost_setup_vq_uaddr(vq);
+ if (r == 0)
+ vhost_setup_vq_uaddr(vq);
if (d->mm)
mmu_notifier_register(>mmu_notifier, d->mm);
--
2.18.1
[PATCH V5 9/9] vhost: do not return -EAGAIN for non blocking invalidation too early
Instead of returning -EAGAIN unconditionally, we'd better do that only
we're sure the range is overlapped with the metadata area.
Reported-by: Jason Gunthorpe
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 32 +++-
1 file changed, 19 insertions(+), 13 deletions(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index d8863aaaf0f6..f98155f28f02 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -371,16 +371,19 @@ static void inline vhost_vq_access_map_end(struct
vhost_virtqueue *vq)
spin_unlock(>mmu_lock);
}
-static void vhost_invalidate_vq_start(struct vhost_virtqueue *vq,
- int index,
- unsigned long start,
- unsigned long end)
+static int vhost_invalidate_vq_start(struct vhost_virtqueue *vq,
+int index,
+unsigned long start,
+unsigned long end,
+bool blockable)
{
struct vhost_uaddr *uaddr = >uaddrs[index];
struct vhost_map *map;
if (!vhost_map_range_overlap(uaddr, start, end))
- return;
+ return 0;
+ else if (!blockable)
+ return -EAGAIN;
spin_lock(>mmu_lock);
++vq->invalidate_count;
@@ -394,6 +397,8 @@ static void vhost_invalidate_vq_start(struct
vhost_virtqueue *vq,
vhost_set_map_dirty(vq, map, index);
vhost_map_unprefetch(map);
}
+
+ return 0;
}
static void vhost_invalidate_vq_end(struct vhost_virtqueue *vq,
@@ -414,18 +419,19 @@ static int vhost_invalidate_range_start(struct
mmu_notifier *mn,
{
struct vhost_dev *dev = container_of(mn, struct vhost_dev,
mmu_notifier);
- int i, j;
-
- if (!mmu_notifier_range_blockable(range))
- return -EAGAIN;
+ bool blockable = mmu_notifier_range_blockable(range);
+ int i, j, ret;
for (i = 0; i < dev->nvqs; i++) {
struct vhost_virtqueue *vq = dev->vqs[i];
- for (j = 0; j < VHOST_NUM_ADDRS; j++)
- vhost_invalidate_vq_start(vq, j,
- range->start,
- range->end);
+ for (j = 0; j < VHOST_NUM_ADDRS; j++) {
+ ret = vhost_invalidate_vq_start(vq, j,
+ range->start,
+ range->end, blockable);
+ if (ret)
+ return ret;
+ }
}
return 0;
--
2.18.1
[PATCH V5 5/9] vhost: mark dirty pages during map uninit
We don't mark dirty pages if the map was teared down outside MMU
notifier. This will lead untracked dirty pages. Fixing by marking
dirty pages during map uninit.
Reported-by: Michael S. Tsirkin
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 2a7217c33668..c12cdadb0855 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -305,6 +305,18 @@ static void vhost_map_unprefetch(struct vhost_map *map)
kfree(map);
}
+static void vhost_set_map_dirty(struct vhost_virtqueue *vq,
+ struct vhost_map *map, int index)
+{
+ struct vhost_uaddr *uaddr = >uaddrs[index];
+ int i;
+
+ if (uaddr->write) {
+ for (i = 0; i < map->npages; i++)
+ set_page_dirty(map->pages[i]);
+ }
+}
+
static void vhost_uninit_vq_maps(struct vhost_virtqueue *vq)
{
struct vhost_map *map[VHOST_NUM_ADDRS];
@@ -314,8 +326,10 @@ static void vhost_uninit_vq_maps(struct vhost_virtqueue
*vq)
for (i = 0; i < VHOST_NUM_ADDRS; i++) {
map[i] = rcu_dereference_protected(vq->maps[i],
lockdep_is_held(>mmu_lock));
- if (map[i])
+ if (map[i]) {
+ vhost_set_map_dirty(vq, map[i], i);
rcu_assign_pointer(vq->maps[i], NULL);
+ }
}
spin_unlock(>mmu_lock);
@@ -353,7 +367,6 @@ static void vhost_invalidate_vq_start(struct
vhost_virtqueue *vq,
{
struct vhost_uaddr *uaddr = >uaddrs[index];
struct vhost_map *map;
- int i;
if (!vhost_map_range_overlap(uaddr, start, end))
return;
@@ -364,10 +377,7 @@ static void vhost_invalidate_vq_start(struct
vhost_virtqueue *vq,
map = rcu_dereference_protected(vq->maps[index],
lockdep_is_held(>mmu_lock));
if (map) {
- if (uaddr->write) {
- for (i = 0; i < map->npages; i++)
- set_page_dirty(map->pages[i]);
- }
+ vhost_set_map_dirty(vq, map, index);
rcu_assign_pointer(vq->maps[index], NULL);
}
spin_unlock(>mmu_lock);
--
2.18.1
[PATCH V5 8/9] vhost: correctly set dirty pages in MMU notifiers callback
We need make sure there's no reference on the map before trying to
mark set dirty pages.
Reported-by: Michael S. Tsirkin
Fixes: 7f466032dc9e ("vhost: access vq metadata through kernel virtual address")
Signed-off-by: Jason Wang
---
drivers/vhost/vhost.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index 29e8abe694f7..d8863aaaf0f6 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -386,13 +386,12 @@ static void vhost_invalidate_vq_start(struct
vhost_virtqueue *vq,
++vq->invalidate_count;
map = vq->maps[index];
- if (map) {
+ if (map)
vq->maps[index] = NULL;
- vhost_set_map_dirty(vq, map, index);
- }
spin_unlock(>mmu_lock);
if (map) {
+ vhost_set_map_dirty(vq, map, index);
vhost_map_unprefetch(map);
}
}
--
2.18.1
[PATCH V5 0/9] Fixes for vhost metadata acceleration
Hi all: This series try to fix several issues introduced by meta data accelreation series. Please review. Changes from V4: - switch to use spinlock synchronize MMU notifier with accessors Changes from V3: - remove the unnecessary patch Changes from V2: - use seqlck helper to synchronize MMU notifier with vhost worker Changes from V1: - try not use RCU to syncrhonize MMU notifier with vhost worker - set dirty pages after no readers - return -EAGAIN only when we find the range is overlapped with metadata Jason Wang (9): vhost: don't set uaddr for invalid address vhost: validate MMU notifier registration vhost: fix vhost map leak vhost: reset invalidate_count in vhost_set_vring_num_addr() vhost: mark dirty pages during map uninit vhost: don't do synchronize_rcu() in vhost_uninit_vq_maps() vhost: do not use RCU to synchronize MMU notifier with worker vhost: correctly set dirty pages in MMU notifiers callback vhost: do not return -EAGAIN for non blocking invalidation too early drivers/vhost/vhost.c | 202 +- drivers/vhost/vhost.h | 6 +- 2 files changed, 122 insertions(+), 86 deletions(-) -- 2.18.1
RE: [PATCH V5 2/2] cpufreq: intel_pstate: Implement QoS supported freq constraints
On 2019.08.08 19:23 Viresh Kumar wrote: > --- > V4->V5: > - dev_pm_qos_update_request() can return 1 in case of success, handle > that. O.K. thanks, That fixes the "Fail" messages I was getting with V4. ... Doug
[PATCH net-next v6 1/3] net: phy: modify assignment to OR for dev_flags in phy_attach_direct
Modify the assignment to OR when dealing with phydev->dev_flags in phy_attach_direct function, and this is to make sure dev_flags set in driver's probe callback won't be lost. Suggested-by: Andrew Lunn CC: Heiner Kallweit CC: Vladimir Oltean Signed-off-by: Tao Ren Reviewed-by: Andrew Lunn --- Changes: - nothing is changed in v1-v5: it's given v6 to align with the version of patch series. drivers/net/phy/phy_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c index 7ddd91df99e3..252a712d1b2b 100644 --- a/drivers/net/phy/phy_device.c +++ b/drivers/net/phy/phy_device.c @@ -1270,7 +1270,7 @@ int phy_attach_direct(struct net_device *dev, struct phy_device *phydev, phydev_err(phydev, "error creating 'phy_standalone' sysfs entry\n"); } - phydev->dev_flags = flags; + phydev->dev_flags |= flags; phydev->interface = interface; -- 2.17.1
[PATCH net-next v6 2/3] net: phy: add support for clause 37 auto-negotiation
From: Heiner Kallweit
This patch adds support for clause 37 1000Base-X auto-negotiation.
Signed-off-by: Heiner Kallweit
Signed-off-by: Tao Ren
---
Changes in v6:
- add "Signed-off-by: Tao Ren "
Changes in v1-v5:
- nothing changed. It's given v6 just to align with the version of
patch series.
drivers/net/phy/phy_device.c | 139 +++
include/linux/phy.h | 5 ++
2 files changed, 144 insertions(+)
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index 252a712d1b2b..7c5315302937 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -1617,6 +1617,40 @@ static int genphy_config_advert(struct phy_device
*phydev)
return changed;
}
+/**
+ * genphy_c37_config_advert - sanitize and advertise auto-negotiation
parameters
+ * @phydev: target phy_device struct
+ *
+ * Description: Writes MII_ADVERTISE with the appropriate values,
+ * after sanitizing the values to make sure we only advertise
+ * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
+ * hasn't changed, and > 0 if it has changed. This function is intended
+ * for Clause 37 1000Base-X mode.
+ */
+static int genphy_c37_config_advert(struct phy_device *phydev)
+{
+ u16 adv = 0;
+
+ /* Only allow advertising what this PHY supports */
+ linkmode_and(phydev->advertising, phydev->advertising,
+phydev->supported);
+
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XFULL;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPAUSE;
+ if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
+ phydev->advertising))
+ adv |= ADVERTISE_1000XPSE_ASYM;
+
+ return phy_modify_changed(phydev, MII_ADVERTISE,
+ ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
+ ADVERTISE_1000XHALF | ADVERTISE_1000XPSE_ASYM,
+ adv);
+}
+
/**
* genphy_config_eee_advert - disable unwanted eee mode advertisement
* @phydev: target phy_device struct
@@ -1726,6 +1760,54 @@ int genphy_config_aneg(struct phy_device *phydev)
}
EXPORT_SYMBOL(genphy_config_aneg);
+/**
+ * genphy_c37_config_aneg - restart auto-negotiation or write BMCR
+ * @phydev: target phy_device struct
+ *
+ * Description: If auto-negotiation is enabled, we configure the
+ * advertising, and then restart auto-negotiation. If it is not
+ * enabled, then we write the BMCR. This function is intended
+ * for use with Clause 37 1000Base-X mode.
+ */
+int genphy_c37_config_aneg(struct phy_device *phydev)
+{
+ int err, changed;
+
+ if (AUTONEG_ENABLE != phydev->autoneg)
+ return genphy_setup_forced(phydev);
+
+ err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
+BMCR_SPEED1000);
+ if (err)
+ return err;
+
+ changed = genphy_c37_config_advert(phydev);
+ if (changed < 0) /* error */
+ return changed;
+
+ if (!changed) {
+ /* Advertisement hasn't changed, but maybe aneg was never on to
+* begin with? Or maybe phy was isolated?
+*/
+ int ctl = phy_read(phydev, MII_BMCR);
+
+ if (ctl < 0)
+ return ctl;
+
+ if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
+ changed = 1; /* do restart aneg */
+ }
+
+ /* Only restart aneg if we are advertising something different
+* than we were before.
+*/
+ if (changed > 0)
+ return genphy_restart_aneg(phydev);
+
+ return 0;
+}
+EXPORT_SYMBOL(genphy_c37_config_aneg);
+
/**
* genphy_aneg_done - return auto-negotiation status
* @phydev: target phy_device struct
@@ -1864,6 +1946,63 @@ int genphy_read_status(struct phy_device *phydev)
}
EXPORT_SYMBOL(genphy_read_status);
+/**
+ * genphy_c37_read_status - check the link status and update current link state
+ * @phydev: target phy_device struct
+ *
+ * Description: Check the link, then figure out the current state
+ * by comparing what we advertise with what the link partner
+ * advertises. This function is for Clause 37 1000Base-X mode.
+ */
+int genphy_c37_read_status(struct phy_device *phydev)
+{
+ int lpa, err, old_link = phydev->link;
+
+ /* Update the link, but return if there was an error */
+ err = genphy_update_link(phydev);
+ if (err)
+ return err;
+
+ /* why bother the PHY if nothing can have changed */
+ if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+ return 0;
+
+ phydev->duplex = DUPLEX_UNKNOWN;
+
Re: [PATCH v2 2/4] soundwire: core: add device tree support for slave devices
On 08-08-19, 16:17, Srinivas Kandagatla wrote:
> Thanks for taking time to review.
>
> On 08/08/2019 16:00, Pierre-Louis Bossart wrote:
> >
> > > @@ -35,6 +36,7 @@ static int sdw_slave_add(struct sdw_bus *bus,
> > > slave->dev.release = sdw_slave_release;
> > > slave->dev.bus = _bus_type;
> > > + slave->dev.of_node = of_node_get(to_of_node(fwnode));
> >
> > shouldn't this protected by
> > #if IS_ENABLED(CONFIG_OF) ?
> >
> These macros and functions have dummy entries, so it should not be an issue.
> I did build soundwire with i386_defconfig with no issues.
That means this function was compiled without errors, that is not strange
nowadays
given the ARM compiles ACPI and x86 OF, so check with OF being disable
just to be safe :) I think dummy entries are helping
>
> > > slave->bus = bus;
> > > slave->status = SDW_SLAVE_UNATTACHED;
> > > slave->dev_num = 0;
> > > @@ -112,3 +114,48 @@ int sdw_acpi_find_slaves(struct sdw_bus *bus)
> > > }
> > > #endif
> > > +
> > > +/*
> > > + * sdw_of_find_slaves() - Find Slave devices in master device tree node
> > > + * @bus: SDW bus instance
> > > + *
> > > + * Scans Master DT node for SDW child Slave devices and registers it.
> > > + */
> > > +int sdw_of_find_slaves(struct sdw_bus *bus)
> > > +{
> > > + struct device *dev = bus->dev;
> > > + struct device_node *node;
> > > +
> > > + for_each_child_of_node(bus->dev->of_node, node) {
> > > + struct sdw_slave_id id;
> > > + const char *compat = NULL;
> > > + int unique_id, ret;
> > > + int ver, mfg_id, part_id, class_id;
> > > +
> > > + compat = of_get_property(node, "compatible", NULL);
> > > + if (!compat)
> > > + continue;
> > > +
> > > + ret = sscanf(compat, "sdw%x,%x,%x,%x",
> > > + , _id, _id, _id);
> > > + if (ret != 4) {
> > > + dev_err(dev, "Manf ID & Product code not found %s\n",
> > > + compat);
> > > + continue;
> > > + }
> > > +
> > > + ret = of_property_read_u32(node, "sdw-instance-id", _id);
> > > + if (ret) {
> > > + dev_err(dev, "Instance id not found:%d\n", ret);
> > > + continue;
> >
> > I am confused here.
> > If you have two identical devices on the same link, isn't this property
> > required and that should be a real error instead of a continue?
>
> Yes, I agree it will be mandatory in such cases.
>
> Am okay either way, I dont mind changing it to returning EINVAL in all the
> cases.
Do we want to abort? We are in loop scanning for devices so makes sense
if we do not do that and continue to check next one..
--
~Vinod
[PATCH net-next v6 3/3] net: phy: broadcom: add 1000Base-X support for BCM54616S
The BCM54616S PHY cannot work properly in RGMII->1000Base-KX mode (for
example, on Facebook CMM BMC platform), mainly because genphy functions
are designed for copper links, and 1000Base-X (clause 37) auto negotiation
needs to be handled differently.
This patch enables 1000Base-X support for BCM54616S by customizing 3
driver callbacks:
- probe: probe callback detects PHY's operation mode based on
INTERF_SEL[1:0] pins and 1000X/100FX selection bit in SerDES 100-FX
Control register.
- config_aneg: calls genphy_c37_config_aneg when the PHY is running in
1000Base-X mode; otherwise, genphy_config_aneg will be called.
- read_status: calls genphy_c37_read_status when the PHY is running in
1000Base-X mode; otherwise, genphy_read_status will be called.
Signed-off-by: Tao Ren
---
Changes in v6:
- nothing changed.
Changes in v5:
- include Heiner's patch "net: phy: add support for clause 37
auto-negotiation" into the series.
- use genphy_c37_config_aneg and genphy_c37_read_status in BCM54616S
PHY driver's callback when the PHY is running in 1000Base-X mode.
Changes in v4:
- add bcm54616s_config_aneg_1000bx() to deal with auto negotiation in
1000Base-X mode.
Changes in v3:
- rename bcm5482_read_status to bcm54xx_read_status so the callback can
be shared by BCM5482 and BCM54616S.
Changes in v2:
- Auto-detect PHY operation mode instead of passing DT node.
- move PHY mode auto-detect logic from config_init to probe callback.
- only set speed (not including duplex) in read_status callback.
- update patch description with more background to avoid confusion.
- patch #1 in the series ("net: phy: broadcom: set features explicitly
for BCM54616") is dropped: the fix should go to get_features callback
which may potentially depend on this patch.
drivers/net/phy/broadcom.c | 54 +++---
include/linux/brcmphy.h| 10 +--
2 files changed, 58 insertions(+), 6 deletions(-)
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 937d0059e8ac..fbd76a31c142 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -383,9 +383,9 @@ static int bcm5482_config_init(struct phy_device *phydev)
/*
* Select 1000BASE-X register set (primary SerDes)
*/
- reg = bcm_phy_read_shadow(phydev, BCM5482_SHD_MODE);
- bcm_phy_write_shadow(phydev, BCM5482_SHD_MODE,
-reg | BCM5482_SHD_MODE_1000BX);
+ reg = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
+ bcm_phy_write_shadow(phydev, BCM54XX_SHD_MODE,
+reg | BCM54XX_SHD_MODE_1000BX);
/*
* LED1=ACTIVITYLED, LED3=LINKSPD[2]
@@ -451,12 +451,44 @@ static int bcm5481_config_aneg(struct phy_device *phydev)
return ret;
}
+static int bcm54616s_probe(struct phy_device *phydev)
+{
+ int val, intf_sel;
+
+ val = bcm_phy_read_shadow(phydev, BCM54XX_SHD_MODE);
+ if (val < 0)
+ return val;
+
+ /* The PHY is strapped in RGMII to fiber mode when INTERF_SEL[1:0]
+* is 01b.
+*/
+ intf_sel = (val & BCM54XX_SHD_INTF_SEL_MASK) >> 1;
+ if (intf_sel == 1) {
+ val = bcm_phy_read_shadow(phydev, BCM54616S_SHD_100FX_CTRL);
+ if (val < 0)
+ return val;
+
+ /* Bit 0 of the SerDes 100-FX Control register, when set
+* to 1, sets the MII/RGMII -> 100BASE-FX configuration.
+* When this bit is set to 0, it sets the GMII/RGMII ->
+* 1000BASE-X configuration.
+*/
+ if (!(val & BCM54616S_100FX_MODE))
+ phydev->dev_flags |= PHY_BCM_FLAGS_MODE_1000BX;
+ }
+
+ return 0;
+}
+
static int bcm54616s_config_aneg(struct phy_device *phydev)
{
int ret;
/* Aneg firsly. */
- ret = genphy_config_aneg(phydev);
+ if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
+ ret = genphy_c37_config_aneg(phydev);
+ else
+ ret = genphy_config_aneg(phydev);
/* Then we can set up the delay. */
bcm54xx_config_clock_delay(phydev);
@@ -464,6 +496,18 @@ static int bcm54616s_config_aneg(struct phy_device *phydev)
return ret;
}
+static int bcm54616s_read_status(struct phy_device *phydev)
+{
+ int err;
+
+ if (phydev->dev_flags & PHY_BCM_FLAGS_MODE_1000BX)
+ err = genphy_c37_read_status(phydev);
+ else
+ err = genphy_read_status(phydev);
+
+ return err;
+}
+
static int brcm_phy_setbits(struct phy_device *phydev, int reg, int set)
{
int val;
@@ -655,6 +699,8 @@ static struct phy_driver broadcom_drivers[] = {
.config_aneg= bcm54616s_config_aneg,
.ack_interrupt = bcm_phy_ack_intr,
.config_intr
[PATCH] KVM: LAPIC: Periodically revaluate appropriate lapic_timer_advance_ns
From: Wanpeng Li
Even if for realtime CPUs, cache line bounces, frequency scaling, presence
of higher-priority RT tasks, etc can cause different response. These
interferences should be considered and periodically revaluate whether
or not the lapic_timer_advance_ns value is the best, do nothing if it is,
otherwise recaluate again.
Cc: Paolo Bonzini
Cc: Radim Krčmář
Signed-off-by: Wanpeng Li
---
arch/x86/kvm/lapic.c | 16 +++-
arch/x86/kvm/lapic.h | 1 +
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index df5cd07..8b62008 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -69,6 +69,7 @@
#define LAPIC_TIMER_ADVANCE_ADJUST_INIT 1000
/* step-by-step approximation to mitigate fluctuation */
#define LAPIC_TIMER_ADVANCE_ADJUST_STEP 8
+#define LAPIC_TIMER_ADVANCE_RECALC_PERIOD (600 * HZ)
static inline int apic_test_vector(int vec, void *bitmap)
{
@@ -1484,6 +1485,17 @@ static inline void adjust_lapic_timer_advance(struct
kvm_vcpu *vcpu,
u32 timer_advance_ns = apic->lapic_timer.timer_advance_ns;
u64 ns;
+ /* periodic revaluate */
+ if (unlikely(apic->lapic_timer.timer_advance_adjust_done)) {
+ apic->lapic_timer.recalc_timer_advance_ns = jiffies +
+ LAPIC_TIMER_ADVANCE_RECALC_PERIOD;
+ if (abs(advance_expire_delta) >
LAPIC_TIMER_ADVANCE_ADJUST_DONE) {
+ timer_advance_ns = LAPIC_TIMER_ADVANCE_ADJUST_INIT;
+ apic->lapic_timer.timer_advance_adjust_done = false;
+ } else
+ return;
+ }
+
/* too early */
if (advance_expire_delta < 0) {
ns = -advance_expire_delta * 100ULL;
@@ -1523,7 +1535,8 @@ static void __kvm_wait_lapic_expire(struct kvm_vcpu *vcpu)
if (guest_tsc < tsc_deadline)
__wait_lapic_expire(vcpu, tsc_deadline - guest_tsc);
- if (unlikely(!apic->lapic_timer.timer_advance_adjust_done))
+ if (unlikely(!apic->lapic_timer.timer_advance_adjust_done) ||
+ time_before(apic->lapic_timer.recalc_timer_advance_ns, jiffies))
adjust_lapic_timer_advance(vcpu,
apic->lapic_timer.advance_expire_delta);
}
@@ -2301,6 +2314,7 @@ int kvm_create_lapic(struct kvm_vcpu *vcpu, int
timer_advance_ns)
if (timer_advance_ns == -1) {
apic->lapic_timer.timer_advance_ns =
LAPIC_TIMER_ADVANCE_ADJUST_INIT;
apic->lapic_timer.timer_advance_adjust_done = false;
+ apic->lapic_timer.recalc_timer_advance_ns = jiffies;
} else {
apic->lapic_timer.timer_advance_ns = timer_advance_ns;
apic->lapic_timer.timer_advance_adjust_done = true;
diff --git a/arch/x86/kvm/lapic.h b/arch/x86/kvm/lapic.h
index 50053d2..31ced36 100644
--- a/arch/x86/kvm/lapic.h
+++ b/arch/x86/kvm/lapic.h
@@ -31,6 +31,7 @@ struct kvm_timer {
u32 timer_mode_mask;
u64 tscdeadline;
u64 expired_tscdeadline;
+ unsigned long recalc_timer_advance_ns;
u32 timer_advance_ns;
s64 advance_expire_delta;
atomic_t pending; /* accumulated triggered timers
*/
--
2.7.4
Re: [PATCH v2] net: tundra: tsi108: use spin_lock_irqsave instead of spin_lock_irq in IRQ context
From: Fuqian Huang Date: Fri, 9 Aug 2019 13:35:39 +0800 > As spin_unlock_irq will enable interrupts. > Function tsi108_stat_carry is called from interrupt handler tsi108_irq. > Interrupts are enabled in interrupt handler. > Use spin_lock_irqsave/spin_unlock_irqrestore instead of spin_(un)lock_irq > in IRQ context to avoid this. > > Signed-off-by: Fuqian Huang > --- > Changes in v2: > - Preserve reverse christmas tree ordering of local variables. Applied, thanks.
Re: [PATCH V4 0/9] Fixes for metadata accelreation
On 2019/8/9 下午1:15, David Miller wrote: From: Jason Wang Date: Wed, 7 Aug 2019 03:06:08 -0400 This series try to fix several issues introduced by meta data accelreation series. Please review. ... My impression is that patch #7 will be changed to use spinlocks so there will be a v5. Yes. V5 is on the way. Thanks
Re: [PATCH v2] team: Add vlan tx offload to hw_enc_features
From: YueHaibing
Date: Thu, 8 Aug 2019 14:22:47 +0800
> We should also enable team's vlan tx offload in hw_enc_features,
> pass the vlan packets to the slave devices with vlan tci, let the
> slave handle vlan tunneling offload implementation.
>
> Fixes: 3268e5cb494d ("team: Advertise tunneling offload features")
> Signed-off-by: YueHaibing
> ---
> v2: fix commit log typo
Applied and queued up for -stable.
Re: [PATCH] liquidio: Use pcie_flr() instead of reimplementing it
From: Denis Efremov Date: Thu, 8 Aug 2019 07:57:53 +0300 > octeon_mbox_process_cmd() directly writes the PCI_EXP_DEVCTL_BCR_FLR > bit, which bypasses timing requirements imposed by the PCIe spec. > This patch fixes the function to use the pcie_flr() interface instead. > > Signed-off-by: Denis Efremov Applied to net-next.
[PATCH v2] net: tundra: tsi108: use spin_lock_irqsave instead of spin_lock_irq in IRQ context
As spin_unlock_irq will enable interrupts.
Function tsi108_stat_carry is called from interrupt handler tsi108_irq.
Interrupts are enabled in interrupt handler.
Use spin_lock_irqsave/spin_unlock_irqrestore instead of spin_(un)lock_irq
in IRQ context to avoid this.
Signed-off-by: Fuqian Huang
---
Changes in v2:
- Preserve reverse christmas tree ordering of local variables.
drivers/net/ethernet/tundra/tsi108_eth.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/tundra/tsi108_eth.c
b/drivers/net/ethernet/tundra/tsi108_eth.c
index 78a7de3fb622..c62f474b6d08 100644
--- a/drivers/net/ethernet/tundra/tsi108_eth.c
+++ b/drivers/net/ethernet/tundra/tsi108_eth.c
@@ -371,9 +371,10 @@ tsi108_stat_carry_one(int carry, int carry_bit, int
carry_shift,
static void tsi108_stat_carry(struct net_device *dev)
{
struct tsi108_prv_data *data = netdev_priv(dev);
+ unsigned long flags;
u32 carry1, carry2;
- spin_lock_irq(>misclock);
+ spin_lock_irqsave(>misclock, flags);
carry1 = TSI_READ(TSI108_STAT_CARRY1);
carry2 = TSI_READ(TSI108_STAT_CARRY2);
@@ -441,7 +442,7 @@ static void tsi108_stat_carry(struct net_device *dev)
TSI108_STAT_TXPAUSEDROP_CARRY,
>tx_pause_drop);
- spin_unlock_irq(>misclock);
+ spin_unlock_irqrestore(>misclock, flags);
}
/* Read a stat counter atomically with respect to carries.
--
2.11.0
Re: [PATCH net-next] fq_codel: remove set but not used variables 'prev_ecn_mark' and 'prev_drop_count'
From: David Miller
Date: Thu, 08 Aug 2019 22:31:36 -0700 (PDT)
> From: YueHaibing
> Date: Wed, 7 Aug 2019 21:10:55 +0800
>
>> Fixes gcc '-Wunused-but-set-variable' warning:
>>
>> net/sched/sch_fq_codel.c: In function fq_codel_dequeue:
>> net/sched/sch_fq_codel.c:288:23: warning: variable prev_ecn_mark set but not
>> used [-Wunused-but-set-variable]
>> net/sched/sch_fq_codel.c:288:6: warning: variable prev_drop_count set but
>> not used [-Wunused-but-set-variable]
>>
>> They are not used since commit 77ddaff218fc ("fq_codel: Kill
>> useless per-flow dropped statistic")
>>
>> Reported-by: Hulk Robot
>> Signed-off-by: YueHaibing
>
> Do you even compile test this stuff?
>
> CC [M] net/sched/sch_fq_codel.o
> net/sched/sch_fq_codel.c: In function ‘fq_codel_dequeue’:
> net/sched/sch_fq_codel.c:309:42: error: ‘prev_drop_count’ undeclared (first
> use in this function); did you mean ‘page_ref_count’?
Never mind, this is my fault.
I was build testing the patch on the wrong tree, I'm very sorry.
Re: [PATCH net-next] fq_codel: remove set but not used variables 'prev_ecn_mark' and 'prev_drop_count'
From: YueHaibing
Date: Wed, 7 Aug 2019 21:10:55 +0800
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> net/sched/sch_fq_codel.c: In function fq_codel_dequeue:
> net/sched/sch_fq_codel.c:288:23: warning: variable prev_ecn_mark set but not
> used [-Wunused-but-set-variable]
> net/sched/sch_fq_codel.c:288:6: warning: variable prev_drop_count set but not
> used [-Wunused-but-set-variable]
>
> They are not used since commit 77ddaff218fc ("fq_codel: Kill
> useless per-flow dropped statistic")
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
Do you even compile test this stuff?
CC [M] net/sched/sch_fq_codel.o
net/sched/sch_fq_codel.c: In function ‘fq_codel_dequeue’:
net/sched/sch_fq_codel.c:309:42: error: ‘prev_drop_count’ undeclared (first use
in this function); did you mean ‘page_ref_count’?
flow->dropped += q->cstats.drop_count - prev_drop_count;
^~~
page_ref_count
net/sched/sch_fq_codel.c:309:42: note: each undeclared identifier is reported
only once for each function it appears in
net/sched/sch_fq_codel.c:310:40: error: ‘prev_ecn_mark’ undeclared (first use
in this function); did you mean ‘pmd_pfn_mask’?
flow->dropped += q->cstats.ecn_mark - prev_ecn_mark;
^
pmd_pfn_mask
make[1]: *** [scripts/Makefile.build:274: net/sched/sch_fq_codel.o] Error 1
make: *** [Makefile:1769: net/sched/sch_fq_codel.o] Error 2
Re: [PATCH net-next] net/ncsi: allow to customize BMC MAC Address offset
On 8/8/19 4:03 PM, Andrew Lunn wrote:
>> After giving it more thought, I'm thinking about adding ncsi dt node
>> with following structure (mac/ncsi similar to mac/mdio/phy):
>>
>> {
>> /* MAC properties... */
>>
>> use-ncsi;
>
> This property seems to be specific to Faraday FTGMAC100. Are you going
> to make it more generic?
I'm also using ftgmac100 on my platform, and I don't have plan to change this
property.
>> ncsi {
>> /* ncsi level properties if any */
>>
>> package@0 {
>
> You should get Rob Herring involved. This is not really describing
> hardware, so it might get rejected by the device tree maintainer.
Got it. Thank you for the sharing, and let me think it over :-)
>> 1) mac driver doesn't need to parse "mac-offset" stuff: these
>> ncsi-network-controller specific settings should be parsed in ncsi
>> stack.
>
>> 2) get_bmc_mac_address command is a channel specific command, and
>> technically people can configure different offset/formula for
>> different channels.
>
> Does that mean the NCSA code puts the interface into promiscuous mode?
> Or at least adds these unicast MAC addresses to the MAC receive
> filter? Humm, ftgmac100 only seems to support multicast address
> filtering, not unicast filters, so it must be using promisc mode, if
> you expect to receive frames using this MAC address.
Uhh, I actually didn't think too much about this: basically it's how to
configure frame filtering when there are multiple packages/channels active:
single BMC MAC or multiple BMC MAC is also allowed?
I don't have the answer yet, but will talk to NCSI expert and figure it out.
Thanks,
Tao
Re: [PATCH net-next] net: dsa: sja1105: remove set but not used variables 'tx_vid' and 'rx_vid'
From: YueHaibing
Date: Wed, 7 Aug 2019 21:08:56 +0800
> Fixes gcc '-Wunused-but-set-variable' warning:
>
> drivers/net/dsa/sja1105/sja1105_main.c: In function sja1105_fdb_dump:
> drivers/net/dsa/sja1105/sja1105_main.c:1226:14: warning:
> variable tx_vid set but not used [-Wunused-but-set-variable]
> drivers/net/dsa/sja1105/sja1105_main.c:1226:6: warning:
> variable rx_vid set but not used [-Wunused-but-set-variable]
>
> They are not used since commit 6d7c7d948a2e ("net: dsa:
> sja1105: Fix broken learning with vlan_filtering disabled")
>
> Reported-by: Hulk Robot
> Signed-off-by: YueHaibing
Applied to 'net'.
Re: [PATCH net-next v3 00/10] net: stmmac: Improvements for -next
From: Jose Abreu Date: Wed, 7 Aug 2019 10:03:08 +0200 > [ This is just a rebase of v2 into latest -next in order to avoid a merge > conflict ] > > Couple of improvements for -next tree. More info in commit logs. Series applied, thank you.
linux-next: manual merge of the usb tree with the net-next tree
Hi all,
Today's linux-next merge of the usb tree got conflicts in:
drivers/staging/Kconfig
drivers/staging/Makefile
between commit:
955315b0dc8c ("qlge: Move drivers/net/ethernet/qlogic/qlge/ to
drivers/staging/qlge/")
from the net-next tree and commit:
71ed79b0e4be ("USB: Move wusbcore and UWB to staging as it is obsolete")
from the usb tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc drivers/staging/Kconfig
index 0b8a614be11e,cf419d9c942d..
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@@ -120,6 -120,7 +120,9 @@@ source "drivers/staging/kpc2000/Kconfig
source "drivers/staging/isdn/Kconfig"
+source "drivers/staging/qlge/Kconfig"
+
+ source "drivers/staging/wusbcore/Kconfig"
+ source "drivers/staging/uwb/Kconfig"
+
endif # STAGING
diff --cc drivers/staging/Makefile
index 741152511a10,38179bc842a8..
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@@ -50,4 -50,5 +50,6 @@@ obj-$(CONFIG_EROFS_FS)+= erofs
obj-$(CONFIG_FIELDBUS_DEV) += fieldbus/
obj-$(CONFIG_KPC2000) += kpc2000/
obj-$(CONFIG_ISDN_CAPI) += isdn/
+obj-$(CONFIG_QLGE)+= qlge/
+ obj-$(CONFIG_UWB) += uwb/
+ obj-$(CONFIG_USB_WUSB)+= wusbcore/
pgpSZk06Tyqy3.pgp
Description: OpenPGP digital signature
Re: [PATCH] net: tundra: tsi108: use spin_lock_irqsave instead of spin_lock_irq in IRQ context
From: Fuqian Huang
Date: Wed, 7 Aug 2019 15:43:00 +0800
> @@ -372,8 +372,9 @@ static void tsi108_stat_carry(struct net_device *dev)
> {
> struct tsi108_prv_data *data = netdev_priv(dev);
> u32 carry1, carry2;
> + unsigned long flags;
Please preserve reverse christmas tree ordering of local variables.
Thank you.
Re: [PATCH V4 0/9] Fixes for metadata accelreation
From: Jason Wang Date: Wed, 7 Aug 2019 03:06:08 -0400 > This series try to fix several issues introduced by meta data > accelreation series. Please review. ... My impression is that patch #7 will be changed to use spinlocks so there will be a v5.
Re: [PATCH v1] Bluetooth: hci_qca: wait for Pre shutdown to command complete event before sending the Power off pulse
Hi Matthias,
On 2019-08-08 20:29, Matthias Kaehlcke wrote:
On Thu, Aug 08, 2019 at 02:55:53PM +0530, Harish Bandi wrote:
When SoC receives pre shut down command, it share the same
with other COEX shared clients. So SoC needs a short
time after sending VS pre shutdown command before
turning off the regulators and sending the power off pulse.
Signed-off-by: Harish Bandi
---
drivers/bluetooth/btqca.c | 5 +++--
drivers/bluetooth/hci_qca.c | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/btqca.c b/drivers/bluetooth/btqca.c
index 2221935..f20991e 100644
--- a/drivers/bluetooth/btqca.c
+++ b/drivers/bluetooth/btqca.c
@@ -106,8 +106,9 @@ int qca_send_pre_shutdown_cmd(struct hci_dev
*hdev)
bt_dev_dbg(hdev, "QCA pre shutdown cmd");
- skb = __hci_cmd_sync(hdev, QCA_PRE_SHUTDOWN_CMD, 0,
- NULL, HCI_INIT_TIMEOUT);
+ skb = __hci_cmd_sync_ev(hdev, QCA_PRE_SHUTDOWN_CMD, 0,
+ NULL, HCI_EV_CMD_COMPLETE, HCI_INIT_TIMEOUT);
+
The commit message does not mention this change, it only talks about
adding a delay.
[Harish] - I will add reason fo HCI_EV_CMD_COMPLETE in commit text and
post new patch.
In commit text title I mentioned about command complete event, However I
will add more details
about reason for command complete in commit text
if (IS_ERR(skb)) {
err = PTR_ERR(skb);
bt_dev_err(hdev, "QCA preshutdown_cmd failed (%d)", err);
diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c
index 16db6c0..566aa28 100644
--- a/drivers/bluetooth/hci_qca.c
+++ b/drivers/bluetooth/hci_qca.c
@@ -1386,6 +1386,8 @@ static int qca_power_off(struct hci_dev *hdev)
/* Perform pre shutdown command */
qca_send_pre_shutdown_cmd(hdev);
+ usleep_range(8000, 1);
+
qca_power_shutdown(hu);
return 0;
}
Re: [PATCH v2 2/4] soundwire: core: add device tree support for slave devices
On 08-08-19, 15:45, Srinivas Kandagatla wrote:
> This patch adds support to parsing device tree based
> SoundWire slave devices.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> drivers/soundwire/bus.c | 2 ++
> drivers/soundwire/bus.h | 1 +
> drivers/soundwire/slave.c | 47 +++
> 3 files changed, 50 insertions(+)
>
> diff --git a/drivers/soundwire/bus.c b/drivers/soundwire/bus.c
> index fe745830a261..324c54dc52fb 100644
> --- a/drivers/soundwire/bus.c
> +++ b/drivers/soundwire/bus.c
> @@ -77,6 +77,8 @@ int sdw_add_bus_master(struct sdw_bus *bus)
>*/
> if (IS_ENABLED(CONFIG_ACPI) && ACPI_HANDLE(bus->dev))
> ret = sdw_acpi_find_slaves(bus);
> + else if (IS_ENABLED(CONFIG_OF) && bus->dev->of_node)
> + ret = sdw_of_find_slaves(bus);
> else
> ret = -ENOTSUPP; /* No ACPI/DT so error out */
>
> diff --git a/drivers/soundwire/bus.h b/drivers/soundwire/bus.h
> index 3048ca153f22..ee46befedbd1 100644
> --- a/drivers/soundwire/bus.h
> +++ b/drivers/soundwire/bus.h
> @@ -15,6 +15,7 @@ static inline int sdw_acpi_find_slaves(struct sdw_bus *bus)
> }
> #endif
>
> +int sdw_of_find_slaves(struct sdw_bus *bus);
> void sdw_extract_slave_id(struct sdw_bus *bus,
> u64 addr, struct sdw_slave_id *id);
>
> diff --git a/drivers/soundwire/slave.c b/drivers/soundwire/slave.c
> index f39a5815e25d..8ab76f5d5a56 100644
> --- a/drivers/soundwire/slave.c
> +++ b/drivers/soundwire/slave.c
> @@ -2,6 +2,7 @@
> // Copyright(c) 2015-17 Intel Corporation.
>
> #include
> +#include
> #include
> #include
> #include "bus.h"
> @@ -35,6 +36,7 @@ static int sdw_slave_add(struct sdw_bus *bus,
>
> slave->dev.release = sdw_slave_release;
> slave->dev.bus = _bus_type;
> + slave->dev.of_node = of_node_get(to_of_node(fwnode));
> slave->bus = bus;
> slave->status = SDW_SLAVE_UNATTACHED;
> slave->dev_num = 0;
> @@ -112,3 +114,48 @@ int sdw_acpi_find_slaves(struct sdw_bus *bus)
> }
>
> #endif
> +
> +/*
> + * sdw_of_find_slaves() - Find Slave devices in master device tree node
> + * @bus: SDW bus instance
> + *
> + * Scans Master DT node for SDW child Slave devices and registers it.
> + */
> +int sdw_of_find_slaves(struct sdw_bus *bus)
> +{
> + struct device *dev = bus->dev;
> + struct device_node *node;
> +
> + for_each_child_of_node(bus->dev->of_node, node) {
> + struct sdw_slave_id id;
> + const char *compat = NULL;
> + int unique_id, ret;
> + int ver, mfg_id, part_id, class_id;
> +
> + compat = of_get_property(node, "compatible", NULL);
> + if (!compat)
> + continue;
Why not use of_find_compatible_node() that will return the node which is
sdw* and we dont need to checks on that..
> +
> + ret = sscanf(compat, "sdw%x,%x,%x,%x",
> + , _id, _id, _id);
> + if (ret != 4) {
> + dev_err(dev, "Manf ID & Product code not found %s\n",
> + compat);
> + continue;
> + }
> +
> + ret = of_property_read_u32(node, "sdw-instance-id", _id);
> + if (ret) {
> + dev_err(dev, "Instance id not found:%d\n", ret);
> + continue;
> + }
> +
> + id.sdw_version = ver - 0xF;
> + id.unique_id = unique_id;
> + id.mfg_id = mfg_id;
> + id.part_id = part_id;
> + id.class_id = class_id;
empty line here please
> + sdw_slave_add(bus, , of_fwnode_handle(node));
> + }
and here as well
> + return 0;
> +}
> --
> 2.21.0
--
~Vinod
Re: [PATCH net-next v5 2/3] net: phy: add support for clause 37 auto-negotiation
On 8/8/19 9:58 PM, Vladimir Oltean wrote: > On Fri, 9 Aug 2019 at 02:48, Tao Ren wrote: >> >> From: Heiner Kallweit >> >> This patch adds support for clause 37 1000Base-X auto-negotiation. >> It's compile-tested only as I don't have fiber equipment. >> >> Signed-off-by: Heiner Kallweit >> --- > > This needs your signed-off-by as well. I see. I didn't understand signed-off-by correctly and removed myself from the list explicitly. Adding it back now.. Thanks, Tao
Re: [PATCH v2] bonding: Add vlan tx offload to hw_enc_features
From: YueHaibing
Date: Wed, 7 Aug 2019 10:19:59 +0800
> As commit 30d8177e8ac7 ("bonding: Always enable vlan tx offload")
> said, we should always enable bonding's vlan tx offload, pass the
> vlan packets to the slave devices with vlan tci, let them to handle
> vlan implementation.
>
> Now if encapsulation protocols like VXLAN is used, skb->encapsulation
> may be set, then the packet is passed to vlan device which based on
> bonding device. However in netif_skb_features(), the check of
> hw_enc_features:
>
>if (skb->encapsulation)
> features &= dev->hw_enc_features;
>
> clears NETIF_F_HW_VLAN_CTAG_TX/NETIF_F_HW_VLAN_STAG_TX. This results
> in same issue in commit 30d8177e8ac7 like this:
>
> vlan_dev_hard_start_xmit
> -->dev_queue_xmit
> -->validate_xmit_skb
> -->netif_skb_features //NETIF_F_HW_VLAN_CTAG_TX is cleared
> -->validate_xmit_vlan
> -->__vlan_hwaccel_push_inside //skb->tci is cleared
> ...
> --> bond_start_xmit
>--> bond_xmit_hash //BOND_XMIT_POLICY_ENCAP34
> --> __skb_flow_dissect // nhoff point to IP header
> --> case htons(ETH_P_8021Q)
> // skb_vlan_tag_present is false, so
> vlan = __skb_header_pointer(skb, nhoff, sizeof(_vlan),
> //vlan point to ip header wrongly
>
> Fixes: b2a103e6d0af ("bonding: convert to ndo_fix_features")
> Signed-off-by: YueHaibing
> Acked-by: Jay Vosburgh
Applied and queued up for -stable.
Re: [PATCH v2] net: sched: sch_taprio: fix memleak in error path for sched list parse
From: Ivan Khoronzhuk
Date: Wed, 7 Aug 2019 01:45:40 +0300
> In error case, all entries should be freed from the sched list
> before deleting it. For simplicity use rcu way.
>
> Fixes: 5a781ccbd19e46 ("tc: Add support for configuring the taprio scheduler")
> Acked-by: Vinicius Costa Gomes
> Signed-off-by: Ivan Khoronzhuk
Applied and queued up for -stable, thank you.
Re: [PATCH v2 1/4] dt-bindings: soundwire: add slave bindings
On 08-08-19, 15:45, Srinivas Kandagatla wrote:
> This patch adds bindings for Soundwire Slave devices which includes how
> SoundWire enumeration address is represented in SoundWire slave device
> tree nodes.
>
> Signed-off-by: Srinivas Kandagatla
> ---
> .../devicetree/bindings/soundwire/slave.txt | 46 +++
> 1 file changed, 46 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/soundwire/slave.txt
>
> diff --git a/Documentation/devicetree/bindings/soundwire/slave.txt
> b/Documentation/devicetree/bindings/soundwire/slave.txt
> new file mode 100644
> index ..b8e8d34bbc92
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/soundwire/slave.txt
> @@ -0,0 +1,46 @@
> +SoundWire slave device bindings.
> +
> +SoundWire is a 2-pin multi-drop interface with data and clock line.
> +It facilitates development of low cost, efficient, high performance systems.
> +
> +SoundWire slave devices:
> +Every SoundWire controller node can contain zero or more child nodes
> +representing slave devices on the bus. Every SoundWire slave device is
> +uniquely determined by the enumeration address containing 5 fields:
> +SoundWire Version, Instance ID, Manufacturer ID, Part ID and Class ID
> +for a device. Addition to below required properties, child nodes can
It would help to list them rather than free flowing text
> +have device specific bindings.
> +
> +Required property for SoundWire child node if it is present:
As said earlier, lets make it "Required properties:"
> +- compatible: "sdwVER,MFD,PID,CID". The textual representation of
> + SoundWire Enumeration address comprising SoundWire
> + Version, Manufacturer ID, Part ID and Class ID,
> + shall be in lower-case hexadecimal with leading
> + zeroes suppressed.
> + Version number '0x10' represents SoundWire 1.0
> + Version number '0x11' represents SoundWire 1.1
> + ex: "sdw10,0217,2010,0"
> +
> +- sdw-instance-id: Should be ('Instance ID') from SoundWire
> + Enumeration Address. Instance ID is for the cases
> + where multiple Devices of the same type or Class
> + are attached to the bus.
> +
> +SoundWire example for Qualcomm's SoundWire controller:
> +
> +soundwire@c2d {
> + compatible = "qcom,soundwire-v1.5.0"
> + reg = <0x0c2d 0x2000>;
> +
> + spkr_left:wsa8810-left{
> + compatible = "sdw10,0217,2010,0";
> + sdw-instance-id = <1>;
> + ...
> + };
> +
> + spkr_right:wsa8810-right{
> + compatible = "sdw10,0217,2010,0";
> + sdw-instance-id = <2>;
> + ...
> + };
> +};
> --
> 2.21.0
--
~Vinod
Re: [PATCH net-next v5 2/3] net: phy: add support for clause 37 auto-negotiation
On Fri, 9 Aug 2019 at 02:48, Tao Ren wrote:
>
> From: Heiner Kallweit
>
> This patch adds support for clause 37 1000Base-X auto-negotiation.
> It's compile-tested only as I don't have fiber equipment.
>
> Signed-off-by: Heiner Kallweit
> ---
This needs your signed-off-by as well.
> drivers/net/phy/phy_device.c | 139 +++
> include/linux/phy.h | 5 ++
> 2 files changed, 144 insertions(+)
>
> diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
> index 252a712d1b2b..7c5315302937 100644
> --- a/drivers/net/phy/phy_device.c
> +++ b/drivers/net/phy/phy_device.c
> @@ -1617,6 +1617,40 @@ static int genphy_config_advert(struct phy_device
> *phydev)
> return changed;
> }
>
> +/**
> + * genphy_c37_config_advert - sanitize and advertise auto-negotiation
> parameters
> + * @phydev: target phy_device struct
> + *
> + * Description: Writes MII_ADVERTISE with the appropriate values,
> + * after sanitizing the values to make sure we only advertise
> + * what is supported. Returns < 0 on error, 0 if the PHY's advertisement
> + * hasn't changed, and > 0 if it has changed. This function is intended
> + * for Clause 37 1000Base-X mode.
> + */
> +static int genphy_c37_config_advert(struct phy_device *phydev)
> +{
> + u16 adv = 0;
> +
> + /* Only allow advertising what this PHY supports */
> + linkmode_and(phydev->advertising, phydev->advertising,
> +phydev->supported);
> +
> + if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
> + phydev->advertising))
> + adv |= ADVERTISE_1000XFULL;
> + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Pause_BIT,
> + phydev->advertising))
> + adv |= ADVERTISE_1000XPAUSE;
> + if (linkmode_test_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT,
> + phydev->advertising))
> + adv |= ADVERTISE_1000XPSE_ASYM;
> +
> + return phy_modify_changed(phydev, MII_ADVERTISE,
> + ADVERTISE_1000XFULL | ADVERTISE_1000XPAUSE |
> + ADVERTISE_1000XHALF |
> ADVERTISE_1000XPSE_ASYM,
> + adv);
> +}
> +
> /**
> * genphy_config_eee_advert - disable unwanted eee mode advertisement
> * @phydev: target phy_device struct
> @@ -1726,6 +1760,54 @@ int genphy_config_aneg(struct phy_device *phydev)
> }
> EXPORT_SYMBOL(genphy_config_aneg);
>
> +/**
> + * genphy_c37_config_aneg - restart auto-negotiation or write BMCR
> + * @phydev: target phy_device struct
> + *
> + * Description: If auto-negotiation is enabled, we configure the
> + * advertising, and then restart auto-negotiation. If it is not
> + * enabled, then we write the BMCR. This function is intended
> + * for use with Clause 37 1000Base-X mode.
> + */
> +int genphy_c37_config_aneg(struct phy_device *phydev)
> +{
> + int err, changed;
> +
> + if (AUTONEG_ENABLE != phydev->autoneg)
> + return genphy_setup_forced(phydev);
> +
> + err = phy_modify(phydev, MII_BMCR, BMCR_SPEED1000 | BMCR_SPEED100,
> +BMCR_SPEED1000);
> + if (err)
> + return err;
> +
> + changed = genphy_c37_config_advert(phydev);
> + if (changed < 0) /* error */
> + return changed;
> +
> + if (!changed) {
> + /* Advertisement hasn't changed, but maybe aneg was never on
> to
> +* begin with? Or maybe phy was isolated?
> +*/
> + int ctl = phy_read(phydev, MII_BMCR);
> +
> + if (ctl < 0)
> + return ctl;
> +
> + if (!(ctl & BMCR_ANENABLE) || (ctl & BMCR_ISOLATE))
> + changed = 1; /* do restart aneg */
> + }
> +
> + /* Only restart aneg if we are advertising something different
> +* than we were before.
> +*/
> + if (changed > 0)
> + return genphy_restart_aneg(phydev);
> +
> + return 0;
> +}
> +EXPORT_SYMBOL(genphy_c37_config_aneg);
> +
> /**
> * genphy_aneg_done - return auto-negotiation status
> * @phydev: target phy_device struct
> @@ -1864,6 +1946,63 @@ int genphy_read_status(struct phy_device *phydev)
> }
> EXPORT_SYMBOL(genphy_read_status);
>
> +/**
> + * genphy_c37_read_status - check the link status and update current link
> state
> + * @phydev: target phy_device struct
> + *
> + * Description: Check the link, then figure out the current state
> + * by comparing what we advertise with what the link partner
> + * advertises. This function is for Clause 37 1000Base-X mode.
> + */
> +int genphy_c37_read_status(struct phy_device *phydev)
> +{
> + int lpa, err, old_link = phydev->link;
> +
> + /* Update the link, but return if there was an error */
> + err = genphy_update_link(phydev);
> + if (err)
> +
Re: [PATCH v2 0/4] ASoC: codecs: Add WSA881x Smart Speaker amplifier support
On 08-08-19, 15:45, Srinivas Kandagatla wrote: > This patchset adds support to WSA8810/WSA8815 Class-D Smart Speaker > Amplifier which is SoundWire interfaced. > This also adds support to some missing bits in SoundWire bus layer like > Device Tree support and module_sdw_driver macro. ^^^ That part we already applied :D > This patchset along with DB845c machine driver and WCD934x codec driver > has been tested on SDM845 SoC based DragonBoard DB845c with two > WSA8810 speakers. > > Most of the code in this driver is rework of Qualcomm downstream drivers > used in Andriod. Credits to Banajit Goswami and Patrick Lai's Team. > > TODO: > Add thermal sensor support in WSA881x. > > This patchset also depends on the soundwire Kconfig patch > https://lkml.org/lkml/2019/7/18/834 from Pierre > > Thanks, > srini > > Changes since v1 RFC: > - bindings document renamed to slave.txt > - fix error code from dt slave parsing > > Srinivas Kandagatla (4): > dt-bindings: soundwire: add slave bindings > soundwire: core: add device tree support for slave devices > dt-bindings: ASoC: Add WSA881x bindings > ASoC: codecs: add wsa881x amplifier support > > .../bindings/sound/qcom,wsa881x.txt | 27 + > .../devicetree/bindings/soundwire/slave.txt | 46 + > drivers/soundwire/bus.c |2 + > drivers/soundwire/bus.h |1 + > drivers/soundwire/slave.c | 47 + > sound/soc/codecs/Kconfig | 10 + > sound/soc/codecs/Makefile |2 + > sound/soc/codecs/wsa881x.c| 1160 + > 8 files changed, 1295 insertions(+) > create mode 100644 Documentation/devicetree/bindings/sound/qcom,wsa881x.txt > create mode 100644 Documentation/devicetree/bindings/soundwire/slave.txt > create mode 100644 sound/soc/codecs/wsa881x.c > > -- > 2.21.0 -- ~Vinod
Re: [PATCH net] net: phy: rtl8211f: do a double read to get real time link status
On 2019/8/9 4:34, Andrew Lunn wrote: > On Thu, Aug 08, 2019 at 10:01:39PM +0200, Heiner Kallweit wrote: >> On 08.08.2019 21:40, Andrew Lunn wrote: @@ -568,6 +568,11 @@ int phy_start_aneg(struct phy_device *phydev) if (err < 0) goto out_unlock; + /* The PHY may not yet have cleared aneg-completed and link-up bit + * w/o this delay when the following read is done. + */ + usleep_range(1000, 2000); + >>> >>> Hi Heiner >>> >>> Does 802.3 C22 say anything about this? >>> >> C22 says: >> "The Auto-Negotiation process shall be restarted by setting bit 0.9 to a >> logic one. This bit is self- >> clearing, and a PHY shall return a value of one in bit 0.9 until the >> Auto-Negotiation process has been >> initiated." >> >> Maybe we should read bit 0.9 in genphy_update_link() after having read BMSR >> and report >> aneg-complete and link-up as false (no matter of their current value) if 0.9 >> is set. > > Yes. That sounds sensible. > > Andrew > > . > Hi Heiner: I have test more than 50 times, it works. Previously less than 20 times must be recurrence. so I think this patch solved the problem. And I checked about 40 times of the time gap between read and autoneg started, all of them is more than 2ms, as below: kworker/u257:1-670 [015] 27.182632: mdio_access: mii-:bd:00.3 write phy:0x07 reg:0x00 val:0x1240 kworker/u257:1-670 [015] 27.184670: mdio_access: mii-:bd:00.3 read phy:0x07 reg:0x01 val:0x7989
Re: [PATCH v2 1/4] dt-bindings: soundwire: add slave bindings
On 08-08-19, 20:52, Mark Brown wrote:
> On Thu, Aug 08, 2019 at 05:48:56PM +0100, Srinivas Kandagatla wrote:
> > On 08/08/2019 16:58, Pierre-Louis Bossart wrote:
>
> > > > +- sdw-instance-id: Should be ('Instance ID') from SoundWire
> > > > + Enumeration Address. Instance ID is for the cases
> > > > + where multiple Devices of the same type or Class
> > > > + are attached to the bus.
>
> > > so it is actually required if you have a single Slave device? Or is it
> > > only required when you have more than 1 device of the same type?
>
> > This is mandatory for any slave device!
>
> If it's mandatory the wording is a bit unclear. How about something
> like:
>
> Should be ('Instance ID') from the SoundWire Enumeration
> Address. This must always be provided, if multiple devices
> with the same type or class or attached to the bus each
> instance must have a distinct value.
That helps to make it clear.
Also the section of properties starts with Mandatory property, it should
be made Mandatory Properties instead, like in other binding docs to make
it clear that properties mentioned in the section are mandatory
--
~Vinod
Re: [PATCH] soundwire: fix regmap dependencies and align with other serial links
On 18-07-19, 18:02, Pierre-Louis Bossart wrote: > The existing code has a mixed select/depend usage which makes no sense. > > config SOUNDWIRE_BUS >tristate >select REGMAP_SOUNDWIRE > > config REGMAP_SOUNDWIRE > tristate > depends on SOUNDWIRE_BUS > > Let's remove one layer of Kconfig definitions and align with the > solutions used by all other serial links. Applied, thanks -- ~Vinod
Re: [PATCH v1] Bluetooth: hci_qca: wait for Pre shutdown to command complete event before sending the Power off pulse
Hi Bala,
On 2019-08-08 16:25, Balakrishna Godavarthi wrote:
Hi Harish,
On 2019-08-08 14:55, Harish Bandi wrote:
When SoC receives pre shut down command, it share the same
with other COEX shared clients. So SoC needs a short
time after sending VS pre shutdown command before
turning off the regulators and sending the power off pulse.
Signed-off-by: Harish Bandi
---
drivers/bluetooth/btqca.c | 5 +++--
drivers/bluetooth/hci_qca.c | 2 ++
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/bluetooth/btqca.c b/drivers/bluetooth/btqca.c
index 2221935..f20991e 100644
--- a/drivers/bluetooth/btqca.c
+++ b/drivers/bluetooth/btqca.c
@@ -106,8 +106,9 @@ int qca_send_pre_shutdown_cmd(struct hci_dev
*hdev)
bt_dev_dbg(hdev, "QCA pre shutdown cmd");
- skb = __hci_cmd_sync(hdev, QCA_PRE_SHUTDOWN_CMD, 0,
- NULL, HCI_INIT_TIMEOUT);
+ skb = __hci_cmd_sync_ev(hdev, QCA_PRE_SHUTDOWN_CMD, 0,
+ NULL, HCI_EV_CMD_COMPLETE, HCI_INIT_TIMEOUT);
[Bala]: nit: can you also add reason in commit text for adding
HCI_EV_CMD_COMPLETE
[Harish] - I will add reason fo HCI_EV_CMD_COMPLETE in commit text and
post new patch.
+
if (IS_ERR(skb)) {
err = PTR_ERR(skb);
bt_dev_err(hdev, "QCA preshutdown_cmd failed (%d)", err);
diff --git a/drivers/bluetooth/hci_qca.c b/drivers/bluetooth/hci_qca.c
index 16db6c0..566aa28 100644
--- a/drivers/bluetooth/hci_qca.c
+++ b/drivers/bluetooth/hci_qca.c
@@ -1386,6 +1386,8 @@ static int qca_power_off(struct hci_dev *hdev)
/* Perform pre shutdown command */
qca_send_pre_shutdown_cmd(hdev);
+ usleep_range(8000, 1);
+
qca_power_shutdown(hu);
return 0;
}
Reviewed-by: Balakrishna Godavarthi
Thanks,
Harish
Re: [PATCH v3 1/2] PCI: PCIe: ASPM: Introduce pcie_aspm_enabled()
s|PCI: PCIe: ASPM: Introduce pcie_aspm_enabled()|PCI/ASPM: Add
pcie_aspm_enabled()|
to match previous history.
On Thu, Aug 08, 2019 at 11:55:07PM +0200, Rafael J. Wysocki wrote:
> From: Rafael J. Wysocki
>
> Add a function checking whether or not PCIe ASPM has been enabled for
> a given device.
>
> It will be used by the NVMe driver to decide how to handle the
> device during system suspend.
>
> Signed-off-by: Rafael J. Wysocki
Acked-by: Bjorn Helgaas
> ---
>
> v2 -> v3:
> * Make the new function return bool.
> * Change its name back to pcie_aspm_enabled().
> * Fix kerneldoc comment formatting.
>
> -> v2:
> * Move the PCI/PCIe ASPM changes to a separate patch.
> * Add the _mask suffix to the new function name.
> * Add EXPORT_SYMBOL_GPL() to the new function.
> * Avoid adding an unnecessary blank line.
>
> ---
> drivers/pci/pcie/aspm.c | 20
> include/linux/pci.h |3 +++
> 2 files changed, 23 insertions(+)
>
> Index: linux-pm/drivers/pci/pcie/aspm.c
> ===
> --- linux-pm.orig/drivers/pci/pcie/aspm.c
> +++ linux-pm/drivers/pci/pcie/aspm.c
> @@ -1170,6 +1170,26 @@ static int pcie_aspm_get_policy(char *bu
> module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
> NULL, 0644);
>
> +/**
> + * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
> + * @pci_device: Target device.
> + */
> +bool pcie_aspm_enabled(struct pci_dev *pci_device)
The typical name in this file is "pdev".
> +{
> + struct pci_dev *bridge = pci_upstream_bridge(pci_device);
> + bool ret;
> +
> + if (!bridge)
> + return false;
> +
> + mutex_lock(_lock);
> + ret = bridge->link_state ? !!bridge->link_state->aspm_enabled : false;
> + mutex_unlock(_lock);
> +
> + return ret;
> +}
> +EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
> +
> #ifdef CONFIG_PCIEASPM_DEBUG
> static ssize_t link_state_show(struct device *dev,
> struct device_attribute *attr,
> Index: linux-pm/include/linux/pci.h
> ===
> --- linux-pm.orig/include/linux/pci.h
> +++ linux-pm/include/linux/pci.h
> @@ -1567,8 +1567,11 @@ extern bool pcie_ports_native;
>
> #ifdef CONFIG_PCIEASPM
> bool pcie_aspm_support_enabled(void);
> +bool pcie_aspm_enabled(struct pci_dev *pci_device);
> #else
> static inline bool pcie_aspm_support_enabled(void) { return false; }
> +static inline bool pcie_aspm_enabled(struct pci_dev *pci_device)
> +{ return false; }
> #endif
>
> #ifdef CONFIG_PCIEAER
>
>
>
[PATCH V15 12/13] phy: tegra: Add PCIe PIPE2UPHY support
Synopsys DesignWare core based PCIe controllers in Tegra 194 SoC interface
with Universal PHY (UPHY) module through a PIPE2UPHY (P2U) module.
For each PCIe lane of a controller, there is a P2U unit instantiated at
hardware level. This driver provides support for the programming required
for each P2U that is going to be used for a PCIe controller.
Signed-off-by: Vidya Sagar
Acked-by: Kishon Vijay Abraham I
---
V15:
* None
V14:
* None
V13:
* None
V12:
* None
V11:
* Replaced PTR_ERR_OR_ZERO() with PTR_ERR() as the check for zero is already
present in the code.
V10:
* Used _relaxed() versions of readl() & writel()
V9:
* Made it dependent on ARCH_TEGRA_194_SOC directly instead of ARCH_TEGRA
V8:
* Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c
V7:
* None
V6:
* Addressed review comments from Thierry
V5:
* None
V4:
* Rebased on top of linux-next top of the tree
V3:
* Replaced spaces with tabs in Kconfig file
* Sorted header file inclusion alphabetically
V2:
* Added COMPILE_TEST in Kconfig
* Removed empty phy_ops implementations
* Modified code according to DT documentation file modifications
drivers/phy/tegra/Kconfig| 7 ++
drivers/phy/tegra/Makefile | 1 +
drivers/phy/tegra/phy-tegra194-p2u.c | 120 +++
3 files changed, 128 insertions(+)
create mode 100644 drivers/phy/tegra/phy-tegra194-p2u.c
diff --git a/drivers/phy/tegra/Kconfig b/drivers/phy/tegra/Kconfig
index e516967d695b..f9817c3ae85f 100644
--- a/drivers/phy/tegra/Kconfig
+++ b/drivers/phy/tegra/Kconfig
@@ -7,3 +7,10 @@ config PHY_TEGRA_XUSB
To compile this driver as a module, choose M here: the module will
be called phy-tegra-xusb.
+
+config PHY_TEGRA194_P2U
+ tristate "NVIDIA Tegra194 PIPE2UPHY PHY driver"
+ depends on ARCH_TEGRA_194_SOC || COMPILE_TEST
+ select GENERIC_PHY
+ help
+ Enable this to support the P2U (PIPE to UPHY) that is part of Tegra
19x SOCs.
diff --git a/drivers/phy/tegra/Makefile b/drivers/phy/tegra/Makefile
index 64ccaeacb631..320dd389f34d 100644
--- a/drivers/phy/tegra/Makefile
+++ b/drivers/phy/tegra/Makefile
@@ -6,3 +6,4 @@ phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_124_SOC) += xusb-tegra124.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_132_SOC) += xusb-tegra124.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_210_SOC) += xusb-tegra210.o
phy-tegra-xusb-$(CONFIG_ARCH_TEGRA_186_SOC) += xusb-tegra186.o
+obj-$(CONFIG_PHY_TEGRA194_P2U) += phy-tegra194-p2u.o
diff --git a/drivers/phy/tegra/phy-tegra194-p2u.c
b/drivers/phy/tegra/phy-tegra194-p2u.c
new file mode 100644
index ..7042bed9feaa
--- /dev/null
+++ b/drivers/phy/tegra/phy-tegra194-p2u.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * P2U (PIPE to UPHY) driver for Tegra T194 SoC
+ *
+ * Copyright (C) 2019 NVIDIA Corporation.
+ *
+ * Author: Vidya Sagar
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define P2U_PERIODIC_EQ_CTRL_GEN3 0xc0
+#define P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN BIT(0)
+#define P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN BIT(1)
+#define P2U_PERIODIC_EQ_CTRL_GEN4 0xc4
+#define P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN BIT(1)
+
+#define P2U_RX_DEBOUNCE_TIME 0xa4
+#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK 0x
+#define P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL160
+
+struct tegra_p2u {
+ void __iomem *base;
+};
+
+static inline void p2u_writel(struct tegra_p2u *phy, const u32 value,
+ const u32 reg)
+{
+ writel_relaxed(value, phy->base + reg);
+}
+
+static inline u32 p2u_readl(struct tegra_p2u *phy, const u32 reg)
+{
+ return readl_relaxed(phy->base + reg);
+}
+
+static int tegra_p2u_power_on(struct phy *x)
+{
+ struct tegra_p2u *phy = phy_get_drvdata(x);
+ u32 val;
+
+ val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN3);
+ val &= ~P2U_PERIODIC_EQ_CTRL_GEN3_PERIODIC_EQ_EN;
+ val |= P2U_PERIODIC_EQ_CTRL_GEN3_INIT_PRESET_EQ_TRAIN_EN;
+ p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN3);
+
+ val = p2u_readl(phy, P2U_PERIODIC_EQ_CTRL_GEN4);
+ val |= P2U_PERIODIC_EQ_CTRL_GEN4_INIT_PRESET_EQ_TRAIN_EN;
+ p2u_writel(phy, val, P2U_PERIODIC_EQ_CTRL_GEN4);
+
+ val = p2u_readl(phy, P2U_RX_DEBOUNCE_TIME);
+ val &= ~P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_MASK;
+ val |= P2U_RX_DEBOUNCE_TIME_DEBOUNCE_TIMER_VAL;
+ p2u_writel(phy, val, P2U_RX_DEBOUNCE_TIME);
+
+ return 0;
+}
+
+static const struct phy_ops ops = {
+ .power_on = tegra_p2u_power_on,
+ .owner = THIS_MODULE,
+};
+
+static int tegra_p2u_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct device *dev = >dev;
+ struct phy *generic_phy;
+ struct tegra_p2u *phy;
+ struct resource *res;
+
+ phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL);
[PATCH V15 13/13] PCI: tegra: Add Tegra194 PCIe support
Add support for Synopsys DesignWare core IP based PCIe host controller present in Tegra194 SoC. Signed-off-by: Vidya Sagar Acked-by: Thierry Reding --- V15: * Refactored the code to use only tegra_bpmp_transfer() API in .probe() as well as .resume_noirq() path. This is made possible by http://patchwork.ozlabs.org/patch/1140973/ change. V14: * Addressed Lorenzo's review comments * Removed unused header files * Gathered all ASPM related programming under one define * Refactored tegra_pcie_dw_host_init() API to avoid using upward goto statement * Started using dw_pcie_wait_for_link() API for link up check * Modified condition to call tegra_bpmp_transfer_atomic()/tegra_bpmp_transfer() APIs V13: * Modified according to modifications in PATCH V13 01/12 V12: * None V11: * None V10: * Used _relaxed() versions of readl() & writel() V9: * Made it dependent on ARCH_TEGRA_194_SOC directly V8: * Addressed review comments from Thierry V7: * Removed code around "nvidia,disable-aspm-states" DT property * Refactored code to remove code duplication V6: * Addressed review comments from Thierry V5: * None V4: * None V3: * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed' * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios' * Removed .runtime_suspend() & .runtime_resume() implementations V2: * Made CONFIG_PCIE_TEGRA194 as 'm' by default from its previous 'y' state * Modified code as per changes made to DT documentation * Refactored code to address Bjorn & Thierry's review comments * Added goto to avoid recursion in tegra_pcie_dw_host_init() API * Merged .scan_bus() of dw_pcie_host_ops implementation to tegra_pcie_dw_host_init() API drivers/pci/controller/dwc/Kconfig | 10 + drivers/pci/controller/dwc/Makefile|1 + drivers/pci/controller/dwc/pcie-tegra194.c | 1620 3 files changed, 1631 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-tegra194.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 6ea778ae4877..49475f5c42c3 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -220,6 +220,16 @@ config PCI_MESON and therefore the driver re-uses the DesignWare core functions to implement the driver. +config PCIE_TEGRA194 + tristate "NVIDIA Tegra194 (and later) PCIe controller" + depends on ARCH_TEGRA_194_SOC || COMPILE_TEST + depends on PCI_MSI_IRQ_DOMAIN + select PCIE_DW_HOST + select PHY_TEGRA194_P2U + help + Say Y here if you want support for DesignWare core based PCIe host + controller found in NVIDIA Tegra194 SoC. + config PCIE_UNIPHIER bool "Socionext UniPhier PCIe controllers" depends on ARCH_UNIPHIER || COMPILE_TEST diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index b085dfd4fab7..b30336181d46 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o obj-$(CONFIG_PCI_MESON) += pci-meson.o +obj-$(CONFIG_PCIE_TEGRA194) += pcie-tegra194.o obj-$(CONFIG_PCIE_UNIPHIER) += pcie-uniphier.o # The following drivers are for devices that use the generic ACPI diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c new file mode 100644 index ..05352d34a33a --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -0,0 +1,1620 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * PCIe host controller driver for Tegra194 SoC + * + * Copyright (C) 2019 NVIDIA Corporation. + * + * Author: Vidya Sagar + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "pcie-designware.h" +#include +#include +#include "../../pci.h" + +#define APPL_PINMUX0x0 +#define APPL_PINMUX_PEX_RSTBIT(0) +#define APPL_PINMUX_CLKREQ_OVERRIDE_EN BIT(2) +#define APPL_PINMUX_CLKREQ_OVERRIDEBIT(3) +#define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN BIT(4) +#define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE BIT(5) +#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN BIT(9) +#define APPL_PINMUX_CLKREQ_OUT_OVRDBIT(10) + +#define APPL_CTRL 0x4 +#define APPL_CTRL_SYS_PRE_DET_STATEBIT(6) +#define APPL_CTRL_LTSSM_EN BIT(7) +#define APPL_CTRL_HW_HOT_RST_ENBIT(20) +#define APPL_CTRL_HW_HOT_RST_MODE_MASK GENMASK(1, 0) +#define APPL_CTRL_HW_HOT_RST_MODE_SHIFT22 +#define APPL_CTRL_HW_HOT_RST_MODE_IMDT_RST 0x1 + +#define APPL_INTR_EN_L0_0 0x8
[PATCH V15 11/13] dt-bindings: PHY: P2U: Add Tegra194 P2U block
Add support for Tegra194 P2U (PIPE to UPHY) module block which is a glue
module instantiated one for each PCIe lane between Synopsys DesignWare core
based PCIe IP and Universal PHY block.
Signed-off-by: Vidya Sagar
Reviewed-by: Rob Herring
Acked-by: Thierry Reding
Acked-by: Kishon Vijay Abraham I
---
V15:
* None
V14:
* None
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* None
V8:
* None
V7:
* None
V6:
* Added Sob
* Changed node name from "p2u@" to "phy@"
V5:
* None
V4:
* None
V3:
* Changed node label to reflect new format that includes either 'hsio' or
'nvhs' in its name to reflect which UPHY brick they belong to
V2:
* This is a new patch in v2 series
.../bindings/phy/phy-tegra194-p2u.txt | 28 +++
1 file changed, 28 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
diff --git a/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
new file mode 100644
index ..d23ff90baad5
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/phy-tegra194-p2u.txt
@@ -0,0 +1,28 @@
+NVIDIA Tegra194 P2U binding
+
+Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
+Speed) each interfacing with 12 and 8 P2U instances respectively.
+A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
+interface and PHY of HSIO/NVHS bricks. Each P2U instance represents one PCIe
+lane.
+
+Required properties:
+- compatible: For Tegra19x, must contain "nvidia,tegra194-p2u".
+- reg: Should be the physical address space and length of respective each P2U
+ instance.
+- reg-names: Must include the entry "ctl".
+
+Required properties for PHY port node:
+- #phy-cells: Defined by generic PHY bindings. Must be 0.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Example:
+
+p2u_hsio_0: phy@3e1 {
+ compatible = "nvidia,tegra194-p2u";
+ reg = <0x03e1 0x1>;
+ reg-names = "ctl";
+
+ #phy-cells = <0>;
+};
--
2.17.1
[PATCH V15 03/13] PCI: dwc: Perform dbi regs write lock towards the end
Some of DesignWare core's DBI registers (a.k.a configuration space
registers) are write-protected with a lock without enabling which they are
read-only by default. These write-protected registers are implementation
specific. Tegra194's BAR-0 register which is at offset 0x10 in the
configuration space is an example. Current implementation in
dw_pcie_setup_rc() API attempts to unlock those write-protected registers
whenever they are updated and lock them back again for writing. This patch
attempts to unlock all such write-protected registers for writing in the
beginning of the API once and lock them back again towards the end to avoid
bloating the API with multiple unlock/lock sequences for all those
write-protected registers.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
Acked-by: Jingoo Han
---
V15:
* None
V14:
* None
V13:
* None
V12:
* Modified commit message to make it explicit that write-protected registers are
implementation specific.
V11:
* None
V10:
* None
V9:
* None
V8:
* None
V7:
* None
V6:
* Moved write enable to the beginning of the API and write disable to the end
V5:
* None
V4:
* None
V3:
* None
V2:
* None
drivers/pci/controller/dwc/pcie-designware-host.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c
b/drivers/pci/controller/dwc/pcie-designware-host.c
index f93252d0da5b..d3156446ff27 100644
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -628,6 +628,12 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
u32 val, ctrl, num_ctrls;
struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
+ /*
+* Enable DBI read-only registers for writing/updating configuration.
+* Write permission gets disabled towards the end of this function.
+*/
+ dw_pcie_dbi_ro_wr_en(pci);
+
dw_pcie_setup(pci);
if (!pp->ops->msi_host_init) {
@@ -650,12 +656,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0x);
/* Setup interrupt pins */
- dw_pcie_dbi_ro_wr_en(pci);
val = dw_pcie_readl_dbi(pci, PCI_INTERRUPT_LINE);
val &= 0x00ff;
val |= 0x0100;
dw_pcie_writel_dbi(pci, PCI_INTERRUPT_LINE, val);
- dw_pcie_dbi_ro_wr_dis(pci);
/* Setup bus numbers */
val = dw_pcie_readl_dbi(pci, PCI_PRIMARY_BUS);
@@ -687,15 +691,13 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
- /* Enable write permission for the DBI read-only register */
- dw_pcie_dbi_ro_wr_en(pci);
/* Program correct class for RC */
dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
- /* Better disable write permission right after the update */
- dw_pcie_dbi_ro_wr_dis(pci);
dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, );
val |= PORT_LOGIC_SPEED_CHANGE;
dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
+
+ dw_pcie_dbi_ro_wr_dis(pci);
}
EXPORT_SYMBOL_GPL(dw_pcie_setup_rc);
--
2.17.1
[PATCH V15 05/13] PCI: dwc: Add ext config space capability search API
Add extended configuration space capability search API using struct dw_pcie *
pointer.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Acked-by: Thierry Reding
---
V15:
* None
V14:
* Added a full stop(.) at the end of commit message.
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* Added Acked-by from Thierry
V8:
* Changed data types of return and arguments to be inline with data being
returned
and passed.
V7:
* None
V6:
* None
V5:
* None
V4:
* None
V3:
* None
V2:
* This is a new patch in v2 series
drivers/pci/controller/dwc/pcie-designware.c | 41
drivers/pci/controller/dwc/pcie-designware.h | 1 +
2 files changed, 42 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 7818b4febb08..181449e342f1 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -53,6 +53,47 @@ u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
}
EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
+static u16 dw_pcie_find_next_ext_capability(struct dw_pcie *pci, u16 start,
+ u8 cap)
+{
+ u32 header;
+ int ttl;
+ int pos = PCI_CFG_SPACE_SIZE;
+
+ /* minimum 8 bytes per capability */
+ ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
+
+ if (start)
+ pos = start;
+
+ header = dw_pcie_readl_dbi(pci, pos);
+ /*
+* If we have no capabilities, this is indicated by cap ID,
+* cap version and next pointer all being 0.
+*/
+ if (header == 0)
+ return 0;
+
+ while (ttl-- > 0) {
+ if (PCI_EXT_CAP_ID(header) == cap && pos != start)
+ return pos;
+
+ pos = PCI_EXT_CAP_NEXT(header);
+ if (pos < PCI_CFG_SPACE_SIZE)
+ break;
+
+ header = dw_pcie_readl_dbi(pci, pos);
+ }
+
+ return 0;
+}
+
+u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap)
+{
+ return dw_pcie_find_next_ext_capability(pci, 0, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_ext_capability);
+
int dw_pcie_read(void __iomem *addr, int size, u32 *val)
{
if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h
b/drivers/pci/controller/dwc/pcie-designware.h
index d8c66a6827dc..11c223471416 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -252,6 +252,7 @@ struct dw_pcie {
container_of((endpoint), struct dw_pcie, ep)
u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+u16 dw_pcie_find_ext_capability(struct dw_pcie *pci, u8 cap);
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
--
2.17.1
[PATCH V15 10/13] dt-bindings: PCI: tegra: Add device tree support for Tegra194
Add support for Tegra194 PCIe controllers. These controllers are based on Synopsys DesignWare core IP. Signed-off-by: Vidya Sagar Reviewed-by: Rob Herring Acked-by: Thierry Reding --- V15: * None V14: * None V13: * None V12: * None V11: * None V10: * None V9: * Added Acked-by from Thierry V8: * Addressed review comments from Thierry * Modified DT example to reflect new changes V7: * Changed description of the property "nvidia,bpmp". * Removed property "nvidia,disable-aspm-states". V6: * Removed 'max-link-speed' as it is going to be a common sub-system property * Removed 'nvidia,init-link-speed' as there isn't much value addition * Removed 'nvidia,wake-gpios' for now * Addressed review comments from Thierry and Rob in general V5: * None V4: * None V3: * Using only 'Cx' (x-being controller number) format to represent a controller * Changed to 'value: description' format where applicable * Changed 'nvidia,init-speed' to 'nvidia,init-link-speed' * Provided more documentation for 'nvidia,init-link-speed' property * Changed 'nvidia,pex-wake' to 'nvidia,wake-gpios' V2: * Added documentation for 'power-domains' property * Removed 'window1' and 'window2' properties * Removed '_clk' and '_rst' from clock and reset names * Dropped 'pcie' from phy-names * Added entry for BPMP-FW handle * Removed offsets for some of the registers and added them in code and would be pickedup based on controller ID * Changed 'nvidia,max-speed' to 'max-link-speed' and is made as an optional * Changed 'nvidia,disable-clock-request' to 'supports-clkreq' with inverted operation * Added more documentation for 'nvidia,update-fc-fixup' property * Removed 'nvidia,enable-power-down' and 'nvidia,plat-gpios' properties * Added '-us' to all properties that represent time in microseconds * Moved P2U documentation to a separate file .../bindings/pci/nvidia,tegra194-pcie.txt | 155 ++ 1 file changed, 155 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt new file mode 100644 index ..674e5adb2895 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt @@ -0,0 +1,155 @@ +NVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) + +This PCIe host controller is based on the Synopsis Designware PCIe IP +and thus inherits all the common properties defined in designware-pcie.txt. + +Required properties: +- compatible: For Tegra19x, must contain "nvidia,tegra194-pcie". +- device_type: Must be "pci" +- power-domains: A phandle to the node that controls power to the respective + PCIe controller and a specifier name for the PCIe controller. Following are + the specifiers for the different PCIe controllers +TEGRA194_POWER_DOMAIN_PCIEX8B: C0 +TEGRA194_POWER_DOMAIN_PCIEX1A: C1 +TEGRA194_POWER_DOMAIN_PCIEX1A: C2 +TEGRA194_POWER_DOMAIN_PCIEX1A: C3 +TEGRA194_POWER_DOMAIN_PCIEX4A: C4 +TEGRA194_POWER_DOMAIN_PCIEX8A: C5 + these specifiers are defined in + "include/dt-bindings/power/tegra194-powergate.h" file. +- reg: A list of physical base address and length pairs for each set of + controller registers. Must contain an entry for each entry in the reg-names + property. +- reg-names: Must include the following entries: + "appl": Controller's application logic registers + "config": As per the definition in designware-pcie.txt + "atu_dma": iATU and DMA registers. This is where the iATU (internal Address + Translation Unit) registers of the PCIe core are made available + for SW access. + "dbi": The aperture where root port's own configuration registers are + available +- interrupts: A list of interrupt outputs of the controller. Must contain an + entry for each entry in the interrupt-names property. +- interrupt-names: Must include the following entries: + "intr": The Tegra interrupt that is asserted for controller interrupts + "msi": The Tegra interrupt that is asserted when an MSI is received +- bus-range: Range of bus numbers associated with this controller +- #address-cells: Address representation for root ports (must be 3) + - cell 0 specifies the bus and device numbers of the root port: +[23:16]: bus number +[15:11]: device number + - cell 1 denotes the upper 32 address bits and should be 0 + - cell 2 contains the lower 32 address bits and is used to translate to the +CPU address space +- #size-cells: Size representation for root ports (must be 2) +- ranges: Describes the translation of addresses for root ports and standard + PCI regions. The entries must be 7 cells each, where the first three cells + correspond to the address as described for the #address-cells property + above, the fourth and fifth cells are for the physical CPU address to + translate to and the sixth and seventh cells are as described for the
Re: [PATCH v2 2/2] nvme-pci: Allow PCI bus-level PM to be used if ASPM is disabled
On Thu, Aug 08, 2019 at 10:41:56PM +0200, Rafael J. Wysocki wrote:
> On Thu, Aug 8, 2019, 20:39 Bjorn Helgaas wrote:
> > On Thu, Aug 08, 2019 at 04:47:45PM +0200, Rafael J. Wysocki wrote:
> > > On Thu, Aug 8, 2019 at 3:43 PM Bjorn Helgaas wrote:
> > > > On Thu, Aug 08, 2019 at 12:10:06PM +0200, Rafael J. Wysocki wrote:
> > > > > From: Rafael J. Wysocki
> > > > >
> > > > > One of the modifications made by commit d916b1be94b6 ("nvme-pci: use
> > > > > host managed power state for suspend") was adding a pci_save_state()
> > > > > call to nvme_suspend() in order to prevent the PCI bus-level PM from
> > > > > being applied to the suspended NVMe devices, but if ASPM is not
> > > > > enabled for the target NVMe device, that causes its PCIe link to stay
> > > > > up and the platform may not be able to get into its optimum low-power
> > > > > state because of that.
> > > > >
> > > > > For example, if ASPM is disabled for the NVMe drive (PC401 NVMe SK
> > > > > hynix 256GB) in my Dell XPS13 9380, leaving it in D0 during
> > > > > suspend-to-idle prevents the SoC from reaching package idle states
> > > > > deeper than PC3, which is way insufficient for system suspend.
> > > >
> > > > Just curious: I assume the SoC you reference is some part of the NVMe
> > > > drive?
> > >
> > > No, the SoC is what contains the Intel processor and PCH (formerly
> > > "chipset").
> > >
> > > > > To address this shortcoming, make nvme_suspend() check if ASPM is
> > > > > enabled for the target device and fall back to full device shutdown
> > > > > and PCI bus-level PM if that is not the case.
> > > > >
> > > > > Fixes: d916b1be94b6 ("nvme-pci: use host managed power state for
> > > > > suspend")
> > > > > Link:
> > > > > https://lore.kernel.org/linux-pm/2763495.NmdaWeg79L@kreacher/T/#t
> > > > > Signed-off-by: Rafael J. Wysocki
> > > > > ---
> > > > >
> > > > > -> v2:
> > > > > * Move the PCI/PCIe ASPM changes to a separate patch.
> > > > > * Do not add a redundant ndev->last_ps == U32_MAX check in
> > > > > nvme_suspend().
> > > > >
> > > > > ---
> > > > > drivers/nvme/host/pci.c | 13 ++---
> > > > > 1 file changed, 10 insertions(+), 3 deletions(-)
> > > > >
> > > > > Index: linux-pm/drivers/nvme/host/pci.c
> > > > > ===
> > > > > --- linux-pm.orig/drivers/nvme/host/pci.c
> > > > > +++ linux-pm/drivers/nvme/host/pci.c
> > > > > @@ -2846,7 +2846,7 @@ static int nvme_resume(struct device *de
> > > > > struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
> > > > > struct nvme_ctrl *ctrl = >ctrl;
> > > > >
> > > > > - if (pm_resume_via_firmware() || !ctrl->npss ||
> > > > > + if (ndev->last_ps == U32_MAX ||
> > > > > nvme_set_power_state(ctrl, ndev->last_ps) != 0)
> > > > > nvme_reset_ctrl(ctrl);
> > > > > return 0;
> > > > > @@ -2859,6 +2859,8 @@ static int nvme_suspend(struct device *d
> > > > > struct nvme_ctrl *ctrl = >ctrl;
> > > > > int ret = -EBUSY;
> > > > >
> > > > > + ndev->last_ps = U32_MAX;
> > > > > +
> > > > > /*
> > > > >* The platform does not remove power for a kernel managed
> > > > > suspend so
> > > > >* use host managed nvme power settings for lowest idle power if
> > > > > @@ -2866,8 +2868,14 @@ static int nvme_suspend(struct device *d
> > > > >* shutdown. But if the firmware is involved after the suspend
> > > > > or the
> > > > >* device does not support any non-default power states, shut
> > > > > down the
> > > > >* device fully.
> > > > > + *
> > > > > + * If ASPM is not enabled for the device, shut down the device
> > > > > and allow
> > > > > + * the PCI bus layer to put it into D3 in order to take the
> > > > > PCIe link
> > > > > + * down, so as to allow the platform to achieve its minimum
> > > > > low-power
> > > > > + * state (which may not be possible if the link is up).
> > > > >*/
> > > > > - if (pm_suspend_via_firmware() || !ctrl->npss) {
> > > > > + if (pm_suspend_via_firmware() || !ctrl->npss ||
> > > > > + !pcie_aspm_enabled_mask(pdev)) {
> > > >
> > > > This seems like a layering violation, in the sense that ASPM is
> > > > supposed to be hardware-autonomous and invisible to software.
> > >
> > > But software has to enable it.
> > >
> > > If it is not enabled, it will not be used, and that's what the check
> > > is about.
> > >
> > > > IIUC the NVMe device will go to the desired package idle state if
> > > > the link is in L0s or L1, but not if the link is in L0. I don't
> > > > understand that connection; AFAIK that would be something outside
> > > > the scope of the PCIe spec.
> > >
> > > Yes, it is outside of the PCIe spec.
> > >
> > > No, this is not about the NVMe device, it is about the Intel SoC
> > > (System-on-a-Chip) the platform is based on.
> >
> > Ah. So this problem could occur with any device, not just NVMe? If
> > so, how
[PATCH V15 07/13] dt-bindings: PCI: designware: Add binding for CDM register check
Add support to enable CDM (Configuration Dependent Module) registers check for any data corruption. CDM registers include standard PCIe configuration space registers, Port Logic registers and iATU and DMA registers. Refer Section S.4 of Synopsys DesignWare Cores PCI Express Controller Databook Version 4.90a. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Reviewed-by: Rob Herring --- V15: * None V14: * Added a full stop(.) at the end of commit message. V13: * None V12: * None V11: * None V10: * None V9: * None V8: * None V7: * Changed "enable-cdm-check" to "snps,enable-cdm-check" V6: * None V5: * None V4: * None V3: * Changed flag name from 'cdm-check' to 'enable-cdm-check' * Added info about Port Logic and DMA registers being part of CDM V2: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/designware-pcie.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/designware-pcie.txt b/Documentation/devicetree/bindings/pci/designware-pcie.txt index 5561a1c060d0..3fba04da6a59 100644 --- a/Documentation/devicetree/bindings/pci/designware-pcie.txt +++ b/Documentation/devicetree/bindings/pci/designware-pcie.txt @@ -34,6 +34,11 @@ Optional properties: - clock-names: Must include the following entries: - "pcie" - "pcie_bus" +- snps,enable-cdm-check: This is a boolean property and if present enables + automatic checking of CDM (Configuration Dependent Module) registers + for data corruption. CDM registers include standard PCIe configuration + space registers, Port Logic registers, DMA and iATU (internal Address + Translation Unit) registers. RC mode: - num-viewport: number of view ports configured in hardware. If a platform does not specify it, the driver assumes 2. -- 2.17.1
[PATCH V15 04/13] PCI: dwc: Move config space capability search API
Move PCIe config space capability search API to common DesignWare file
as this can be used by both host and ep mode codes.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Reviewed-by: Thierry Reding
---
V15:
* None
V14:
* None
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* None
V8:
* Changed comment to explicitly state their mere resemblance to standard APIs
but not their operation and place of use.
V7:
* Exported dw_pcie_find_capability() API
V6:
* None
V5:
* Removed redundant APIs in pcie-designware-ep.c file after moving them
to pcie-designware.c file based on Bjorn's comments.
V4:
* Rebased to linux-next top of the tree
V3:
* None
V2:
* Removed dw_pcie_find_next_ext_capability() API from here and made a
separate patch for that
.../pci/controller/dwc/pcie-designware-ep.c | 37 +-
drivers/pci/controller/dwc/pcie-designware.c | 39 +++
drivers/pci/controller/dwc/pcie-designware.h | 2 +
3 files changed, 43 insertions(+), 35 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c
b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 2bf5a35c0570..65f479250087 100644
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -40,39 +40,6 @@ void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum
pci_barno bar)
__dw_pcie_ep_reset_bar(pci, bar, 0);
}
-static u8 __dw_pcie_ep_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
- u8 cap)
-{
- u8 cap_id, next_cap_ptr;
- u16 reg;
-
- if (!cap_ptr)
- return 0;
-
- reg = dw_pcie_readw_dbi(pci, cap_ptr);
- cap_id = (reg & 0x00ff);
-
- if (cap_id > PCI_CAP_ID_MAX)
- return 0;
-
- if (cap_id == cap)
- return cap_ptr;
-
- next_cap_ptr = (reg & 0xff00) >> 8;
- return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
-}
-
-static u8 dw_pcie_ep_find_capability(struct dw_pcie *pci, u8 cap)
-{
- u8 next_cap_ptr;
- u16 reg;
-
- reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
- next_cap_ptr = (reg & 0x00ff);
-
- return __dw_pcie_ep_find_next_cap(pci, next_cap_ptr, cap);
-}
-
static int dw_pcie_ep_write_header(struct pci_epc *epc, u8 func_no,
struct pci_epf_header *hdr)
{
@@ -612,9 +579,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep)
dev_err(dev, "Failed to reserve memory for MSI/MSI-X\n");
return -ENOMEM;
}
- ep->msi_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSI);
+ ep->msi_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
- ep->msix_cap = dw_pcie_ep_find_capability(pci, PCI_CAP_ID_MSIX);
+ ep->msix_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_MSIX);
offset = dw_pcie_ep_find_ext_capability(pci, PCI_EXT_CAP_ID_REBAR);
if (offset) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 7d25102c304c..7818b4febb08 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -14,6 +14,45 @@
#include "pcie-designware.h"
+/*
+ * These interfaces resemble the pci_find_*capability() interfaces, but these
+ * are for configuring host controllers, which are bridges *to* PCI devices but
+ * are not PCI devices themselves.
+ */
+static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
+ u8 cap)
+{
+ u8 cap_id, next_cap_ptr;
+ u16 reg;
+
+ if (!cap_ptr)
+ return 0;
+
+ reg = dw_pcie_readw_dbi(pci, cap_ptr);
+ cap_id = (reg & 0x00ff);
+
+ if (cap_id > PCI_CAP_ID_MAX)
+ return 0;
+
+ if (cap_id == cap)
+ return cap_ptr;
+
+ next_cap_ptr = (reg & 0xff00) >> 8;
+ return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+}
+
+u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap)
+{
+ u8 next_cap_ptr;
+ u16 reg;
+
+ reg = dw_pcie_readw_dbi(pci, PCI_CAPABILITY_LIST);
+ next_cap_ptr = (reg & 0x00ff);
+
+ return __dw_pcie_find_next_cap(pci, next_cap_ptr, cap);
+}
+EXPORT_SYMBOL_GPL(dw_pcie_find_capability);
+
int dw_pcie_read(void __iomem *addr, int size, u32 *val)
{
if (!IS_ALIGNED((uintptr_t)addr, size)) {
diff --git a/drivers/pci/controller/dwc/pcie-designware.h
b/drivers/pci/controller/dwc/pcie-designware.h
index ffed084a0b4f..d8c66a6827dc 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -251,6 +251,8 @@ struct dw_pcie {
#define to_dw_pcie_from_ep(endpoint) \
container_of((endpoint), struct dw_pcie, ep)
+u8 dw_pcie_find_capability(struct dw_pcie *pci, u8 cap);
+
int dw_pcie_read(void __iomem *addr, int size, u32 *val);
int dw_pcie_write(void __iomem *addr, int size, u32 val);
--
2.17.1
[PATCH V15 08/13] PCI: dwc: Add support to enable CDM register check
Add support to enable CDM (Configuration Dependent Module) register check
for any data corruption based on the device-tree flag 'snps,enable-cdm-check'.
Signed-off-by: Vidya Sagar
Acked-by: Gustavo Pimentel
Reviewed-by: Thierry Reding
---
V15:
* None
V14:
* None
V13:
* None
V12:
* None
V11:
* None
V10:
* None
V9:
* None
V8:
* None
V7:
* Changed "enable-cdm-check" to "snps,enable-cdm-check"
V6:
* None
V5:
* None
V4:
* None
V3:
* Changed code and commit description to reflect change in flag from
'cdm-check' to 'enable-cdm-check'
V2:
* This is a new patch in v2 series
drivers/pci/controller/dwc/pcie-designware.c | 7 +++
drivers/pci/controller/dwc/pcie-designware.h | 9 +
2 files changed, 16 insertions(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 1d87e823de21..59eaeeb21dbe 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -547,4 +547,11 @@ void dw_pcie_setup(struct dw_pcie *pci)
break;
}
dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, val);
+
+ if (of_property_read_bool(np, "snps,enable-cdm-check")) {
+ val = dw_pcie_readl_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS);
+ val |= PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS |
+ PCIE_PL_CHK_REG_CHK_REG_START;
+ dw_pcie_writel_dbi(pci, PCIE_PL_CHK_REG_CONTROL_STATUS, val);
+ }
}
diff --git a/drivers/pci/controller/dwc/pcie-designware.h
b/drivers/pci/controller/dwc/pcie-designware.h
index 11c223471416..5a18e94e52c8 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -86,6 +86,15 @@
#define PCIE_MISC_CONTROL_1_OFF0x8BC
#define PCIE_DBI_RO_WR_EN BIT(0)
+#define PCIE_PL_CHK_REG_CONTROL_STATUS 0xB20
+#define PCIE_PL_CHK_REG_CHK_REG_START BIT(0)
+#define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS BIT(1)
+#define PCIE_PL_CHK_REG_CHK_REG_COMPARISON_ERROR BIT(16)
+#define PCIE_PL_CHK_REG_CHK_REG_LOGIC_ERRORBIT(17)
+#define PCIE_PL_CHK_REG_CHK_REG_COMPLETE BIT(18)
+
+#define PCIE_PL_CHK_REG_ERR_ADDR 0xB28
+
/*
* iATU Unroll-specific register definitions
* From 4.80 core version the address translation will be made by unroll
--
2.17.1
[PATCH V15 09/13] dt-bindings: Add PCIe supports-clkreq property
Some host controllers need to know the existence of clkreq signal routing to downstream devices to be able to advertise low power features like ASPM L1 substates. Without clkreq signal routing being present, enabling ASPM L1 substates might lead to downstream devices being disconnected from the bus. Hence a new device tree property 'supports-clkreq' is added to make such host controllers aware of clkreq signal routing to downstream devices. Signed-off-by: Vidya Sagar Reviewed-by: Rob Herring Reviewed-by: Thierry Reding --- V15: * None V14: * s/falling off the bus/being disconnected from the bus/ in commit message. V13: * None V12: * Rebased on top of linux-next top of the tree V11: * None V10: * None V9: * None V8: * None V7: * None V6: * s/Documentation\/devicetree/dt-bindings/ in the subject V5: * None V4: * Rebased on top of linux-next top of the tree V3: * None V2: * This is a new patch in v2 series Documentation/devicetree/bindings/pci/pci.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 2a5d91024059..29bcbd88f457 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -27,6 +27,11 @@ driver implementation may support the following properties: - reset-gpios: If present this property specifies PERST# GPIO. Host drivers can parse the GPIO and apply fundamental reset to endpoints. +- supports-clkreq: + If present this property specifies that CLKREQ signal routing exists from + root port to downstream device and host bridge drivers can do programming + which depends on CLKREQ signal existence. For example, programming root port + not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. PCI-PCI Bridge properties - -- 2.17.1
[PATCH V15 06/13] PCI: dwc: Export dw_pcie_wait_for_link() API
Export dw_pcie_wait_for_link() API to be able to build drivers using
this API as loadable modules (Ex:- Tegra194 PCIe host controller driver).
Signed-off-by: Vidya Sagar
---
V15:
* None
V14:
* This is a new patch in V14 series.
drivers/pci/controller/dwc/pcie-designware.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pci/controller/dwc/pcie-designware.c
b/drivers/pci/controller/dwc/pcie-designware.c
index 181449e342f1..1d87e823de21 100644
--- a/drivers/pci/controller/dwc/pcie-designware.c
+++ b/drivers/pci/controller/dwc/pcie-designware.c
@@ -460,6 +460,7 @@ int dw_pcie_wait_for_link(struct dw_pcie *pci)
return -ETIMEDOUT;
}
+EXPORT_SYMBOL_GPL(dw_pcie_wait_for_link);
int dw_pcie_link_up(struct dw_pcie *pci)
{
--
2.17.1
[PATCH V15 02/13] PCI: Disable MSI for Tegra root ports
Tegra PCIe rootports don't generate MSI interrupts for PME and AER events.
Since PCIe spec (Ref: r4.0 sec 7.7.1.2 and 7.7.2.2) doesn't support using
a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid root ports
service drivers registering their respective ISRs with MSI interrupt and
to let only INTx be used for all events.
Signed-off-by: Vidya Sagar
Reviewed-by: Thierry Reding
---
V15:
* None
V14:
* None
V13:
* None
V12:
* None
V11:
* Included older Tegra chips to extend the quirk as this issue is present in
older Tegra chips as well.
V10:
* None
V9:
* None
V8:
* Changed quirk macro to consider class code as well to avoid this quirk
getting applied to Tegra194 when it is operating in endpoint mode. Also
quoted relevant sections from PCIe spec in comments.
V7:
* This is a new patch
drivers/pci/quirks.c | 53
1 file changed, 53 insertions(+)
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 208aacf39329..168782c5d23b 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2592,6 +2592,59 @@ DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
PCI_DEVICE_ID_NVIDIA_NVENET_15,
nvenet_msi_disable);
+/*
+ * PCIe spec r4.0 sec 7.7.1.2 and sec 7.7.2.2 say that if MSI/MSI-X is enabled,
+ * then the device can't use INTx interrupts. Tegra's PCIe root ports don't
+ * generate MSI interrupts for PME and AER events instead only INTx interrupts
+ * are generated. Though Tegra's PCIe root ports can generate MSI interrupts
+ * for other events, since PCIe specificiation doesn't support using a mix of
+ * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port
+ * service drivers registering their respective ISRs for MSIs.
+ */
+static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev)
+{
+ dev->no_msi = 1;
+}
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6,
+ PCI_CLASS_BRIDGE_PCI, 8,
+ pci_quirk_nvidia_tegra_disable_rp_msi);
+
/*
* Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
* config register. This register controls the routing of legacy
--
2.17.1
[PATCH V15 01/13] PCI: Add #defines for some of PCIe spec r4.0 features
Add #defines only for the Data Link Feature and Physical Layer 16.0 GT/s features as defined in PCIe spec r4.0, sec 7.7.4 for Data Link Feature and sec 7.7.5 for Physical Layer 16.0 GT/s. Signed-off-by: Vidya Sagar Reviewed-by: Thierry Reding Acked-by: Bjorn Helgaas --- V15: * None V14: * Added 'Acked-by: Bjorn Helgaas ' V13: * Updated commit message to include references from spec * Removed unused defines and moved some from pcie-tegra194.c file * Addressed review comments from Bjorn V12: * None V11: * None V10: * None V9: * None V8: * None V7: * None V6: * None V5: * None V4: * None V3: * Updated commit message and description to explicitly mention that defines are added only for some of the features and not all. V2: * None include/uapi/linux/pci_regs.h | 14 +- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index f28e562d7ca8..d28d0319d932 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -713,7 +713,9 @@ #define PCI_EXT_CAP_ID_DPC 0x1D/* Downstream Port Containment */ #define PCI_EXT_CAP_ID_L1SS0x1E/* L1 PM Substates */ #define PCI_EXT_CAP_ID_PTM 0x1F/* Precision Time Measurement */ -#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PTM +#define PCI_EXT_CAP_ID_DLF 0x25/* Data Link Feature */ +#define PCI_EXT_CAP_ID_PL_16GT 0x26/* Physical Layer 16.0 GT/s */ +#define PCI_EXT_CAP_ID_MAX PCI_EXT_CAP_ID_PL_16GT #define PCI_EXT_CAP_DSN_SIZEOF 12 #define PCI_EXT_CAP_MCAST_ENDPOINT_SIZEOF 40 @@ -1053,4 +1055,14 @@ #define PCI_L1SS_CTL1_LTR_L12_TH_SCALE0xe000 /* LTR_L1.2_THRESHOLD_Scale */ #define PCI_L1SS_CTL2 0x0c/* Control 2 Register */ +/* Data Link Feature */ +#define PCI_DLF_CAP0x04/* Capabilities Register */ +#define PCI_DLF_EXCHANGE_ENABLE 0x8000 /* Data Link Feature Exchange Enable */ + +/* Physical Layer 16.0 GT/s */ +#define PCI_PL_16GT_LE_CTRL0x20/* Lane Equalization Control Register */ +#define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK0x000F +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK0x00F0 +#define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 + #endif /* LINUX_PCI_REGS_H */ -- 2.17.1
[PATCH V15 00/13] PCI: tegra: Add Tegra194 PCIe support
Tegra194 has six PCIe controllers based on Synopsys DesignWare core. There are two Universal PHY (UPHY) blocks with each supporting 12(HSIO: Hisg Speed IO) and 8(NVHS: NVIDIA High Speed) lanes respectively. Controllers:0~4 use UPHY lanes from HSIO brick whereas Controller:5 uses UPHY lanes from NVHS brick. Lane mapping in HSIO UPHY brick to each PCIe controller (0~4) is controlled in XBAR module by BPMP-FW. Since PCIe core has PIPE interface, a glue module called PIPE-to-UPHY (P2U) is used to connect each UPHY lane (applicable to both HSIO and NVHS UPHY bricks) to PCIe controller This patch series - Adds support for P2U PHY driver - Adds support for PCIe host controller - Adds device tree nodes each PCIe controllers - Enables nodes applicable to p2972- platform - Adds helper APIs in Designware core driver to get capability regs offset - Adds defines for new feature registers of PCIe spec revision 4 - Makes changes in DesignWare core driver to get Tegra194 PCIe working Testing done on P2972- platform - Able to get PCIe link up with on-board Marvel eSATA controller - Able to get PCIe link up with NVMe cards connected to M.2 Key-M slot - Able to do data transfers with both SATA drives and NVMe cards - Able to perform suspend-resume sequence Note - Enabling x8 slot on P2972- platform requires pinmux driver for Tegra194. It is being worked on currently and hence Controller:5 (i.e. x8 slot) is disabled in this patch series. A future patch series would enable this. - This series is based on top of the following series Jisheng's patches to add support to .remove() in Designware sub-system https://patchwork.kernel.org/project/linux-pci/list/?series=98559 (Update: Jisheng's patches are now accepted and applied for v5.2) My patches made on top of Jisheng's patches to export various symbols http://patchwork.ozlabs.org/project/linux-pci/list/?series=115671 (Update: My above patch series is accepted and applied for v5.3) Another patch of mine to enable BPMP-FW resume in noirq phase http://patchwork.ozlabs.org/patch/1140973/ (This is already accepted) V15: * Refactored pcie-tegra194.c code to call only tegra_bpmp_transfer() API in both .probe() path and .resume_noirq() path. V14: * Addressed Lorenzo's review comments in pcie-tegra194.c file (Patch 13/13) * Added a new patch to export dw_pcie_wait_for_link() API V13: * Addressed Bjorn's review comments for adding Gen-4 specific defines to pci_regs.h header file V12: * Modified the commit message of patch-3 in this series to address review comments from Lorenzo V11: * Removed device-tree patches from the series as they are applied to relevant Tegra specific trees by Thierry Reding. * Included older Tegra chips to extend quirk that disables MSI interrupt being used for Tegra PCIe root ports. * Addressed review comments in P2U driver file. V10: * Used _relaxed() versions of readl() & writel() V9: * Made the drivers dependent on ARCH_TEGRA_194_SOC directly * Addressed review comments from Dmitry V8: * Changed P2U driver file name from pcie-p2u-tegra194.c to phy-tegra194-p2u.c * Addressed review comments from Thierry and Rob V7: * Took care of review comments from Rob * Added a quirk to disable MSI for root ports * Removed using pcie_pme_disable_msi() API in host controller driver V6: * Removed patch that exports pcie_bus_config symbol * Took care of review comments from Thierry and Rob V5: * Removed redundant APIs in pcie-designware-ep.c file after moving them to pcie-designware.c file based on Bjorn's review comments V4: * Rebased on top of linux-next top of the tree * Addressed Gustavo's comments and added his Ack for some of the changes. V3: * Addressed review comments from Thierry V2: * Addressed review comments from Bjorn, Thierry, Jonathan, Rob & Kishon * Added more patches in v2 series Vidya Sagar (13): PCI: Add #defines for some of PCIe spec r4.0 features PCI: Disable MSI for Tegra root ports PCI: dwc: Perform dbi regs write lock towards the end PCI: dwc: Move config space capability search API PCI: dwc: Add ext config space capability search API PCI: dwc: Export dw_pcie_wait_for_link() API dt-bindings: PCI: designware: Add binding for CDM register check PCI: dwc: Add support to enable CDM register check dt-bindings: Add PCIe supports-clkreq property dt-bindings: PCI: tegra: Add device tree support for Tegra194 dt-bindings: PHY: P2U: Add Tegra194 P2U block phy: tegra: Add PCIe PIPE2UPHY support PCI: tegra: Add Tegra194 PCIe support .../bindings/pci/designware-pcie.txt |5 + .../bindings/pci/nvidia,tegra194-pcie.txt | 155 ++ Documentation/devicetree/bindings/pci/pci.txt |5 + .../bindings/phy/phy-tegra194-p2u.txt | 28 + drivers/pci/controller/dwc/Kconfig| 10 + drivers/pci/controller/dwc/Makefile |1 + .../pci/controller/dwc/pcie-designware-ep.c | 37 +- .../pci/controller/dwc/pcie-designware-host.c | 14 +-
Re: [PATCH 2/2] regulator: qcom-rpmh: Add support for SM8150
On 08-08-19, 20:32, Bjorn Andersson wrote:
> On Thu 08 Aug 02:33 PDT 2019, Vinod Koul wrote:
> > diff --git a/drivers/regulator/qcom-rpmh-regulator.c
> > b/drivers/regulator/qcom-rpmh-regulator.c
> [..]
> > +static const struct rpmh_vreg_hw_data pmic5_bob = {
> > + .regulator_type = VRM,
> > + .ops = _regulator_vrm_bypass_ops,
> > + .voltage_range = REGULATOR_LINEAR_RANGE(30, 0, 135, 32000),
> > + .n_voltages = 135,
>
> There are 136 voltages in [0,135]
Oops, will send an update
>
> > + .pmic_mode_map = pmic_mode_map_pmic4_bob,
> > + .of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode,
> > +};
> > +
> [..]
> > @@ -755,6 +890,18 @@ static const struct of_device_id
> > rpmh_regulator_match_table[] = {
> > .compatible = "qcom,pm8005-rpmh-regulators",
> > .data = pm8005_vreg_data,
> > },
> > + {
> > + .compatible = "qcom,pm8150-rpmh-regulators",
> > + .data = pm8150_vreg_data,
> > + },
> > + {
> > + .compatible = "qcom,pm8150l-rpmh-regulators",
> > + .data = pm8150l_vreg_data,
> > + },
> > + {
> > + .compatible = "qcom,pm8009-rpmh-regulators",
> > + .data = pm8009_vreg_data,
> > + },
>
> Sort order...
Yes will sort all entries.
> > {}
> > };
> > MODULE_DEVICE_TABLE(of, rpmh_regulator_match_table);
>
> Apart from these nits this looks good.
Thanks :)
--
~Vinod
Re: linux-next: Tree for Aug 8
Hi Heiko, Stephen,
On Fri, Aug 9, 2019 at 7:53 AM Heiko Carstens wrote:
>
> On Thu, Aug 08, 2019 at 06:17:39PM +1000, Stephen Rothwell wrote:
> > Hi all,
> >
> > Changes since 20190807:
> >
> > I reverted a commit from the kbuild-current tree by request.
>
> Hello Masahiro,
>
> it looks like there is (another?) bug in kbuild. With your patch
>
> commit 421a15c167b2d1f43f287da5b75ef2704650640b (refs/bisect/bad)
> Author: Masahiro Yamada
> Date: Fri Jul 26 11:17:47 2019 +0900
>
> kbuild: clean-up subdir-ym computation
>
> The intermediate variables __subdir-{y,m} are unneeded.
>
> Signed-off-by: Masahiro Yamada
>
> the file modules.builtin starts to miss a lot of entries when building
> the kernel tree. Reverting that patch on top of linux-next 20190808
> restores the old behaviour.
>
> This is the diff I get without and with the above commit (s390 with
> defconfig):
>
> --- modules.builtin.ok 2019-08-09 00:39:58.148624485 +0200
> +++ modules.builtin 2019-08-09 00:40:07.878637541 +0200
You are right. This commit is bad.
Stephen, could you revert this commit for today's linux-next ?
BTW, I had dropped this commit from my branch (with another reason),
but I forgot to push it to the public place...
--
Best Regards
Masahiro Yamada
Re: [PATCH 1/2] regulator: dt-bindings: Add PM8150x compatibles
On 08-08-19, 20:29, Bjorn Andersson wrote: > On Thu 08 Aug 02:33 PDT 2019, Vinod Koul wrote: > > > Add PM8150, PM8150L and PM8009 compatibles for these PMICs found > > in some Qualcomm platforms. > > > > Signed-off-by: Vinod Koul > > --- > > .../devicetree/bindings/regulator/qcom,rpmh-regulator.txt | 8 +++- > > 1 file changed, 7 insertions(+), 1 deletion(-) > > > > diff --git > > a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > > b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > > index 14d2eee96b3d..1a9cab50503a 100644 > > --- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > > +++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > > @@ -25,6 +25,9 @@ Supported regulator node names: > > PM8998: smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2 > > PMI8998:bob > > PM8005: smps1 - smps4 > > + PM8150: smps1 - smps10, ldo1 - ldo18 > > + PM8150L:smps1 - smps8, ldo1 - ldo11, bob, flash, rgb > > + PM8009: smps1 - smps2, ld01 - ldo7 > > Please maintain the sort order. Ah yes, Mark has applied the patch, I will send a sort order patch. Even in previous entries, PM8005 should be the first one.. > > Apart from that > > Reviewed-by: Bjorn Andersson Thanks for the review. -- ~Vinod
[PATCH 1/2] arm64: defconfig: Cleanup the defconfig
Re-run savedefconfig to cleanup the defconfig. Signed-off-by: Alistair Francis --- arch/arm64/configs/defconfig | 24 ++-- 1 file changed, 6 insertions(+), 18 deletions(-) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 0e58ef02880c..b17ed20e1754 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -88,7 +88,6 @@ CONFIG_ARM_TEGRA186_CPUFREQ=y CONFIG_ARM_SCPI_PROTOCOL=y CONFIG_RASPBERRYPI_FIRMWARE=y CONFIG_INTEL_STRATIX10_SERVICE=y -CONFIG_TI_SCI_PROTOCOL=y CONFIG_EFI_CAPSULE_LOADER=y CONFIG_IMX_SCU=y CONFIG_IMX_SCU_PD=y @@ -193,7 +192,6 @@ CONFIG_PCIE_QCOM=y CONFIG_PCIE_ARMADA_8K=y CONFIG_PCIE_KIRIN=y CONFIG_PCIE_HISI_STB=y -CONFIG_PCIE_TEGRA194=m CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y CONFIG_HISILICON_LPC=y @@ -260,18 +258,12 @@ CONFIG_HNS3_ENET=y CONFIG_E1000E=y CONFIG_IGB=y CONFIG_IGBVF=y -CONFIG_MLX4_EN=m -CONFIG_MLX4_CORE=m -CONFIG_MLX4_DEBUG=y -CONFIG_MLX4_CORE_GEN2=y -CONFIG_MLX5_CORE=m -CONFIG_MLX5_CORE_EN=y -CONFIG_MLX5_EN_ARFS=y -CONFIG_MLX5_EN_RXNFC=y -CONFIG_MLX5_MPFS=y CONFIG_MVNETA=y CONFIG_MVPP2=y CONFIG_SKY2=y +CONFIG_MLX4_EN=m +CONFIG_MLX5_CORE=m +CONFIG_MLX5_CORE_EN=y CONFIG_QCOM_EMAC=m CONFIG_RAVB=y CONFIG_SMC91X=y @@ -386,8 +378,8 @@ CONFIG_SPI_PL022=y CONFIG_SPI_ROCKCHIP=y CONFIG_SPI_QUP=y CONFIG_SPI_S3C64XX=y -CONFIG_SPI_SPIDEV=m CONFIG_SPI_SUN6I=y +CONFIG_SPI_SPIDEV=m CONFIG_SPMI=y CONFIG_PINCTRL_SINGLE=y CONFIG_PINCTRL_MAX77620=y @@ -593,7 +585,6 @@ CONFIG_USB_GADGET=y CONFIG_USB_RENESAS_USBHS_UDC=m CONFIG_USB_RENESAS_USB3=m CONFIG_TYPEC=m -CONFIG_TYPEC_HD3SS3220=m CONFIG_MMC=y CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_ARMMMCI=y @@ -648,9 +639,9 @@ CONFIG_RTC_DRV_SNVS=m CONFIG_RTC_DRV_IMX_SC=m CONFIG_RTC_DRV_XGENE=y CONFIG_DMADEVICES=y -CONFIG_FSL_EDMA=y CONFIG_DMA_BCM2835=m CONFIG_DMA_SUN6I=m +CONFIG_FSL_EDMA=y CONFIG_K3_DMA=y CONFIG_MV_XOR=y CONFIG_MV_XOR_V2=y @@ -696,7 +687,6 @@ CONFIG_ARM_MHU=y CONFIG_IMX_MBOX=y CONFIG_PLATFORM_MHU=y CONFIG_BCM2835_MBOX=y -CONFIG_TI_MESSAGE_MANAGER=y CONFIG_QCOM_APCS_IPC=y CONFIG_ROCKCHIP_IOMMU=y CONFIG_TEGRA_IOMMU_SMMU=y @@ -736,9 +726,7 @@ CONFIG_ARCH_TEGRA_186_SOC=y CONFIG_ARCH_TEGRA_194_SOC=y CONFIG_ARCH_K3_AM6_SOC=y CONFIG_ARCH_K3_J721E_SOC=y -CONFIG_SOC_TI=y CONFIG_TI_SCI_PM_DOMAINS=y -CONFIG_DEVFREQ_GOV_SIMPLE_ONDEMAND=y CONFIG_EXTCON_USB_GPIO=y CONFIG_EXTCON_USBC_CROS_EC=y CONFIG_MEMORY=y @@ -783,11 +771,11 @@ CONFIG_PHY_TEGRA_XUSB=y CONFIG_HISI_PMU=y CONFIG_QCOM_L2_PMU=y CONFIG_QCOM_L3_PMU=y -CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_IMX_OCOTP=y CONFIG_NVMEM_IMX_OCOTP_SCU=y CONFIG_QCOM_QFPROM=y CONFIG_ROCKCHIP_EFUSE=y +CONFIG_NVMEM_SUNXI_SID=y CONFIG_UNIPHIER_EFUSE=y CONFIG_MESON_EFUSE=m CONFIG_FPGA=y -- 2.22.0
[PATCH 2/2] arm64: defconfig: Enable sound drivers on Allwinner devices
Enable the sound drivers for Allwinner devices. Signed-off-by: Alistair Francis --- arch/arm64/configs/defconfig | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b17ed20e1754..3dc12c3b9bf8 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -550,6 +550,12 @@ CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m +CONFIG_SND_SUN4I_CODEC=m +CONFIG_SND_SUN8I_CODEC=m +CONFIG_SND_SUN8I_CODEC_ANALOG=m +CONFIG_SND_SUN50I_CODEC_ANALOG=m +CONFIG_SND_SUN4I_I2S=m +CONFIG_SND_SUN4I_SPDIF=m CONFIG_SND_SOC_AK4613=m CONFIG_SND_SOC_ES7134=m CONFIG_SND_SOC_ES7241=m -- 2.22.0
Re: [EXTERNAL]Re: MIPS Cache Coherency Issue
On Tue, 2019-08-06 at 01:43 +, Tommy Jin wrote: > Hi Chris, > > If you're busy with other things, maybe I can give you a hand, so how > can I replicate this issue locally? Thanks for the offer but I'm not sure you'll be able to do much without our specific hardware. > > From your log, I can get the following information, please correct me > if I miss anything. > kernel version: 5.1.0 That's what I was using at the time. I imagine 5.2 or 5.3 would behave the same. > hardware platform: broadcom BMIPS4350 The specific SoC is BCM6818GR which I believe is the same core as the BMIPS4355. > I probably couldn't get a broadcom BMIPS4350, is there any simulator > for this board(e.g. QEMU)? Yeah it's a pretty old chip. I'm not aware of any QEMU support, but I haven't looked. > > Best regards, > Tommy > From: linux-mips-ow...@vger.kernel.org org> on behalf of Chris Packham > Sent: Tuesday, August 6, 2019 5:13 AM > To: Tommy Jin > Cc: linux-kernel@vger.kernel.org ; linu > x-m...@vger.kernel.org > Subject: [EXTERNAL]Re: MIPS Cache Coherency Issue > > On Mon, 2019-08-05 at 14:02 +, Tommy Jin wrote: > > Hi Chris, > > > > My name is Tommy, from wave computing Co,Ltd, our team is working > on > > the maintenance of the MIPS kernel. > > > > You raised a MIPS cache coherency patch which can be found in the > > following links > > https://lore.kernel.org/linux-mips/20190528221255.22460-1-chris.pac > kh > > a...@alliedtelesis.co.nz/T/#u > > > > With Paul's patch, It seems you still get "other bad behaviour", it > > doesn't work for you. Has this issue been resolved? > > In short no it hasn't been resolved. I haven't been able to spend > much > time looking at the issue(s) so I haven't been able to tell if Paul's > patch uncovered pre-existing issues or caused new ones. > > Unfortunately I probably won't get onto it any time soon. I was > hoping > to get some of my other team members to pick up the issue but they're > all busy as well.
Re: linux-next: build warning after merge of the block tree
On 8/8/19 9:00 PM, Stephen Rothwell wrote:
> Hi all,
>
> After merging the block tree, today's linux-next build (x86_64
> allmodconfig) produced this warning:
>
> drivers/lightnvm/pblk-read.c: In function 'pblk_submit_read_gc':
> drivers/lightnvm/pblk-read.c:421:18: warning: unused variable 'geo'
> [-Wunused-variable]
>struct nvm_geo *geo = >geo;
>^~~
>
> Introduced by commit
>
>ba6f7da99aaf ("lightnvm: remove set but not used variables 'data_len' and
> 'rq_len'")
>
> Removing the above line will also remove the last use of the variable
> "dev" ...
Thanks, will fix it up.
--
Jens Axboe
RE: [EXT] Re: i2c: imx: support slave mode for imx I2C driver
>
> Hi,
>
> On Thu, Aug 08, 2019 at 11:53:43AM +0800, Biwen Li wrote:
> > The patch supports slave mode for imx I2C driver
> >
> > Signed-off-by: Biwen Li
> > ---
> > drivers/i2c/busses/i2c-imx.c | 199
> > ---
> > 1 file changed, 185 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-imx.c
> > b/drivers/i2c/busses/i2c-imx.c index b1b8b938d7f4..f7583a9fa56f 100644
> > --- a/drivers/i2c/busses/i2c-imx.c
> > +++ b/drivers/i2c/busses/i2c-imx.c
> > @@ -202,6 +202,9 @@ struct imx_i2c_struct {
> > struct pinctrl_state *pinctrl_pins_gpio;
> >
> > struct imx_i2c_dma *dma;
> > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > + struct i2c_client *slave;
> > +#endif /* CONFIG_I2C_SLAVE */
>
> Other drivers just do a "select I2C_SLAVE" in Kconfig to get rid of these
> #ifs. We
> should do the same.
Hi sascha, I don't know your meaning, could you let it clearer?
>
> > };
> >
> > static const struct imx_i2c_hwdata imx1_i2c_hwdata = { @@ -583,23
> > +586,40 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
> > imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); }
> >
> > -static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
> > +/* Clear interrupt flag bit */
> > +static void i2c_imx_clr_if_bit(struct imx_i2c_struct *i2c_imx)
> > {
> > - struct imx_i2c_struct *i2c_imx = dev_id;
> > - unsigned int temp;
> > + unsigned int status;
> >
> > - temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > - if (temp & I2SR_IIF) {
> > - /* save status register */
> > - i2c_imx->i2csr = temp;
> > - temp &= ~I2SR_IIF;
> > - temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> > - imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
> > - wake_up(_imx->queue);
> > - return IRQ_HANDLED;
> > - }
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + status &= ~I2SR_IIF;
> > + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> > +
> > +/* Clear arbitration lost bit */
> > +static void i2c_imx_clr_al_bit(struct imx_i2c_struct *i2c_imx) {
> > + unsigned int status;
> > +
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + status &= ~I2SR_IAL;
> > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> >
> > - return IRQ_NONE;
> > +static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx)
> > +{
> > + unsigned int status;
> > +
> > + dev_dbg(_imx->adapter.dev, "<%s>: master interrupt\n",
> > + __func__);
>
> Generally this driver has way too many dev_dbg spread around in hot pathes
> already. IMO adding more doesn't make the output more useful.
Ok, got it. I will delete it in v2.
>
> > +
> > + /* Save status register */
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + i2c_imx->i2csr = status | I2SR_IIF;
> > +
> > + wake_up(_imx->queue);
> > +
> > + return IRQ_HANDLED;
> > }
> >
> > static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, @@
> > -1043,11 +1063,162 @@ static u32 i2c_imx_func(struct i2c_adapter
> *adapter)
> > | I2C_FUNC_SMBUS_READ_BLOCK_DATA; }
> >
> > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > +static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) {
> > + unsigned int temp;
> > +
> > + dev_dbg(_imx->adapter.dev, "<%s>\n", __func__);
> > +
> > + /* Set slave addr. */
> > + imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx,
> > + IMX_I2C_IADR);
> > +
> > + /* Disable i2c module */
> > + temp = i2c_imx->hwdata->i2cr_ien_opcode
> > + ^ I2CR_IEN;
>
> unnecessary line break.
Ok, no problem. I will remove the line break in v2.
>
> > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +
> > + /* Reset status register */
> > + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
> > + IMX_I2C_I2SR);
> > +
> > + /* Enable module and enable interrupt from i2c module */
> > + temp = i2c_imx->hwdata->i2cr_ien_opcode
> > + | I2CR_IIEN;
>
> ditto.
Ok. I will remove the line break in v2.
>
> > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +
> > + /* Wait controller to be stable */
> > + usleep_range(50, 150);
> > +}
> > +
> > +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx)
> > +{
> > + unsigned int status, ctl;
> > + u8 value;
> > +
> > + if (!i2c_imx->slave) {
> > + dev_err(_imx->adapter.dev, "cannot deal with slave
> irq,i2c_imx->slave is null");
> > + return IRQ_NONE;
> > + }
> > +
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
> > + if (status & I2SR_IAL) { /* Arbitration lost */
> > + i2c_imx_clr_al_bit(i2c_imx);
> > + } else if (status &
linux-next: build warning after merge of the block tree
Hi all,
After merging the block tree, today's linux-next build (x86_64
allmodconfig) produced this warning:
drivers/lightnvm/pblk-read.c: In function 'pblk_submit_read_gc':
drivers/lightnvm/pblk-read.c:421:18: warning: unused variable 'geo'
[-Wunused-variable]
struct nvm_geo *geo = >geo;
^~~
Introduced by commit
ba6f7da99aaf ("lightnvm: remove set but not used variables 'data_len' and
'rq_len'")
Removing the above line will also remove the last use of the variable
"dev" ...
--
Cheers,
Stephen Rothwell
pgpQHtz0E10Lr.pgp
Description: OpenPGP digital signature
[PATCH] fs/ceph: use release_pages() directly
From: John Hubbard
release_pages() has been available to modules since Oct, 2010,
when commit 0be8557bcd34 ("fuse: use release_pages()") added
EXPORT_SYMBOL(release_pages). However, this ceph code was still
using a workaround.
Remove the workaround, and call release_pages() directly.
Cc: Jeff Layton
Cc: Sage Weil
Cc: Ilya Dryomov
Cc: ceph-de...@vger.kernel.org
Signed-off-by: John Hubbard
---
Hi,
I noticed this while I trying to understand mlock.c's use of
pagevec_release(). So I was looking around for examples, and stumbled
across this, which seems worth cleaning up.
thanks,
John Hubbard
NVIDIA
fs/ceph/addr.c | 19 +--
1 file changed, 1 insertion(+), 18 deletions(-)
diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c
index e078cc55b989..22ed45d143be 100644
--- a/fs/ceph/addr.c
+++ b/fs/ceph/addr.c
@@ -679,23 +679,6 @@ static int ceph_writepage(struct page *page, struct
writeback_control *wbc)
return err;
}
-/*
- * lame release_pages helper. release_pages() isn't exported to
- * modules.
- */
-static void ceph_release_pages(struct page **pages, int num)
-{
- struct pagevec pvec;
- int i;
-
- pagevec_init();
- for (i = 0; i < num; i++) {
- if (pagevec_add(, pages[i]) == 0)
- pagevec_release();
- }
- pagevec_release();
-}
-
/*
* async writeback completion handler.
*
@@ -769,7 +752,7 @@ static void writepages_finish(struct ceph_osd_request *req)
dout("writepages_finish %p wrote %llu bytes cleaned %d pages\n",
inode, osd_data->length, rc >= 0 ? num_pages : 0);
- ceph_release_pages(osd_data->pages, num_pages);
+ release_pages(osd_data->pages, num_pages);
}
ceph_put_wrbuffer_cap_refs(ci, total_pages, snapc);
--
2.22.0
[PATCH 0/3] x86/mtrr, pat: make PAT independent from MTRR
Make PAT(Page Attribute Table) independent from MTRR(Memory Type Range Register). Some environments (mainly virtual ones) support only PAT, but not MTRR because PAT replaces MTRR. It's tricky and no gain to support both MTRR and PAT except compatibility. So some VM technologies don't support MTRR, but only PAT. This patch series makes PAT available on such environments without MTRR. patch 1 and 2 are only preparation. no logic change, function rename (mtrr_ => mtrr_pat_ which is commonly used by both MTRR and PAT) and moving functions out from mtrr specific files to a common file. patch 3 is an essential patch which makes PAT independent from MTRR. Isaku Yamahata (3): x86/mtrr: split common funcs from mtrr.c x86/mtrr: split common funcs from generic.c x86/mtrr, pat: make PAT independent from MTRR arch/x86/Kconfig | 1 - arch/x86/include/asm/mtrr.h | 37 ++- arch/x86/include/asm/pat.h| 2 + arch/x86/kernel/cpu/common.c | 2 +- arch/x86/kernel/cpu/mtrr/Makefile | 2 +- arch/x86/kernel/cpu/mtrr/generic.c| 116 + arch/x86/kernel/cpu/mtrr/mtrr.c | 211 + arch/x86/kernel/cpu/mtrr/mtrr.h | 8 +- arch/x86/kernel/cpu/mtrr/rendezvous.c | 324 ++ arch/x86/kernel/setup.c | 4 +- arch/x86/kernel/smpboot.c | 8 +- arch/x86/mm/Makefile | 3 + arch/x86/mm/pat.c | 99 +++- arch/x86/power/cpu.c | 2 +- 14 files changed, 479 insertions(+), 340 deletions(-) create mode 100644 arch/x86/kernel/cpu/mtrr/rendezvous.c -- 2.17.1
[PATCH 2/3] x86/mtrr: split common funcs from generic.c
This is a preparation for make PAT(Page Attribute Table) independent
from MTRR(Memory Type Range Register).
It renames prefix of common functions in mtrr/generic.c from mtrr_ to
mtrr_pat_ which are commonly used by both MTRR and PAT and moves out
them from mtrr/generic.c to rendezvous.c.
Only prefix rename and movement, no logic change.
Signed-off-by: Isaku Yamahata
---
arch/x86/include/asm/mtrr.h | 4 +
arch/x86/kernel/cpu/mtrr/generic.c| 111 ++
arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +-
arch/x86/kernel/cpu/mtrr/mtrr.h | 3 +-
arch/x86/kernel/cpu/mtrr/rendezvous.c | 91 +
5 files changed, 106 insertions(+), 105 deletions(-)
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index d90e87c55302..5b056374f5a6 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -33,6 +33,8 @@
*/
# ifdef CONFIG_MTRR
extern bool mtrr_enabled(void);
+extern void mtrr_pat_prepare_set(void) __acquires(set_atomicity_lock);
+extern void mtrr_pat_post_set(void) __releases(set_atomicity_lock);
extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform);
extern void mtrr_save_fixed_ranges(void *);
extern void mtrr_save_state(void);
@@ -55,6 +57,8 @@ static inline bool mtrr_enabled(void)
{
return false;
}
+static inline void mtrr_pat_prepare_set(void) { };
+static inline void mtrr_pat_post_set(void) { };
static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform)
{
/*
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c
b/arch/x86/kernel/cpu/mtrr/generic.c
index aa5c064a6a22..a44f05f64846 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -397,9 +397,6 @@ print_fixed(unsigned base, unsigned step, const mtrr_type
*types)
}
}
-static void prepare_set(void);
-static void post_set(void);
-
static void __init print_mtrr_state(void)
{
unsigned int i;
@@ -445,20 +442,6 @@ static void __init print_mtrr_state(void)
pr_debug("TOM2: %016llx aka %lldM\n", mtrr_tom2, mtrr_tom2>>20);
}
-/* PAT setup for BP. We need to go through sync steps here */
-void __init mtrr_bp_pat_init(void)
-{
- unsigned long flags;
-
- local_irq_save(flags);
- prepare_set();
-
- pat_init();
-
- post_set();
- local_irq_restore(flags);
-}
-
/* Grab all of the MTRR state for this CPU into *state */
bool __init get_mtrr_state(void)
{
@@ -680,8 +663,6 @@ static bool set_mtrr_var_ranges(unsigned int index, struct
mtrr_var_range *vr)
return changed;
}
-static u32 deftype_lo, deftype_hi;
-
/**
* set_mtrr_state - Set the MTRR state for this CPU.
*
@@ -705,100 +686,24 @@ static unsigned long set_mtrr_state(void)
* Set_mtrr_restore restores the old value of MTRRdefType,
* so to set it we fiddle with the saved value:
*/
- if ((deftype_lo & 0xff) != mtrr_state.def_type
- || ((deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
+ if ((mtrr_deftype_lo & 0xff) != mtrr_state.def_type
+ || ((mtrr_deftype_lo & 0xc00) >> 10) != mtrr_state.enabled) {
- deftype_lo = (deftype_lo & ~0xcff) | mtrr_state.def_type |
-(mtrr_state.enabled << 10);
+ mtrr_deftype_lo = (mtrr_deftype_lo & ~0xcff) |
+ mtrr_state.def_type | (mtrr_state.enabled << 10);
change_mask |= MTRR_CHANGE_MASK_DEFTYPE;
}
return change_mask;
}
-
-static unsigned long cr4;
-static DEFINE_RAW_SPINLOCK(set_atomicity_lock);
-
-/*
- * Since we are disabling the cache don't allow any interrupts,
- * they would run extremely slow and would only increase the pain.
- *
- * The caller must ensure that local interrupts are disabled and
- * are reenabled after post_set() has been called.
- */
-static void prepare_set(void) __acquires(set_atomicity_lock)
-{
- unsigned long cr0;
-
- /*
-* Note that this is not ideal
-* since the cache is only flushed/disabled for this CPU while the
-* MTRRs are changed, but changing this requires more invasive
-* changes to the way the kernel boots
-*/
-
- raw_spin_lock(_atomicity_lock);
-
- /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */
- cr0 = read_cr0() | X86_CR0_CD;
- write_cr0(cr0);
-
- /*
-* Cache flushing is the most time-consuming step when programming
-* the MTRRs. Fortunately, as per the Intel Software Development
-* Manual, we can skip it if the processor supports cache self-
-* snooping.
-*/
- if (!static_cpu_has(X86_FEATURE_SELFSNOOP))
- wbinvd();
-
- /* Save value of CR4 and clear Page Global Enable (bit 7) */
- if (boot_cpu_has(X86_FEATURE_PGE)) {
- cr4 = __read_cr4();
- __write_cr4(cr4 & ~X86_CR4_PGE);
- }
-
- /* Flush all TLBs via a
[PATCH 3/3] x86/mtrr, pat: make PAT independent from MTRR
This patch makes PAT(Page Attribute Table) independent from
MTRR(Memory Type Range Register)
Some environments (mainly virtual ones) support only PAT, not MTRR.
It's tricky and no gain to support both MTRR and PAT at the
same time except compatibility because PAT replaces MTRR.
So some VM technologies don't support MTRR, but only PAT.
This patch make PAT available on such environments without MTRR.
Signed-off-by: Isaku Yamahata
---
arch/x86/Kconfig | 1 -
arch/x86/include/asm/mtrr.h | 32 +
arch/x86/include/asm/pat.h| 2 +
arch/x86/kernel/cpu/mtrr/generic.c| 5 --
arch/x86/kernel/cpu/mtrr/mtrr.c | 8 +--
arch/x86/kernel/cpu/mtrr/mtrr.h | 1 -
arch/x86/kernel/cpu/mtrr/rendezvous.c | 76 +++-
arch/x86/mm/Makefile | 3 +
arch/x86/mm/pat.c | 99 ---
9 files changed, 158 insertions(+), 69 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 222855cc0158..5654283e010f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1838,7 +1838,6 @@ config MTRR_SANITIZER_SPARE_REG_NR_DEFAULT
config X86_PAT
def_bool y
prompt "x86 PAT support" if EXPERT
- depends on MTRR
---help---
Use PAT attributes to setup page level cache control.
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index 5b056374f5a6..a401ad106c28 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -31,10 +31,25 @@
* The following functions are for use by other drivers that cannot use
* arch_phys_wc_add and arch_phys_wc_del.
*/
-# ifdef CONFIG_MTRR
-extern bool mtrr_enabled(void);
+#if defined(CONFIG_MTRR) || defined(CONFIG_X86_PAT)
+/* common method for MTRR and PAT */
extern void mtrr_pat_prepare_set(void) __acquires(set_atomicity_lock);
extern void mtrr_pat_post_set(void) __releases(set_atomicity_lock);
+extern void mtrr_pat_ap_init(void);
+extern void set_mtrr_pat_aps_delayed_init(void);
+extern void mtrr_pat_aps_init(void);
+extern void mtrr_pat_bp_restore(void);
+#else
+static inline void mtrr_pat_prepare_set(void) { }
+static inline void mtrr_pat_post_set(void) { }
+static inline void mtrr_pat_ap_init(void) { };
+static inline void set_mtrr_pat_aps_delayed_init(void) { };
+static inline void mtrr_pat_aps_init(void) { };
+static inline void mtrr_pat_bp_restore(void) { };
+#endif
+
+# ifdef CONFIG_MTRR
+extern bool mtrr_enabled(void);
extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform);
extern void mtrr_save_fixed_ranges(void *);
extern void mtrr_save_state(void);
@@ -45,11 +60,7 @@ extern int mtrr_add_page(unsigned long base, unsigned long
size,
extern int mtrr_del(int reg, unsigned long base, unsigned long size);
extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
-extern void mtrr_pat_ap_init(void);
extern void mtrr_pat_bp_init(void);
-extern void set_mtrr_pat_aps_delayed_init(void);
-extern void mtrr_pat_aps_init(void);
-extern void mtrr_pat_bp_restore(void);
extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
extern int amd_special_default_mtrr(void);
# else
@@ -57,8 +68,6 @@ static inline bool mtrr_enabled(void)
{
return false;
}
-static inline void mtrr_pat_prepare_set(void) { };
-static inline void mtrr_pat_post_set(void) { };
static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform)
{
/*
@@ -95,13 +104,8 @@ static inline void mtrr_centaur_report_mcr(int mcr, u32 lo,
u32 hi)
}
static inline void mtrr_pat_bp_init(void)
{
- pat_disable("MTRRs disabled, skipping PAT initialization too.");
+ pat_bp_init();
}
-
-static inline void mtrr_pat_ap_init(void) { };
-static inline void set_mtrr_pat_aps_delayed_init(void) { };
-static inline void mtrr_pat_aps_init(void) { };
-static inline void mtrr_pat_bp_restore(void) { };
# endif
#ifdef CONFIG_COMPAT
diff --git a/arch/x86/include/asm/pat.h b/arch/x86/include/asm/pat.h
index 92015c65fa2a..2a355ce94ebf 100644
--- a/arch/x86/include/asm/pat.h
+++ b/arch/x86/include/asm/pat.h
@@ -7,7 +7,9 @@
bool pat_enabled(void);
void pat_disable(const char *reason);
+extern void pat_set(void);
extern void pat_init(void);
+extern void pat_bp_init(void);
extern void init_cache_modes(void);
extern int reserve_memtype(u64 start, u64 end,
diff --git a/arch/x86/kernel/cpu/mtrr/generic.c
b/arch/x86/kernel/cpu/mtrr/generic.c
index a44f05f64846..f9a7ca79e2c2 100644
--- a/arch/x86/kernel/cpu/mtrr/generic.c
+++ b/arch/x86/kernel/cpu/mtrr/generic.c
@@ -6,13 +6,8 @@
#define DEBUG
#include
-#include
-#include
#include
-#include
-#include
-#include
#include
#include
#include
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 475627ca2c1b..2d28c9b37ae7 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -657,13
[PATCH 1/3] x86/mtrr: split common funcs from mtrr.c
This is a preparation for make PAT(Page Attribute Table) independent
from MTRR(Memory Type Range Register).
It renames prefix of common functions in mtrr.c from mtrr_ to
mtrr_pat_ which are commonly used by both MTRR and PAT and moves out
them from mtrr.c to rendezvous.c.
Only prefix rename and movement, no logic change.
Signed-off-by: Isaku Yamahata
---
arch/x86/include/asm/mtrr.h | 25 +--
arch/x86/kernel/cpu/common.c | 2 +-
arch/x86/kernel/cpu/mtrr/Makefile | 2 +-
arch/x86/kernel/cpu/mtrr/mtrr.c | 201 ++-
arch/x86/kernel/cpu/mtrr/mtrr.h | 6 +
arch/x86/kernel/cpu/mtrr/rendezvous.c | 221 ++
arch/x86/kernel/setup.c | 4 +-
arch/x86/kernel/smpboot.c | 8 +-
arch/x86/power/cpu.c | 2 +-
9 files changed, 260 insertions(+), 211 deletions(-)
create mode 100644 arch/x86/kernel/cpu/mtrr/rendezvous.c
diff --git a/arch/x86/include/asm/mtrr.h b/arch/x86/include/asm/mtrr.h
index dbff1456d215..d90e87c55302 100644
--- a/arch/x86/include/asm/mtrr.h
+++ b/arch/x86/include/asm/mtrr.h
@@ -32,6 +32,7 @@
* arch_phys_wc_add and arch_phys_wc_del.
*/
# ifdef CONFIG_MTRR
+extern bool mtrr_enabled(void);
extern u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform);
extern void mtrr_save_fixed_ranges(void *);
extern void mtrr_save_state(void);
@@ -42,14 +43,18 @@ extern int mtrr_add_page(unsigned long base, unsigned long
size,
extern int mtrr_del(int reg, unsigned long base, unsigned long size);
extern int mtrr_del_page(int reg, unsigned long base, unsigned long size);
extern void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi);
-extern void mtrr_ap_init(void);
-extern void mtrr_bp_init(void);
-extern void set_mtrr_aps_delayed_init(void);
-extern void mtrr_aps_init(void);
-extern void mtrr_bp_restore(void);
+extern void mtrr_pat_ap_init(void);
+extern void mtrr_pat_bp_init(void);
+extern void set_mtrr_pat_aps_delayed_init(void);
+extern void mtrr_pat_aps_init(void);
+extern void mtrr_pat_bp_restore(void);
extern int mtrr_trim_uncached_memory(unsigned long end_pfn);
extern int amd_special_default_mtrr(void);
# else
+static inline bool mtrr_enabled(void)
+{
+ return false;
+}
static inline u8 mtrr_type_lookup(u64 addr, u64 end, u8 *uniform)
{
/*
@@ -84,15 +89,15 @@ static inline int mtrr_trim_uncached_memory(unsigned long
end_pfn)
static inline void mtrr_centaur_report_mcr(int mcr, u32 lo, u32 hi)
{
}
-static inline void mtrr_bp_init(void)
+static inline void mtrr_pat_bp_init(void)
{
pat_disable("MTRRs disabled, skipping PAT initialization too.");
}
-#define mtrr_ap_init() do {} while (0)
-#define set_mtrr_aps_delayed_init() do {} while (0)
-#define mtrr_aps_init() do {} while (0)
-#define mtrr_bp_restore() do {} while (0)
+static inline void mtrr_pat_ap_init(void) { };
+static inline void set_mtrr_pat_aps_delayed_init(void) { };
+static inline void mtrr_pat_aps_init(void) { };
+static inline void mtrr_pat_bp_restore(void) { };
# endif
#ifdef CONFIG_COMPAT
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 11472178e17f..39b7942cb6fc 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1550,7 +1550,7 @@ void identify_secondary_cpu(struct cpuinfo_x86 *c)
#ifdef CONFIG_X86_32
enable_sep_cpu();
#endif
- mtrr_ap_init();
+ mtrr_pat_ap_init();
validate_apic_and_package_id(c);
x86_spec_ctrl_setup_ap();
}
diff --git a/arch/x86/kernel/cpu/mtrr/Makefile
b/arch/x86/kernel/cpu/mtrr/Makefile
index cc4f9f1cb94c..e339d729f349 100644
--- a/arch/x86/kernel/cpu/mtrr/Makefile
+++ b/arch/x86/kernel/cpu/mtrr/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0-only
-obj-y := mtrr.o if.o generic.o cleanup.o
+obj-y := mtrr.o if.o generic.o cleanup.o rendezvous.o
obj-$(CONFIG_X86_32) += amd.o cyrix.o centaur.o
diff --git a/arch/x86/kernel/cpu/mtrr/mtrr.c b/arch/x86/kernel/cpu/mtrr/mtrr.c
index 507039c20128..3d35edb1aa42 100644
--- a/arch/x86/kernel/cpu/mtrr/mtrr.c
+++ b/arch/x86/kernel/cpu/mtrr/mtrr.c
@@ -35,7 +35,6 @@
#include /* FIXME: kvm_para.h needs this */
-#include
#include
#include
#include
@@ -46,10 +45,7 @@
#include
#include
#include
-#include
-#include
-#include
#include
#include
#include
@@ -62,7 +58,7 @@
u32 num_var_ranges;
static bool __mtrr_enabled;
-static bool mtrr_enabled(void)
+bool mtrr_enabled(void)
{
return __mtrr_enabled;
}
@@ -71,15 +67,11 @@ unsigned int mtrr_usage_table[MTRR_MAX_VAR_RANGES];
static DEFINE_MUTEX(mtrr_mutex);
u64 size_or_mask, size_and_mask;
-static bool mtrr_aps_delayed_init;
static const struct mtrr_ops *mtrr_ops[X86_VENDOR_NUM] __ro_after_init;
const struct mtrr_ops *mtrr_if;
-static void set_mtrr(unsigned int reg, unsigned long base,
-unsigned long size, mtrr_type type);
-
void __init set_mtrr_ops(const struct mtrr_ops
Re: [PATCH] ata: ahci: Lookup PCS register offset based on PCI device ID
On 8/8/19 1:24 PM, Stephen Douthit wrote:
> Intel moved the PCS register from 0x92 to 0x94 on Denverton for some
> reason, so now we get to check the device ID before poking it on reset.
>
> Signed-off-by: Stephen Douthit
> ---
> drivers/ata/ahci.c | 42 +++---
> 1 file changed, 39 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
> index f7652baa6337..7090c7754fc2 100644
> --- a/drivers/ata/ahci.c
> +++ b/drivers/ata/ahci.c
> @@ -623,6 +623,41 @@ static void ahci_pci_save_initial_config(struct pci_dev
> *pdev,
> ahci_save_initial_config(>dev, hpriv);
> }
>
> +/*
> + * Intel moved the PCS register on the Denverton AHCI controller, see which
> + * offset this controller is using
> + */
> +static int ahci_pcs_offset(struct ata_host *host)
> +{
> + struct pci_dev *pdev = to_pci_dev(host->dev);
> +
> + switch (pdev->device) {
> + case 0x19b0:
> + case 0x19b1:
> + case 0x19b2:
> + case 0x19b3:
> + case 0x19b4:
> + case 0x19b5:
> + case 0x19b6:
> + case 0x19b7:
> + case 0x19bE:
> + case 0x19bF:
> + case 0x19c0:
> + case 0x19c1:
> + case 0x19c2:
> + case 0x19c3:
> + case 0x19c4:
> + case 0x19c5:
> + case 0x19c6:
> + case 0x19c7:
> + case 0x19cE:
> + case 0x19cF:
Any particular reason why you made some of hex alphas upper case?
--
Jens Axboe
linux-next: manual merge of the sound-asoc tree with the sound tree
Hi all,
Today's linux-next merge of the sound-asoc tree got a conflict in:
sound/soc/sof/intel/hda-dsp.c
between commit:
19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
from the sound tree and commits:
fd15f2f5e272 ("ASoC: SOF: Intel: hda: Enable jack detection")
d06973515f95 ("ASoC: SOF: Intel: hda: use SOF defined init chip in resume")
from the sound-asoc tree.
I fixed it up (I used the latter version and added the following merge
fix patch) and can carry the fix as necessary. This is now fixed as far as
linux-next is concerned, but any non trivial conflicts should be mentioned
to your upstream maintainer when your tree is submitted for merging.
You may also want to consider cooperating with the maintainer of the
conflicting tree to minimise any particularly complex conflicts.
From: Stephen Rothwell
Date: Fri, 9 Aug 2019 13:28:00 +1000
Subject: [PATCH] ASoc: SOF: Intel: hda: merge fix up for "ALSA: hda: Direct
MMIO accesses"
Signed-off-by: Stephen Rothwell
---
sound/soc/sof/intel/hda-ctrl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/sound/soc/sof/intel/hda-ctrl.c b/sound/soc/sof/intel/hda-ctrl.c
index a7fee403cb90..bc41028a7a01 100644
--- a/sound/soc/sof/intel/hda-ctrl.c
+++ b/sound/soc/sof/intel/hda-ctrl.c
@@ -254,7 +254,7 @@ int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool
full_reset)
#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
/* Reset stream-to-link mapping */
list_for_each_entry(hlink, >hlink_list, list)
- bus->io_ops->reg_writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
+ writel(0, hlink->ml_addr + AZX_REG_ML_LOSIDV);
#endif
bus->chip_init = true;
--
2.20.1
--
Cheers,
Stephen Rothwell
pgpWpRlSGL0Dy.pgp
Description: OpenPGP digital signature
Re: [PATCH 2/2] regulator: qcom-rpmh: Add support for SM8150
On Thu 08 Aug 02:33 PDT 2019, Vinod Koul wrote:
> diff --git a/drivers/regulator/qcom-rpmh-regulator.c
> b/drivers/regulator/qcom-rpmh-regulator.c
[..]
> +static const struct rpmh_vreg_hw_data pmic5_bob = {
> + .regulator_type = VRM,
> + .ops = _regulator_vrm_bypass_ops,
> + .voltage_range = REGULATOR_LINEAR_RANGE(30, 0, 135, 32000),
> + .n_voltages = 135,
There are 136 voltages in [0,135]
> + .pmic_mode_map = pmic_mode_map_pmic4_bob,
> + .of_map_mode = rpmh_regulator_pmic4_bob_of_map_mode,
> +};
> +
[..]
> @@ -755,6 +890,18 @@ static const struct of_device_id
> rpmh_regulator_match_table[] = {
> .compatible = "qcom,pm8005-rpmh-regulators",
> .data = pm8005_vreg_data,
> },
> + {
> + .compatible = "qcom,pm8150-rpmh-regulators",
> + .data = pm8150_vreg_data,
> + },
> + {
> + .compatible = "qcom,pm8150l-rpmh-regulators",
> + .data = pm8150l_vreg_data,
> + },
> + {
> + .compatible = "qcom,pm8009-rpmh-regulators",
> + .data = pm8009_vreg_data,
> + },
Sort order...
> {}
> };
> MODULE_DEVICE_TABLE(of, rpmh_regulator_match_table);
Apart from these nits this looks good.
Regards,
Bjorn
Re: [PATCH 1/2] regulator: dt-bindings: Add PM8150x compatibles
On Thu 08 Aug 02:33 PDT 2019, Vinod Koul wrote: > Add PM8150, PM8150L and PM8009 compatibles for these PMICs found > in some Qualcomm platforms. > > Signed-off-by: Vinod Koul > --- > .../devicetree/bindings/regulator/qcom,rpmh-regulator.txt | 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git > a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > index 14d2eee96b3d..1a9cab50503a 100644 > --- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > +++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.txt > @@ -25,6 +25,9 @@ Supported regulator node names: > PM8998: smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2 > PMI8998:bob > PM8005: smps1 - smps4 > + PM8150: smps1 - smps10, ldo1 - ldo18 > + PM8150L:smps1 - smps8, ldo1 - ldo11, bob, flash, rgb > + PM8009: smps1 - smps2, ld01 - ldo7 Please maintain the sort order. Apart from that Reviewed-by: Bjorn Andersson Regards, Bjorn > > > First Level Nodes - PMIC > @@ -35,7 +38,10 @@ First Level Nodes - PMIC > Value type: > Definition: Must be one of: "qcom,pm8998-rpmh-regulators", > "qcom,pmi8998-rpmh-regulators" or > - "qcom,pm8005-rpmh-regulators". > + "qcom,pm8005-rpmh-regulators" or > + "qcom,pm8150-rpmh-regulators" or > + "qcom,pm8150l-rpmh-regulators" or > + "qcom,pm8009-rpmh-regulators". > > - qcom,pmic-id > Usage: required > -- > 2.20.1 >
Re: [PATCH 4.19 00/45] 4.19.66-stable review
On Fri, 9 Aug 2019 at 00:39, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.19.66 release. > There are 45 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat 10 Aug 2019 07:03:19 PM UTC. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.19.66-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.19.y > and the diffstat can be found below. > > thanks, > > greg k-h Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.19.66-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.19.y git commit: d43238541496ae2b216aaac84e0933bb06eeb0a6 git describe: v4.19.64-128-gd43238541496 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.19-oe/build/v4.19.64-128-gd43238541496 No regressions (compared to build v4.19.64) No fixes (compared to build v4.19.64) Ran 23168 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * build * install-android-platform-tools-r2600 * kselftest * libgpiod * libhugetlbfs * ltp-cap_bounds-tests * ltp-containers-tests * ltp-cpuhotplug-tests * ltp-cve-tests * ltp-dio-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-mm-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-timers-tests * perf * spectre-meltdown-checker-test * v4l2-compliance * ltp-commands-tests * ltp-fs-tests * ltp-math-tests * ltp-syscalls-tests * network-basic-tests * ltp-open-posix-tests * kvm-unit-tests * ssuite * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none -- Linaro LKFT https://lkft.linaro.org
RE: [EXT] Re: i2c: imx: support slave mode for imx I2C driver
> > The patch supports slave mode for imx I2C driver
> >
> > Signed-off-by: Biwen Li
>
> Wow, this is much simpler than the other approach flying around:
>
> http://patchwork.ozlabs.org/patch/1124048/
>
> Can this one be master and slave on the same bus, too?
At the same time, the same bus is in master mode or slave mode.
>
> CCing the author of the other patch.
>
> > ---
> > drivers/i2c/busses/i2c-imx.c | 199
> > ---
> > 1 file changed, 185 insertions(+), 14 deletions(-)
> >
> > diff --git a/drivers/i2c/busses/i2c-imx.c
> > b/drivers/i2c/busses/i2c-imx.c index b1b8b938d7f4..f7583a9fa56f 100644
> > --- a/drivers/i2c/busses/i2c-imx.c
> > +++ b/drivers/i2c/busses/i2c-imx.c
> > @@ -202,6 +202,9 @@ struct imx_i2c_struct {
> > struct pinctrl_state *pinctrl_pins_gpio;
> >
> > struct imx_i2c_dma *dma;
> > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > + struct i2c_client *slave;
> > +#endif /* CONFIG_I2C_SLAVE */
> > };
> >
> > static const struct imx_i2c_hwdata imx1_i2c_hwdata = { @@ -583,23
> > +586,40 @@ static void i2c_imx_stop(struct imx_i2c_struct *i2c_imx)
> > imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR); }
> >
> > -static irqreturn_t i2c_imx_isr(int irq, void *dev_id)
> > +/* Clear interrupt flag bit */
> > +static void i2c_imx_clr_if_bit(struct imx_i2c_struct *i2c_imx)
> > {
> > - struct imx_i2c_struct *i2c_imx = dev_id;
> > - unsigned int temp;
> > + unsigned int status;
> >
> > - temp = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > - if (temp & I2SR_IIF) {
> > - /* save status register */
> > - i2c_imx->i2csr = temp;
> > - temp &= ~I2SR_IIF;
> > - temp |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> > - imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2SR);
> > - wake_up(_imx->queue);
> > - return IRQ_HANDLED;
> > - }
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + status &= ~I2SR_IIF;
> > + status |= (i2c_imx->hwdata->i2sr_clr_opcode & I2SR_IIF);
> > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> > +
> > +/* Clear arbitration lost bit */
> > +static void i2c_imx_clr_al_bit(struct imx_i2c_struct *i2c_imx) {
> > + unsigned int status;
> > +
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + status &= ~I2SR_IAL;
> > + imx_i2c_write_reg(status, i2c_imx, IMX_I2C_I2SR); }
> >
> > - return IRQ_NONE;
> > +static irqreturn_t i2c_imx_master_isr(struct imx_i2c_struct *i2c_imx)
> > +{
> > + unsigned int status;
> > +
> > + dev_dbg(_imx->adapter.dev, "<%s>: master interrupt\n",
> > +__func__);
> > +
> > + /* Save status register */
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + i2c_imx->i2csr = status | I2SR_IIF;
> > +
> > + wake_up(_imx->queue);
> > +
> > + return IRQ_HANDLED;
> > }
> >
> > static int i2c_imx_dma_write(struct imx_i2c_struct *i2c_imx, @@
> > -1043,11 +1063,162 @@ static u32 i2c_imx_func(struct i2c_adapter
> *adapter)
> > | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
> > }
> >
> > +#if IS_ENABLED(CONFIG_I2C_SLAVE)
> > +static void i2c_imx_slave_init(struct imx_i2c_struct *i2c_imx) {
> > + unsigned int temp;
> > +
> > + dev_dbg(_imx->adapter.dev, "<%s>\n", __func__);
> > +
> > + /* Set slave addr. */
> > + imx_i2c_write_reg((i2c_imx->slave->addr << 1), i2c_imx,
> > +IMX_I2C_IADR);
> > +
> > + /* Disable i2c module */
> > + temp = i2c_imx->hwdata->i2cr_ien_opcode
> > + ^ I2CR_IEN;
> > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +
> > + /* Reset status register */
> > + imx_i2c_write_reg(i2c_imx->hwdata->i2sr_clr_opcode, i2c_imx,
> > + IMX_I2C_I2SR);
> > +
> > + /* Enable module and enable interrupt from i2c module */
> > + temp = i2c_imx->hwdata->i2cr_ien_opcode
> > + | I2CR_IIEN;
> > + imx_i2c_write_reg(temp, i2c_imx, IMX_I2C_I2CR);
> > +
> > + /* Wait controller to be stable */
> > + usleep_range(50, 150);
> > +}
> > +
> > +static irqreturn_t i2c_imx_slave_isr(struct imx_i2c_struct *i2c_imx)
> > +{
> > + unsigned int status, ctl;
> > + u8 value;
> > +
> > + if (!i2c_imx->slave) {
> > + dev_err(_imx->adapter.dev, "cannot deal with slave
> irq,i2c_imx->slave is null");
> > + return IRQ_NONE;
> > + }
> > +
> > + status = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR);
> > + ctl = imx_i2c_read_reg(i2c_imx, IMX_I2C_I2CR);
> > + if (status & I2SR_IAL) { /* Arbitration lost */
> > + i2c_imx_clr_al_bit(i2c_imx);
> > + } else if (status & I2SR_IAAS) { /* Addressed as a slave */
> > + if (status & I2SR_SRW) { /* Master wants to read from us*/
> > + dev_dbg(_imx->adapter.dev, "read requested");
> > + i2c_slave_event(i2c_imx->slave,
> > I2C_SLAVE_READ_REQUESTED,
> );
> > +
> > + /* Slave transimt */
> > + ctl |= I2CR_MTX;
> > + imx_i2c_write_reg(ctl,
Re: [PATCH 4.14 00/33] 4.14.138-stable review
On Fri, 9 Aug 2019 at 00:41, Greg Kroah-Hartman wrote: > > This is the start of the stable review cycle for the 4.14.138 release. > There are 33 patches in this series, all will be posted as a response > to this one. If anyone has any issues with these being applied, please > let me know. > > Responses should be made by Sat 10 Aug 2019 07:03:19 PM UTC. > Anything received after that time might be too late. > > The whole patch series can be found in one patch at: > > https://www.kernel.org/pub/linux/kernel/v4.x/stable-review/patch-4.14.138-rc1.gz > or in the git tree and branch at: > > git://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git > linux-4.14.y > and the diffstat can be found below. > > thanks, > > greg k-h Results from Linaro’s test farm. No regressions on arm64, arm, x86_64, and i386. Summary kernel: 4.14.138-rc1 git repo: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux-stable-rc.git git branch: linux-4.14.y git commit: 4ec3ef9505a33da8c993347fc2e178b46356bb92 git describe: v4.14.136-94-g4ec3ef9505a3 Test details: https://qa-reports.linaro.org/lkft/linux-stable-rc-4.14-oe/build/v4.14.136-94-g4ec3ef9505a3 No regressions (compared to build v4.14.136) No fixes (compared to build v4.14.136) Ran 23722 total tests in the following environments and test suites. Environments -- - dragonboard-410c - arm64 - hi6220-hikey - arm64 - i386 - juno-r2 - arm64 - qemu_arm - qemu_arm64 - qemu_i386 - qemu_x86_64 - x15 - arm - x86_64 Test Suites --- * build * install-android-platform-tools-r2600 * kselftest * libhugetlbfs * ltp-cap_bounds-tests * ltp-commands-tests * ltp-cpuhotplug-tests * ltp-cve-tests * ltp-dio-tests * ltp-fcntl-locktests-tests * ltp-filecaps-tests * ltp-fs-tests * ltp-fs_bind-tests * ltp-fs_perms_simple-tests * ltp-fsx-tests * ltp-hugetlb-tests * ltp-io-tests * ltp-ipc-tests * ltp-math-tests * ltp-mm-tests * ltp-nptl-tests * ltp-pty-tests * ltp-sched-tests * ltp-securebits-tests * ltp-syscalls-tests * ltp-timers-tests * perf * spectre-meltdown-checker-test * v4l2-compliance * ltp-containers-tests * network-basic-tests * ltp-open-posix-tests * kvm-unit-tests * kselftest-vsyscall-mode-native * kselftest-vsyscall-mode-none * ssuite -- Linaro LKFT https://lkft.linaro.org
linux-next: manual merge of the sound-asoc tree with the sound tree
Hi all,
Today's linux-next merge of the sound-asoc tree (yesterday' version)
got a conflict in:
sound/soc/intel/skylake/skl.c
between commit:
19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
from the sound tree and commit:
bcc2a2dc3ba8 ("ASoC: Intel: Skylake: Merge skl_sst and skl into skl_dev
struct")
from the sound-asoc tree.
I fixed it up (see below) and can carry the fix as necessary. This
is now fixed as far as linux-next is concerned, but any non trivial
conflicts should be mentioned to your upstream maintainer when your tree
is submitted for merging. You may also want to consider cooperating
with the maintainer of the conflicting tree to minimise any particularly
complex conflicts.
--
Cheers,
Stephen Rothwell
diff --cc sound/soc/intel/skylake/skl.c
index 239348b0596b,6be25e617c21..
--- a/sound/soc/intel/skylake/skl.c
+++ b/sound/soc/intel/skylake/skl.c
@@@ -858,10 -854,11 +858,10 @@@ out_err
* constructor
*/
static int skl_create(struct pci_dev *pci,
- struct skl **rskl)
-const struct hdac_io_ops *io_ops,
+ struct skl_dev **rskl)
{
struct hdac_ext_bus_ops *ext_ops = NULL;
- struct skl *skl;
+ struct skl_dev *skl;
struct hdac_bus *bus;
struct hda_bus *hbus;
int err;
pgp7yYvvSZkbj.pgp
Description: OpenPGP digital signature
linux-next: build failure after merge of the sound-asoc tree
Hi all,
After merging the sound-asoc tree, today's linux-next build (x86_64
allmodconfig) failed like this:
In file included from include/linux/kobject.h:19,
from include/linux/device.h:16,
from include/sound/hdaudio.h:9,
from include/sound/hdaudio_ext.h:5,
from sound/soc/sof/intel/hda-dsp.c:18:
sound/soc/sof/intel/hda-dsp.c: In function 'hda_resume':
sound/soc/sof/intel/hda-dsp.c:360:22: error: 'hlink' undeclared (first use in
this function)
list_for_each_entry(hlink, >hlink_list, list)
^
include/linux/list.h:577:7: note: in definition of macro 'list_for_each_entry'
for (pos = list_first_entry(head, typeof(*pos), member); \
^~~
sound/soc/sof/intel/hda-dsp.c:360:22: note: each undeclared identifier is
reported only once for each function it appears in
list_for_each_entry(hlink, >hlink_list, list)
^
include/linux/list.h:577:7: note: in definition of macro 'list_for_each_entry'
for (pos = list_first_entry(head, typeof(*pos), member); \
^~~
In file included from include/linux/list.h:9,
from include/linux/kobject.h:19,
from include/linux/device.h:16,
from include/sound/hdaudio.h:9,
from include/sound/hdaudio_ext.h:5,
from sound/soc/sof/intel/hda-dsp.c:18:
sound/soc/sof/intel/hda-dsp.c:360:30: error: 'bus' undeclared (first use in
this function)
list_for_each_entry(hlink, >hlink_list, list)
^~~
include/linux/kernel.h:972:26: note: in definition of macro 'container_of'
void *__mptr = (void *)(ptr); \
^~~
include/linux/list.h:490:2: note: in expansion of macro 'list_entry'
list_entry((ptr)->next, type, member)
^~
include/linux/list.h:577:13: note: in expansion of macro 'list_first_entry'
for (pos = list_first_entry(head, typeof(*pos), member); \
^~~~
sound/soc/sof/intel/hda-dsp.c:360:2: note: in expansion of macro
'list_for_each_entry'
list_for_each_entry(hlink, >hlink_list, list)
^~~
sound/soc/sof/intel/hda-dsp.c:364:2: error: #else without #if
#else
^~~~
sound/soc/sof/intel/hda-dsp.c:390:2: error: #endif without #if
#endif
^
Caused by commit
c2f16a94a804 ("Merge branch 'topic/hda-bus-ops-cleanup' of
https://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound into asoc-5.4")
Looks like the merge resolution is not quite right.
I have used the sound-asoc tree from next-20190808 for today.
--
Cheers,
Stephen Rothwell
pgpz4rErB7zke.pgp
Description: OpenPGP digital signature
Re: [PATCH] genirq/affinity: report extra vectors on uneven nodes
On Thu, Aug 08, 2019 at 10:32:24AM -0600, Keith Busch wrote:
> On Thu, Aug 08, 2019 at 09:04:28AM +0200, Thomas Gleixner wrote:
> > On Wed, 7 Aug 2019, Jon Derrick wrote:
> > > The current irq spreading algorithm spreads vectors amongst cpus evenly
> > > per node. If a node has more cpus than another node, the extra vectors
> > > being spread may not be reported back to the caller.
> > >
> > > This is most apparent with the NVMe driver and nr_cpus < vectors, where
> > > the underreporting results in the caller's WARN being triggered:
> > >
> > > irq_build_affinity_masks()
> > > ...
> > > if (nr_present < numvecs)
> > > WARN_ON(nr_present + nr_others < numvecs);
> > >
> > > Signed-off-by: Jon Derrick
> > > ---
> > > kernel/irq/affinity.c | 7 +--
> > > 1 file changed, 5 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c
> > > index 4352b08ae48d..9beafb8c7e92 100644
> > > --- a/kernel/irq/affinity.c
> > > +++ b/kernel/irq/affinity.c
> > > @@ -127,7 +127,8 @@ static int __irq_build_affinity_masks(unsigned int
> > > startvec,
> > > }
> > >
> > > for_each_node_mask(n, nodemsk) {
> > > - unsigned int ncpus, v, vecs_to_assign, vecs_per_node;
> > > + unsigned int ncpus, v, vecs_to_assign, total_vecs_to_assign,
> > > + vecs_per_node;
> > >
> > > /* Spread the vectors per node */
> > > vecs_per_node = (numvecs - (curvec - firstvec)) / nodes;
> > > @@ -141,14 +142,16 @@ static int __irq_build_affinity_masks(unsigned int
> > > startvec,
> > >
> > > /* Account for rounding errors */
> > > extra_vecs = ncpus - vecs_to_assign * (ncpus / vecs_to_assign);
> > > + total_vecs_to_assign = vecs_to_assign + extra_vecs;
> > >
> > > - for (v = 0; curvec < last_affv && v < vecs_to_assign;
> > > + for (v = 0; curvec < last_affv && v < total_vecs_to_assign;
> > >curvec++, v++) {
> > > cpus_per_vec = ncpus / vecs_to_assign;
> > >
> > > /* Account for extra vectors to compensate rounding
> > > errors */
> > > if (extra_vecs) {
> > > cpus_per_vec++;
> > > + v++;
> > > --extra_vecs;
> > > }
> > > irq_spread_init_one([curvec].mask, nmsk,
> > > --
>
> This looks like it will break the spread to non-present CPUs since
> it's not accurately reporting how many vectors were assigned for the
> present spread.
>
> I think the real problem is the spread's vecs_per_node doesn't account
> which nodes contribute more CPUs than others. For example:
>
> Node 0 has 32 CPUs
> Node 1 has 8 CPUs
> Assign 32 vectors
>
> The current algorithm assigns 16 vectors to node 0 because vecs_per_node
> is calculated as 32 vectors / 2 nodes on the first iteration. The
> subsequent iteration for node 1 gets 8 vectors because it has only 8
> CPUs, leaving 8 vectors unassigned.
>
> A more fair spread would give node 0 the remaining 8 vectors. This
> optimization, however, is a bit more complex than the current algorithm,
> which is probably why it wasn't done, so I think the warning should just
> be removed.
Another policy is to assign vectors among nodes according to the
following ratio:
ncpus in this node / total ncpus in un-assigned nodes
I have tried the following patch, looks it works fine:
diff --git a/kernel/irq/affinity.c b/kernel/irq/affinity.c
index 6fef48033f96..a598f20701a3 100644
--- a/kernel/irq/affinity.c
+++ b/kernel/irq/affinity.c
@@ -94,6 +94,28 @@ static int get_nodes_in_cpumask(cpumask_var_t
*node_to_cpumask,
return nodes;
}
+static int nodes_cpus(unsigned start_node, const nodemask_t nodemsk,
+ const cpumask_var_t *node_to_cpumask,
+ const struct cpumask *cpu_mask, struct cpumask *nmsk)
+{
+ unsigned n, ncpus, total_cpus = 0;
+
+ for_each_node_mask(n, nodemsk) {
+ if (n < start_node)
+ continue;
+
+ /* Get the cpus on this node which are in the mask */
+ cpumask_and(nmsk, cpu_mask, node_to_cpumask[n]);
+
+ /* Calculate the number of cpus per vector */
+ ncpus = cpumask_weight(nmsk);
+
+ total_cpus += ncpus;
+ }
+
+ return total_cpus;
+}
+
static int __irq_build_affinity_masks(unsigned int startvec,
unsigned int numvecs,
unsigned int firstvec,
@@ -128,15 +150,25 @@ static int __irq_build_affinity_masks(unsigned int
startvec,
for_each_node_mask(n, nodemsk) {
unsigned int ncpus, v, vecs_to_assign, vecs_per_node;
-
- /* Spread the vectors per node */
- vecs_per_node = (numvecs - (curvec - firstvec)) / nodes;
+ unsigned int ncpus_left = nodes_cpus(n,
[PATCH] regulator: core: Add devres versions of regulator_enable/disable
I wrote a coccinelle script to detect possible chances
of utilizing devm_() APIs to simplify the driver.
The script found 147 drivers in total and 22 of them
have be patched.
Within the 125 left ones, at least 31 of them (24.8%)
are hindered from benefiting from devm_() APIs because
of lack of a devres version of regulator_enable().
Therefore I implemented devm_regulator_enable/disable()
to make more drivers possible to use devm_() APIs.
Signed-off-by: Chuhong Yuan
---
drivers/regulator/devres.c | 55 ++
1 file changed, 55 insertions(+)
diff --git a/drivers/regulator/devres.c b/drivers/regulator/devres.c
index 3ea1c170f840..507151a71fd3 100644
--- a/drivers/regulator/devres.c
+++ b/drivers/regulator/devres.c
@@ -115,6 +115,61 @@ void devm_regulator_put(struct regulator *regulator)
}
EXPORT_SYMBOL_GPL(devm_regulator_put);
+static void devm_regulator_off(struct device *dev, void *res)
+{
+ regulator_disable(*(struct regulator **)res);
+}
+
+/**
+ * devm_regulator_enable - Resource managed regulator_enable()
+ * @regulator: regulator to enable
+ *
+ * Managed regulator_enable(). Regulator enabled is automatically
+ * disabled on driver detach. See regulator_enable() for more
+ * information.
+ */
+int devm_regulator_enable(struct device *dev, struct regulator *regulator)
+{
+ struct regulator **ptr;
+ int ret;
+
+ ptr = devres_alloc(devm_regulator_off, sizeof(*ptr), GFP_KERNEL);
+ if (!ptr)
+ return -ENOMEM;
+
+ ret = regulator_enable(regulator);
+ if (!ret) {
+ *ptr = regulator;
+ devres_add(dev, ptr);
+ } else {
+ devres_free(ptr);
+ }
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(devm_regulator_enable);
+
+/**
+ * devm_regulator_disable - Resource managed regulator_disable()
+ * @regulator: regulator to disable
+ *
+ * Disable a regulator enabled by devm_regulator_enable().
+ * Normally this function will not need to be called and the
+ * resource management code will ensure that the regulator is
+ * disabled.
+ */
+void devm_regulator_disable(struct regulator *regulator)
+{
+ int rc;
+
+ rc = devres_release(regulator->dev, devm_regulator_off,
+ devm_regulator_match, regulator);
+
+ if (rc != 0)
+ WARN_ON(rc);
+}
+EXPORT_SYMBOL_GPL(devm_regulator_disable);
+
struct regulator_bulk_devres {
struct regulator_bulk_data *consumers;
int num_consumers;
--
2.20.1
linux-next: build failure after merge of the sound tree
Hi all,
After merging the sound tree, today's linux-next build (arm
multi_v7_defconfig) failed like this:
sound/hda/hdac_bus.c: In function 'snd_hdac_aligned_read':
sound/hda/hdac_bus.c:228:6: error: implicit declaration of function 'readl';
did you mean 'd_real'? [-Werror=implicit-function-declaration]
v = readl(aligned_addr);
^
d_real
sound/hda/hdac_bus.c: In function 'snd_hdac_aligned_write':
sound/hda/hdac_bus.c:244:2: error: implicit declaration of function 'writel'
[-Werror=implicit-function-declaration]
writel(v, aligned_addr);
^~
Caused by commit
19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
I have applied the following patch for today:
From: Stephen Rothwell
Date: Fri, 9 Aug 2019 12:50:25 +1000
Subject: [PATCH] ALSA: hda: readl/writel need linux/io.h
Fixes: 19abfefd4c76 ("ALSA: hda: Direct MMIO accesses")
Signed-off-by: Stephen Rothwell
---
sound/hda/hdac_bus.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/hda/hdac_bus.c b/sound/hda/hdac_bus.c
index dc2523ef7d98..cd25e2b3f7f2 100644
--- a/sound/hda/hdac_bus.c
+++ b/sound/hda/hdac_bus.c
@@ -4,6 +4,7 @@
*/
#include
+#include
#include
#include
#include
--
2.20.1
--
Cheers,
Stephen Rothwell
pgpal1llm6qTz.pgp
Description: OpenPGP digital signature
[PATCH net-next 02/12] net: hns3: fix interrupt clearing error for VF
Currently, VF driver has two kinds of interrupts, reset & CMDQ RX.
For revision 0x21, according to the UM, each interrupt should be
cleared by write 0 to the corresponding bit, but the implementation
writes 0 to the whole register in fact, it will clear other
interrupt at the same time, then the VF will loss the interrupt.
But for revision 0x20, this interrupt clear register is a read &
write register, for compatible, we just keep the old implementation
for 0x20.
This patch fixes it, also, adds a new register for reading the interrupt
status according to hardware user manual.
Fixes: e2cb1dec9779 ("net: hns3: Add HNS3 VF HCL(Hardware Compatibility Layer)
Support")
Fixes: b90fcc5bd904 ("net: hns3: add reset handling for VF when doing
Core/Global/IMP reset")
Signed-off-by: Huazhong Tan
Reviewed-by: Yunsheng Lin
---
.../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 28 +++---
.../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 2 ++
2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
index ce82b2b..d8b8281 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
@@ -1889,21 +1889,20 @@ static void hclgevf_clear_event_cause(struct
hclgevf_dev *hdev, u32 regclr)
static enum hclgevf_evt_cause hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
u32 *clearval)
{
- u32 val, cmdq_src_reg, rst_ing_reg;
+ u32 val, cmdq_stat_reg, rst_ing_reg;
/* fetch the events from their corresponding regs */
- cmdq_src_reg = hclgevf_read_dev(>hw,
- HCLGEVF_VECTOR0_CMDQ_SRC_REG);
+ cmdq_stat_reg = hclgevf_read_dev(>hw,
+HCLGEVF_VECTOR0_CMDQ_STAT_REG);
- if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_src_reg) {
+ if (BIT(HCLGEVF_VECTOR0_RST_INT_B) & cmdq_stat_reg) {
rst_ing_reg = hclgevf_read_dev(>hw, HCLGEVF_RST_ING);
dev_info(>pdev->dev,
"receive reset interrupt 0x%x!\n", rst_ing_reg);
set_bit(HNAE3_VF_RESET, >reset_pending);
set_bit(HCLGEVF_RESET_PENDING, >reset_state);
set_bit(HCLGEVF_STATE_CMD_DISABLE, >state);
- cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RST_INT_B);
- *clearval = cmdq_src_reg;
+ *clearval = ~(1U << HCLGEVF_VECTOR0_RST_INT_B);
hdev->rst_stats.vf_rst_cnt++;
/* set up VF hardware reset status, its PF will clear
* this status when PF has initialized done.
@@ -1915,9 +1914,20 @@ static enum hclgevf_evt_cause
hclgevf_check_evt_cause(struct hclgevf_dev *hdev,
}
/* check for vector0 mailbox(=CMDQ RX) event source */
- if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_src_reg) {
- cmdq_src_reg &= ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
- *clearval = cmdq_src_reg;
+ if (BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B) & cmdq_stat_reg) {
+ /* for revision 0x21, clearing interrupt is writing bit 0
+* to the clear register, writing bit 1 means to keep the
+* old value.
+* for revision 0x20, the clear register is a read & write
+* register, so we should just write 0 to the bit we are
+* handling, and keep other bits as cmdq_stat_reg.
+*/
+ if (hdev->pdev->revision >= 0x21)
+ *clearval = ~(1U << HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
+ else
+ *clearval = cmdq_stat_reg &
+ ~BIT(HCLGEVF_VECTOR0_RX_CMDQ_INT_B);
+
return HCLGEVF_VECTOR0_EVENT_MBX;
}
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
index f0736b0..4ccf107 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
@@ -87,6 +87,8 @@
/* Vector0 interrupt CMDQ event source register(RW) */
#define HCLGEVF_VECTOR0_CMDQ_SRC_REG 0x27100
+/* Vector0 interrupt CMDQ event status register(RO) */
+#define HCLGEVF_VECTOR0_CMDQ_STAT_REG 0x27104
/* CMDQ register bits for RX event(=MBX event) */
#define HCLGEVF_VECTOR0_RX_CMDQ_INT_B 1
/* RST register bits for RESET event */
--
2.7.4
Re: [RFC PATCH v2] mm: slub: print kernel addresses in slub debug messages
On Fri, Aug 09, 2019 at 09:08:37AM +0800, miles.c...@mediatek.com wrote: > Possible approaches are: > 1. stop printing kernel addresses > 2. print with %pK, > 3. print with %px. No. The point of obscuring kernel addresses is that if the attacker manages to find a way to get the kernel to spit out some debug messages that we shouldn't leak all this extra information. > 4. do nothing 5. Find something more useful to print. > INFO: Slab 0x(ptrval) objects=25 used=10 fp=0x(ptrval) ... you don't have any randomness on your platform? > INFO: Object 0x(ptrval) @offset=1408 fp=0x(ptrval) > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone (ptrval): bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object (ptrval): 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 > Redzone (ptrval): bb bb bb bb bb bb bb bb > Padding (ptrval): 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > Padding (ptrval): 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > Padding (ptrval): 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > Padding (ptrval): 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > ... > FIX kmalloc-128: Object at 0x(ptrval) not freed But if you have randomness, at least some of these "pointers" are valuable because you can compare them against "pointers" printed by other parts of the kernel. > After this patch: > > INFO: Slab 0xffbf00f57000 objects=25 used=23 fp=0xffc03d5c3500 > INFO: Object 0xffc03d5c3500 @offset=13568 fp=0xffc03d5c0800 > Redzone : bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0010: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0020: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0030: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0040: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0050: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0060: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Redzone 0070: bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb bb > Object : 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0010: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0020: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0030: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0040: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0050: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0060: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b > Object 0070: 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b 6b a5 > Redzone : bb bb bb bb bb bb bb bb > Padding : 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > Padding 0010: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > Padding 0020: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > Padding 0030: 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a 5a > ... > FIX kmalloc-128: Object at 0xffc03d5c3500 not freed It looks prettier, but I'm not convinced it's more useful. Unless your platform lacks randomness ...
Re: [PATCH V2 04/10] cpufreq: powerpc_cbe: Switch to QoS requests instead of cpufreq notifier
On 23-07-19, 11:44, Viresh Kumar wrote:
> The cpufreq core now takes the min/max frequency constraints via QoS
> requests and the CPUFREQ_ADJUST notifier shall get removed later on.
>
> Switch over to using the QoS request for maximum frequency constraint
> for ppc_cbe_cpufreq driver.
>
> Signed-off-by: Viresh Kumar
> ---
> drivers/cpufreq/ppc_cbe_cpufreq.c | 19 +-
> drivers/cpufreq/ppc_cbe_cpufreq.h | 8 +++
> drivers/cpufreq/ppc_cbe_cpufreq_pmi.c | 96 +--
> 3 files changed, 86 insertions(+), 37 deletions(-)
-8<-
>From b84e1c119d63ab842c9e4f3acbc3aec22efa866d Mon Sep 17 00:00:00 2001
Message-Id:
From: Viresh Kumar
Date: Fri, 5 Jul 2019 15:49:48 +0530
Subject: [PATCH] cpufreq: powerpc_cbe: Switch to QoS requests instead of
cpufreq notifier
The cpufreq core now takes the min/max frequency constraints via QoS
requests and the CPUFREQ_ADJUST notifier shall get removed later on.
Switch over to using the QoS request for maximum frequency constraint
for ppc_cbe_cpufreq driver.
Signed-off-by: Viresh Kumar
---
- dev_pm_qos_update_request() can return 1 on success
drivers/cpufreq/ppc_cbe_cpufreq.c | 19 +-
drivers/cpufreq/ppc_cbe_cpufreq.h | 8 +++
drivers/cpufreq/ppc_cbe_cpufreq_pmi.c | 96 +--
3 files changed, 86 insertions(+), 37 deletions(-)
diff --git a/drivers/cpufreq/ppc_cbe_cpufreq.c
b/drivers/cpufreq/ppc_cbe_cpufreq.c
index b83f36febf03..c58abb4cca3a 100644
--- a/drivers/cpufreq/ppc_cbe_cpufreq.c
+++ b/drivers/cpufreq/ppc_cbe_cpufreq.c
@@ -110,6 +110,13 @@ static int cbe_cpufreq_cpu_init(struct cpufreq_policy
*policy)
#endif
policy->freq_table = cbe_freqs;
+ cbe_cpufreq_pmi_policy_init(policy);
+ return 0;
+}
+
+static int cbe_cpufreq_cpu_exit(struct cpufreq_policy *policy)
+{
+ cbe_cpufreq_pmi_policy_exit(policy);
return 0;
}
@@ -129,6 +136,7 @@ static struct cpufreq_driver cbe_cpufreq_driver = {
.verify = cpufreq_generic_frequency_table_verify,
.target_index = cbe_cpufreq_target,
.init = cbe_cpufreq_cpu_init,
+ .exit = cbe_cpufreq_cpu_exit,
.name = "cbe-cpufreq",
.flags = CPUFREQ_CONST_LOOPS,
};
@@ -139,15 +147,24 @@ static struct cpufreq_driver cbe_cpufreq_driver = {
static int __init cbe_cpufreq_init(void)
{
+ int ret;
+
if (!machine_is(cell))
return -ENODEV;
- return cpufreq_register_driver(_cpufreq_driver);
+ cbe_cpufreq_pmi_init();
+
+ ret = cpufreq_register_driver(_cpufreq_driver);
+ if (ret)
+ cbe_cpufreq_pmi_exit();
+
+ return ret;
}
static void __exit cbe_cpufreq_exit(void)
{
cpufreq_unregister_driver(_cpufreq_driver);
+ cbe_cpufreq_pmi_exit();
}
module_init(cbe_cpufreq_init);
diff --git a/drivers/cpufreq/ppc_cbe_cpufreq.h
b/drivers/cpufreq/ppc_cbe_cpufreq.h
index 9d973519d669..00cd8633b0d9 100644
--- a/drivers/cpufreq/ppc_cbe_cpufreq.h
+++ b/drivers/cpufreq/ppc_cbe_cpufreq.h
@@ -20,6 +20,14 @@ int cbe_cpufreq_set_pmode_pmi(int cpu, unsigned int pmode);
#if IS_ENABLED(CONFIG_CPU_FREQ_CBE_PMI)
extern bool cbe_cpufreq_has_pmi;
+void cbe_cpufreq_pmi_policy_init(struct cpufreq_policy *policy);
+void cbe_cpufreq_pmi_policy_exit(struct cpufreq_policy *policy);
+void cbe_cpufreq_pmi_init(void);
+void cbe_cpufreq_pmi_exit(void);
#else
#define cbe_cpufreq_has_pmi (0)
+static inline void cbe_cpufreq_pmi_policy_init(struct cpufreq_policy *policy)
{}
+static inline void cbe_cpufreq_pmi_policy_exit(struct cpufreq_policy *policy)
{}
+static inline void cbe_cpufreq_pmi_init(void) {}
+static inline void cbe_cpufreq_pmi_exit(void) {}
#endif
diff --git a/drivers/cpufreq/ppc_cbe_cpufreq_pmi.c
b/drivers/cpufreq/ppc_cbe_cpufreq_pmi.c
index 97c8ee4614b7..bc9dd30395c4 100644
--- a/drivers/cpufreq/ppc_cbe_cpufreq_pmi.c
+++ b/drivers/cpufreq/ppc_cbe_cpufreq_pmi.c
@@ -12,6 +12,7 @@
#include
#include
#include
+#include
#include
#include
@@ -24,8 +25,6 @@
#include "ppc_cbe_cpufreq.h"
-static u8 pmi_slow_mode_limit[MAX_CBE];
-
bool cbe_cpufreq_has_pmi = false;
EXPORT_SYMBOL_GPL(cbe_cpufreq_has_pmi);
@@ -65,64 +64,89 @@ EXPORT_SYMBOL_GPL(cbe_cpufreq_set_pmode_pmi);
static void cbe_cpufreq_handle_pmi(pmi_message_t pmi_msg)
{
+ struct cpufreq_policy *policy;
+ struct dev_pm_qos_request *req;
u8 node, slow_mode;
+ int cpu, ret;
BUG_ON(pmi_msg.type != PMI_TYPE_FREQ_CHANGE);
node = pmi_msg.data1;
slow_mode = pmi_msg.data2;
- pmi_slow_mode_limit[node] = slow_mode;
+ cpu = cbe_node_to_cpu(node);
pr_debug("cbe_handle_pmi: node: %d max_freq: %d\n", node, slow_mode);
-}
-
-static int pmi_notifier(struct notifier_block *nb,
- unsigned long event, void *data)
-{
- struct cpufreq_policy *policy = data;
-
[PATCH net-next 11/12] net: hns3: add handshake with VF for PF reset
Before PF asserting function reset, it should make sure
that all its VFs have been ready, otherwise, it will cause
some hardware errors.
So this patch adds function hclge_func_reset_sync_vf() to
synchronize VF before asserting PF function reset. For new
firmware which supports command HCLGE_OPC_QUERY_VF_RST_RDY,
we will try to query VFs' ready status within 30 seconds.
And keep the old implementation for compatible with firmware
which does not support this command.
Signed-off-by: Huazhong Tan
Reviewed-by: Yunsheng Lin
---
.../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 7 +++
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c| 56 ++
2 files changed, 55 insertions(+), 8 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
index dade20a..29979be 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
@@ -87,6 +87,7 @@ enum hclge_opcode_type {
HCLGE_OPC_QUERY_VF_RSRC = 0x0024,
HCLGE_OPC_GET_CFG_PARAM = 0x0025,
HCLGE_OPC_PF_RST_DONE = 0x0026,
+ HCLGE_OPC_QUERY_VF_RST_RDY = 0x0027,
HCLGE_OPC_STATS_64_BIT = 0x0030,
HCLGE_OPC_STATS_32_BIT = 0x0031,
@@ -588,6 +589,12 @@ struct hclge_config_mac_mode_cmd {
u8 rsv[20];
};
+struct hclge_pf_rst_sync_cmd {
+#define HCLGE_PF_RST_ALL_VF_RDY_B 0
+ u8 all_vf_ready;
+ u8 rsv[23];
+};
+
#define HCLGE_CFG_SPEED_S 0
#define HCLGE_CFG_SPEED_M GENMASK(5, 0)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 1315275..d207dac 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -35,6 +35,9 @@
#define BUF_RESERVE_PERCENT90
#define HCLGE_RESET_MAX_FAIL_CNT 5
+#define HCLGE_RESET_SYNC_TIME 100
+#define HCLGE_PF_RESET_SYNC_TIME 20
+#define HCLGE_PF_RESET_SYNC_CNT1500
/* Get DFX BD number offset */
#define HCLGE_DFX_BIOS_BD_OFFSET1
@@ -3184,6 +3187,39 @@ static int hclge_set_all_vf_rst(struct hclge_dev *hdev,
bool reset)
return 0;
}
+int hclge_func_reset_sync_vf(struct hclge_dev *hdev)
+{
+ struct hclge_pf_rst_sync_cmd *req;
+ struct hclge_desc desc;
+ int cnt = 0;
+ int ret;
+
+ req = (struct hclge_pf_rst_sync_cmd *)desc.data;
+ hclge_cmd_setup_basic_desc(, HCLGE_OPC_QUERY_VF_RST_RDY, true);
+
+ do {
+ ret = hclge_cmd_send(>hw, , 1);
+ /* for compatible with old firmware, wait
+* 100 ms for VF to stop IO
+*/
+ if (ret == -EOPNOTSUPP) {
+ msleep(HCLGE_RESET_SYNC_TIME);
+ return 0;
+ } else if (ret) {
+ dev_err(>pdev->dev, "sync with VF fail %d!\n",
+ ret);
+ return ret;
+ } else if (req->all_vf_ready) {
+ return 0;
+ }
+ msleep(HCLGE_PF_RESET_SYNC_TIME);
+ hclge_cmd_reuse_desc(, true);
+ } while (cnt++ < HCLGE_PF_RESET_SYNC_CNT);
+
+ dev_err(>pdev->dev, "sync with VF timeout!\n");
+ return -ETIME;
+}
+
int hclge_func_reset_cmd(struct hclge_dev *hdev, int func_id)
{
struct hclge_desc desc;
@@ -3350,17 +3386,18 @@ static void hclge_reset_handshake(struct hclge_dev
*hdev, bool enable)
static int hclge_reset_prepare_wait(struct hclge_dev *hdev)
{
-#define HCLGE_RESET_SYNC_TIME 100
-
u32 reg_val;
int ret = 0;
switch (hdev->reset_type) {
case HNAE3_FUNC_RESET:
- /* There is no mechanism for PF to know if VF has stopped IO
-* for now, just wait 100 ms for VF to stop IO
+ /* to confirm whether all running VF is ready
+* before request PF reset
*/
- msleep(HCLGE_RESET_SYNC_TIME);
+ ret = hclge_func_reset_sync_vf(hdev);
+ if (ret)
+ return ret;
+
ret = hclge_func_reset_cmd(hdev, 0);
if (ret) {
dev_err(>pdev->dev,
@@ -3377,10 +3414,13 @@ static int hclge_reset_prepare_wait(struct hclge_dev
*hdev)
hdev->rst_stats.pf_rst_cnt++;
break;
case HNAE3_FLR_RESET:
- /* There is no mechanism for PF to know if VF has stopped IO
-* for now, just wait 100 ms for VF to stop IO
+ /* to confirm whether all running VF is ready
+* before request PF reset
*/
- msleep(HCLGE_RESET_SYNC_TIME);
+ ret =
[PATCH net-next 08/12] net: hns3: add check for max TX BD num for tso and non-tso case
From: Yunsheng Lin
Hardware supports up to 8 TX BD for non-TSO skb and 63 TX
BD for TSO skb. Currently hns3 driver does not check the max
BD num that required by a skb before filling desc, which may
cause the hardware to issue a RAS error throug PCIe AER.
This patch adds the max BD num check before filling desc,
if the bd num is not within the hardware limit, it will
record the error by ring->stats.sw_err_cnt counter and
free the skb.
This patch also cleans up the hns3_nic_bd_num function by
changing the return type and removing an unnecessary check.
Signed-off-by: Yunsheng Lin
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 38 ++---
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h | 3 +-
2 files changed, 17 insertions(+), 24 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index b2a668d..df08f9e 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -1186,28 +1186,20 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring,
void *priv,
return 0;
}
-static int hns3_nic_bd_num(struct sk_buff *skb)
+static unsigned int hns3_nic_bd_num(struct sk_buff *skb)
{
- int size = skb_headlen(skb);
- int i, bd_num;
+ unsigned int bd_num;
+ int i;
/* if the total len is within the max bd limit */
if (likely(skb->len <= HNS3_MAX_BD_SIZE))
return skb_shinfo(skb)->nr_frags + 1;
- bd_num = hns3_tx_bd_count(size);
+ bd_num = hns3_tx_bd_count(skb_headlen(skb));
for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
skb_frag_t *frag = _shinfo(skb)->frags[i];
- int frag_bd_num;
-
- size = skb_frag_size(frag);
- frag_bd_num = hns3_tx_bd_count(size);
-
- if (unlikely(frag_bd_num > HNS3_MAX_BD_PER_FRAG))
- return -ENOMEM;
-
- bd_num += frag_bd_num;
+ bd_num += hns3_tx_bd_count(skb_frag_size(frag));
}
return bd_num;
@@ -1228,7 +1220,7 @@ static unsigned int hns3_gso_hdr_len(struct sk_buff *skb)
*/
static bool hns3_skb_need_linearized(struct sk_buff *skb)
{
- int bd_limit = HNS3_MAX_BD_PER_FRAG - 1;
+ int bd_limit = HNS3_MAX_BD_NUM_NORMAL - 1;
unsigned int tot_len = 0;
int i;
@@ -1258,21 +1250,16 @@ static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring
*ring,
struct sk_buff **out_skb)
{
struct sk_buff *skb = *out_skb;
- int bd_num;
+ unsigned int bd_num;
bd_num = hns3_nic_bd_num(skb);
- if (bd_num < 0)
- return bd_num;
-
- if (unlikely(bd_num > HNS3_MAX_BD_PER_FRAG)) {
+ if (unlikely(bd_num > HNS3_MAX_BD_NUM_NORMAL)) {
struct sk_buff *new_skb;
- if (skb_is_gso(skb) && !hns3_skb_need_linearized(skb))
+ if (skb_is_gso(skb) && bd_num <= HNS3_MAX_BD_NUM_TSO &&
+ !hns3_skb_need_linearized(skb))
goto out;
- bd_num = hns3_tx_bd_count(skb->len);
- if (unlikely(ring_space(ring) < bd_num))
- return -EBUSY;
/* manual split the send packet */
new_skb = skb_copy(skb, GFP_ATOMIC);
if (!new_skb)
@@ -1280,6 +1267,11 @@ static int hns3_nic_maybe_stop_tx(struct hns3_enet_ring
*ring,
dev_kfree_skb_any(skb);
*out_skb = new_skb;
+ bd_num = hns3_nic_bd_num(new_skb);
+ if ((skb_is_gso(new_skb) && bd_num > HNS3_MAX_BD_NUM_TSO) ||
+ (!skb_is_gso(new_skb) && bd_num > HNS3_MAX_BD_NUM_NORMAL))
+ return -ENOMEM;
+
u64_stats_update_begin(>syncp);
ring->stats.tx_copy++;
u64_stats_update_end(>syncp);
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
index a76712c..5b0ee1f 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
@@ -195,7 +195,8 @@ enum hns3_nic_state {
#define HNS3_VECTOR_INITED 1
#define HNS3_MAX_BD_SIZE 65535
-#define HNS3_MAX_BD_PER_FRAG 8
+#define HNS3_MAX_BD_NUM_NORMAL 8
+#define HNS3_MAX_BD_NUM_TSO63
#define HNS3_MAX_BD_PER_PKTMAX_SKB_FRAGS
#define HNS3_VECTOR_GL0_OFFSET 0x100
--
2.7.4
[PATCH net-next 09/12] net: hns3: add function display NCL_CONFIG info
From: Yufeng Mo
This adds a new function hclge_ncl_config_data_print()
to print the data of NCL_CONFIG, to make the code more
readable. Also, using macro replaces some magic number.
Signed-off-by: Yufeng Mo
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
.../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 52 +-
1 file changed, 30 insertions(+), 22 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
index 933dec5..f0295d1 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
@@ -995,6 +995,33 @@ void hclge_dbg_get_m7_stats_info(struct hclge_dev *hdev)
kfree(desc_src);
}
+#define HCLGE_CMD_NCL_CONFIG_BD_NUM5
+
+static void hclge_ncl_config_data_print(struct hclge_dev *hdev,
+ struct hclge_desc *desc, int *offset,
+ int *length)
+{
+#define HCLGE_CMD_DATA_NUM 6
+
+ int i;
+ int j;
+
+ for (i = 0; i < HCLGE_CMD_NCL_CONFIG_BD_NUM; i++) {
+ for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) {
+ if (i == 0 && j == 0)
+ continue;
+
+ dev_info(>pdev->dev, "0x%04x | 0x%08x\n",
+*offset,
+le32_to_cpu(desc[i].data[j]));
+ *offset += sizeof(u32);
+ *length -= sizeof(u32);
+ if (*length <= 0)
+ return;
+ }
+ }
+}
+
/* hclge_dbg_dump_ncl_config: print specified range of NCL_CONFIG file
* @hdev: pointer to struct hclge_dev
* @cmd_buf: string that contains offset and length
@@ -1004,17 +1031,13 @@ static void hclge_dbg_dump_ncl_config(struct hclge_dev
*hdev,
{
#define HCLGE_MAX_NCL_CONFIG_OFFSET4096
#define HCLGE_MAX_NCL_CONFIG_LENGTH(20 + 24 * 4)
-#define HCLGE_CMD_DATA_NUM 6
- struct hclge_desc desc[5];
- u32 byte_offset;
- int bd_num = 5;
+ struct hclge_desc desc[HCLGE_CMD_NCL_CONFIG_BD_NUM];
+ int bd_num = HCLGE_CMD_NCL_CONFIG_BD_NUM;
int offset;
int length;
int data0;
int ret;
- int i;
- int j;
ret = sscanf(cmd_buf, "%x %x", , );
if (ret != 2 || offset >= HCLGE_MAX_NCL_CONFIG_OFFSET ||
@@ -1040,22 +1063,7 @@ static void hclge_dbg_dump_ncl_config(struct hclge_dev
*hdev,
if (ret)
return;
- byte_offset = offset;
- for (i = 0; i < bd_num; i++) {
- for (j = 0; j < HCLGE_CMD_DATA_NUM; j++) {
- if (i == 0 && j == 0)
- continue;
-
- dev_info(>pdev->dev, "0x%04x | 0x%08x\n",
-byte_offset,
-le32_to_cpu(desc[i].data[j]));
- byte_offset += sizeof(u32);
- length -= sizeof(u32);
- if (length <= 0)
- return;
- }
- }
- offset += HCLGE_MAX_NCL_CONFIG_LENGTH;
+ hclge_ncl_config_data_print(hdev, desc, , );
}
}
--
2.7.4
[PATCH net-next 03/12] net: hns3: clean up for vlan handling in hns3_fill_desc_vtags
From: Yunsheng Lin
This patch refactors the hns3_fill_desc_vtags function
by avoiding passing too many parameters, reducing indent
level and some other clean up.
This patch also adds the hns3_fill_skb_desc function to
fill the first desc of a skb.
Signed-off-by: Yunsheng Lin
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 167 +---
1 file changed, 89 insertions(+), 78 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index ed05fb9..fd6a3d5 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -45,6 +45,9 @@ MODULE_PARM_DESC(debug, " Network interface message level
setting");
#define DEFAULT_MSG_LEVEL (NETIF_MSG_PROBE | NETIF_MSG_LINK | \
NETIF_MSG_IFDOWN | NETIF_MSG_IFUP)
+#define HNS3_INNER_VLAN_TAG1
+#define HNS3_OUTER_VLAN_TAG2
+
/* hns3_pci_tbl - PCI Device ID Table
*
* Last entry must be all 0s
@@ -961,16 +964,16 @@ static void hns3_set_txbd_baseinfo(u16
*bdtp_fe_sc_vld_ra_ri, int frag_end)
hns3_set_field(*bdtp_fe_sc_vld_ra_ri, HNS3_TXD_VLD_B, 1U);
}
-static int hns3_fill_desc_vtags(struct sk_buff *skb,
- struct hns3_enet_ring *tx_ring,
- u32 *inner_vlan_flag,
- u32 *out_vlan_flag,
- u16 *inner_vtag,
- u16 *out_vtag)
+static int hns3_handle_vtags(struct hns3_enet_ring *tx_ring,
+struct sk_buff *skb)
{
-#define HNS3_TX_VLAN_PRIO_SHIFT 13
-
struct hnae3_handle *handle = tx_ring->tqp->handle;
+ struct vlan_ethhdr *vhdr;
+ int rc;
+
+ if (!(skb->protocol == htons(ETH_P_8021Q) ||
+ skb_vlan_tag_present(skb)))
+ return 0;
/* Since HW limitation, if port based insert VLAN enabled, only one VLAN
* header is allowed in skb, otherwise it will cause RAS error.
@@ -981,8 +984,7 @@ static int hns3_fill_desc_vtags(struct sk_buff *skb,
return -EINVAL;
if (skb->protocol == htons(ETH_P_8021Q) &&
- !(tx_ring->tqp->handle->kinfo.netdev->features &
- NETIF_F_HW_VLAN_CTAG_TX)) {
+ !(handle->kinfo.netdev->features & NETIF_F_HW_VLAN_CTAG_TX)) {
/* When HW VLAN acceleration is turned off, and the stack
* sets the protocol to 802.1q, the driver just need to
* set the protocol to the encapsulated ethertype.
@@ -992,45 +994,92 @@ static int hns3_fill_desc_vtags(struct sk_buff *skb,
}
if (skb_vlan_tag_present(skb)) {
- u16 vlan_tag;
-
- vlan_tag = skb_vlan_tag_get(skb);
- vlan_tag |= (skb->priority & 0x7) << HNS3_TX_VLAN_PRIO_SHIFT;
-
/* Based on hw strategy, use out_vtag in two layer tag case,
* and use inner_vtag in one tag case.
*/
- if (skb->protocol == htons(ETH_P_8021Q)) {
- if (handle->port_base_vlan_state ==
- HNAE3_PORT_BASE_VLAN_DISABLE){
- hns3_set_field(*out_vlan_flag,
- HNS3_TXD_OVLAN_B, 1);
- *out_vtag = vlan_tag;
- } else {
- hns3_set_field(*inner_vlan_flag,
- HNS3_TXD_VLAN_B, 1);
- *inner_vtag = vlan_tag;
- }
- } else {
- hns3_set_field(*inner_vlan_flag, HNS3_TXD_VLAN_B, 1);
- *inner_vtag = vlan_tag;
- }
- } else if (skb->protocol == htons(ETH_P_8021Q)) {
- struct vlan_ethhdr *vhdr;
- int rc;
+ if (skb->protocol == htons(ETH_P_8021Q) &&
+ handle->port_base_vlan_state ==
+ HNAE3_PORT_BASE_VLAN_DISABLE)
+ rc = HNS3_OUTER_VLAN_TAG;
+ else
+ rc = HNS3_INNER_VLAN_TAG;
- rc = skb_cow_head(skb, 0);
- if (unlikely(rc < 0))
- return rc;
- vhdr = (struct vlan_ethhdr *)skb->data;
- vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority & 0x7)
- << HNS3_TX_VLAN_PRIO_SHIFT);
+ skb->protocol = vlan_get_protocol(skb);
+ return rc;
}
+ rc = skb_cow_head(skb, 0);
+ if (unlikely(rc < 0))
+ return rc;
+
+ vhdr = (struct vlan_ethhdr *)skb->data;
+ vhdr->h_vlan_TCI |= cpu_to_be16((skb->priority << VLAN_PRIO_SHIFT)
+& VLAN_PRIO_MASK);
+
skb->protocol =
[PATCH net-next 04/12] net: hns3: add input length check for debugfs write function
From: Yufeng Mo If the input length reaches the maximum value of size_t, the reverse is triggered when 1 is added. In addition, there is no need to have such a large length. Therefore, the input length should be checked and the value should be less than or equal to 1024. Signed-off-by: Yufeng Mo Reviewed-by: Peng Li Signed-off-by: Huazhong Tan --- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c index a4b9372..7996dcc 100644 --- a/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c +++ b/drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c @@ -8,6 +8,7 @@ #include "hns3_enet.h" #define HNS3_DBG_READ_LEN 256 +#define HNS3_DBG_WRITE_LEN 1024 static struct dentry *hns3_dbgfs_root; @@ -322,6 +323,9 @@ static ssize_t hns3_dbg_cmd_write(struct file *filp, const char __user *buffer, test_bit(HNS3_NIC_STATE_RESETTING, >state)) return 0; + if (count > HNS3_DBG_WRITE_LEN) + return -ENOSPC; + cmd_buf = kzalloc(count + 1, GFP_KERNEL); if (!cmd_buf) return count; -- 2.7.4
[PATCH net-next 06/12] net: hns3: add DFX registers information for ethtool -d
From: Guangbin Huang
Now we can use ethtool -d command to dump some registers. However,
these registers information is not enough to find out where the problem is.
This patch adds DFX registers information after original registers
when use ethtool -d commmand to dump registers. Also, using macro
replaces some related magic number.
Signed-off-by: Guangbin Huang
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
.../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 12 +-
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c| 342 ++---
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.h| 2 +
3 files changed, 301 insertions(+), 55 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
index f16bfc6..933dec5 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c
@@ -14,16 +14,8 @@ static int hclge_dbg_get_dfx_bd_num(struct hclge_dev *hdev,
int offset)
struct hclge_desc desc[4];
int ret;
- hclge_cmd_setup_basic_desc([0], HCLGE_OPC_DFX_BD_NUM, true);
- desc[0].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
- hclge_cmd_setup_basic_desc([1], HCLGE_OPC_DFX_BD_NUM, true);
- desc[1].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
- hclge_cmd_setup_basic_desc([2], HCLGE_OPC_DFX_BD_NUM, true);
- desc[2].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
- hclge_cmd_setup_basic_desc([3], HCLGE_OPC_DFX_BD_NUM, true);
-
- ret = hclge_cmd_send(>hw, desc, 4);
- if (ret != HCLGE_CMD_EXEC_SUCCESS) {
+ ret = hclge_query_bd_num_cmd_send(hdev, desc);
+ if (ret) {
dev_err(>pdev->dev,
"get dfx bdnum fail, status is %d.\n", ret);
return ret;
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 381f195..7d7ab9e 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -36,6 +36,20 @@
#define HCLGE_RESET_MAX_FAIL_CNT 5
+/* Get DFX BD number offset */
+#define HCLGE_DFX_BIOS_BD_OFFSET1
+#define HCLGE_DFX_SSU_0_BD_OFFSET 2
+#define HCLGE_DFX_SSU_1_BD_OFFSET 3
+#define HCLGE_DFX_IGU_BD_OFFSET 4
+#define HCLGE_DFX_RPU_0_BD_OFFSET 5
+#define HCLGE_DFX_RPU_1_BD_OFFSET 6
+#define HCLGE_DFX_NCSI_BD_OFFSET7
+#define HCLGE_DFX_RTC_BD_OFFSET 8
+#define HCLGE_DFX_PPP_BD_OFFSET 9
+#define HCLGE_DFX_RCB_BD_OFFSET 10
+#define HCLGE_DFX_TQP_BD_OFFSET 11
+#define HCLGE_DFX_SSU_2_BD_OFFSET 12
+
static int hclge_set_mac_mtu(struct hclge_dev *hdev, int new_mps);
static int hclge_init_vlan_config(struct hclge_dev *hdev);
static void hclge_sync_vlan_filter(struct hclge_dev *hdev);
@@ -317,6 +331,36 @@ static const u8 hclge_hash_key[] = {
0x6A, 0x42, 0xB7, 0x3B, 0xBE, 0xAC, 0x01, 0xFA
};
+static const u32 hclge_dfx_bd_offset_list[] = {
+ HCLGE_DFX_BIOS_BD_OFFSET,
+ HCLGE_DFX_SSU_0_BD_OFFSET,
+ HCLGE_DFX_SSU_1_BD_OFFSET,
+ HCLGE_DFX_IGU_BD_OFFSET,
+ HCLGE_DFX_RPU_0_BD_OFFSET,
+ HCLGE_DFX_RPU_1_BD_OFFSET,
+ HCLGE_DFX_NCSI_BD_OFFSET,
+ HCLGE_DFX_RTC_BD_OFFSET,
+ HCLGE_DFX_PPP_BD_OFFSET,
+ HCLGE_DFX_RCB_BD_OFFSET,
+ HCLGE_DFX_TQP_BD_OFFSET,
+ HCLGE_DFX_SSU_2_BD_OFFSET
+};
+
+static const enum hclge_opcode_type hclge_dfx_reg_opcode_list[] = {
+ HCLGE_OPC_DFX_BIOS_COMMON_REG,
+ HCLGE_OPC_DFX_SSU_REG_0,
+ HCLGE_OPC_DFX_SSU_REG_1,
+ HCLGE_OPC_DFX_IGU_EGU_REG,
+ HCLGE_OPC_DFX_RPU_REG_0,
+ HCLGE_OPC_DFX_RPU_REG_1,
+ HCLGE_OPC_DFX_NCSI_REG,
+ HCLGE_OPC_DFX_RTC_REG,
+ HCLGE_OPC_DFX_PPP_REG,
+ HCLGE_OPC_DFX_RCB_REG,
+ HCLGE_OPC_DFX_TQP_REG,
+ HCLGE_OPC_DFX_SSU_REG_2
+};
+
static int hclge_mac_update_stats_defective(struct hclge_dev *hdev)
{
#define HCLGE_MAC_CMD_NUM 21
@@ -9332,106 +9376,314 @@ static int hclge_get_64_bit_regs(struct hclge_dev
*hdev, u32 regs_num,
}
#define MAX_SEPARATE_NUM 4
-#define SEPARATOR_VALUE0x
+#define SEPARATOR_VALUE0xFDFCFBFA
#define REG_NUM_PER_LINE 4
#define REG_LEN_PER_LINE (REG_NUM_PER_LINE * sizeof(u32))
+#define REG_SEPARATOR_LINE 1
+#define REG_NUM_REMAIN_MASK3
+#define BD_LIST_MAX_NUM30
-static int hclge_get_regs_len(struct hnae3_handle *handle)
+int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, struct hclge_desc
*desc)
{
- int cmdq_lines, common_lines, ring_lines, tqp_intr_lines;
- struct hnae3_knic_private_info *kinfo = >kinfo;
- struct hclge_vport *vport = hclge_get_vport(handle);
- struct hclge_dev *hdev = vport->back;
- u32 regs_num_32_bit, regs_num_64_bit;
+ /*prepare 4
Re: [PATCH V2 05/10] ACPI: cpufreq: Switch to QoS requests instead of cpufreq notifier
On 06-08-19, 14:17, Viresh Kumar wrote:
> On 06-08-19, 10:01, Rafael J. Wysocki wrote:
> > Yes, it does, thanks!
> >
> > [No need to resend, I'll take it from this message.]
>
> Forgot to write CPU in caps in print messages, updated now.
And here is another version.
-8<-
>From 6d2c1e8034562043a758524d6078e2dd1624195c Mon Sep 17 00:00:00 2001
Message-Id:
<6d2c1e8034562043a758524d6078e2dd1624195c.1565317925.git.viresh.ku...@linaro.org>
From: Viresh Kumar
Date: Mon, 15 Jul 2019 15:06:02 +0530
Subject: [PATCH] ACPI: cpufreq: Switch to QoS requests instead of cpufreq
notifier
The cpufreq core now takes the min/max frequency constraints via QoS
requests and the CPUFREQ_ADJUST notifier shall get removed later on.
Switch over to using the QoS request for maximum frequency constraint
for acpi driver.
Signed-off-by: Viresh Kumar
---
- dev_pm_qos_update_request() can return 1 on success
drivers/acpi/processor_driver.c | 37 ++--
drivers/acpi/processor_perflib.c | 96 +++-
drivers/acpi/processor_thermal.c | 81 +--
include/acpi/processor.h | 21 ---
4 files changed, 118 insertions(+), 117 deletions(-)
diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c
index aea8d674a33d..2c911fcaa4b4 100644
--- a/drivers/acpi/processor_driver.c
+++ b/drivers/acpi/processor_driver.c
@@ -284,6 +284,29 @@ static int acpi_processor_stop(struct device *dev)
return 0;
}
+bool acpi_processor_cpufreq_init;
+
+static int acpi_processor_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct cpufreq_policy *policy = data;
+ int cpu = policy->cpu;
+
+ if (event == CPUFREQ_CREATE_POLICY) {
+ acpi_thermal_cpufreq_init(cpu);
+ acpi_processor_ppc_init(cpu);
+ } else if (event == CPUFREQ_REMOVE_POLICY) {
+ acpi_processor_ppc_exit(cpu);
+ acpi_thermal_cpufreq_exit(cpu);
+ }
+
+ return 0;
+}
+
+static struct notifier_block acpi_processor_notifier_block = {
+ .notifier_call = acpi_processor_notifier,
+};
+
/*
* We keep the driver loaded even when ACPI is not running.
* This is needed for the powernow-k8 driver, that works even without
@@ -310,8 +333,10 @@ static int __init acpi_processor_driver_init(void)
cpuhp_setup_state_nocalls(CPUHP_ACPI_CPUDRV_DEAD, "acpi/cpu-drv:dead",
NULL, acpi_soft_cpu_dead);
- acpi_thermal_cpufreq_init();
- acpi_processor_ppc_init();
+ if (!cpufreq_register_notifier(_processor_notifier_block,
+ CPUFREQ_POLICY_NOTIFIER))
+ acpi_processor_cpufreq_init = true;
+
acpi_processor_throttling_init();
return 0;
err:
@@ -324,8 +349,12 @@ static void __exit acpi_processor_driver_exit(void)
if (acpi_disabled)
return;
- acpi_processor_ppc_exit();
- acpi_thermal_cpufreq_exit();
+ if (acpi_processor_cpufreq_init) {
+ cpufreq_unregister_notifier(_processor_notifier_block,
+ CPUFREQ_POLICY_NOTIFIER);
+ acpi_processor_cpufreq_init = false;
+ }
+
cpuhp_remove_state_nocalls(hp_online);
cpuhp_remove_state_nocalls(CPUHP_ACPI_CPUDRV_DEAD);
driver_unregister(_processor_driver);
diff --git a/drivers/acpi/processor_perflib.c b/drivers/acpi/processor_perflib.c
index ee87cb6f6e59..277fcbbe3be4 100644
--- a/drivers/acpi/processor_perflib.c
+++ b/drivers/acpi/processor_perflib.c
@@ -50,57 +50,13 @@ module_param(ignore_ppc, int, 0644);
MODULE_PARM_DESC(ignore_ppc, "If the frequency of your machine gets wrongly" \
"limited by BIOS, this should help");
-#define PPC_REGISTERED 1
-#define PPC_IN_USE 2
-
-static int acpi_processor_ppc_status;
-
-static int acpi_processor_ppc_notifier(struct notifier_block *nb,
- unsigned long event, void *data)
-{
- struct cpufreq_policy *policy = data;
- struct acpi_processor *pr;
- unsigned int ppc = 0;
-
- if (ignore_ppc < 0)
- ignore_ppc = 0;
-
- if (ignore_ppc)
- return 0;
-
- if (event != CPUFREQ_ADJUST)
- return 0;
-
- mutex_lock(_mutex);
-
- pr = per_cpu(processors, policy->cpu);
- if (!pr || !pr->performance)
- goto out;
-
- ppc = (unsigned int)pr->performance_platform_limit;
-
- if (ppc >= pr->performance->state_count)
- goto out;
-
- cpufreq_verify_within_limits(policy, 0,
-pr->performance->states[ppc].
-core_frequency * 1000);
-
- out:
- mutex_unlock(_mutex);
-
- return 0;
-}
-
-static struct notifier_block
[PATCH net-next 07/12] net: hns3: add some statitics info to tx process
From: Yunsheng Lin
This patch adds tx_vlan_err, tx_l4_proto_err, tx_l2l3l4_err
and tx_tso_err counter to tx process, in order to better
debug the desc filling error.
This patch also adds a missing u64_stats_update_* around
ring->stats.sw_err_cnt and adds hns3_rl_err to limit the
error printing in the IO patch.
Signed-off-by: Yunsheng Lin
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c| 58 --
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h| 4 ++
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 4 ++
3 files changed, 52 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index fd6a3d5..b2a668d 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -28,6 +28,12 @@
#define hns3_set_field(origin, shift, val) ((origin) |= ((val) << (shift)))
#define hns3_tx_bd_count(S)DIV_ROUND_UP(S, HNS3_MAX_BD_SIZE)
+#define hns3_rl_err(fmt, ...) \
+ do {\
+ if (net_ratelimit())\
+ netdev_err(fmt, ##__VA_ARGS__); \
+ } while (0)
+
static void hns3_clear_all_ring(struct hnae3_handle *h, bool force);
static void hns3_remove_hw_addr(struct net_device *netdev);
@@ -1033,6 +1039,9 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring *ring,
ret = hns3_handle_vtags(ring, skb);
if (unlikely(ret < 0)) {
+ u64_stats_update_begin(>syncp);
+ ring->stats.tx_vlan_err++;
+ u64_stats_update_end(>syncp);
return ret;
} else if (ret == HNS3_INNER_VLAN_TAG) {
inner_vtag = skb_vlan_tag_get(skb);
@@ -1053,19 +1062,31 @@ static int hns3_fill_skb_desc(struct hns3_enet_ring
*ring,
skb_reset_mac_len(skb);
ret = hns3_get_l4_protocol(skb, _proto, _proto);
- if (unlikely(ret))
+ if (unlikely(ret)) {
+ u64_stats_update_begin(>syncp);
+ ring->stats.tx_l4_proto_err++;
+ u64_stats_update_end(>syncp);
return ret;
+ }
ret = hns3_set_l2l3l4(skb, ol4_proto, il4_proto,
_cs_vlan_tso,
_type_vlan_len_msec);
- if (unlikely(ret))
+ if (unlikely(ret)) {
+ u64_stats_update_begin(>syncp);
+ ring->stats.tx_l2l3l4_err++;
+ u64_stats_update_end(>syncp);
return ret;
+ }
ret = hns3_set_tso(skb, , ,
_cs_vlan_tso);
- if (unlikely(ret))
+ if (unlikely(ret)) {
+ u64_stats_update_begin(>syncp);
+ ring->stats.tx_tso_err++;
+ u64_stats_update_end(>syncp);
return ret;
+ }
}
/* Set txbd */
@@ -1107,7 +1128,9 @@ static int hns3_fill_desc(struct hns3_enet_ring *ring,
void *priv,
}
if (unlikely(dma_mapping_error(dev, dma))) {
+ u64_stats_update_begin(>syncp);
ring->stats.sw_err_cnt++;
+ u64_stats_update_end(>syncp);
return -ENOMEM;
}
@@ -1330,9 +1353,7 @@ netdev_tx_t hns3_nic_net_xmit(struct sk_buff *skb, struct
net_device *netdev)
u64_stats_update_end(>syncp);
}
- if (net_ratelimit())
- netdev_err(netdev, "xmit error: %d!\n", buf_num);
-
+ hns3_rl_err(netdev, "xmit error: %d!\n", buf_num);
goto out_err_tx_ok;
}
@@ -1498,7 +1519,15 @@ static void hns3_nic_get_stats64(struct net_device
*netdev,
tx_bytes += ring->stats.tx_bytes;
tx_pkts += ring->stats.tx_pkts;
tx_drop += ring->stats.sw_err_cnt;
+ tx_drop += ring->stats.tx_vlan_err;
+ tx_drop += ring->stats.tx_l4_proto_err;
+ tx_drop += ring->stats.tx_l2l3l4_err;
+ tx_drop += ring->stats.tx_tso_err;
tx_errors += ring->stats.sw_err_cnt;
+ tx_errors += ring->stats.tx_vlan_err;
+ tx_errors += ring->stats.tx_l4_proto_err;
+ tx_errors += ring->stats.tx_l2l3l4_err;
+ tx_errors += ring->stats.tx_tso_err;
} while (u64_stats_fetch_retry_irq(>syncp, start));
/* fetch the rx stats */
@@ -2382,8 +2411,9
[PATCH net-next 10/12] net: hns3: refine MAC pause statistics querying function
From: Yufeng Mo
This patch refines the interface for querying MAC pause
statistics, and adds structure hns3_mac_stats to keep the
count of TX & RX.
Signed-off-by: Yufeng Mo
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hnae3.h | 11 +--
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c | 11 ---
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 12 +++-
3 files changed, 20 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
index a4624db..43740ee 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
@@ -91,6 +91,11 @@ struct hnae3_queue {
u16 rx_desc_num;/* total number of rx desc */
};
+struct hns3_mac_stats {
+ u64 tx_pause_cnt;
+ u64 rx_pause_cnt;
+};
+
/*hnae3 loop mode*/
enum hnae3_loop {
HNAE3_LOOP_APP,
@@ -298,6 +303,8 @@ struct hnae3_ae_dev {
* Remove multicast address from mac table
* update_stats()
* Update Old network device statistics
+ * get_mac_stats()
+ * get mac pause statistics including tx_cnt and rx_cnt
* get_ethtool_stats()
* Get ethtool network device statistics
* get_strings()
@@ -426,8 +433,8 @@ struct hnae3_ae_ops {
void (*update_stats)(struct hnae3_handle *handle,
struct net_device_stats *net_stats);
void (*get_stats)(struct hnae3_handle *handle, u64 *data);
- void (*get_mac_pause_stats)(struct hnae3_handle *handle, u64 *tx_cnt,
- u64 *rx_cnt);
+ void (*get_mac_stats)(struct hnae3_handle *handle,
+ struct hns3_mac_stats *mac_stats);
void (*get_strings)(struct hnae3_handle *handle,
u32 stringset, u8 *data);
int (*get_sset_count)(struct hnae3_handle *handle, int stringset);
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
index df08f9e..1750f80 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
@@ -1726,15 +1726,12 @@ static bool hns3_get_tx_timeo_queue_info(struct
net_device *ndev)
/* When mac received many pause frames continuous, it's unable to send
* packets, which may cause tx timeout
*/
- if (h->ae_algo->ops->update_stats &&
- h->ae_algo->ops->get_mac_pause_stats) {
- u64 tx_pause_cnt, rx_pause_cnt;
+ if (h->ae_algo->ops->get_mac_stats) {
+ struct hns3_mac_stats mac_stats;
- h->ae_algo->ops->update_stats(h, >stats);
- h->ae_algo->ops->get_mac_pause_stats(h, _pause_cnt,
-_pause_cnt);
+ h->ae_algo->ops->get_mac_stats(h, _stats);
netdev_info(ndev, "tx_pause_cnt: %llu, rx_pause_cnt: %llu\n",
- tx_pause_cnt, rx_pause_cnt);
+ mac_stats.tx_pause_cnt, mac_stats.rx_pause_cnt);
}
hw_head = readl_relaxed(tx_ring->tqp->io_base +
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index 7d7ab9e..1315275 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -750,14 +750,16 @@ static void hclge_get_stats(struct hnae3_handle *handle,
u64 *data)
p = hclge_tqps_get_stats(handle, p);
}
-static void hclge_get_mac_pause_stat(struct hnae3_handle *handle, u64 *tx_cnt,
-u64 *rx_cnt)
+static void hclge_get_mac_stat(struct hnae3_handle *handle,
+ struct hns3_mac_stats *mac_stats)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
- *tx_cnt = hdev->hw_stats.mac_stats.mac_tx_mac_pause_num;
- *rx_cnt = hdev->hw_stats.mac_stats.mac_rx_mac_pause_num;
+ hclge_update_stats(handle, NULL);
+
+ mac_stats->tx_pause_cnt = hdev->hw_stats.mac_stats.mac_tx_mac_pause_num;
+ mac_stats->rx_pause_cnt = hdev->hw_stats.mac_stats.mac_rx_mac_pause_num;
}
static int hclge_parse_func_status(struct hclge_dev *hdev,
@@ -9798,7 +9800,7 @@ static const struct hnae3_ae_ops hclge_ops = {
.set_mtu = hclge_set_mtu,
.reset_queue = hclge_reset_tqp,
.get_stats = hclge_get_stats,
- .get_mac_pause_stats = hclge_get_mac_pause_stat,
+ .get_mac_stats = hclge_get_mac_stat,
.update_stats = hclge_update_stats,
.get_strings = hclge_get_strings,
.get_sset_count = hclge_get_sset_count,
--
2.7.4
[PATCH net-next 00/12] net: hns3: add some bugfixes & optimizations & cleanups for HNS3 driver
This patch-set includes code optimizations, bugfixes and cleanups for the HNS3 ethernet controller driver. [patch 01/12] fixes a GFP flag error. [patch 02/12] fixes a VF interrupt error. [patch 03/12] adds a cleanup for VLAN handling. [patch 04/12] fixes a bug in debugfs. [patch 05/12] modifies pause displaying format. [patch 06/12] adds more DFX information for ethtool -d. [patch 07/12] adds more TX statistics information. [patch 08/12] adds a check for TX BD number. [patch 09/12] adds a cleanup for dumping NCL_CONFIG. [patch 10/12] refines function for querying MAC pause statistics. [patch 11/12] adds a handshake with VF when doing PF reset. [patch 12/12] refines some macro definitions. Guangbin Huang (1): net: hns3: add DFX registers information for ethtool -d Guojia Liao (1): net: hns3: refine some macro definitions Huazhong Tan (2): net: hns3: fix interrupt clearing error for VF net: hns3: add handshake with VF for PF reset Yonglong Liu (1): net: hns3: modify how pause options is displayed Yufeng Mo (3): net: hns3: add input length check for debugfs write function net: hns3: add function display NCL_CONFIG info net: hns3: refine MAC pause statistics querying function Yunsheng Lin (3): net: hns3: clean up for vlan handling in hns3_fill_desc_vtags net: hns3: add some statitics info to tx process net: hns3: add check for max TX BD num for tso and non-tso case Zhongzhu Liu (1): net: hns3: fix GFP flag error in hclge_mac_update_stats() drivers/net/ethernet/hisilicon/hns3/hnae3.h| 15 +- drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c | 4 + drivers/net/ethernet/hisilicon/hns3/hns3_enet.c| 268 ++-- drivers/net/ethernet/hisilicon/hns3/hns3_enet.h| 7 +- drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c | 4 + .../net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h | 7 + .../ethernet/hisilicon/hns3/hns3pf/hclge_debugfs.c | 64 +-- .../ethernet/hisilicon/hns3/hns3pf/hclge_main.c| 454 + .../ethernet/hisilicon/hns3/hns3pf/hclge_main.h| 2 + .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c | 28 +- .../ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 4 +- 11 files changed, 615 insertions(+), 242 deletions(-) -- 2.7.4
[PATCH net-next 05/12] net: hns3: modify how pause options is displayed
From: Yonglong Liu
Currently, the pause options of HNS3 shown like this:
"RX/TX" is always the same with "RX negotiated/TX negotiated".
Because of the driver covered the value of "RX/TX" with the value
of "RX negotiated/TX negotiated" after adjust link.
This patch records the pause configurations of the user, and never
covered them in adjust link.
Signed-off-by: Yonglong Liu
Reviewed-by: Yunsheng Lin
Signed-off-by: Huazhong Tan
---
.../ethernet/hisilicon/hns3/hns3pf/hclge_main.c| 38 --
1 file changed, 21 insertions(+), 17 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index c0feae3a..381f195 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -8207,28 +8207,15 @@ static int hclge_cfg_pauseparam(struct hclge_dev *hdev,
u32 rx_en, u32 tx_en)
{
int ret;
- if (rx_en && tx_en)
- hdev->fc_mode_last_time = HCLGE_FC_FULL;
- else if (rx_en && !tx_en)
- hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
- else if (!rx_en && tx_en)
- hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
- else
- hdev->fc_mode_last_time = HCLGE_FC_NONE;
-
if (hdev->tm_info.fc_mode == HCLGE_FC_PFC)
return 0;
ret = hclge_mac_pause_en_cfg(hdev, tx_en, rx_en);
- if (ret) {
- dev_err(>pdev->dev, "configure pauseparam error, ret =
%d.\n",
- ret);
- return ret;
- }
-
- hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
+ if (ret)
+ dev_err(>pdev->dev,
+ "configure pauseparam error, ret = %d.\n", ret);
- return 0;
+ return ret;
}
int hclge_cfg_flowctrl(struct hclge_dev *hdev)
@@ -8293,6 +8280,21 @@ static void hclge_get_pauseparam(struct hnae3_handle
*handle, u32 *auto_neg,
}
}
+static void hclge_record_user_pauseparam(struct hclge_dev *hdev,
+u32 rx_en, u32 tx_en)
+{
+ if (rx_en && tx_en)
+ hdev->fc_mode_last_time = HCLGE_FC_FULL;
+ else if (rx_en && !tx_en)
+ hdev->fc_mode_last_time = HCLGE_FC_RX_PAUSE;
+ else if (!rx_en && tx_en)
+ hdev->fc_mode_last_time = HCLGE_FC_TX_PAUSE;
+ else
+ hdev->fc_mode_last_time = HCLGE_FC_NONE;
+
+ hdev->tm_info.fc_mode = hdev->fc_mode_last_time;
+}
+
static int hclge_set_pauseparam(struct hnae3_handle *handle, u32 auto_neg,
u32 rx_en, u32 tx_en)
{
@@ -8318,6 +8320,8 @@ static int hclge_set_pauseparam(struct hnae3_handle
*handle, u32 auto_neg,
hclge_set_flowctrl_adv(hdev, rx_en, tx_en);
+ hclge_record_user_pauseparam(hdev, rx_en, tx_en);
+
if (!auto_neg)
return hclge_cfg_pauseparam(hdev, rx_en, tx_en);
--
2.7.4
[PATCH net-next 01/12] net: hns3: fix GFP flag error in hclge_mac_update_stats()
From: Zhongzhu Liu
When CONFIG_DEBUG_ATOMIC_SLEEP on, calling kzalloc with
GFP_KERNEL in hclge_mac_update_stats() will get below warning:
[ 52.514677] BUG: sleeping function called from invalid context at
mm/slab.h:501
[ 52.522051] in_atomic(): 0, irqs_disabled(): 0, pid: 1015, name: ifconfig
[ 52.528827] 2 locks held by ifconfig/1015:
[ 52.532921] #0: (ptrval) (>lock){}, at: seq_read+0x54/0x748
[ 52.539878] #1: (ptrval) (rcu_read_lock){}, at:
dev_seq_start+0x0/0x140
[ 52.547610] CPU: 16 PID: 1015 Comm: ifconfig Not tainted
5.3.0-rc3-00697-g20b80be #98
[ 52.555408] Hardware name: Huawei TaiShan 2280 V2/BC82AMDC, BIOS 2280-V2 CS
V3.B050.01 08/08/2019
[ 52.564242] Call trace:
[ 52.566687] dump_backtrace+0x0/0x1f8
[ 52.570338] show_stack+0x14/0x20
[ 52.573646] dump_stack+0xb4/0xec
[ 52.576950] ___might_sleep+0x178/0x198
[ 52.580773] __might_sleep+0x74/0xe0
[ 52.584338] __kmalloc+0x244/0x2d8
[ 52.587744] hclge_mac_update_stats+0xc8/0x1f8 [hclge]
[ 52.592870] hclge_update_stats+0xe0/0x170 [hclge]
[ 52.597651] hns3_nic_get_stats64+0xa0/0x458 [hns3]
[ 52.602514] dev_get_stats+0x58/0x138
[ 52.606165] dev_seq_printf_stats+0x8c/0x280
[ 52.610420] dev_seq_show+0x14/0x40
[ 52.613898] seq_read+0x574/0x748
[ 52.617205] proc_reg_read+0xb4/0x108
[ 52.620857] __vfs_read+0x54/0xa8
[ 52.624162] vfs_read+0xa0/0x190
[ 52.627380] ksys_read+0xc8/0x178
[ 52.630685] __arm64_sys_read+0x40/0x50
[ 52.634509] el0_svc_common.constprop.0+0x120/0x1e0
[ 52.639369] el0_svc_handler+0x50/0x90
[ 52.643106] el0_svc+0x8/0xc
So this patch uses GFP_ATOMIC instead of GFP_KERNEL to fix it.
Fixes: d174ea75c96a ("net: hns3: add statistics for PFC frames and MAC control
frames")
Signed-off-by: Zhongzhu Liu
Reviewed-by: Yunsheng Lin
Reviewed-by: Peng Li
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
index b7399f5..c0feae3a 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c
@@ -364,9 +364,13 @@ static int hclge_mac_update_stats_complete(struct
hclge_dev *hdev, u32 desc_num)
u16 i, k, n;
int ret;
- desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_KERNEL);
+ /* This may be called inside atomic sections,
+* so GFP_ATOMIC is more suitalbe here
+*/
+ desc = kcalloc(desc_num, sizeof(struct hclge_desc), GFP_ATOMIC);
if (!desc)
return -ENOMEM;
+
hclge_cmd_setup_basic_desc([0], HCLGE_OPC_STATS_MAC_ALL, true);
ret = hclge_cmd_send(>hw, desc, desc_num);
if (ret) {
--
2.7.4
[PATCH net-next 12/12] net: hns3: refine some macro definitions
From: Guojia Liao
Macro arguments should be enclosed in parentheses, in case of
expression argument, but parentheses of pure number in macro
definition should be removed for simplicity.
Signed-off-by: Guojia Liao
Signed-off-by: Guangbin Huang
Signed-off-by: Huazhong Tan
---
drivers/net/ethernet/hisilicon/hns3/hnae3.h | 4 ++--
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
index 43740ee..6c9fd58 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hnae3.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hnae3.h
@@ -58,10 +58,10 @@
BIT(HNAE3_DEV_SUPPORT_ROCE_B))
#define hnae3_dev_roce_supported(hdev) \
- hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
+ hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_ROCE_B)
#define hnae3_dev_dcb_supported(hdev) \
- hnae3_get_bit(hdev->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
+ hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_DCB_B)
#define hnae3_dev_fd_supported(hdev) \
hnae3_get_bit((hdev)->ae_dev->flag, HNAE3_DEV_SUPPORT_FD_B)
diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
index 4ccf107..bdde3af 100644
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.h
@@ -125,7 +125,7 @@
#define HCLGEVF_S_IP_BIT BIT(3)
#define HCLGEVF_V_TAG_BIT BIT(4)
-#define HCLGEVF_STATS_TIMER_INTERVAL (36)
+#define HCLGEVF_STATS_TIMER_INTERVAL 36U
enum hclgevf_evt_cause {
HCLGEVF_VECTOR0_EVENT_RST,
--
2.7.4
