On Fri, 26 Jan 2024 01:57:58 -0600
Avadhut Naik wrote:
> This patchset updates the mce_record tracepoint so that the recently added
> fields of struct mce are exported through it to userspace.
>
> The first patch adds PPIN (Protected Processor Inventory Number) field to
> the tracepoint.
>
>
On Thu, 11 Jan 2024 21:05:30 +
Carlos Galo wrote:
> The current implementation of the mark_victim tracepoint provides only
> the process ID (pid) of the victim process. This limitation poses
> challenges for userspace tools that need additional information
> about the OOM victim. The
This disables runtime PM on module exit automatically for us, currently
we manually disable runtime PM which can be error-prone if not done
in the right order or missed in some exit path. This also allows us
to simplify the probe exit path and remove callbacks. Do that here.
While here, as we can
This will unregister the HW spinlock on module exit automatically for us,
currently we manually unregister which can be error-prone if not done in
the right order. This also allows us to remove the remove callback.
Do that here.
Signed-off-by: Andrew Davis
---
Changes for v2:
- Clarify commit
We do not use the OF node anymore, nor does it matter how
we got to probe, so remove the check for of_node.
Signed-off-by: Andrew Davis
---
drivers/hwspinlock/omap_hwspinlock.c | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/hwspinlock/omap_hwspinlock.c
For loops with multiple initializers and increments are hard to read
and reason about, simplify this by using the looping index to index
into the hwspinlock array.
Signed-off-by: Andrew Davis
---
drivers/hwspinlock/omap_hwspinlock.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
On Thu, 8 Feb 2024 07:21:40 +
"Tian, Kevin" wrote:
> > From: Ankit Agrawal
> > Sent: Thursday, February 8, 2024 3:13 PM
> > >> > + * Determine how many bytes to be actually read from the
> > >> > device memory.
> > >> > + * Read request beyond the actual device memory size is
> > >>
From: "Steven Rostedt (Google)"
While looking at improving the saved_cmdlines cache I found a huge amount
of wasted memory that should be used for the cmdlines.
The tracing data saves pids during the trace. At sched switch, if a trace
occurred, it will save the comm of the task that did the
> I did not even think of that, and it actually makes sense so I'll go
> with what you propose: I'll replace atomic_inc() with
> atomic_inc_return_release(). And I'll add the following comment if
> that's ok with you:
>
> "Make sure the patching store is effective *before* we increment the
>
Hi Andrea,
On Thu, Feb 8, 2024 at 12:42 PM Andrea Parri wrote:
>
> > +static int __ftrace_modify_code(void *data)
> > +{
> > + struct ftrace_modify_param *param = data;
> > +
> > + if (atomic_inc_return(>cpu_count) == num_online_cpus()) {
> > +
On 2/7/24 07:51, limingming3 wrote:
> Since the sched_priority for SCHED_OTHER is always 0, it makes no
> sence to set it.
> Setting nice for SCHED_OTHER seems more meaningful.
Thanks!
This is actually a fix, I meant to set nice since the beginning.
-- Daniel
On Sun, 04 Feb 2024 18:24:20 +0100, Marijn Suijten wrote:
> Inherit PM660L PMIC LPG/triled block configuration from downstream
> drivers and DT sources, consisting of a triled block with automatic
> trickle charge control and source selection, three colored led channels
> belonging to the
> +static int __ftrace_modify_code(void *data)
> +{
> + struct ftrace_modify_param *param = data;
> +
> + if (atomic_inc_return(>cpu_count) == num_online_cpus()) {
> + ftrace_modify_all_code(param->command);
> + atomic_inc(>cpu_count);
I stared at
>> >>
>> >> If mem_count == 0, going through nvgrace_gpu_map_and_read() is not
>> >> necessary.
>> >
>> > Harmless, other than the possibly unnecessary call through to
>> > nvgrace_gpu_map_device_mem(). Maybe both
>> nvgrace_gpu_map_and_read()
>> > and nvgrace_gpu_map_and_write() could
On 1/31/24 15:00, Abel Vesa wrote:
On 24-01-29 17:17:28, Dmitry Baryshkov wrote:
On Mon, 29 Jan 2024 at 15:35, Abel Vesa wrote:
From: Sibi Sankar
The UEFI loads a lite variant of the ADSP firmware to support charging
use cases. The kernel needs to unload and reload it with the firmware
On 2/6/24 16:48, Nathan Chancellor wrote:
> On Tue, Feb 06, 2024 at 12:05:29PM +0100, Daniel Bristot de Oliveira wrote:
>> The following errors are showing up when compiling rtla with clang:
>>
>> $ make HOSTCC=clang CC=clang LLVM_IAS=1
>> [...]
>>
>> clang -O -g -DVERSION=\"6.8.0-rc1\"
On 2/7/24 16:47, Steven Rostedt wrote:
On Wed, 07 Feb 2024 14:33:21 +0100
Sven Schnelle wrote:
My assumption without reading the code is that something like this
happens:
CPU0 CPU1
[ringbuffer enabled]
ring_buffer_write()
On 05/02/2024 23:10, Masahiro Yamada wrote:
I think what you can contribute are:
- Explore the UTS_RELEASE users, and check if you can get rid of it.
Unfortunately I expect resistance for this. I also expect places like FW
loader it is necessary. And when this is used in sysfs, people will
The QCM6490 Linux Android firmware needs this workaround as well. Add it
to the list.
Acked-by: Heikki Krogerus
Reviewed-by: Dmitry Baryshkov
Signed-off-by: Luca Weiss
---
drivers/usb/typec/ucsi/ucsi_glink.c | 1 +
1 file changed, 1 insertion(+)
diff --git
Document the QCM6490 compatible used to describe the pmic glink on this
platform.
Reviewed-by: Krzysztof Kozlowski
Signed-off-by: Luca Weiss
---
Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git
This series adds all the necessary bits to enable USB-C role switching,
charger and fuel gauge (all via pmic-glink) on Fairphone 5.
Signed-off-by: Luca Weiss
---
Changes in v2:
- Rebase on -next, drop applied patch
- Pick up tags
- Link to v1:
Just polite ping
On Tue, Jan 16, 2024 at 12:32 AM Michael S. Tsirkin wrote:
>
> On Mon, Jan 15, 2024 at 09:48:40PM +0200, Andrew Melnychenko wrote:
> > When the Qemu launched with vhost but without tap vnet_hdr,
> > vhost tries to copy vnet_hdr from socket iter with size 0
> > to the page that
On Mon, Feb 05, 2024 at 01:06:23PM -0800, Haitao Huang wrote:
> SGX Enclave Page Cache (EPC) memory allocations are separate from normal
> RAM allocations, and are managed solely by the SGX subsystem. The existing
> cgroup memory controller cannot be used to limit or account for SGX EPC
> memory,
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