this patch series is
touching common code so this has been raised as RFC.
Abhishek Sahu (12):
clk: qcom: support for register offsets from rcg2 clock node
clk: qcom: flag for 64 bit CONFIG_CTL
clk: qcom: support for alpha mode configuration
clk: qcom: use offset from alpha pll node
clk: qcom
On 2017-07-25 00:47, Rob Herring wrote:
On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CR
On 2017-07-25 00:47, Rob Herring wrote:
On Wed, Jul 19, 2017 at 05:18:00PM +0530, Abhishek Sahu wrote:
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CR
On 2017-07-20 01:09, Boris Brezillon wrote:
On Wed, 19 Jul 2017 17:18:00 +0530
Abhishek Sahu <abs...@codeaurora.org> wrote:
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses
On 2017-07-20 01:09, Boris Brezillon wrote:
On Wed, 19 Jul 2017 17:18:00 +0530
Abhishek Sahu wrote:
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CR
On 2017-07-19 15:41, Vinod Koul wrote:
On Mon, Jul 17, 2017 at 02:54:21PM +0530, Abhishek Sahu wrote:
On 2017-06-26 18:19, Abhishek Sahu wrote:
>Some of the DMA controllers are capable of issuing the commands
>to peripheral by the DMA. These commands can be list of register
>rea
On 2017-07-19 15:41, Vinod Koul wrote:
On Mon, Jul 17, 2017 at 02:54:21PM +0530, Abhishek Sahu wrote:
On 2017-06-26 18:19, Abhishek Sahu wrote:
>Some of the DMA controllers are capable of issuing the commands
>to peripheral by the DMA. These commands can be list of register
>rea
On 2017-07-19 15:37, Vinod Koul wrote:
On Mon, Jun 26, 2017 at 06:19:27PM +0530, Abhishek Sahu wrote:
Some of the DMA controllers are capable of issuing the commands
to peripheral by the DMA. These commands can be list of register
reads/writes and its different from normal data reads/writes
On 2017-07-19 15:37, Vinod Koul wrote:
On Mon, Jun 26, 2017 at 06:19:27PM +0530, Abhishek Sahu wrote:
Some of the DMA controllers are capable of issuing the commands
to peripheral by the DMA. These commands can be list of register
reads/writes and its different from normal data reads/writes
the flash buffer from which data should be
read
b. Amount of data to be read
c. Flag bit specifying the last read request from the flash
buffer. Following the last read request the NANDc refers to the
buffer as empty.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mt
the flash buffer from which data should be
read
b. Amount of data to be read
c. Flag bit specifying the last read request from the flash
buffer. Following the last read request the NANDc refers to the
buffer as empty.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 72
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 52 +++
1 file changed, 48 inse
offsets array. A new compatible string has been added for
version 1.5.0 in BAM mode which uses version 1.5.0 register
offsets.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 52 +++
1 file changed, 48 insertions(+), 4 deletions(-)
diff
A new compatible string has been added for QPIC NAND version 1.5.0.
Since only register offsets are diffferent in version 1.5.0 so no
new dts property is required for QPIC NAND version 1.5.0.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
Documentation/devicetree/bindin
A new compatible string has been added for QPIC NAND version 1.5.0.
Since only register offsets are diffferent in version 1.5.0 so no
new dts property is required for QPIC NAND version 1.5.0.
Signed-off-by: Abhishek Sahu
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
1 file
. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 154 +++
. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 154 +++---
1 file changed, 100
transaction and call it before every new request
4. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.
5. Enable the BAM in NAND_CTRL.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c
BAM requires EOT flag should be set only for the
last data write in a codeword.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
transaction and call it before every new request
4. Check DMA mode for ADM or BAM and call the appropriate
descriptor formation function.
5. Enable the BAM in NAND_CTRL.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 197 ++
1 file
BAM requires EOT flag should be set only for the
last data write in a codeword.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index d0e7b9f
should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/mt
should be reset
before every page read by setting and clearing bit 0 of
NAND_ERASED_CW_DETECT_CFG.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd
-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index cb2b245..f49c3da 100644
--- a/drivers/mtd/nand/qcom_nandc.c
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c
-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 40
1 file changed, 40 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index cb2b245..f49c3da 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand/qcom_nandc.c
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 120
the registers read/write descriptors in
command channel.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 143 ++
1 file changed, 130 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
the registers read/write descriptors in
command channel.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 143 ++
1 file changed, 130 insertions(+), 13 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index
every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from BAM
transaction.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mt
1. QPIC NAND uses 3 BAM channels: command, data tx and data
rx while EBI2 NAND uses only single ADM channel.
2. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.
every transfer, it will be
cleared. The BAM transaction contains the array of command
elements, command and data scatter gather list and indexes. For
every transfer, all the resource will be taken from BAM
transaction.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 114
1. QPIC NAND uses 3 BAM channels: command, data tx and data
rx while EBI2 NAND uses only single ADM channel.
2. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 83
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abhishek
1. QPIC NAND will use compatible string "qcom,qpic-nandc-v1.4.0"
2. QPIC NAND will 3 BAM channels: command, data tx and data rx
while EBI2 NAND uses only single ADM channel.
3. CRCI is only required for ADM DMA and its not required for
QPIC NAND.
Signed-off-by: Abh
the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 11 +++
1 file changed, 11 ins
the QPIC NAND support in current
NAND driver with compatible string "qcom,qpic-nandc-v1.4.0" and
maps it with different configuration parameter in driver data.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/d
the ONFI parameter
page will be read from each connected device followed by MTD
device registration.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 88 +--
1 file changed, 59 insertions(+), 29 deletions(-)
-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8f9e86c..3b0ae91 100644
--- a/drivers/mtd/nand/qcom_nandc.c
the ONFI parameter
page will be read from each connected device followed by MTD
device registration.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 88 +--
1 file changed, 59 insertions(+), 29 deletions(-)
diff --git a/drivers/mtd/nand
-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 23 +--
1 file changed, 17 insertions(+), 6 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 8f9e86c..3b0ae91 100644
--- a/drivers/mtd/nand/qcom_nandc.c
+++ b/drivers/mtd/nand
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 2 --
1 file changed, 2 del
The memset in clear_read_regs is overhead. All the register data
will be filled by DMA during NAND operation so making these
register variables zero is not required.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mtd
and per codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 --
1 file changed, 2 deletions(-)
diff
river currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
b/Do
” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 2 --
1 file changed, 2 deletions(-)
diff --git a/Documentation/devicetree
and per codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 32
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index
river currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu
---
Documentation/devicetree/bindings/mtd/qcom_nandc.txt | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mtd/qcom_nandc.txt
b/Documentation/devicetree/binding
codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
codeword specific
registers for each NAND ECC step.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 37 +++--
1 file changed, 27 insertions(+), 10 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 110a26a
” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 26 --
1 file changed, 12 insertions(+), 14 del
” for specifying NAND device
sub nodes.
Since there is no user for this driver currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 26 --
1 file changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers
river currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f3b995d..8fa
quot;mtd: nand: Qualcomm NAND controller driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand
The current driver is failing without complete bootchain since
NAND_DEV_CMD_VLD value is not valid.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mt
river currently in so
changing compatible string is safe.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index f3b995d..8fa2f0c 100644
--- a/drivers/mtd
quot;mtd: nand: Qualcomm NAND controller driver")
Cc: sta...@vger.kernel.org
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index 57d483a..b
The current driver is failing without complete bootchain since
NAND_DEV_CMD_VLD value is not valid.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/qcom_nandc.c b/drivers/mtd/nand/qcom_nandc.c
index bc0408c
://www.spinics.net/lists/devicetree/msg183706.html
Abhishek Sahu (25):
mtd: nand: qcom: fix config error for BCH
mtd: nand: qcom: program NAND_DEV_CMD_VLD register
mtd: nand: qcom: change compatible string for EBI2 NANDC
dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC
mtd: nand
://www.spinics.net/lists/devicetree/msg183706.html
Abhishek Sahu (25):
mtd: nand: qcom: fix config error for BCH
mtd: nand: qcom: program NAND_DEV_CMD_VLD register
mtd: nand: qcom: change compatible string for EBI2 NANDC
dt-bindings: qcom_nandc: change compatible string for EBI2 NANDC
mtd: nand
On 2017-07-19 15:39, Vinod Koul wrote:
On Mon, Jun 26, 2017 at 06:19:28PM +0530, Abhishek Sahu wrote:
QCOM BAM also supports command descriptor which allows the SW to
create descriptors of type command which does not generate any
data transmissions but configures registers in the peripheral
On 2017-07-19 15:39, Vinod Koul wrote:
On Mon, Jun 26, 2017 at 06:19:28PM +0530, Abhishek Sahu wrote:
QCOM BAM also supports command descriptor which allows the SW to
create descriptors of type command which does not generate any
data transmissions but configures registers in the peripheral
On 2017-06-26 18:19, Abhishek Sahu wrote:
Some of the DMA controllers are capable of issuing the commands
to peripheral by the DMA. These commands can be list of register
reads/writes and its different from normal data reads/writes.
This patch adds new flag DMA_PREP_CMD in DMA API which tells
On 2017-06-26 18:19, Abhishek Sahu wrote:
Some of the DMA controllers are capable of issuing the commands
to peripheral by the DMA. These commands can be list of register
reads/writes and its different from normal data reads/writes.
This patch adds new flag DMA_PREP_CMD in DMA API which tells
On 2017-07-17 12:52, Boris Brezillon wrote:
On Mon, 17 Jul 2017 11:41:01 +0530
Abhishek Sahu <abs...@codeaurora.org> wrote:
>> > +
>> > +nand@79b {
>
> nand-controller@ {
>
> BTW, glad to see another driver moving to the new DT representation
>
On 2017-07-17 12:52, Boris Brezillon wrote:
On Mon, 17 Jul 2017 11:41:01 +0530
Abhishek Sahu wrote:
>> > +
>> > +nand@79b {
>
> nand-controller@ {
>
> BTW, glad to see another driver moving to the new DT representation
> :-).
>
>> > + comp
On 2017-07-10 19:48, Sricharan R wrote:
On 6/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function
On 2017-07-10 19:48, Sricharan R wrote:
On 6/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation function
On 2017-07-04 15:27, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data
On 2017-07-04 15:27, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current QCOM NAND driver only supports version 1.4.0
QCOM QPIC NAND controller. This patch adds the support for
version 1.5.0 which contains some of the registers at
different offsets. The driver data
On 2017-07-04 15:25, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping
On 2017-07-04 15:25, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
The current driver defines the register offset with preprocessor
macro which is defined crossponding to NAND controller version
1.4.0. This patch changes these macro with enumeration. It also
adds mapping
On 2017-07-04 15:14, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation
On 2017-07-04 15:14, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. Add the function for command descriptor preparation which
will be used only by BAM DMA and it will form the DMA descriptors
containing command elements.
2. Add the data descriptor preparation
On 2017-07-04 15:10, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. The BAM mode requires few registers configuration before each
NAND page read and codeword read which is different from ADM
so add the helper functions which will be called in BAM mode
only.
2
On 2017-07-04 15:10, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. The BAM mode requires few registers configuration before each
NAND page read and codeword read which is different from ADM
so add the helper functions which will be called in BAM mode
only.
2
On 2017-07-04 12:24, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status
On 2017-07-04 12:24, Archit Taneja wrote:
On 06/29/2017 12:46 PM, Abhishek Sahu wrote:
1. NAND_READ_LOCATION: provides the offset in page for
reading in BAM DMA mode
2. NAND_ERASED_CW_DETECT_CFG: contains the status for erased
code words
3. NAND_BUFFER_STATUS: contains the status
On 2017-07-10 19:40, Sricharan R wrote:
Hi,
On 7/4/2017 12:19 PM, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function
On 2017-07-10 19:40, Sricharan R wrote:
Hi,
On 7/4/2017 12:19 PM, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function
On 2017-07-04 11:40, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA
On 2017-07-04 11:40, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. prepare_bam_async_desc is the function which will call
all the DMA API’s. It will fetch the outstanding scatter gather
list for passed channel and will do the DMA descriptor formation.
The DMA
nsaction(nandc,
+ nandc->max_cwperpage);
Somehow, looks like something is missing because, nandc->max_cwperpage
passed from
here is used in alloc_bam_transaction, but it is assigned in the same
function ?
Yes. This assignment is not required. I will fix this in v2.
Regards,
Sricharan
--
Abhishek Sahu
nsaction(nandc,
+ nandc->max_cwperpage);
Somehow, looks like something is missing because, nandc->max_cwperpage
passed from
here is used in alloc_bam_transaction, but it is assigned in the same
function ?
Yes. This assignment is not required. I will fix this in v2.
Regards,
Sricharan
--
Abhishek Sahu
On 2017-06-29 15:20, Marek Vasut wrote:
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every
On 2017-06-29 15:20, Marek Vasut wrote:
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
The BAM transaction is the core data structure which will be used
for all the data transfers in QPIC NAND. Since the base layer is
serializing all the NAND requests so allocating BAM transaction
before every
On 2017-07-04 01:17, Boris Brezillon wrote:
On Thu, 29 Jun 2017 11:49:07 +0200
Marek Vasut <marek.va...@gmail.com> wrote:
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The configuration for BCH is not correct in the current
> driver so this patch fixed the same.
Fix the commi
On 2017-07-04 01:17, Boris Brezillon wrote:
On Thu, 29 Jun 2017 11:49:07 +0200
Marek Vasut wrote:
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
> The configuration for BCH is not correct in the current
> driver so this patch fixed the same.
Fix the commit message, I have no ide
On 2017-06-29 15:18, Marek Vasut wrote:
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
1. The QPIC NAND uses 3 BAM channels: command, data tx and
data rx while EBI2 NAND uses only single ADM channel.
2. The EBI2 NAND uses normal register read buffer since this
buffer will be remapped
On 2017-06-29 15:18, Marek Vasut wrote:
On 06/29/2017 09:15 AM, Abhishek Sahu wrote:
1. The QPIC NAND uses 3 BAM channels: command, data tx and
data rx while EBI2 NAND uses only single ADM channel.
2. The EBI2 NAND uses normal register read buffer since this
buffer will be remapped
On 2017-07-03 10:47, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. The QPIC NAND uses 3 BAM channels: command, data tx and
data rx while EBI2 NAND uses only single ADM channel.
2. The EBI2 NAND uses normal register read buffer since this
buffer will be remapped
On 2017-07-03 10:47, Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
1. The QPIC NAND uses 3 BAM channels: command, data tx and
data rx while EBI2 NAND uses only single ADM channel.
2. The EBI2 NAND uses normal register read buffer since this
buffer will be remapped
On 2017-07-04 01:11, Boris Brezillon wrote:
On Mon, 3 Jul 2017 10:08:32 +0530
Archit Taneja <arch...@codeaurora.org> wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAN
On 2017-07-04 01:11, Boris Brezillon wrote:
On Mon, 3 Jul 2017 10:08:32 +0530
Archit Taneja wrote:
On 06/29/2017 12:45 PM, Abhishek Sahu wrote:
> The current driver only support EBI2 NAND which uses ADM DMA. The
> latest QCOM controller supports QPIC NAND which uses BAM DMA. NAND
>
the ONFI parameter
page will be read from each connected device followed by MTD
device registration.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 92 ---
1 file changed, 61 insertions(+), 31 deletions(-)
the ONFI parameter
page will be read from each connected device followed by MTD
device registration.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 92 ---
1 file changed, 61 insertions(+), 31 deletions(-)
diff --git a/drivers/mtd/nand
. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c | 136 +++
. This mapping array will be
referenced before each register read and writes, where the register
offset enumeration is being replaced with actual register offsets.
Signed-off-by: Abhishek Sahu
---
drivers/mtd/nand/qcom_nandc.c | 136 +++---
1 file changed, 89
The BAM has multiple flags to control the transfer. This patch
adds flags parameter in register and data transfer functions and
modifies all these function call with appropriate flags.
Signed-off-by: Abhishek Sahu <abs...@codeaurora.org>
---
drivers/mtd/nand/qcom_nandc.c
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