Re: [PATCH 2/2] ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board
Hi Arnd,
thanks for the comments and sorry for the large 'To' list. In my v2 I'll
limit to Patrice Chotard (STi maintainer).
On Thu, Jan 28, 2021 at 02:08:51PM +0100, Arnd Bergmann wrote:
> On Thu, Jan 28, 2021 at 8:58 AM Alain Volmat wrote:
> >
> > 4KOpen (B2264) is a board based on the STMicroelectronics STiH418 soc:
> > - 2GB DDR
> > - HDMI
> > - Ethernet 1000-BaseT
> > - PCIe (mini PCIe connector)
> > - MicroSD slot
> > - USB2 and USB3 connectors
> > - Sata
> > - 40 pins GPIO header
> >
> > Signed-off-by: Alain Volmat
>
> The changelog text seems fine here.
>
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2021 STMicroelectronics
> > + * Author: Alain Volmat
> > + */
> > +/dts-v1/;
> > +#include "stih418.dtsi"
> > +#include
> > +/ {
> > + model = "STiH418 B2264";
> > + compatible = "st,stih418-b2264", "st,stih418";
> > +
> > + chosen {
> > + bootargs = "console=ttyAS0,115200 clk_ignore_unused";
> > + stdout-path = &sbc_serial0;
> > + };
>
> I don't think the bootargs should be there, both are just hacks
> when things don't work correctly. If they don't, then try to fix them
> first, by making sure that all clocks are properly listed, and that the
> stdou-path points the working console.
Indeed, bootargs can be cleaned up. console is not necessary, however
it's going to be hard to get rid of the clk_ignore_unused now and I'd
prefer to keep it now, in the same way as for the other sti DTs.
>
> > +&rng11 {
> > + status = "disabled";
> > +};
>
> Why do you disable the random number generator?
I shouldn't have putted this within the board DT. This rng11 is not
available on the STiH418.
In the v2 serie I'll had a separate commit to fix the stih418.dtsi instead.
Alain
>
>Arnd
[PATCH v2 0/3] Introduction of STiH418 based 4KOpen board
This serie introduces the 4KOpen (stih418-b2264) board based on a stih418 soc. Since it is the first board to use the spi-fsm SPI NOR controller available since stih407, the controller is also added within the stih407-family DT. It also contains a fix within the stih418 DT since the rng11 is not available on this platform and is thus disabled. Alain Volmat (3): ARM: dts: sti: add the spinor controller node within stih407-family ARM: dts: sti: disable rng11 on the stih418 platform ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/stih407-family.dtsi | 15 arch/arm/boot/dts/stih418-b2264.dts | 123 ++ arch/arm/boot/dts/stih418.dtsi| 4 + 4 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stih418-b2264.dts
[PATCH v2 1/3] ARM: dts: sti: add the spinor controller node within stih407-family
The STiH407 family (and further versions STiH410/STiH418) embedded
a serial flash controller allowing fast access to SPI-NOR.
This commit adds the corresponding node, relying on the st-spi-fsm
drivers.
Signed-off-by: Alain Volmat
---
v2: commit log improvement
arch/arm/boot/dts/stih407-family.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/stih407-family.dtsi
b/arch/arm/boot/dts/stih407-family.dtsi
index 23a1746f3baa..21f3347a91d6 100644
--- a/arch/arm/boot/dts/stih407-family.dtsi
+++ b/arch/arm/boot/dts/stih407-family.dtsi
@@ -616,6 +616,21 @@
st,lpc-mode = ;
};
+ spifsm: spifsm@9022000{
+ compatible = "st,spi-fsm";
+ reg = <0x9022000 0x1000>;
+ reg-names = "spi-fsm";
+ clocks = <&clk_s_c0_flexgen CLK_FLASH_PROMIP>;
+ clock-names = "emi_clk";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_fsm>;
+ st,syscfg = <&syscfg_core>;
+ st,boot-device-reg = <0x8c4>;
+ st,boot-device-spi = <0x68>;
+
+ status = "disabled";
+ };
+
sata0: sata@9b2 {
compatible = "st,ahci";
reg = <0x9b2 0x1000>;
--
2.17.1
[PATCH v2 2/3] ARM: dts: sti: disable rng11 on the stih418 platform
The rng11 is not available on the STiH418 hence is disabled in the
stih418.dtsi
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/boot/dts/stih418.dtsi b/arch/arm/boot/dts/stih418.dtsi
index a05e2278b448..39a249983496 100644
--- a/arch/arm/boot/dts/stih418.dtsi
+++ b/arch/arm/boot/dts/stih418.dtsi
@@ -27,6 +27,10 @@
};
soc {
+ rng11: rng@8a8a000 {
+ status = "disabled";
+ };
+
usb2_picophy1: phy2@0 {
compatible = "st,stih407-usb2-phy";
reg = <0 0>;
--
2.17.1
[PATCH v2 3/3] ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board
4KOpen (B2264) is a board based on the STMicroelectronics STiH418 soc:
- 2GB DDR
- HDMI
- Ethernet 1000-BaseT
- PCIe (mini PCIe connector)
- MicroSD slot
- USB2 and USB3 connectors
- Sata
- 40 pins GPIO header
Signed-off-by: Alain Volmat
---
v2: fix bootargs (removal of console=)
removal of rng11 node, moved into stih418.dtsi
arch/arm/boot/dts/Makefile | 3 +-
arch/arm/boot/dts/stih418-b2264.dts | 123
2 files changed, 125 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/boot/dts/stih418-b2264.dts
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3d1ea0b25168..5ad1b0854b66 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -1059,7 +1059,8 @@ dtb-$(CONFIG_ARCH_STI) += \
stih407-b2120.dtb \
stih410-b2120.dtb \
stih410-b2260.dtb \
- stih418-b2199.dtb
+ stih418-b2199.dtb \
+ stih418-b2264.dtb
dtb-$(CONFIG_ARCH_STM32) += \
stm32f429-disco.dtb \
stm32f469-disco.dtb \
diff --git a/arch/arm/boot/dts/stih418-b2264.dts
b/arch/arm/boot/dts/stih418-b2264.dts
new file mode 100644
index ..b70a76d3faa2
--- /dev/null
+++ b/arch/arm/boot/dts/stih418-b2264.dts
@@ -0,0 +1,123 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 STMicroelectronics
+ * Author: Alain Volmat
+ */
+/dts-v1/;
+#include "stih418.dtsi"
+#include
+/ {
+ model = "STiH418 B2264";
+ compatible = "st,stih418-b2264", "st,stih418";
+
+ chosen {
+ bootargs = "clk_ignore_unused";
+ stdout-path = &sbc_serial0;
+ };
+
+ memory@4000 {
+ device_type = "memory";
+ reg = <0x4000 0xc000>;
+ };
+
+ cpus {
+ cpu@0 {
+ operating-points-v2 = <&cpu_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ cpu@1 {
+ operating-points-v2 = <&cpu_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ cpu@2 {
+ operating-points-v2 = <&cpu_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ cpu@3 {
+ operating-points-v2 = <&cpu_opp_table>;
+ /* u-boot puts hpen in SBC dmem at 0xb8 offset */
+ cpu-release-addr = <0x94100b8>;
+ };
+ };
+
+ cpu_opp_table: opp_table {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp00 {
+ opp-hz = /bits/ 64 <5>;
+ opp-microvolt = <784000>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <8>;
+ opp-microvolt = <784000>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <12>;
+ opp-microvolt = <784000>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <15>;
+ opp-microvolt = <784000>;
+ };
+ };
+
+ aliases {
+ ttyAS0 = &sbc_serial0;
+ ethernet0 = ðernet0;
+ };
+};
+
+&ehci0 {
+ status = "okay";
+};
+
+ðernet0 {
+ phy-mode = "rgmii";
+ pinctrl-0 = <&pinctrl_rgmii1 &pinctrl_rgmii1_mdio_1>;
+ st,tx-retime-src = "clkgen";
+
+ snps,reset-gpio = <&pio0 7 0>;
+ snps,reset-active-low;
+ snps,reset-delays-us = <0 1 100>;
+
+ status = "okay";
+};
+
+&miphy28lp_phy {
+ phy_port0: port@9b22000 {
+ st,sata-gen = <2>; /* SATA GEN3 */
+ st,osc-rdy;
+ };
+};
+
+&mmc0 {
+ status = "okay";
+};
+
+&ohci1 {
+ status = "okay";
+};
+
+&pwm1 {
+ status = "okay";
+};
+
+&sata0 {
+ status = "okay";
+};
+
+&sbc_serial0 {
+ status = "okay";
+};
+
+&spifsm {
+ status = "okay";
+};
+
+&st_dwc3 {
+ status = "okay";
+};
--
2.17.1
[PATCH v2 0/3] Introduction of STiH418 based 4KOpen board
This serie introduces the 4KOpen (stih418-b2264) board based on a stih418 soc. Since it is the first board to use the spi-fsm SPI NOR controller available since stih407, the controller is also added within the stih407-family DT. It also contains a fix within the stih418 DT since the rng11 is not available on this platform and is thus disabled. Alain Volmat (3): ARM: dts: sti: add the spinor controller node within stih407-family ARM: dts: sti: disable rng11 on the stih418 platform ARM: dts: sti: Introduce 4KOpen (stih418-b2264) board arch/arm/boot/dts/Makefile| 3 +- arch/arm/boot/dts/stih407-family.dtsi | 15 arch/arm/boot/dts/stih418-b2264.dts | 123 ++ arch/arm/boot/dts/stih418.dtsi| 4 + 4 files changed, 144 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stih418-b2264.dts
[PATCH 2/5] i2c: stm32f7: support DT binding i2c-analog-filter
Replace driver internally coded enabling/disabling of the
analog-filter with the DT binding "i2c-analog-filter".
Signed-off-by: Alain Volmat
---
drivers/i2c/busses/i2c-stm32f7.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 473fbe144b7e..0c539fea2754 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -164,7 +164,6 @@ enum {
#define STM32F7_I2C_DNF_DEFAULT0
#define STM32F7_I2C_DNF_MAX15
-#define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN50 /* ns */
#define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX260 /* ns */
@@ -224,7 +223,6 @@ struct stm32f7_i2c_spec {
* @rise_time: Rise time (ns)
* @fall_time: Fall time (ns)
* @dnf: Digital filter coefficient (0-16)
- * @analog_filter: Analog filter delay (On/Off)
* @fmp_clr_offset: Fast Mode Plus clear register offset from set register
*/
struct stm32f7_i2c_setup {
@@ -233,7 +231,6 @@ struct stm32f7_i2c_setup {
u32 rise_time;
u32 fall_time;
u8 dnf;
- bool analog_filter;
u32 fmp_clr_offset;
};
@@ -312,6 +309,7 @@ struct stm32f7_i2c_msg {
* @wakeup_src: boolean to know if the device is a wakeup source
* @smbus_mode: states that the controller is configured in SMBus mode
* @host_notify_client: SMBus host-notify client
+ * @analog_filter: boolean to indicate enabling of the analog filter
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -340,6 +338,7 @@ struct stm32f7_i2c_dev {
bool wakeup_src;
bool smbus_mode;
struct i2c_client *host_notify_client;
+ bool analog_filter;
};
/*
@@ -386,14 +385,12 @@ static const struct stm32f7_i2c_setup stm32f7_setup = {
.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
.dnf = STM32F7_I2C_DNF_DEFAULT,
- .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
};
static const struct stm32f7_i2c_setup stm32mp15_setup = {
.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
.dnf = STM32F7_I2C_DNF_DEFAULT,
- .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
.fmp_clr_offset = 0x40,
};
@@ -471,10 +468,10 @@ static int stm32f7_i2c_compute_timing(struct
stm32f7_i2c_dev *i2c_dev,
/* Analog and Digital Filters */
af_delay_min =
- (setup->analog_filter ?
+ (i2c_dev->analog_filter ?
STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
af_delay_max =
- (setup->analog_filter ?
+ (i2c_dev->analog_filter ?
STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
dnf_delay = setup->dnf * i2cclk;
@@ -676,12 +673,15 @@ static int stm32f7_i2c_setup_timing(struct
stm32f7_i2c_dev *i2c_dev,
return ret;
}
+ i2c_dev->analog_filter = of_property_read_bool(i2c_dev->dev->of_node,
+ "i2c-analog-filter");
+
dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
setup->speed_freq, setup->clock_src);
dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
setup->rise_time, setup->fall_time);
dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
- (setup->analog_filter ? "On" : "Off"), setup->dnf);
+ (i2c_dev->analog_filter ? "On" : "Off"), setup->dnf);
i2c_dev->bus_rate = setup->speed_freq;
@@ -720,8 +720,8 @@ static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev
*i2c_dev)
timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
- /* Enable I2C */
- if (i2c_dev->setup.analog_filter)
+ /* Configure the Analog Filter */
+ if (i2c_dev->analog_filter)
stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
STM32F7_I2C_CR1_ANFOFF);
else
--
2.17.1
[PATCH 5/5] i2c: stm32f7: indicate the address being accessed on errors
To help debugging issues, add the address of the slave being
accessed when getting an error.
Signed-off-by: Alain Volmat
---
drivers/i2c/busses/i2c-stm32f7.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index f77cd6512a86..ef642fe1eb2c 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -1602,7 +1602,8 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void
*data)
/* Bus error */
if (status & STM32F7_I2C_ISR_BERR) {
- dev_err(dev, "<%s>: Bus error\n", __func__);
+ dev_err(dev, "<%s>: Bus error accessing addr 0x%x\n",
+ __func__, f7_msg->addr);
writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
stm32f7_i2c_release_bus(&i2c_dev->adap);
f7_msg->result = -EIO;
@@ -1610,13 +1611,15 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void
*data)
/* Arbitration loss */
if (status & STM32F7_I2C_ISR_ARLO) {
- dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
+ dev_dbg(dev, "<%s>: Arbitration loss accessing addr 0x%x\n",
+ __func__, f7_msg->addr);
writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
f7_msg->result = -EAGAIN;
}
if (status & STM32F7_I2C_ISR_PECERR) {
- dev_err(dev, "<%s>: PEC error in reception\n", __func__);
+ dev_err(dev, "<%s>: PEC error in reception accessing addr
0x%x\n",
+ __func__, f7_msg->addr);
writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
f7_msg->result = -EINVAL;
}
--
2.17.1
[PATCH 3/5] i2c: stm32f7: add support for DNF i2c-digital-filter binding
Add the support for the i2c-digital-filter binding, allowing to enable
the digital filter via the device-tree and indicate its value in the DT.
Signed-off-by: Alain Volmat
---
drivers/i2c/busses/i2c-stm32f7.c | 27 ---
1 file changed, 16 insertions(+), 11 deletions(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 0c539fea2754..f77cd6512a86 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -222,7 +222,6 @@ struct stm32f7_i2c_spec {
* @clock_src: I2C clock source frequency (Hz)
* @rise_time: Rise time (ns)
* @fall_time: Fall time (ns)
- * @dnf: Digital filter coefficient (0-16)
* @fmp_clr_offset: Fast Mode Plus clear register offset from set register
*/
struct stm32f7_i2c_setup {
@@ -230,7 +229,6 @@ struct stm32f7_i2c_setup {
u32 clock_src;
u32 rise_time;
u32 fall_time;
- u8 dnf;
u32 fmp_clr_offset;
};
@@ -310,6 +308,8 @@ struct stm32f7_i2c_msg {
* @smbus_mode: states that the controller is configured in SMBus mode
* @host_notify_client: SMBus host-notify client
* @analog_filter: boolean to indicate enabling of the analog filter
+ * @dnf_dt: value of digital filter requested via dt
+ * @dnf: value of digital filter to apply
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -339,6 +339,8 @@ struct stm32f7_i2c_dev {
bool smbus_mode;
struct i2c_client *host_notify_client;
bool analog_filter;
+ u32 dnf_dt;
+ u32 dnf;
};
/*
@@ -384,13 +386,11 @@ static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
static const struct stm32f7_i2c_setup stm32f7_setup = {
.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
- .dnf = STM32F7_I2C_DNF_DEFAULT,
};
static const struct stm32f7_i2c_setup stm32mp15_setup = {
.rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
.fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
- .dnf = STM32F7_I2C_DNF_DEFAULT,
.fmp_clr_offset = 0x40,
};
@@ -459,10 +459,11 @@ static int stm32f7_i2c_compute_timing(struct
stm32f7_i2c_dev *i2c_dev,
return -EINVAL;
}
- if (setup->dnf > STM32F7_I2C_DNF_MAX) {
+ i2c_dev->dnf = DIV_ROUND_CLOSEST(i2c_dev->dnf_dt, i2cclk);
+ if (i2c_dev->dnf > STM32F7_I2C_DNF_MAX) {
dev_err(i2c_dev->dev,
"DNF out of bound %d/%d\n",
- setup->dnf, STM32F7_I2C_DNF_MAX);
+ i2c_dev->dnf * i2cclk, STM32F7_I2C_DNF_MAX * i2cclk);
return -EINVAL;
}
@@ -473,13 +474,13 @@ static int stm32f7_i2c_compute_timing(struct
stm32f7_i2c_dev *i2c_dev,
af_delay_max =
(i2c_dev->analog_filter ?
STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
- dnf_delay = setup->dnf * i2cclk;
+ dnf_delay = i2c_dev->dnf * i2cclk;
sdadel_min = specs->hddat_min + setup->fall_time -
- af_delay_min - (setup->dnf + 3) * i2cclk;
+ af_delay_min - (i2c_dev->dnf + 3) * i2cclk;
sdadel_max = specs->vddat_max - setup->rise_time -
- af_delay_max - (setup->dnf + 4) * i2cclk;
+ af_delay_max - (i2c_dev->dnf + 4) * i2cclk;
scldel_min = setup->rise_time + specs->sudat_min;
@@ -645,6 +646,7 @@ static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev
*i2c_dev,
setup->speed_freq = t->bus_freq_hz;
i2c_dev->setup.rise_time = t->scl_rise_ns;
i2c_dev->setup.fall_time = t->scl_fall_ns;
+ i2c_dev->dnf_dt = t->digital_filter_width_ns;
setup->clock_src = clk_get_rate(i2c_dev->clk);
if (!setup->clock_src) {
@@ -652,6 +654,9 @@ static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev
*i2c_dev,
return -EINVAL;
}
+ if (!of_property_read_bool(i2c_dev->dev->of_node, "i2c-digital-filter"))
+ i2c_dev->dnf_dt = STM32F7_I2C_DNF_DEFAULT;
+
do {
ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
&i2c_dev->timing);
@@ -681,7 +686,7 @@ static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev
*i2c_dev,
dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
setup->rise_time, setup->fall_time);
dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
- (i2c_dev->analog_filter ? "On" : "Off"), setup->dnf);
+ (i2c_dev->analog_filter ? "On" : "Off"), i2c_dev->dnf);
i2c_dev->bus_rate = setup->speed_freq;
@@ -732,7 +737,7 @@ static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev
*i2c_dev)
stm32f7_i2c_cl
[PATCH 4/5] ARM: dts: stm32: enable the analog filter for all I2C nodes in stm32mp151
Enable the analog filter for all I2C nodes of the stm32mp151. Signed-off-by: Alain Volmat --- arch/arm/boot/dts/stm32mp151.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 3c75abacb374..558fc8fb38b6 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -493,6 +493,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x1>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -508,6 +509,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x2>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -523,6 +525,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x4>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -538,6 +541,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x10>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -1533,6 +1537,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x8>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; @@ -1570,6 +1575,7 @@ #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x20>; wakeup-source; + i2c-analog-filter; status = "disabled"; }; -- 2.17.1
[PATCH 0/5] i2c: stm32: filter binding support & debug info
This serie add support for the analog and digital filter binding for the stm32f7 i2c driver. An additional patch add also debug informations, displayed in case of errors. Alain Volmat (5): i2c: stm32f7: fix configuration of the digital filter i2c: stm32f7: support DT binding i2c-analog-filter i2c: stm32f7: add support for DNF i2c-digital-filter binding ARM: dts: stm32: enable the analog filter for all I2C nodes in stm32mp151 i2c: stm32f7: indicate the address being accessed on errors arch/arm/boot/dts/stm32mp151.dtsi | 6 +++ drivers/i2c/busses/i2c-stm32f7.c | 63 --- 2 files changed, 46 insertions(+), 23 deletions(-)
[PATCH 1/5] i2c: stm32f7: fix configuration of the digital filter
The digital filter related computation are present in the driver
however the programming of the filter within the IP is missing.
The maximum value for the DNF is wrong and should be 15 instead of 16.
Fixes: aeb068c57214 ("i2c: i2c-stm32f7: add driver")
Signed-off-by: Alain Volmat
---
drivers/i2c/busses/i2c-stm32f7.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 9aa8e65b511e..473fbe144b7e 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -57,6 +57,8 @@
#define STM32F7_I2C_CR1_RXDMAENBIT(15)
#define STM32F7_I2C_CR1_TXDMAENBIT(14)
#define STM32F7_I2C_CR1_ANFOFF BIT(12)
+#define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
+#define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
#define STM32F7_I2C_CR1_ERRIE BIT(7)
#define STM32F7_I2C_CR1_TCIE BIT(6)
#define STM32F7_I2C_CR1_STOPIE BIT(5)
@@ -160,7 +162,7 @@ enum {
};
#define STM32F7_I2C_DNF_DEFAULT0
-#define STM32F7_I2C_DNF_MAX16
+#define STM32F7_I2C_DNF_MAX15
#define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
#define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN50 /* ns */
@@ -725,6 +727,13 @@ static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev
*i2c_dev)
else
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
STM32F7_I2C_CR1_ANFOFF);
+
+ /* Program the Digital Filter */
+ stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_DNF_MASK);
+ stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
+
stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
STM32F7_I2C_CR1_PE);
}
--
2.17.1
[PATCH 8/8] spi: stm32: make spurious and overrun interrupts visible
We do not expect to receive spurious interrupts so rise a warning
if it happens.
RX overrun is an error condition that signals a corrupted RX
stream both in dma and in irq modes. Report the error and
abort the transfer in either cases.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 7692e2778df5..e7699758c609 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -895,8 +895,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
mask |= STM32H7_SPI_SR_RXP;
if (!(sr & mask)) {
- dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
- sr, ier);
+ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
+sr, ier);
spin_unlock_irqrestore(&spi->lock, flags);
return IRQ_NONE;
}
@@ -923,15 +923,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
}
if (sr & STM32H7_SPI_SR_OVR) {
- dev_warn(spi->dev, "Overrun: received value discarded\n");
- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
- stm32h7_spi_read_rxfifo(spi, false);
- /*
-* If overrun is detected while using DMA, it means that
-* something went wrong, so stop the current transfer
-*/
- if (spi->cur_usedma)
- end = true;
+ dev_err(spi->dev, "Overrun: RX data lost\n");
+ end = true;
}
if (sr & STM32H7_SPI_SR_EOT) {
--
2.17.1
[PATCH 6/8] spi: stm32: use bitfield macros
From: Amelie Delaunay
To avoid defining shift and mask separately and hand-coding the bit
manipulation, use the bitfield macros.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 54 ++---
1 file changed, 18 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index c40cea0640e6..cacd5b4b6823 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -5,6 +5,7 @@
// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
// Author(s): Amelie Delaunay for STMicroelectronics.
+#include
#include
#include
#include
@@ -94,27 +95,22 @@
#define STM32H7_SPI_CR1_SSIBIT(12)
/* STM32H7_SPI_CR2 bit fields */
-#define STM32H7_SPI_CR2_TSIZE_SHIFT0
#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
+#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
/* STM32H7_SPI_CFG1 bit fields */
-#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
-#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
-#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
+#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR_MIN 0
#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32H7_SPI_CFG2 bit fields */
-#define STM32H7_SPI_CFG2_MIDI_SHIFT4
#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
-#define STM32H7_SPI_CFG2_COMM_SHIFT17
#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
-#define STM32H7_SPI_CFG2_SP_SHIFT 19
#define STM32H7_SPI_CFG2_SPGENMASK(21, 19)
#define STM32H7_SPI_CFG2_MASTERBIT(22)
#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
@@ -140,7 +136,6 @@
#define STM32H7_SPI_SR_OVR BIT(6)
#define STM32H7_SPI_SR_MODFBIT(9)
#define STM32H7_SPI_SR_SUSPBIT(11)
-#define STM32H7_SPI_SR_RXPLVL_SHIFT13
#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
#define STM32H7_SPI_SR_RXWNE BIT(15)
@@ -415,9 +410,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
- max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
- STM32H7_SPI_CFG1_DSIZE_SHIFT;
- max_bpw += 1;
+ max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
spin_unlock_irqrestore(&spi->lock, flags);
@@ -585,8 +578,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
{
u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
while ((spi->rx_len > 0) &&
((sr & STM32H7_SPI_SR_RXP) ||
@@ -613,8 +605,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi,
bool flush)
}
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
}
dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@@ -1397,15 +1388,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
bpw = spi->cur_bpw - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
- cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
-STM32H7_SPI_CFG1_DSIZE;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
- cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
-STM32H7_SPI_CFG1_FTHLV;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
@@ -1423,8 +1412,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32
mbrdiv)
u32 clrb = 0, setb = 0;
clrb |= spi->cfg->regs->br.mask;
- setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
- spi->cfg->regs->br.mask;
+ setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
[PATCH 4/8] spi: stm32: driver uses reset controller only at init
From: Etienne Carriere
Remove reset controller device reference from the device private
structure since it is used only at probe time and can be discarded
once used to reset the SPI device.
Signed-off-by: Etienne Carriere
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 417a2aa2b98d..22bd3d1c8d69 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -268,7 +268,6 @@ struct stm32_spi_cfg {
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
- * @rst: SPI controller reset line
* @lock: prevent I/O concurrent access
* @irq: SPI controller interrupt line
* @fifo_size: size of the embedded fifo in bytes
@@ -294,7 +293,6 @@ struct stm32_spi {
void __iomem *base;
struct clk *clk;
u32 clk_rate;
- struct reset_control *rst;
spinlock_t lock; /* prevent I/O concurrent access */
int irq;
unsigned int fifo_size;
@@ -1831,6 +1829,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
struct spi_master *master;
struct stm32_spi *spi;
struct resource *res;
+ struct reset_control *rst;
int ret;
master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
@@ -1892,11 +1891,11 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (!IS_ERR(spi->rst)) {
- reset_control_assert(spi->rst);
+ rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (!IS_ERR(rst)) {
+ reset_control_assert(rst);
udelay(2);
- reset_control_deassert(spi->rst);
+ reset_control_deassert(rst);
}
if (spi->cfg->has_fifo)
--
2.17.1
[PATCH 7/8] spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC
From: Amelie Delaunay
Replace SPI_1HZ_NS private constant with NSEC_PER_SEC, which is easier
to read and understand.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index cacd5b4b6823..7692e2778df5 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -162,8 +162,6 @@
#define SPI_3WIRE_TX 3
#define SPI_3WIRE_RX 4
-#define SPI_1HZ_NS 10
-
/*
* use PIO for small transfers, avoiding DMA setup/teardown overhead for
drivers
* without fifo buffers.
@@ -1525,7 +1523,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi
*spi, u32 len)
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
if ((len > 1) && (spi->cur_midi > 0)) {
- u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
+ u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
u32 midi = min_t(u32,
DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
FIELD_GET(STM32H7_SPI_CFG2_MIDI,
--
2.17.1
[PATCH 0/8] spi: stm32: fix and enhancements for spi-stm32
The serie provides a fix for the spi-stm32 driver, allowing to properly handle 0 byte transfer (and thus being able to run spi-loopback-test). In addition to that, important enhancements are implemented, among them, supporting transfer larger that what the IP can setup in one go or allowing to use the SPI bus without cs_gpio. Alain Volmat (5): spi: stm32: properly handle 0 byte transfer spi: stm32: do not mandate cs_gpio spi: stm32h7: ensure message are smaller than max size spi: stm32: defer probe for reset spi: stm32: make spurious and overrun interrupts visible Amelie Delaunay (2): spi: stm32: use bitfield macros spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC Etienne Carriere (1): spi: stm32: driver uses reset controller only at init drivers/spi/spi-stm32.c | 116 +++- 1 file changed, 54 insertions(+), 62 deletions(-) -- 2.17.1
[PATCH 3/8] spi: stm32h7: ensure message are smaller than max size
Ensure that messages given to transfer_one handler can actually be
handled by it. For that purpose rely on the SPI framework
spi_split_transfers_maxsize function to split messages whenever necessary.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 8c6af3aa0dc3..417a2aa2b98d 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1013,6 +1013,20 @@ static int stm32_spi_prepare_msg(struct spi_master
*master,
!!(spi_dev->mode & SPI_LSB_FIRST),
!!(spi_dev->mode & SPI_CS_HIGH));
+ /* On STM32H7, messages should not exceed a maximum size setted
+* afterward via the set_number_of_data function. In order to
+* ensure that, split large messages into several messages
+*/
+ if (spi->cfg->set_number_of_data) {
+ int ret;
+
+ ret = spi_split_transfers_maxsize(master, msg,
+ STM32H7_SPI_TSIZE_MAX,
+ GFP_KERNEL | GFP_DMA);
+ if (ret)
+ return ret;
+ }
+
spin_lock_irqsave(&spi->lock, flags);
/* CPOL, CPHA and LSB FIRST bits have common register */
--
2.17.1
[PATCH 1/8] spi: stm32: properly handle 0 byte transfer
On 0 byte transfer request, return straight from the
xfer function after finalizing the transfer.
Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index db3e305d9ec4..137213633e6d 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1657,6 +1657,12 @@ static int stm32_spi_transfer_one(struct spi_master
*master,
struct stm32_spi *spi = spi_master_get_devdata(master);
int ret;
+ /* Don't do anything on 0 bytes transfers */
+ if (transfer->len == 0) {
+ spi_finalize_current_transfer(master);
+ return 0;
+ }
+
spi->tx_buf = transfer->tx_buf;
spi->rx_buf = transfer->rx_buf;
spi->tx_len = spi->tx_buf ? transfer->len : 0;
--
2.17.1
[PATCH 2/8] spi: stm32: do not mandate cs_gpio
CS gpios is not mandatory, the driver should allow working
even when CS are not given.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 137213633e6d..8c6af3aa0dc3 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1946,12 +1946,6 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_pm_disable;
}
- if (!master->cs_gpiods) {
- dev_err(&pdev->dev, "no CS gpios available\n");
- ret = -EINVAL;
- goto err_pm_disable;
- }
-
dev_info(&pdev->dev, "driver initialized\n");
return 0;
--
2.17.1
[PATCH 5/8] spi: stm32: defer probe for reset
Defer the probe operation when a reset controller device is expected
but have not yet been probed.
This change replaces use of devm_reset_control_get_exclusive() with
devm_reset_control_get_optional_exclusive() as reset controller is
optional which is now explicitly stated.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 22bd3d1c8d69..c40cea0640e6 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1891,8 +1891,14 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (!IS_ERR(rst)) {
+ rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (rst) {
+ if (IS_ERR(rst)) {
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
+ "failed to get reset\n");
+ goto err_clk_disable;
+ }
+
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
--
2.17.1
Re: [PATCH 5/8] spi: stm32: defer probe for reset
Hi Mark, sorry about that, I've just noticed the issue. This is probably due to modification of patches ordering I did. STM32H7_SPI_TSIZE_MAX is introduced in the PATCH 6/8 and this is the reason why PATCH 5/8 doesn't build properly. I'll rework that to ensure that all patches compile properly. Sorry again, Alain On Fri, Feb 05, 2021 at 04:41:54PM +, Mark Brown wrote: > On Fri, Feb 05, 2021 at 12:08:59PM +0100, Alain Volmat wrote: > > Defer the probe operation when a reset controller device is expected > > but have not yet been probed. > > > > This change replaces use of devm_reset_control_get_exclusive() with > > devm_reset_control_get_optional_exclusive() as reset controller is > > optional which is now explicitly stated. > > This has trouble building an x86 allmodconfig build: > > /mnt/kernel/drivers/spi/spi-stm32.c: In function 'stm32_spi_prepare_msg': > /mnt/kernel/drivers/spi/spi-stm32.c:1022:9: error: 'STM32H7_SPI_TSIZE_MAX' > undeclared (first use in this function); did you mean 'STM32H7_SPI_CR1_MASRX'? > STM32H7_SPI_TSIZE_MAX, > ^ > STM32H7_SPI_CR1_MASRX > /mnt/kernel/drivers/spi/spi-stm32.c:1022:9: note: each undeclared identifier > is reported only once for each function it appears in > > This may be due to an earlier patch in the series, my script is working > back through the patch series.
[PATCH v2 1/8] spi: stm32: properly handle 0 byte transfer
On 0 byte transfer request, return straight from the
xfer function after finalizing the transfer.
Fixes: dcbe0d84dfa5 ("spi: add driver for STM32 SPI controller")
Signed-off-by: Alain Volmat
---
v2: remove useless spi_finalize_current_transfer
drivers/spi/spi-stm32.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index db3e305d9ec4..6cdecd1c5ec7 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1657,6 +1657,10 @@ static int stm32_spi_transfer_one(struct spi_master
*master,
struct stm32_spi *spi = spi_master_get_devdata(master);
int ret;
+ /* Don't do anything on 0 bytes transfers */
+ if (transfer->len == 0)
+ return 0;
+
spi->tx_buf = transfer->tx_buf;
spi->rx_buf = transfer->rx_buf;
spi->tx_len = spi->tx_buf ? transfer->len : 0;
--
2.17.1
[PATCH v2 6/8] spi: stm32: defer probe for reset
Defer the probe operation when a reset controller device is expected
but have not yet been probed.
This change replaces use of devm_reset_control_get_exclusive() with
devm_reset_control_get_optional_exclusive() as reset controller is
optional which is now explicitly stated.
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 561234829110..54196cecfe2e 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1871,8 +1871,14 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (!IS_ERR(rst)) {
+ rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
+ if (rst) {
+ if (IS_ERR(rst)) {
+ ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
+ "failed to get reset\n");
+ goto err_clk_disable;
+ }
+
reset_control_assert(rst);
udelay(2);
reset_control_deassert(rst);
--
2.17.1
[PATCH v2 3/8] spi: stm32: use bitfield macros
From: Amelie Delaunay
To avoid defining shift and mask separately and hand-coding the bit
manipulation, use the bitfield macros.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 54 ++---
1 file changed, 18 insertions(+), 36 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 2b4ea4cba00b..a46132e81533 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -5,6 +5,7 @@
// Copyright (C) 2017, STMicroelectronics - All Rights Reserved
// Author(s): Amelie Delaunay for STMicroelectronics.
+#include
#include
#include
#include
@@ -94,27 +95,22 @@
#define STM32H7_SPI_CR1_SSIBIT(12)
/* STM32H7_SPI_CR2 bit fields */
-#define STM32H7_SPI_CR2_TSIZE_SHIFT0
#define STM32H7_SPI_CR2_TSIZE GENMASK(15, 0)
+#define STM32H7_SPI_TSIZE_MAX GENMASK(15, 0)
/* STM32H7_SPI_CFG1 bit fields */
-#define STM32H7_SPI_CFG1_DSIZE_SHIFT 0
#define STM32H7_SPI_CFG1_DSIZE GENMASK(4, 0)
-#define STM32H7_SPI_CFG1_FTHLV_SHIFT 5
#define STM32H7_SPI_CFG1_FTHLV GENMASK(8, 5)
#define STM32H7_SPI_CFG1_RXDMAEN BIT(14)
#define STM32H7_SPI_CFG1_TXDMAEN BIT(15)
-#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR GENMASK(30, 28)
+#define STM32H7_SPI_CFG1_MBR_SHIFT 28
#define STM32H7_SPI_CFG1_MBR_MIN 0
#define STM32H7_SPI_CFG1_MBR_MAX (GENMASK(30, 28) >> 28)
/* STM32H7_SPI_CFG2 bit fields */
-#define STM32H7_SPI_CFG2_MIDI_SHIFT4
#define STM32H7_SPI_CFG2_MIDI GENMASK(7, 4)
-#define STM32H7_SPI_CFG2_COMM_SHIFT17
#define STM32H7_SPI_CFG2_COMM GENMASK(18, 17)
-#define STM32H7_SPI_CFG2_SP_SHIFT 19
#define STM32H7_SPI_CFG2_SPGENMASK(21, 19)
#define STM32H7_SPI_CFG2_MASTERBIT(22)
#define STM32H7_SPI_CFG2_LSBFRST BIT(23)
@@ -140,7 +136,6 @@
#define STM32H7_SPI_SR_OVR BIT(6)
#define STM32H7_SPI_SR_MODFBIT(9)
#define STM32H7_SPI_SR_SUSPBIT(11)
-#define STM32H7_SPI_SR_RXPLVL_SHIFT13
#define STM32H7_SPI_SR_RXPLVL GENMASK(14, 13)
#define STM32H7_SPI_SR_RXWNE BIT(15)
@@ -417,9 +412,7 @@ static int stm32h7_spi_get_bpw_mask(struct stm32_spi *spi)
stm32_spi_set_bits(spi, STM32H7_SPI_CFG1, STM32H7_SPI_CFG1_DSIZE);
cfg1 = readl_relaxed(spi->base + STM32H7_SPI_CFG1);
- max_bpw = (cfg1 & STM32H7_SPI_CFG1_DSIZE) >>
- STM32H7_SPI_CFG1_DSIZE_SHIFT;
- max_bpw += 1;
+ max_bpw = FIELD_GET(STM32H7_SPI_CFG1_DSIZE, cfg1) + 1;
spin_unlock_irqrestore(&spi->lock, flags);
@@ -587,8 +580,7 @@ static void stm32f4_spi_read_rx(struct stm32_spi *spi)
static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi, bool flush)
{
u32 sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- u32 rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ u32 rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
while ((spi->rx_len > 0) &&
((sr & STM32H7_SPI_SR_RXP) ||
@@ -615,8 +607,7 @@ static void stm32h7_spi_read_rxfifo(struct stm32_spi *spi,
bool flush)
}
sr = readl_relaxed(spi->base + STM32H7_SPI_SR);
- rxplvl = (sr & STM32H7_SPI_SR_RXPLVL) >>
-STM32H7_SPI_SR_RXPLVL_SHIFT;
+ rxplvl = FIELD_GET(STM32H7_SPI_SR_RXPLVL, sr);
}
dev_dbg(spi->dev, "%s%s: %d bytes left\n", __func__,
@@ -1385,15 +1376,13 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
bpw = spi->cur_bpw - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_DSIZE;
- cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
-STM32H7_SPI_CFG1_DSIZE;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_DSIZE, bpw);
spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
- cfg1_setb |= (fthlv << STM32H7_SPI_CFG1_FTHLV_SHIFT) &
-STM32H7_SPI_CFG1_FTHLV;
+ cfg1_setb |= FIELD_PREP(STM32H7_SPI_CFG1_FTHLV, fthlv);
writel_relaxed(
(readl_relaxed(spi->base + STM32H7_SPI_CFG1) &
@@ -1411,8 +1400,7 @@ static void stm32_spi_set_mbr(struct stm32_spi *spi, u32
mbrdiv)
u32 clrb = 0, setb = 0;
clrb |= spi->cfg->regs->br.mask;
- setb |= ((u32)mbrdiv << spi->cfg->regs->br.shift) &
- spi->cfg->regs->br.mask;
+ setb |= (mbrdiv << spi->cfg->regs->br.shift) & spi->cfg->regs->br.mask;
writel_relaxed((readl_relaxed(spi->base + spi->cfg->regs->br.reg) &
[PATCH v2 2/8] spi: stm32: do not mandate cs_gpio
CS gpios is not mandatory, the driver should allow working
even when CS are not given.
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 6cdecd1c5ec7..2b4ea4cba00b 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1944,12 +1944,6 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_pm_disable;
}
- if (!master->cs_gpiods) {
- dev_err(&pdev->dev, "no CS gpios available\n");
- ret = -EINVAL;
- goto err_pm_disable;
- }
-
dev_info(&pdev->dev, "driver initialized\n");
return 0;
--
2.17.1
[PATCH v2 0/8] spi: stm32: fix and enhancements for spi-stm32
The serie provides a fix for the spi-stm32 driver, allowing to properly handle 0 byte transfer (and thus being able to run spi-loopback-test). In addition to that, important enhancements are implemented, among them, supporting transfer larger that what the IP can setup in one go or allowing to use the SPI bus without cs_gpio. v2: Fix within patch 'spi: stm32: properly handle 0 byte transfer' Reorder patches to avoid compilation issue Alain Volmat (5): spi: stm32: properly handle 0 byte transfer spi: stm32: do not mandate cs_gpio spi: stm32h7: ensure message are smaller than max size spi: stm32: defer probe for reset spi: stm32: make spurious and overrun interrupts visible Amelie Delaunay (2): spi: stm32: use bitfield macros spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC Etienne Carriere (1): spi: stm32: driver uses reset controller only at init drivers/spi/spi-stm32.c | 114 ++-- 1 file changed, 52 insertions(+), 62 deletions(-) -- 2.17.1
[PATCH v2 8/8] spi: stm32: make spurious and overrun interrupts visible
We do not expect to receive spurious interrupts so rise a warning
if it happens.
RX overrun is an error condition that signals a corrupted RX
stream both in dma and in irq modes. Report the error and
abort the transfer in either cases.
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 15 ---
1 file changed, 4 insertions(+), 11 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index f3a4ff60ac4b..25c076461011 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -895,8 +895,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
mask |= STM32H7_SPI_SR_RXP;
if (!(sr & mask)) {
- dev_dbg(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
- sr, ier);
+ dev_warn(spi->dev, "spurious IT (sr=0x%08x, ier=0x%08x)\n",
+sr, ier);
spin_unlock_irqrestore(&spi->lock, flags);
return IRQ_NONE;
}
@@ -923,15 +923,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
}
if (sr & STM32H7_SPI_SR_OVR) {
- dev_warn(spi->dev, "Overrun: received value discarded\n");
- if (!spi->cur_usedma && (spi->rx_buf && (spi->rx_len > 0)))
- stm32h7_spi_read_rxfifo(spi, false);
- /*
-* If overrun is detected while using DMA, it means that
-* something went wrong, so stop the current transfer
-*/
- if (spi->cur_usedma)
- end = true;
+ dev_err(spi->dev, "Overrun: RX data lost\n");
+ end = true;
}
if (sr & STM32H7_SPI_SR_EOT) {
--
2.17.1
[PATCH v2 4/8] spi: stm32h7: ensure message are smaller than max size
Ensure that messages given to transfer_one handler can actually be
handled by it. For that purpose rely on the SPI framework
spi_split_transfers_maxsize function to split messages whenever necessary.
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index a46132e81533..8e4db219b95d 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1004,6 +1004,20 @@ static int stm32_spi_prepare_msg(struct spi_master
*master,
!!(spi_dev->mode & SPI_LSB_FIRST),
!!(spi_dev->mode & SPI_CS_HIGH));
+ /* On STM32H7, messages should not exceed a maximum size setted
+* afterward via the set_number_of_data function. In order to
+* ensure that, split large messages into several messages
+*/
+ if (spi->cfg->set_number_of_data) {
+ int ret;
+
+ ret = spi_split_transfers_maxsize(master, msg,
+ STM32H7_SPI_TSIZE_MAX,
+ GFP_KERNEL | GFP_DMA);
+ if (ret)
+ return ret;
+ }
+
spin_lock_irqsave(&spi->lock, flags);
/* CPOL, CPHA and LSB FIRST bits have common register */
--
2.17.1
[PATCH v2 7/8] spi: stm32h7: replace private SPI_1HZ_NS with NSEC_PER_SEC
From: Amelie Delaunay
Replace SPI_1HZ_NS private constant with NSEC_PER_SEC, which is easier
to read and understand.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 54196cecfe2e..f3a4ff60ac4b 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -162,8 +162,6 @@
#define SPI_3WIRE_TX 3
#define SPI_3WIRE_RX 4
-#define SPI_1HZ_NS 10
-
/*
* use PIO for small transfers, avoiding DMA setup/teardown overhead for
drivers
* without fifo buffers.
@@ -1525,7 +1523,7 @@ static void stm32h7_spi_data_idleness(struct stm32_spi
*spi, u32 len)
cfg2_clrb |= STM32H7_SPI_CFG2_MIDI;
if ((len > 1) && (spi->cur_midi > 0)) {
- u32 sck_period_ns = DIV_ROUND_UP(SPI_1HZ_NS, spi->cur_speed);
+ u32 sck_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, spi->cur_speed);
u32 midi = min_t(u32,
DIV_ROUND_UP(spi->cur_midi, sck_period_ns),
FIELD_GET(STM32H7_SPI_CFG2_MIDI,
--
2.17.1
[PATCH v2 5/8] spi: stm32: driver uses reset controller only at init
From: Etienne Carriere
Remove reset controller device reference from the device private
structure since it is used only at probe time and can be discarded
once used to reset the SPI device.
Signed-off-by: Etienne Carriere
Signed-off-by: Alain Volmat
---
v2: reordered within the serie
drivers/spi/spi-stm32.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 8e4db219b95d..561234829110 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -263,7 +263,6 @@ struct stm32_spi_cfg {
* @base: virtual memory area
* @clk: hw kernel clock feeding the SPI clock generator
* @clk_rate: rate of the hw kernel clock feeding the SPI clock generator
- * @rst: SPI controller reset line
* @lock: prevent I/O concurrent access
* @irq: SPI controller interrupt line
* @fifo_size: size of the embedded fifo in bytes
@@ -289,7 +288,6 @@ struct stm32_spi {
void __iomem *base;
struct clk *clk;
u32 clk_rate;
- struct reset_control *rst;
spinlock_t lock; /* prevent I/O concurrent access */
int irq;
unsigned int fifo_size;
@@ -1811,6 +1809,7 @@ static int stm32_spi_probe(struct platform_device *pdev)
struct spi_master *master;
struct stm32_spi *spi;
struct resource *res;
+ struct reset_control *rst;
int ret;
master = spi_alloc_master(&pdev->dev, sizeof(struct stm32_spi));
@@ -1872,11 +1871,11 @@ static int stm32_spi_probe(struct platform_device *pdev)
goto err_clk_disable;
}
- spi->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
- if (!IS_ERR(spi->rst)) {
- reset_control_assert(spi->rst);
+ rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
+ if (!IS_ERR(rst)) {
+ reset_control_assert(rst);
udelay(2);
- reset_control_deassert(spi->rst);
+ reset_control_deassert(rst);
}
if (spi->cfg->has_fifo)
--
2.17.1
Re: [PATCH] [v2] i2c: stm32f7: Fix runtime PM imbalance on error
Hi,
Reviewed-by: Alain Volmat
Thanks,
Alain
On Wed, May 27, 2020 at 01:38:53AM +, Dinghao Liu wrote:
> pm_runtime_get_sync() increments the runtime PM usage counter even
> the call returns an error code. Thus a pairing decrement is needed
> on the error handling path to keep the counter balanced.
>
> Signed-off-by: Dinghao Liu
> ---
>
> Changelog:
>
> v2: - Use pm_runtime_put_noidle() instead of
> pm_runtime_put_autosuspend(). Fix 5 more
> similar cases within this dirver.
> ---
> drivers/i2c/busses/i2c-stm32f7.c | 24 ++--
> 1 file changed, 18 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/i2c/busses/i2c-stm32f7.c
> b/drivers/i2c/busses/i2c-stm32f7.c
> index 330ffed011e0..822fd1f5b5ae 100644
> --- a/drivers/i2c/busses/i2c-stm32f7.c
> +++ b/drivers/i2c/busses/i2c-stm32f7.c
> @@ -1620,8 +1620,10 @@ static int stm32f7_i2c_xfer(struct i2c_adapter
> *i2c_adap,
> f7_msg->smbus = false;
>
> ret = pm_runtime_get_sync(i2c_dev->dev);
> - if (ret < 0)
> + if (ret < 0) {
> + pm_runtime_put_noidle(i2c_dev->dev);
> return ret;
> + }
>
> ret = stm32f7_i2c_wait_free_bus(i2c_dev);
> if (ret)
> @@ -1666,8 +1668,10 @@ static int stm32f7_i2c_smbus_xfer(struct i2c_adapter
> *adapter, u16 addr,
> f7_msg->smbus = true;
>
> ret = pm_runtime_get_sync(dev);
> - if (ret < 0)
> + if (ret < 0) {
> + pm_runtime_put_noidle(dev);
> return ret;
> + }
>
> ret = stm32f7_i2c_wait_free_bus(i2c_dev);
> if (ret)
> @@ -1767,8 +1771,10 @@ static int stm32f7_i2c_reg_slave(struct i2c_client
> *slave)
> return ret;
>
> ret = pm_runtime_get_sync(dev);
> - if (ret < 0)
> + if (ret < 0) {
> + pm_runtime_put_noidle(dev);
> return ret;
> + }
>
> if (!stm32f7_i2c_is_slave_registered(i2c_dev))
> stm32f7_i2c_enable_wakeup(i2c_dev, true);
> @@ -1837,8 +1843,10 @@ static int stm32f7_i2c_unreg_slave(struct i2c_client
> *slave)
> WARN_ON(!i2c_dev->slave[id]);
>
> ret = pm_runtime_get_sync(i2c_dev->dev);
> - if (ret < 0)
> + if (ret < 0) {
> + pm_runtime_put_noidle(i2c_dev->dev);
> return ret;
> + }
>
> if (id == 0) {
> mask = STM32F7_I2C_OAR1_OA1EN;
> @@ -2182,8 +2190,10 @@ static int stm32f7_i2c_regs_backup(struct
> stm32f7_i2c_dev *i2c_dev)
> struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
>
> ret = pm_runtime_get_sync(i2c_dev->dev);
> - if (ret < 0)
> + if (ret < 0) {
> + pm_runtime_put_noidle(i2c_dev->dev);
> return ret;
> + }
>
> backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
> backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
> @@ -2204,8 +2214,10 @@ static int stm32f7_i2c_regs_restore(struct
> stm32f7_i2c_dev *i2c_dev)
> struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
>
> ret = pm_runtime_get_sync(i2c_dev->dev);
> - if (ret < 0)
> + if (ret < 0) {
> + pm_runtime_put_noidle(i2c_dev->dev);
> return ret;
> + }
>
> cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
> if (cr1 & STM32F7_I2C_CR1_PE)
> --
> 2.17.1
>
[PATCH v3 2/2] i2c: stm32f7: Add SMBus Host-Notify protocol support
Rely on the core functions to implement the host-notify
protocol via the a I2C slave device.
Signed-off-by: Alain Volmat
---
v3: identical to v2
v2: fix slot #0 usage condition within stm32f7_i2c_get_free_slave_id
drivers/i2c/busses/Kconfig | 1 +
drivers/i2c/busses/i2c-stm32f7.c | 110 +--
2 files changed, 96 insertions(+), 15 deletions(-)
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 735bf31a3fdf..ae8671727a4c 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -1036,6 +1036,7 @@ config I2C_STM32F7
tristate "STMicroelectronics STM32F7 I2C support"
depends on ARCH_STM32 || COMPILE_TEST
select I2C_SLAVE
+ select I2C_SMBUS
help
Enable this option to add support for STM32 I2C controller embedded
in STM32F7 SoCs.
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index bff3479fe122..223c238c3c09 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -18,6 +18,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -50,6 +51,7 @@
/* STM32F7 I2C control 1 */
#define STM32F7_I2C_CR1_PECEN BIT(23)
+#define STM32F7_I2C_CR1_SMBHEN BIT(20)
#define STM32F7_I2C_CR1_WUPEN BIT(18)
#define STM32F7_I2C_CR1_SBCBIT(16)
#define STM32F7_I2C_CR1_RXDMAENBIT(15)
@@ -150,7 +152,7 @@
#define STM32F7_I2C_MAX_LEN0xff
#define STM32F7_I2C_DMA_LEN_MIN0x16
-#define STM32F7_I2C_MAX_SLAVE 0x2
+#define STM32F7_I2C_MAX_SLAVE 0x3
#define STM32F7_I2C_DNF_DEFAULT0
#define STM32F7_I2C_DNF_MAX16
@@ -301,6 +303,8 @@ struct stm32f7_i2c_msg {
* @fmp_creg: register address for clearing Fast Mode Plus bits
* @fmp_mask: mask for Fast Mode Plus bits in set register
* @wakeup_src: boolean to know if the device is a wakeup source
+ * @smbus_mode: states that the controller is configured in SMBus mode
+ * @host_notify_client: SMBus host-notify client
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -327,6 +331,8 @@ struct stm32f7_i2c_dev {
u32 fmp_creg;
u32 fmp_mask;
bool wakeup_src;
+ bool smbus_mode;
+ struct i2c_client *host_notify_client;
};
/*
@@ -1321,10 +1327,18 @@ static int stm32f7_i2c_get_free_slave_id(struct
stm32f7_i2c_dev *i2c_dev,
int i;
/*
-* slave[0] supports 7-bit and 10-bit slave address
-* slave[1] supports 7-bit slave address only
+* slave[0] support only SMBus Host address (0x8)
+* slave[1] supports 7-bit and 10-bit slave address
+* slave[2] supports 7-bit slave address only
*/
- for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
+ if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
+ if (i2c_dev->slave[0])
+ goto fail;
+ *id = 0;
+ return 0;
+ }
+
+ for (i = STM32F7_I2C_MAX_SLAVE - 1; i > 0; i--) {
if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
continue;
if (!i2c_dev->slave[i]) {
@@ -1333,6 +1347,7 @@ static int stm32f7_i2c_get_free_slave_id(struct
stm32f7_i2c_dev *i2c_dev,
}
}
+fail:
dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
return -EINVAL;
@@ -1776,7 +1791,13 @@ static int stm32f7_i2c_reg_slave(struct i2c_client
*slave)
if (!stm32f7_i2c_is_slave_registered(i2c_dev))
stm32f7_i2c_enable_wakeup(i2c_dev, true);
- if (id == 0) {
+ switch (id) {
+ case 0:
+ /* Slave SMBus Host */
+ i2c_dev->slave[id] = slave;
+ break;
+
+ case 1:
/* Configure Own Address 1 */
oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
oar1 &= ~STM32F7_I2C_OAR1_MASK;
@@ -1789,7 +1810,9 @@ static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
oar1 |= STM32F7_I2C_OAR1_OA1EN;
i2c_dev->slave[id] = slave;
writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
- } else if (id == 1) {
+ break;
+
+ case 2:
/* Configure Own Address 2 */
oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
oar2 &= ~STM32F7_I2C_OAR2_MASK;
@@ -1802,7 +1825,10 @@ static int stm32f7_i2c_reg_slave(struct i2c_client
*slave)
oar2 |= STM32F7_I2C_OAR2_OA2EN;
i2c_dev->slave[id] = slave;
writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
- } else {
+
[PATCH] i2c: stm32f7: add SMBus-Alert support
Add support for the SMBus-Alert protocol.
Signed-off-by: Alain Volmat
---
This patch has to be integrated on top of the patch
'i2c: stm32f7: Add SMBus Host-Notify protocol support' since SMBus Alert is
enabled by the DT binding 'smbus' introduced in that patch.
drivers/i2c/busses/i2c-stm32f7.c | 71
1 file changed, 71 insertions(+)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index 223c238c3c09..fe7641da54ef 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -51,6 +51,7 @@
/* STM32F7 I2C control 1 */
#define STM32F7_I2C_CR1_PECEN BIT(23)
+#define STM32F7_I2C_CR1_ALERTENBIT(22)
#define STM32F7_I2C_CR1_SMBHEN BIT(20)
#define STM32F7_I2C_CR1_WUPEN BIT(18)
#define STM32F7_I2C_CR1_SBCBIT(16)
@@ -123,6 +124,7 @@
(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
#define STM32F7_I2C_ISR_DIRBIT(16)
#define STM32F7_I2C_ISR_BUSY BIT(15)
+#define STM32F7_I2C_ISR_ALERT BIT(13)
#define STM32F7_I2C_ISR_PECERR BIT(11)
#define STM32F7_I2C_ISR_ARLO BIT(9)
#define STM32F7_I2C_ISR_BERR BIT(8)
@@ -136,6 +138,7 @@
#define STM32F7_I2C_ISR_TXEBIT(0)
/* STM32F7 I2C Interrupt Clear */
+#define STM32F7_I2C_ICR_ALERTCFBIT(13)
#define STM32F7_I2C_ICR_PECCF BIT(11)
#define STM32F7_I2C_ICR_ARLOCF BIT(9)
#define STM32F7_I2C_ICR_BERRCF BIT(8)
@@ -277,6 +280,17 @@ struct stm32f7_i2c_msg {
};
/**
+ * struct stm32f7_i2c_alert - SMBus alert specific data
+ * @setup: platform data for the smbus_alert i2c client
+ * @ara: I2C slave device used to respond to the SMBus Alert with Alert
+ * Response Address
+ */
+struct stm32f7_i2c_alert {
+ struct i2c_smbus_alert_setup setup;
+ struct i2c_client *ara;
+};
+
+/**
* struct stm32f7_i2c_dev - private data of the controller
* @adap: I2C adapter for this controller
* @dev: device for this controller
@@ -305,6 +319,7 @@ struct stm32f7_i2c_msg {
* @wakeup_src: boolean to know if the device is a wakeup source
* @smbus_mode: states that the controller is configured in SMBus mode
* @host_notify_client: SMBus host-notify client
+ * @alert: SMBus alert specific data
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -333,6 +348,7 @@ struct stm32f7_i2c_dev {
bool wakeup_src;
bool smbus_mode;
struct i2c_client *host_notify_client;
+ struct stm32f7_i2c_alert *alert;
};
/*
@@ -1601,6 +1617,13 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void
*data)
f7_msg->result = -EINVAL;
}
+ if (status & STM32F7_I2C_ISR_ALERT) {
+ dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
+ writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
+ i2c_handle_smbus_alert(i2c_dev->alert->ara);
+ return IRQ_HANDLED;
+ }
+
if (!i2c_dev->slave_running) {
u32 mask;
/* Disable interrupts */
@@ -1967,6 +1990,42 @@ static void stm32f7_i2c_disable_smbus_host(struct
stm32f7_i2c_dev *i2c_dev)
}
}
+static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert;
+ struct i2c_adapter *adap = &i2c_dev->adap;
+ struct device *dev = i2c_dev->dev;
+ void __iomem *base = i2c_dev->base;
+
+ alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
+ if (!alert)
+ return -ENOMEM;
+
+ alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
+ if (IS_ERR(alert->ara))
+ return PTR_ERR(alert->ara);
+
+ i2c_dev->alert = alert;
+
+ /* Enable SMBus Alert */
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
+
+ return 0;
+}
+
+static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert = i2c_dev->alert;
+ void __iomem *base = i2c_dev->base;
+
+ if (alert) {
+ /* Disable SMBus Alert */
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_ALERTEN);
+ i2c_unregister_device(alert->ara);
+ }
+}
+
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
{
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
@@ -2161,6 +2220,14 @@ static int stm32f7_i2c_probe(struct platform_device
*pdev)
ret);
goto i2c_adapter_remove;
}
+
+ ret = stm32f7_i
[PATCH v3 1/2] i2c: smbus: add core function handling SMBus host-notify
SMBus Host-Notify protocol, from the adapter point of view
consist of receiving a message from a client, including the
client address and some other data.
It can be simply handled by creating a new slave device
and registering a callback performing the parsing of the
message received from the client.
This commit introduces two new core functions
* i2c_new_slave_host_notify_device
* i2c_free_slave_host_notify_device
that take care of registration of the new slave device and
callback and will call i2c_handle_smbus_host_notify once a
Host-Notify event is received.
Signed-off-by: Alain Volmat
---
v3: move smbus host-notify slave code into i2c-smbus.c file
rework slave callback index handling
add sanity check in slave free function
v2: identical to v1
drivers/i2c/i2c-smbus.c | 107 ++
include/linux/i2c-smbus.h | 12 ++
2 files changed, 119 insertions(+)
diff --git a/drivers/i2c/i2c-smbus.c b/drivers/i2c/i2c-smbus.c
index dc0108287ccf..d3d06e3b4f3b 100644
--- a/drivers/i2c/i2c-smbus.c
+++ b/drivers/i2c/i2c-smbus.c
@@ -197,6 +197,113 @@ EXPORT_SYMBOL_GPL(i2c_handle_smbus_alert);
module_i2c_driver(smbalert_driver);
+#if IS_ENABLED(CONFIG_I2C_SLAVE)
+#define SMBUS_HOST_NOTIFY_LEN 3
+struct i2c_slave_host_notify_status {
+ u8 index;
+ u8 addr;
+};
+
+static int i2c_slave_host_notify_cb(struct i2c_client *client,
+ enum i2c_slave_event event, u8 *val)
+{
+ struct i2c_slave_host_notify_status *status = client->dev.platform_data;
+
+ switch (event) {
+ case I2C_SLAVE_WRITE_RECEIVED:
+ /* We only retrieve the first byte received (addr)
+* since there is currently no support to retrieve the data
+* parameter from the client.
+*/
+ if (status->index == 0)
+ status->addr = *val;
+ if (status->index < U8_MAX)
+ status->index++;
+ break;
+ case I2C_SLAVE_STOP:
+ if (status->index == SMBUS_HOST_NOTIFY_LEN)
+ i2c_handle_smbus_host_notify(client->adapter,
+status->addr);
+ fallthrough;
+ case I2C_SLAVE_WRITE_REQUESTED:
+ status->index = 0;
+ break;
+ case I2C_SLAVE_READ_REQUESTED:
+ case I2C_SLAVE_READ_PROCESSED:
+ *val = 0xff;
+ break;
+ }
+
+ return 0;
+}
+
+/**
+ * i2c_new_slave_host_notify_device - get a client for SMBus host-notify
support
+ * @adapter: the target adapter
+ * Context: can sleep
+ *
+ * Setup handling of the SMBus host-notify protocol on a given I2C bus segment.
+ *
+ * Handling is done by creating a device and its callback and handling data
+ * received via the SMBus host-notify address (0x8)
+ *
+ * This returns the client, which should be ultimately freed using
+ * i2c_free_slave_host_notify_device(); or an ERRPTR to indicate an error.
+ */
+struct i2c_client *i2c_new_slave_host_notify_device(struct i2c_adapter
*adapter)
+{
+ struct i2c_board_info host_notify_board_info = {
+ I2C_BOARD_INFO("smbus_host_notify", 0x08),
+ .flags = I2C_CLIENT_SLAVE,
+ };
+ struct i2c_slave_host_notify_status *status;
+ struct i2c_client *client;
+ int ret;
+
+ status = kzalloc(sizeof(struct i2c_slave_host_notify_status),
+GFP_KERNEL);
+ if (!status)
+ return ERR_PTR(-ENOMEM);
+
+ host_notify_board_info.platform_data = status;
+
+ client = i2c_new_client_device(adapter, &host_notify_board_info);
+ if (IS_ERR(client)) {
+ kfree(status);
+ return client;
+ }
+
+ ret = i2c_slave_register(client, i2c_slave_host_notify_cb);
+ if (ret) {
+ i2c_unregister_device(client);
+ kfree(status);
+ return ERR_PTR(ret);
+ }
+
+ return client;
+}
+EXPORT_SYMBOL_GPL(i2c_new_slave_host_notify_device);
+
+/**
+ * i2c_free_slave_host_notify_device - free the client for SMBus host-notify
+ * support
+ * @client: the client to free
+ * Context: can sleep
+ *
+ * Free the i2c_client allocated via i2c_new_slave_host_notify_device
+ */
+void i2c_free_slave_host_notify_device(struct i2c_client *client)
+{
+ if (IS_ERR_OR_NULL(client))
+ return;
+
+ i2c_slave_unregister(client);
+ kfree(client->dev.platform_data);
+ i2c_unregister_device(client);
+}
+EXPORT_SYMBOL_GPL(i2c_free_slave_host_notify_device);
+#endif
+
/*
* SPD is not part of SMBus but we include it here for convenience as the
* target systems are the same.
diff --git a/include/linux/i2c-smbus.h b/include/linux/i2c-smbus.h
index 1e4e0de4ef8b..1ef421818d3a 100644
--- a/include/linux/i2c-smbus.h
[PATCH v3 0/2] i2c: stm32: add host-notify support via i2c slave
This serie replaces the previous 'stm32-f7: Addition of SMBus Alert / Host-notify features' serie to only focus on the SMBus Host-Notify feature. It should be applied with "[PATCH] i2c: add binding to mark a bus as SMBus" from Wolfram which defines the newly introduced "smbus" binding. Alain Volmat (2): i2c: smbus: add core function handling SMBus host-notify i2c: stm32f7: Add SMBus Host-Notify protocol support drivers/i2c/busses/Kconfig | 1 + drivers/i2c/busses/i2c-stm32f7.c | 110 +-- drivers/i2c/i2c-smbus.c | 107 + include/linux/i2c-smbus.h| 12 + 4 files changed, 215 insertions(+), 15 deletions(-) -- v3: move smbus host-notify slave code into i2c-smbus.c file rework slave callback index handling add sanity check in slave free function v2: fix a bad test within the i2c-stm32f7 driver leading to decrease of available slave slot
[PATCH 0/5] spi: stm32: various driver fixes
This serie is a reduced version of the serie [spi: stm32: various driver enhancements] previously sent. Alain Volmat (1): spi: stm32: always perform registers configuration prior to transfer Amelie Delaunay (3): spi: stm32: fix fifo threshold level in case of short transfer spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate spi: stm32: fixes suspend/resume management Antonio Borneo (1): spi: stm32h7: fix race condition at end of transfer drivers/spi/spi-stm32.c | 95 ++--- 1 file changed, 58 insertions(+), 37 deletions(-)
[PATCH 5/5] spi: stm32: always perform registers configuration prior to transfer
SPI registers content may have been lost upon suspend/resume sequence.
So, always compute and apply the necessary configuration in
stm32_spi_transfer_one_setup routine.
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 42 +-
1 file changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index e196dbc5c432..7968d23347b6 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1594,41 +1594,33 @@ static int stm32_spi_transfer_one_setup(struct
stm32_spi *spi,
unsigned long flags;
unsigned int comm_type;
int nb_words, ret = 0;
+ int mbr;
spin_lock_irqsave(&spi->lock, flags);
spi->cur_xferlen = transfer->len;
- if (spi->cur_bpw != transfer->bits_per_word) {
- spi->cur_bpw = transfer->bits_per_word;
- spi->cfg->set_bpw(spi);
- }
-
- if (spi->cur_speed != transfer->speed_hz) {
- int mbr;
-
- /* Update spi->cur_speed with real clock speed */
- mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
- spi->cfg->baud_rate_div_min,
- spi->cfg->baud_rate_div_max);
- if (mbr < 0) {
- ret = mbr;
- goto out;
- }
+ spi->cur_bpw = transfer->bits_per_word;
+ spi->cfg->set_bpw(spi);
- transfer->speed_hz = spi->cur_speed;
- stm32_spi_set_mbr(spi, mbr);
+ /* Update spi->cur_speed with real clock speed */
+ mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
+ spi->cfg->baud_rate_div_min,
+ spi->cfg->baud_rate_div_max);
+ if (mbr < 0) {
+ ret = mbr;
+ goto out;
}
- comm_type = stm32_spi_communication_type(spi_dev, transfer);
- if (spi->cur_comm != comm_type) {
- ret = spi->cfg->set_mode(spi, comm_type);
+ transfer->speed_hz = spi->cur_speed;
+ stm32_spi_set_mbr(spi, mbr);
- if (ret < 0)
- goto out;
+ comm_type = stm32_spi_communication_type(spi_dev, transfer);
+ ret = spi->cfg->set_mode(spi, comm_type);
+ if (ret < 0)
+ goto out;
- spi->cur_comm = comm_type;
- }
+ spi->cur_comm = comm_type;
if (spi->cfg->set_data_idleness)
spi->cfg->set_data_idleness(spi, transfer->len);
--
2.7.4
[PATCH 4/5] spi: stm32: fixes suspend/resume management
From: Amelie Delaunay
This patch adds pinctrl power management, and reconfigure spi controller
in case of resume.
Fixes: 038ac869c9d2 ("spi: stm32: add runtime PM support")
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index bdd4e70c3f10..e196dbc5c432 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2004,6 +2005,8 @@ static int stm32_spi_remove(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
+ pinctrl_pm_select_sleep_state(&pdev->dev);
+
return 0;
}
@@ -2015,13 +2018,18 @@ static int stm32_spi_runtime_suspend(struct device *dev)
clk_disable_unprepare(spi->clk);
- return 0;
+ return pinctrl_pm_select_sleep_state(dev);
}
static int stm32_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct stm32_spi *spi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret)
+ return ret;
return clk_prepare_enable(spi->clk);
}
@@ -2051,10 +2059,23 @@ static int stm32_spi_resume(struct device *dev)
return ret;
ret = spi_master_resume(master);
- if (ret)
+ if (ret) {
clk_disable_unprepare(spi->clk);
+ return ret;
+ }
- return ret;
+ ret = pm_runtime_get_sync(dev);
+ if (ret) {
+ dev_err(dev, "Unable to power device:%d\n", ret);
+ return ret;
+ }
+
+ spi->cfg->config(spi);
+
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ return 0;
}
#endif
--
2.7.4
[PATCH 3/5] spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate
From: Amelie Delaunay
Fix spi->clk_rate when it is odd to the nearest lowest even value because
minimum SPI divider is 2.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 005bc16bdf2a..bdd4e70c3f10 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -441,7 +441,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32
speed_hz,
{
u32 div, mbrdiv;
- div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
+ /* Ensure spi->clk_rate is even */
+ div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
/*
* SPI framework set xfer->speed_hz to master->max_speed_hz if
--
2.7.4
[PATCH 2/5] spi: stm32: fix fifo threshold level in case of short transfer
From: Amelie Delaunay
When transfer is shorter than half of the fifo, set the data packet size
up to transfer size instead of up to half of the fifo.
Check also that threshold is set at least to 1 data frame.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 814a3ec3b8ad..005bc16bdf2a 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -467,20 +467,24 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi,
u32 speed_hz,
/**
* stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
* @spi: pointer to the spi controller data structure
+ * @xfer_len: length of the message to be transferred
*/
-static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
+static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
{
- u32 fthlv, half_fifo;
+ u32 fthlv, half_fifo, packet;
/* data packet should not exceed 1/2 of fifo space */
half_fifo = (spi->fifo_size / 2);
+ /* data_packet should not exceed transfer length */
+ packet = (half_fifo > xfer_len) ? xfer_len : half_fifo;
+
if (spi->cur_bpw <= 8)
- fthlv = half_fifo;
+ fthlv = packet;
else if (spi->cur_bpw <= 16)
- fthlv = half_fifo / 2;
+ fthlv = packet / 2;
else
- fthlv = half_fifo / 4;
+ fthlv = packet / 4;
/* align packet size with data registers access */
if (spi->cur_bpw > 8)
@@ -488,6 +492,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
else
fthlv -= (fthlv % 4); /* multiple of 4 */
+ if (!fthlv)
+ fthlv = 1;
+
return fthlv;
}
@@ -1393,7 +1400,7 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
STM32H7_SPI_CFG1_DSIZE;
- spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
+ spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
@@ -1588,6 +1595,8 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi
*spi,
spin_lock_irqsave(&spi->lock, flags);
+ spi->cur_xferlen = transfer->len;
+
if (spi->cur_bpw != transfer->bits_per_word) {
spi->cur_bpw = transfer->bits_per_word;
spi->cfg->set_bpw(spi);
@@ -1635,8 +1644,6 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi
*spi,
goto out;
}
- spi->cur_xferlen = transfer->len;
-
dev_dbg(spi->dev, "transfer communication mode set to %d\n",
spi->cur_comm);
dev_dbg(spi->dev,
--
2.7.4
[PATCH 1/5] spi: stm32h7: fix race condition at end of transfer
From: Antonio Borneo
The caller of stm32_spi_transfer_one(), spi_transfer_one_message(),
is waiting for us to call spi_finalize_current_transfer() and will
eventually schedule a new transfer, if available.
We should guarantee that the spi controller is really available
before calling spi_finalize_current_transfer().
Move the call to spi_finalize_current_transfer() _after_ the call
to stm32_spi_disable().
Signed-off-by: Antonio Borneo
Signed-off-by: Alain Volmat
---
drivers/spi/spi-stm32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 4a21feae0103..814a3ec3b8ad 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -971,8 +971,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
spin_unlock_irqrestore(&spi->lock, flags);
if (end) {
- spi_finalize_current_transfer(master);
stm32h7_spi_disable(spi);
+ spi_finalize_current_transfer(master);
}
return IRQ_HANDLED;
--
2.7.4
Re: [PATCH 02/18] spi: stm32-spi: defer probe for reset
On Wed, Aug 05, 2020 at 11:49:06AM +0100, Mark Brown wrote:
> On Wed, Aug 05, 2020 at 09:01:57AM +0200, Alain Volmat wrote:
>
> > - rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
> > - if (!IS_ERR(rst)) {
> > + rst = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL);
> > + if (rst) {
> > + if (IS_ERR(rst)) {
> > + ret = PTR_ERR(rst);
> > + if (ret != -EPROBE_DEFER)
> > + dev_err(&pdev->dev, "reset get failed: %d\n",
> > + ret);
> > + goto err_clk_disable;
> > + }
>
> This will not provide any diagnostics when deferring which isn't very
> helpful if there's issues.
Do you mean that a message when deferring would be needed ?
I am worrying that this would lead to having too much noise during boot
since probe deferring is kinda common. Of course it can also be due to a bad
configuration of the kernel as well but having looked around I think that
usually driver are rather silent in case of deferring.
[PATCH v2 4/5] spi: stm32: fixes suspend/resume management
From: Amelie Delaunay
This patch adds pinctrl power management, and reconfigure spi controller
in case of resume.
Fixes: 038ac869c9d2 ("spi: stm32: add runtime PM support")
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 27 ---
1 file changed, 24 insertions(+), 3 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 571dea72bf7e..9b90a22543fd 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -13,6 +13,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -2007,6 +2008,8 @@ static int stm32_spi_remove(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
+ pinctrl_pm_select_sleep_state(&pdev->dev);
+
return 0;
}
@@ -2018,13 +2021,18 @@ static int stm32_spi_runtime_suspend(struct device *dev)
clk_disable_unprepare(spi->clk);
- return 0;
+ return pinctrl_pm_select_sleep_state(dev);
}
static int stm32_spi_runtime_resume(struct device *dev)
{
struct spi_master *master = dev_get_drvdata(dev);
struct stm32_spi *spi = spi_master_get_devdata(master);
+ int ret;
+
+ ret = pinctrl_pm_select_default_state(dev);
+ if (ret)
+ return ret;
return clk_prepare_enable(spi->clk);
}
@@ -2054,10 +2062,23 @@ static int stm32_spi_resume(struct device *dev)
return ret;
ret = spi_master_resume(master);
- if (ret)
+ if (ret) {
clk_disable_unprepare(spi->clk);
+ return ret;
+ }
- return ret;
+ ret = pm_runtime_get_sync(dev);
+ if (ret) {
+ dev_err(dev, "Unable to power device:%d\n", ret);
+ return ret;
+ }
+
+ spi->cfg->config(spi);
+
+ pm_runtime_mark_last_busy(dev);
+ pm_runtime_put_autosuspend(dev);
+
+ return 0;
}
#endif
--
2.7.4
[PATCH v2 1/5] spi: stm32h7: fix race condition at end of transfer
From: Antonio Borneo
The caller of stm32_spi_transfer_one(), spi_transfer_one_message(),
is waiting for us to call spi_finalize_current_transfer() and will
eventually schedule a new transfer, if available.
We should guarantee that the spi controller is really available
before calling spi_finalize_current_transfer().
Move the call to spi_finalize_current_transfer() _after_ the call
to stm32_spi_disable().
Signed-off-by: Antonio Borneo
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 4a21feae0103..814a3ec3b8ad 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -971,8 +971,8 @@ static irqreturn_t stm32h7_spi_irq_thread(int irq, void
*dev_id)
spin_unlock_irqrestore(&spi->lock, flags);
if (end) {
- spi_finalize_current_transfer(master);
stm32h7_spi_disable(spi);
+ spi_finalize_current_transfer(master);
}
return IRQ_HANDLED;
--
2.7.4
[PATCH v2 5/5] spi: stm32: always perform registers configuration prior to transfer
SPI registers content may have been lost upon suspend/resume sequence.
So, always compute and apply the necessary configuration in
stm32_spi_transfer_one_setup routine.
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 42 +-
1 file changed, 17 insertions(+), 25 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 9b90a22543fd..d4b33b358a31 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -1597,41 +1597,33 @@ static int stm32_spi_transfer_one_setup(struct
stm32_spi *spi,
unsigned long flags;
unsigned int comm_type;
int nb_words, ret = 0;
+ int mbr;
spin_lock_irqsave(&spi->lock, flags);
spi->cur_xferlen = transfer->len;
- if (spi->cur_bpw != transfer->bits_per_word) {
- spi->cur_bpw = transfer->bits_per_word;
- spi->cfg->set_bpw(spi);
- }
-
- if (spi->cur_speed != transfer->speed_hz) {
- int mbr;
-
- /* Update spi->cur_speed with real clock speed */
- mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
- spi->cfg->baud_rate_div_min,
- spi->cfg->baud_rate_div_max);
- if (mbr < 0) {
- ret = mbr;
- goto out;
- }
+ spi->cur_bpw = transfer->bits_per_word;
+ spi->cfg->set_bpw(spi);
- transfer->speed_hz = spi->cur_speed;
- stm32_spi_set_mbr(spi, mbr);
+ /* Update spi->cur_speed with real clock speed */
+ mbr = stm32_spi_prepare_mbr(spi, transfer->speed_hz,
+ spi->cfg->baud_rate_div_min,
+ spi->cfg->baud_rate_div_max);
+ if (mbr < 0) {
+ ret = mbr;
+ goto out;
}
- comm_type = stm32_spi_communication_type(spi_dev, transfer);
- if (spi->cur_comm != comm_type) {
- ret = spi->cfg->set_mode(spi, comm_type);
+ transfer->speed_hz = spi->cur_speed;
+ stm32_spi_set_mbr(spi, mbr);
- if (ret < 0)
- goto out;
+ comm_type = stm32_spi_communication_type(spi_dev, transfer);
+ ret = spi->cfg->set_mode(spi, comm_type);
+ if (ret < 0)
+ goto out;
- spi->cur_comm = comm_type;
- }
+ spi->cur_comm = comm_type;
if (spi->cfg->set_data_idleness)
spi->cfg->set_data_idleness(spi, transfer->len);
--
2.7.4
[PATCH v2 2/5] spi: stm32: fix fifo threshold level in case of short transfer
From: Amelie Delaunay
When transfer is shorter than half of the fifo, set the data packet size
up to transfer size instead of up to half of the fifo.
Check also that threshold is set at least to 1 data frame.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: fix conditional statement
drivers/spi/spi-stm32.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index 814a3ec3b8ad..e5450233f3f8 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -467,20 +467,27 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi,
u32 speed_hz,
/**
* stm32h7_spi_prepare_fthlv - Determine FIFO threshold level
* @spi: pointer to the spi controller data structure
+ * @xfer_len: length of the message to be transferred
*/
-static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
+static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi, u32 xfer_len)
{
- u32 fthlv, half_fifo;
+ u32 fthlv, half_fifo, packet;
/* data packet should not exceed 1/2 of fifo space */
half_fifo = (spi->fifo_size / 2);
+ /* data_packet should not exceed transfer length */
+ if (half_fifo > xfer_len)
+ packet = xfer_len;
+ else
+ packet = half_fifo;
+
if (spi->cur_bpw <= 8)
- fthlv = half_fifo;
+ fthlv = packet;
else if (spi->cur_bpw <= 16)
- fthlv = half_fifo / 2;
+ fthlv = packet / 2;
else
- fthlv = half_fifo / 4;
+ fthlv = packet / 4;
/* align packet size with data registers access */
if (spi->cur_bpw > 8)
@@ -488,6 +495,9 @@ static u32 stm32h7_spi_prepare_fthlv(struct stm32_spi *spi)
else
fthlv -= (fthlv % 4); /* multiple of 4 */
+ if (!fthlv)
+ fthlv = 1;
+
return fthlv;
}
@@ -1393,7 +1403,7 @@ static void stm32h7_spi_set_bpw(struct stm32_spi *spi)
cfg1_setb |= (bpw << STM32H7_SPI_CFG1_DSIZE_SHIFT) &
STM32H7_SPI_CFG1_DSIZE;
- spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi);
+ spi->cur_fthlv = stm32h7_spi_prepare_fthlv(spi, spi->cur_xferlen);
fthlv = spi->cur_fthlv - 1;
cfg1_clrb |= STM32H7_SPI_CFG1_FTHLV;
@@ -1588,6 +1598,8 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi
*spi,
spin_lock_irqsave(&spi->lock, flags);
+ spi->cur_xferlen = transfer->len;
+
if (spi->cur_bpw != transfer->bits_per_word) {
spi->cur_bpw = transfer->bits_per_word;
spi->cfg->set_bpw(spi);
@@ -1635,8 +1647,6 @@ static int stm32_spi_transfer_one_setup(struct stm32_spi
*spi,
goto out;
}
- spi->cur_xferlen = transfer->len;
-
dev_dbg(spi->dev, "transfer communication mode set to %d\n",
spi->cur_comm);
dev_dbg(spi->dev,
--
2.7.4
[PATCH v2 0/5] spi: stm32: various driver fixes
This serie is a reduced version of the serie [spi: stm32: various driver enhancements] previously sent. Alain Volmat (1): spi: stm32: always perform registers configuration prior to transfer Amelie Delaunay (3): spi: stm32: fix fifo threshold level in case of short transfer spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate spi: stm32: fixes suspend/resume management Antonio Borneo (1): spi: stm32h7: fix race condition at end of transfer drivers/spi/spi-stm32.c | 98 ++--- 1 file changed, 61 insertions(+), 37 deletions(-) -- v2: fix conditional statement within [spi: stm32: fix fifo threshold level in case of short transfer]
[PATCH v2 3/5] spi: stm32: fix stm32_spi_prepare_mbr in case of odd clk_rate
From: Amelie Delaunay
Fix spi->clk_rate when it is odd to the nearest lowest even value because
minimum SPI divider is 2.
Signed-off-by: Amelie Delaunay
Signed-off-by: Alain Volmat
---
v2: identical to v1
drivers/spi/spi-stm32.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/spi-stm32.c b/drivers/spi/spi-stm32.c
index e5450233f3f8..571dea72bf7e 100644
--- a/drivers/spi/spi-stm32.c
+++ b/drivers/spi/spi-stm32.c
@@ -441,7 +441,8 @@ static int stm32_spi_prepare_mbr(struct stm32_spi *spi, u32
speed_hz,
{
u32 div, mbrdiv;
- div = DIV_ROUND_UP(spi->clk_rate, speed_hz);
+ /* Ensure spi->clk_rate is even */
+ div = DIV_ROUND_UP(spi->clk_rate & ~0x1, speed_hz);
/*
* SPI framework set xfer->speed_hz to master->max_speed_hz if
--
2.7.4
[PATCH v2 00/16] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. This serie also contains modifications within STi DTS in order to use the newly introduced compatible and remove clock-output-names properties. Alain Volmat (16): clk: st: clkgen-pll: remove used variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible ARM: dts: sti: update flexgen compatible within stih418-clock ARM: dts: sti: update flexgen compatible within stih407-clock ARM: dts: sti: update flexgen compatible within stih410-clock ARM: dts: sti: update clkgen-pll entries in stih407-clock ARM: dts: sti: update clkgen-pll entries in stih410-clock ARM: dts: sti: update clkgen-pll entries in stih418-clock ARM: dts: sti: update clkgen-fsyn entries in stih407-clock ARM: dts: sti: update clkgen-fsyn entries in stih410-clock ARM: dts: sti: update clkgen-fsyn entries in stih418-clock .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + arch/arm/boot/dts/stih407-clock.dtsi | 128 +-- arch/arm/boot/dts/stih410-clock.dtsi | 138 +-- arch/arm/boot/dts/stih418-clock.dtsi | 136 +-- drivers/clk/st/clk-flexgen.c | 344 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 9 files changed, 588 insertions(+), 408 deletions(-) --- v2: fix drivers to update some clocks as CLK_IS_CRITICAL -- 2.17.1
[PATCH v2 01/16] clk: st: clkgen-pll: remove used variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v2 02/16] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: add some missing clock as CLK_IS_CRITICAL
drivers/clk/st/clk-flexgen.c | 344 +--
1 file changed, 330 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..24dd0c7dc6c3 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,267 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = &qu
[PATCH v2 03/16] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH v2 04/16] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: clk-s-a0-pll-odf-0 don't need to be CLK_IS_CRITICAL
mark several clock as CLK_IS_CRITICAL
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..8c6215b3c808 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= &stm_pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, &pll_flags);
- clk = clkgen_pll_
[PATCH v2 05/16] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH v2 08/16] ARM: dts: sti: update flexgen compatible within stih418-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 96 ++--
1 file changed, 5 insertions(+), 91 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 8fa092462102..35d12979cdf4 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
};
};
@@ -132,7 +129,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih418-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -142,49 +139,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-icn-reg",
-"clk-proc-bdisp-0",
-"clk-proc-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phyref",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hevc",
-"clk-clust-hevc",
-"clk-hwpe-hevc",
-"clk-fc-hevc",
-
[PATCH v2 07/16] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH v2 10/16] ARM: dts: sti: update flexgen compatible within stih410-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 95 ++--
1 file changed, 6 insertions(+), 89 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 81a8c25d7ba5..04b0d7080353 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -83,16 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
- clock-critical = ;
};
};
@@ -135,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -145,52 +141,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hades",
-"clk-clust-hades",
-"clk-hwpe-hades",
-&quo
[PATCH v2 06/16] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: clk-s-c0-fs0-ch0 do not need to be CLK_IS_CRITICAL
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..164285d6be97 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, &clk_name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+
[PATCH v2 09/16] ARM: dts: sti: update flexgen compatible within stih407-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 85 ++--
1 file changed, 6 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 1ab40db7c91a..ecd568777e5f 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = ;
};
};
@@ -134,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -144,45 +141,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp";
- clock-critical = ,
-,
-,
-,
-,
-;
-
/*
* ARM Peripheral clock for timers
*/
@@ -219,18 +177,13 @@
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
-
[PATCH v2 11/16] ARM: dts: sti: update clkgen-pll entries in stih407-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index ecd568777e5f..2603226a6ca8 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -36,8 +36,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v2 12/16] ARM: dts: sti: update clkgen-pll entries in stih410-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 04b0d7080353..3aeabdd6e305 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v2 14/16] ARM: dts: sti: update clkgen-fsyn entries in stih407-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 2603226a6ca8..9cce9541e26b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v2 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih418-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -75,11 +73,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH v2 15/16] ARM: dts: sti: update clkgen-fsyn entries in stih410-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 3aeabdd6e305..6b0e6d4477a3 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH v2 16/16] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index d628e656458d..e84c476b83ed 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -94,11 +94,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +145,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +169,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +195,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
Re: [PATCH] i2c-stm32f4: Mundane typo fix
On Wed, Mar 24, 2021 at 07:36:10PM +0530, Bhaskar Chowdhury wrote: > > s/postion/position/ > > Signed-off-by: Bhaskar Chowdhury > --- > drivers/i2c/busses/i2c-stm32f4.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/i2c/busses/i2c-stm32f4.c > b/drivers/i2c/busses/i2c-stm32f4.c > index 937c2c8fd349..4933fc8ce3fd 100644 > --- a/drivers/i2c/busses/i2c-stm32f4.c > +++ b/drivers/i2c/busses/i2c-stm32f4.c > @@ -534,7 +534,7 @@ static void stm32f4_i2c_handle_rx_addr(struct > stm32f4_i2c_dev *i2c_dev) > default: > /* >* N-byte reception: > - * Enable ACK, reset POS (ACK postion) and clear ADDR flag. > + * Enable ACK, reset POS (ACK position) and clear ADDR flag. >* In that way, ACK will be sent as soon as the current byte >* will be received in the shift register >*/ Reviewed-by: Alain Volmat > -- > 2.30.1 >
[PATCH v3 0/7] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. This serie also contains modifications within STi DTS in order to use the newly introduced compatible and remove clock-output-names properties. Alain Volmat (7): clk: st: clkgen-pll: remove used variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + drivers/clk/st/clk-flexgen.c | 366 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 6 files changed, 575 insertions(+), 41 deletions(-) --- v3: - removal some useless CLK_IS_CRITICAL and add some comments - only keep clk drivers/binding patches within the serie v2: fix drivers to update some clocks as CLK_IS_CRITICAL -- 2.17.1
[PATCH v3 2/7] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v3: add comments about CLK_IS_CRITICAL reason
don't put clk-proc-stfe as CLK_IS_CRITICAL
v2: add some missing clock as CLK_IS_CRITICAL
drivers/clk/st/clk-flexgen.c | 366 +--
1 file changed, 352 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..69711c6c47a4 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,289 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ /* This clk needs to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ /* Those clks need to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ /* This clk needs to be on to keep A9 running */
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ /* This c
[PATCH v3 1/7] clk: st: clkgen-pll: remove unused variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
---
v3: s/used/unused within the subject
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v3 6/7] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v2: clk-s-c0-fs0-ch0 do not need to be CLK_IS_CRITICAL
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..164285d6be97 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, &clk_name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+
[PATCH v3 5/7] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH v3 7/7] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH v3 3/7] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH v3 4/7] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
v3: avoid CLK_IS_CRITICAL. PLL are enabled whenever necessary thanks to
child clock
v2: clk-s-a0-pll-odf-0 don't need to be CLK_IS_CRITICAL
mark several clock as CLK_IS_CRITICAL
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..b36e4d803636 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= &stm_pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, &pll_flags);
- clk = clkgen_pll_register(paren
[PATCH 00/16] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. This serie also contains modifications within STi DTS in order to use the newly introduced compatible and remove clock-output-names properties. Alain Volmat (16): clk: st: clkgen-pll: remove used variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible ARM: dts: sti: update flexgen compatible within stih418-clock ARM: dts: sti: update flexgen compatible within stih407-clock ARM: dts: sti: update flexgen compatible within stih410-clock ARM: dts: sti: update clkgen-pll entries in stih407-clock ARM: dts: sti: update clkgen-pll entries in stih410-clock ARM: dts: sti: update clkgen-pll entries in stih418-clock ARM: dts: sti: update clkgen-fsyn entries in stih407-clock ARM: dts: sti: update clkgen-fsyn entries in stih410-clock ARM: dts: sti: update clkgen-fsyn entries in stih418-clock .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + arch/arm/boot/dts/stih407-clock.dtsi | 128 +-- arch/arm/boot/dts/stih410-clock.dtsi | 138 +-- arch/arm/boot/dts/stih418-clock.dtsi | 136 +-- drivers/clk/st/clk-flexgen.c | 344 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 9 files changed, 588 insertions(+), 408 deletions(-) -- 2.17.1
[PATCH 01/16] clk: st: clkgen-pll: remove used variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH 07/16] dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible
New compatible are added, supporting various kind of clkgen-fsyn used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,quadfs.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt index d93d49342e60..c4ba2adb0b4f 100644 --- a/Documentation/devicetree/bindings/clock/st/st,quadfs.txt +++ b/Documentation/devicetree/bindings/clock/st/st,quadfs.txt @@ -12,6 +12,9 @@ This binding uses the common clock binding[1]. Required properties: - compatible : shall be: "st,quadfs" + "st,quadfs-d0" + "st,quadfs-d2" + "st,quadfs-d3" "st,quadfs-pll" -- 2.17.1
[PATCH 05/16] dt-bindings: clock: st: clkgen-pll: add new introduced compatible
New compatible are added, supporting various kind of clkgen-pll used for STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt index f207053e0550..d0fa1e02d06d 100644 --- a/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt +++ b/Documentation/devicetree/bindings/clock/st/st,clkgen-pll.txt @@ -10,7 +10,10 @@ Required properties: - compatible : shall be: "st,clkgen-pll0" + "st,clkgen-pll0-a0" + "st,clkgen-pll0-c0" "st,clkgen-pll1" + "st,clkgen-pll1-c0" "st,stih407-clkgen-plla9" "st,stih418-clkgen-plla9" -- 2.17.1
[PATCH 04/16] clk: st: clkgen-pll: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-pll.c | 120 +++-
1 file changed, 106 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index f6c56ca90c7d..68863f79e1b5 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -57,6 +57,17 @@ struct clkgen_pll_data {
const struct clk_ops *ops;
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_pll_data_clks {
+ struct clkgen_pll_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
+
static const struct clk_ops stm_pll3200c32_ops;
static const struct clk_ops stm_pll3200c32_a9_ops;
static const struct clk_ops stm_pll4600c28_ops;
@@ -74,6 +85,28 @@ static const struct clkgen_pll_data st_pll3200c32_cx_0 = {
.ops= &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_0_legacy_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_ax_0_clks[] = {
+ { .name = "clk-s-a0-pll-odf-0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_a0_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_ax_0_clks,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_0_clks[] = {
+ { .name = "clk-s-c0-pll0-odf-0",.flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c0_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_0,
+ .outputs= st_pll3200c32_cx_0_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
/* 407 C0 PLL1 */
.pdn_status = CLKGEN_FIELD(0x2c8, 0x1,8),
@@ -87,6 +120,19 @@ static const struct clkgen_pll_data st_pll3200c32_cx_1 = {
.ops= &stm_pll3200c32_ops,
};
+static const struct clkgen_pll_data_clks st_pll3200c32_cx_1_legacy_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
+};
+
+static const struct clkgen_clk_out st_pll3200c32_cx_1_clks[] = {
+ { .name = "clk-s-c0-pll1-odf-0",},
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_c1_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_cx_1,
+ .outputs= st_pll3200c32_cx_1_clks,
+};
+
static const struct clkgen_pll_data st_pll3200c32_407_a9 = {
/* 407 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -104,6 +150,15 @@ static const struct clkgen_pll_data st_pll3200c32_407_a9 =
{
.ops= &stm_pll3200c32_a9_ops,
};
+static const struct clkgen_clk_out st_pll3200c32_407_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll3200c32_407_a9_data = {
+ .data = (struct clkgen_pll_data *)&st_pll3200c32_407_a9,
+ .outputs= st_pll3200c32_407_a9_clks,
+};
+
static struct clkgen_pll_data st_pll4600c28_418_a9 = {
/* 418 A9 */
.pdn_status = CLKGEN_FIELD(0x1a8, 0x1,0),
@@ -120,6 +175,15 @@ static struct clkgen_pll_data st_pll4600c28_418_a9 = {
.ops= &stm_pll4600c28_ops,
};
+static const struct clkgen_clk_out st_pll4600c28_418_a9_clks[] = {
+ { .name = "clockgen-a9-pll-odf", },
+};
+
+static const struct clkgen_pll_data_clks st_pll4600c28_418_a9_data = {
+ .data = (struct clkgen_pll_data *)&st_pll4600c28_418_a9,
+ .outputs= st_pll4600c28_418_a9_clks,
+};
+
/**
* DOC: Clock Generated by PLL, rate set and enabled by bootloader
*
@@ -684,7 +748,7 @@ static struct clk * __init clkgen_odf_register(const char
*parent_name,
static void __init clkgen_c32_pll_setup(struct device_node *np,
- struct clkgen_pll_data *data)
+ struct clkgen_pll_data_clks *datac)
{
struct clk *clk;
const char *parent_name, *pll_name;
@@ -704,14 +768,14 @@ static void __init clkgen_c32_pll_setup(struct
device_node *np,
of_clk_detect_critical(np, 0, &pll_flags);
- clk = clkgen_pll_register(parent_name, data, pll_base, pll_flags,
- np->name, data->lock);
+ clk = clkgen_pll_registe
[PATCH 08/16] ARM: dts: sti: update flexgen compatible within stih418-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 96 ++--
1 file changed, 5 insertions(+), 91 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 8fa092462102..35d12979cdf4 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
};
};
@@ -132,7 +129,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih418-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -142,49 +139,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-icn-reg",
-"clk-proc-bdisp-0",
-"clk-proc-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phyref",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hevc",
-"clk-clust-hevc",
-"clk-hwpe-hevc",
-"clk-fc-hevc",
-
[PATCH 02/16] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clk-flexgen.c | 344 +--
1 file changed, 330 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..b2a205d014dc 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,267 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ { .name = "clk-icn-lmi", .f
[PATCH 06/16] clk: st: clkgen-fsyn: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
---
drivers/clk/st/clkgen-fsyn.c | 113 +++
1 file changed, 101 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/st/clkgen-fsyn.c b/drivers/clk/st/clkgen-fsyn.c
index dd6062e043e0..c44a59ba4d85 100644
--- a/drivers/clk/st/clkgen-fsyn.c
+++ b/drivers/clk/st/clkgen-fsyn.c
@@ -66,6 +66,16 @@ struct clkgen_quadfs_data {
unsigned long *);
};
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
+struct clkgen_quadfs_data_clks {
+ struct clkgen_quadfs_data *data;
+ const struct clkgen_clk_out *outputs;
+};
+
static const struct clk_ops st_quadfs_pll_c32_ops;
static int clk_fs660c32_dig_get_params(unsigned long input,
@@ -115,6 +125,18 @@ static const struct clkgen_quadfs_data st_fs660c32_C = {
.get_rate = clk_fs660c32_dig_get_rate,
};
+static const struct clkgen_clk_out st_fs660c32_C_clks[] = {
+ { .name = "clk-s-c0-fs0-ch0", .flags = CLK_IS_CRITICAL, },
+ { .name = "clk-s-c0-fs0-ch1", },
+ { .name = "clk-s-c0-fs0-ch2", },
+ { .name = "clk-s-c0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_C_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_C,
+ .outputs= st_fs660c32_C_clks,
+};
+
static const struct clkgen_quadfs_data st_fs660c32_D = {
.nrst_present = true,
.nrst = { CLKGEN_FIELD(0x2a0, 0x1, 0),
@@ -156,6 +178,46 @@ static const struct clkgen_quadfs_data st_fs660c32_D = {
.get_params = clk_fs660c32_dig_get_params,
.get_rate = clk_fs660c32_dig_get_rate,};
+static const struct clkgen_quadfs_data_clks st_fs660c32_D_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D0_clks[] = {
+ { .name = "clk-s-d0-fs0-ch0", },
+ { .name = "clk-s-d0-fs0-ch1", },
+ { .name = "clk-s-d0-fs0-ch2", },
+ { .name = "clk-s-d0-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D0_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D0_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D2_clks[] = {
+ { .name = "clk-s-d2-fs0-ch0", },
+ { .name = "clk-s-d2-fs0-ch1", },
+ { .name = "clk-s-d2-fs0-ch2", },
+ { .name = "clk-s-d2-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D2_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D2_clks,
+};
+
+static const struct clkgen_clk_out st_fs660c32_D3_clks[] = {
+ { .name = "clk-s-d3-fs0-ch0", },
+ { .name = "clk-s-d3-fs0-ch1", },
+ { .name = "clk-s-d3-fs0-ch2", },
+ { .name = "clk-s-d3-fs0-ch3", },
+};
+
+static const struct clkgen_quadfs_data_clks st_fs660c32_D3_data = {
+ .data = (struct clkgen_quadfs_data *)&st_fs660c32_D,
+ .outputs= st_fs660c32_D3_clks,
+};
+
/**
* DOC: A Frequency Synthesizer that multiples its input clock by a fixed
factor
*
@@ -857,7 +919,7 @@ static struct clk * __init st_clk_register_quadfs_fsynth(
static void __init st_of_create_quadfs_fsynths(
struct device_node *np, const char *pll_name,
- struct clkgen_quadfs_data *quadfs, void __iomem *reg,
+ struct clkgen_quadfs_data_clks *quadfs, void __iomem *reg,
spinlock_t *lock)
{
struct clk_onecell_data *clk_data;
@@ -881,9 +943,15 @@ static void __init st_of_create_quadfs_fsynths(
const char *clk_name;
unsigned long flags = 0;
- if (of_property_read_string_index(np, "clock-output-names",
- fschan, &clk_name)) {
- break;
+ if (quadfs->outputs) {
+ clk_name = quadfs->outputs[fschan].name;
+ flags = quadfs->outputs[fschan].flags;
+ } else {
+ if (of_property_read_string_index(np,
+ "clock-output-names",
+ fschan, &clk_nam
[PATCH 03/16] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH 09/16] ARM: dts: sti: update flexgen compatible within stih407-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 85 ++--
1 file changed, 6 insertions(+), 79 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 1ab40db7c91a..ecd568777e5f 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -83,15 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0";
- clock-critical = ;
};
};
@@ -134,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih407-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -144,45 +141,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp";
- clock-critical = ,
-,
-,
-,
-,
-;
-
/*
* ARM Peripheral clock for timers
*/
@@ -219,18 +177,13 @@
clk_s_d0_flexgen: clk-s-d0-flexgen {
#clock-cells = <1>;
-
[PATCH 10/16] ARM: dts: sti: update flexgen compatible within stih410-clock
With the introduction of new flexgen compatible within the clk-flexgen
driver, remove the clock-output-names entry from the flexgen nodes
and set the new proper compatible corresponding.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 95 ++--
1 file changed, 6 insertions(+), 89 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 81a8c25d7ba5..04b0d7080353 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -83,16 +83,12 @@
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-a0";
#clock-cells = <1>;
clocks = <&clk_s_a0_pll 0>,
<&clk_sysin>;
-
- clock-output-names = "clk-ic-lmi0",
-"clk-ic-lmi1";
- clock-critical = ;
};
};
@@ -135,7 +131,7 @@
clk_s_c0_flexgen: clk-s-c0-flexgen {
#clock-cells = <1>;
- compatible = "st,flexgen";
+ compatible = "st,flexgen",
"st,flexgen-stih410-c0";
clocks = <&clk_s_c0_pll0 0>,
<&clk_s_c0_pll1 0>,
@@ -145,52 +141,6 @@
<&clk_s_c0_quadfs 3>,
<&clk_sysin>;
- clock-output-names = "clk-icn-gpu",
-"clk-fdma",
-"clk-nand",
-"clk-hva",
-"clk-proc-stfe",
-"clk-proc-tp",
-"clk-rx-icn-dmu",
-"clk-rx-icn-hva",
-"clk-icn-cpu",
-"clk-tx-icn-dmu",
-"clk-mmc-0",
-"clk-mmc-1",
-"clk-jpegdec",
-"clk-ext2fa9",
-"clk-ic-bdisp-0",
-"clk-ic-bdisp-1",
-"clk-pp-dmu",
-"clk-vid-dmu",
-"clk-dss-lpc",
-"clk-st231-aud-0",
-"clk-st231-gp-1",
-"clk-st231-dmu",
-"clk-icn-lmi",
-"clk-tx-icn-disp-1",
-"clk-icn-sbc",
-"clk-stfe-frc2",
-"clk-eth-phy",
-"clk-eth-ref-phyclk",
-"clk-flash-promip",
-"clk-main-disp",
-"clk-aux-disp",
-"clk-compo-dvp",
-"clk-tx-icn-hades",
-"clk-rx-icn-hades",
-"clk-icn-reg-16",
-"clk-pp-hades",
-"clk-clust-hades",
-"clk-hwpe-hades",
-&quo
[PATCH 12/16] ARM: dts: sti: update clkgen-pll entries in stih410-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 04b0d7080353..3aeabdd6e305 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH 13/16] ARM: dts: sti: update clkgen-pll entries in stih418-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 14 +++---
1 file changed, 3 insertions(+), 11 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index 35d12979cdf4..d628e656458d 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -39,8 +39,6 @@
compatible = "st,stih418-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -75,11 +73,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -111,20 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
[PATCH 15/16] ARM: dts: sti: update clkgen-fsyn entries in stih410-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih410-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih410-clock.dtsi
b/arch/arm/boot/dts/stih410-clock.dtsi
index 3aeabdd6e305..6b0e6d4477a3 100644
--- a/arch/arm/boot/dts/stih410-clock.dtsi
+++ b/arch/arm/boot/dts/stih410-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH 14/16] ARM: dts: sti: update clkgen-fsyn entries in stih407-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 27 +++
1 file changed, 3 insertions(+), 24 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index 2603226a6ca8..9cce9541e26b 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -93,12 +93,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
- clock-critical = <0>; /* clk-s-c0-fs0-ch0 */
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +144,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +168,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +194,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH 16/16] ARM: dts: sti: update clkgen-fsyn entries in stih418-clock
The clkgen-fsyn driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih418-clock.dtsi | 26 +++---
1 file changed, 3 insertions(+), 23 deletions(-)
diff --git a/arch/arm/boot/dts/stih418-clock.dtsi
b/arch/arm/boot/dts/stih418-clock.dtsi
index d628e656458d..e84c476b83ed 100644
--- a/arch/arm/boot/dts/stih418-clock.dtsi
+++ b/arch/arm/boot/dts/stih418-clock.dtsi
@@ -94,11 +94,6 @@
reg = <0x9103000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-fs0-ch0",
-"clk-s-c0-fs0-ch1",
-"clk-s-c0-fs0-ch2",
-"clk-s-c0-fs0-ch3";
};
clk_s_c0: clockgen-c@9103000 {
@@ -150,15 +145,10 @@
clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d0";
reg = <0x9104000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d0-fs0-ch0",
-"clk-s-d0-fs0-ch1",
-"clk-s-d0-fs0-ch2",
-"clk-s-d0-fs0-ch3";
};
clockgen-d0@9104000 {
@@ -179,15 +169,10 @@
clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d2";
reg = <0x9106000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d2-fs0-ch0",
-"clk-s-d2-fs0-ch1",
-"clk-s-d2-fs0-ch2",
-"clk-s-d2-fs0-ch3";
};
clockgen-d2@9106000 {
@@ -210,15 +195,10 @@
clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 {
#clock-cells = <1>;
- compatible = "st,quadfs";
+ compatible = "st,quadfs-d3";
reg = <0x9107000 0x1000>;
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-d3-fs0-ch0",
-"clk-s-d3-fs0-ch1",
-"clk-s-d3-fs0-ch2",
-"clk-s-d3-fs0-ch3";
};
clockgen-d3@9107000 {
--
2.17.1
[PATCH 11/16] ARM: dts: sti: update clkgen-pll entries in stih407-clock
The clkgen-pll driver now embed the clock names (assuming the
right compatible is used). Remove all clock-output-names property
and update when necessary the compatible.
Signed-off-by: Alain Volmat
---
arch/arm/boot/dts/stih407-clock.dtsi | 16 +++-
1 file changed, 3 insertions(+), 13 deletions(-)
diff --git a/arch/arm/boot/dts/stih407-clock.dtsi
b/arch/arm/boot/dts/stih407-clock.dtsi
index ecd568777e5f..2603226a6ca8 100644
--- a/arch/arm/boot/dts/stih407-clock.dtsi
+++ b/arch/arm/boot/dts/stih407-clock.dtsi
@@ -36,8 +36,6 @@
compatible = "st,stih407-clkgen-plla9";
clocks = <&clk_sysin>;
-
- clock-output-names = "clockgen-a9-pll-odf";
};
};
@@ -74,12 +72,9 @@
clk_s_a0_pll: clk-s-a0-pll {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-a0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-a0-pll-ofd-0";
- clock-critical = <0>; /* clk-s-a0-pll-ofd-0 */
};
clk_s_a0_flexgen: clk-s-a0-flexgen {
@@ -112,21 +107,16 @@
clk_s_c0_pll0: clk-s-c0-pll0 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll0";
+ compatible = "st,clkgen-pll0-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll0-odf-0";
- clock-critical = <0>; /* clk-s-c0-pll0-odf-0 */
};
clk_s_c0_pll1: clk-s-c0-pll1 {
#clock-cells = <1>;
- compatible = "st,clkgen-pll1";
+ compatible = "st,clkgen-pll1-c0";
clocks = <&clk_sysin>;
-
- clock-output-names = "clk-s-c0-pll1-odf-0";
};
clk_s_c0_flexgen: clk-s-c0-flexgen {
--
2.17.1
Re: [PATCH 00/16] clk: st: embed clock outputs within drivers
Hello, it turns out that some CLK_IS_CRITICAL are missing in the patches I sent. (especially for the stih418). I will send a v2 soon. Alain On Sun, Mar 21, 2021 at 09:40:22PM +0100, Alain Volmat wrote: > Most of ST clock drivers used by STi platform are updated in > order to introduce clock outputs informations within each drivers > and thus allow to avoid having to rely on clock-output-names properties > within DT clock nodes. > For that purpose, drivers are updated to allow handling both modes > (with or without clock-output-names). > Once all DT will have been updated, the legacy mode could be removed > from the drivers. > This will also allow, once all STi DT will be corrected, to remove the > of_clk_detect_critical API from clk core code since STi clock drivers > are the only drivers using this API. > > This serie also contains modifications within STi DTS in order to use > the newly introduced compatible and remove clock-output-names > properties. > > Alain Volmat (16): > clk: st: clkgen-pll: remove used variable of struct clkgen_pll > clk: st: flexgen: embed soc clock outputs within compatible data > dt-bindings: clock: st: flexgen: add new introduced compatible > clk: st: clkgen-pll: embed soc clock outputs within compatible data > dt-bindings: clock: st: clkgen-pll: add new introduced compatible > clk: st: clkgen-fsyn: embed soc clock outputs within compatible data > dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible > ARM: dts: sti: update flexgen compatible within stih418-clock > ARM: dts: sti: update flexgen compatible within stih407-clock > ARM: dts: sti: update flexgen compatible within stih410-clock > ARM: dts: sti: update clkgen-pll entries in stih407-clock > ARM: dts: sti: update clkgen-pll entries in stih410-clock > ARM: dts: sti: update clkgen-pll entries in stih418-clock > ARM: dts: sti: update clkgen-fsyn entries in stih407-clock > ARM: dts: sti: update clkgen-fsyn entries in stih410-clock > ARM: dts: sti: update clkgen-fsyn entries in stih418-clock > > .../bindings/clock/st/st,clkgen-pll.txt | 3 + > .../bindings/clock/st/st,flexgen.txt | 10 + > .../bindings/clock/st/st,quadfs.txt | 3 + > arch/arm/boot/dts/stih407-clock.dtsi | 128 +-- > arch/arm/boot/dts/stih410-clock.dtsi | 138 +-- > arch/arm/boot/dts/stih418-clock.dtsi | 136 +-- > drivers/clk/st/clk-flexgen.c | 344 +- > drivers/clk/st/clkgen-fsyn.c | 113 +- > drivers/clk/st/clkgen-pll.c | 121 +- > 9 files changed, 588 insertions(+), 408 deletions(-) > > -- > 2.17.1 >
[PATCH v3 0/2] i2c: stm32f7: add SMBus-Alert support
This serie adds support for SMBus Alert on the STM32F7. A new binding st,smbus-alert is added in order to differenciate with the existing smbus binding. SMBA alert control and status logic must be enabled along with SMBALERT# pin configured via pinctrl in the device tree. This is the rational for adding "st,smbus-alert" property. --- v3: use lore.kernel.org links instead of marc.info v2: When SMBUS alert isn't available on the board (SMBA unused), this logic musn't be enabled. Enabling it unconditionally wrongly lead to get SMBA interrupts. So, add "st,smbus-alert" dedicated binding to have a smbus alert with a consistent pin configuration in DT. Alain Volmat (2): dt-bindings: i2c: stm32f7: add st,smbus-alert binding for SMBus Alert i2c: stm32f7: add SMBus-Alert support .../devicetree/bindings/i2c/st,stm32-i2c.yaml | 5 ++ drivers/i2c/busses/i2c-stm32f7.c | 73 +++ 2 files changed, 78 insertions(+) -- 2.17.1
[PATCH v3 1/2] dt-bindings: i2c: stm32f7: add st,smbus-alert binding for SMBus Alert
Based on the SMBus specification, SMBus Alert active state is low. As often on SoC, the SMBus Alert pin is not only dedicated to this feature and can also be used for another purpose (by configuring it as alternate function for other functions via pinctrl). "smbus" dt-binding has been introduced recently [1], however it is also used to indicate usage of host-notify feature. Relying on 'smbus' binding for SMBus-Alert as well as it was discussed previously [2] would lead to requiring the SMBALERT# pin to be configured as alternate function for i2c/smbus controller even if only host-notify is needed. Indeed, not doing so would lead to spurious SMBus Alert interrupts since the i2c/smbus controller would see the (not configured) SMBA pin as low level. For that reason, SMBus-Alert needs to have its own binding in order to only be enabled whenever SMBALERT# pin is configured as alternate function for i2c/smbus controller. [1] https://lore.kernel.org/linux-i2c/20200721062217.GA1044@kunai/ [2] https://lore.kernel.org/linux-i2c/20200701143738.gf3...@gnbcxd0016.gnb.st.com/ Signed-off-by: Alain Volmat Reviewed-by: Rob Herring --- v3: use lore.kernel.org links v2: introduce st,smbus-alert property --- Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml index d747f4990ad8..0d45ead7d835 100644 --- a/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/st,stm32-i2c.yaml @@ -36,6 +36,11 @@ allOf: minItems: 3 maxItems: 3 +st,smbus-alert: + description: Enable the SMBus-Alert via SMBA pin, note SMBA pin + must also be configured via pinctrl. + type: boolean + - if: properties: compatible: -- 2.17.1
[PATCH v3 2/2] i2c: stm32f7: add SMBus-Alert support
Add support for the SMBus-Alert protocol to the STM32F7 that has
dedicated control and status logic.
If SMBus-Alert is used, the SMBALERT# pin must be configured as alternate
function for I2C Alert.
Signed-off-by: Alain Volmat
Reviewed-by: Pierre-Yves MORDRET
---
v2: - rely on st,smbus-alert binding instead of smbus
---
drivers/i2c/busses/i2c-stm32f7.c | 73
1 file changed, 73 insertions(+)
diff --git a/drivers/i2c/busses/i2c-stm32f7.c b/drivers/i2c/busses/i2c-stm32f7.c
index c62c815b88eb..bd840cd2b9e4 100644
--- a/drivers/i2c/busses/i2c-stm32f7.c
+++ b/drivers/i2c/busses/i2c-stm32f7.c
@@ -51,6 +51,7 @@
/* STM32F7 I2C control 1 */
#define STM32F7_I2C_CR1_PECEN BIT(23)
+#define STM32F7_I2C_CR1_ALERTENBIT(22)
#define STM32F7_I2C_CR1_SMBHEN BIT(20)
#define STM32F7_I2C_CR1_WUPEN BIT(18)
#define STM32F7_I2C_CR1_SBCBIT(16)
@@ -125,6 +126,7 @@
(((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
#define STM32F7_I2C_ISR_DIRBIT(16)
#define STM32F7_I2C_ISR_BUSY BIT(15)
+#define STM32F7_I2C_ISR_ALERT BIT(13)
#define STM32F7_I2C_ISR_PECERR BIT(11)
#define STM32F7_I2C_ISR_ARLO BIT(9)
#define STM32F7_I2C_ISR_BERR BIT(8)
@@ -138,6 +140,7 @@
#define STM32F7_I2C_ISR_TXEBIT(0)
/* STM32F7 I2C Interrupt Clear */
+#define STM32F7_I2C_ICR_ALERTCFBIT(13)
#define STM32F7_I2C_ICR_PECCF BIT(11)
#define STM32F7_I2C_ICR_ARLOCF BIT(9)
#define STM32F7_I2C_ICR_BERRCF BIT(8)
@@ -283,6 +286,17 @@ struct stm32f7_i2c_msg {
u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
};
+/**
+ * struct stm32f7_i2c_alert - SMBus alert specific data
+ * @setup: platform data for the smbus_alert i2c client
+ * @ara: I2C slave device used to respond to the SMBus Alert with Alert
+ * Response Address
+ */
+struct stm32f7_i2c_alert {
+ struct i2c_smbus_alert_setup setup;
+ struct i2c_client *ara;
+};
+
/**
* struct stm32f7_i2c_dev - private data of the controller
* @adap: I2C adapter for this controller
@@ -312,6 +326,7 @@ struct stm32f7_i2c_msg {
* @wakeup_src: boolean to know if the device is a wakeup source
* @smbus_mode: states that the controller is configured in SMBus mode
* @host_notify_client: SMBus host-notify client
+ * @alert: SMBus alert specific data
*/
struct stm32f7_i2c_dev {
struct i2c_adapter adap;
@@ -340,6 +355,7 @@ struct stm32f7_i2c_dev {
bool wakeup_src;
bool smbus_mode;
struct i2c_client *host_notify_client;
+ struct stm32f7_i2c_alert *alert;
};
/*
@@ -1616,6 +1632,13 @@ static irqreturn_t stm32f7_i2c_isr_error(int irq, void
*data)
f7_msg->result = -EINVAL;
}
+ if (status & STM32F7_I2C_ISR_ALERT) {
+ dev_dbg(dev, "<%s>: SMBus alert received\n", __func__);
+ writel_relaxed(STM32F7_I2C_ICR_ALERTCF, base + STM32F7_I2C_ICR);
+ i2c_handle_smbus_alert(i2c_dev->alert->ara);
+ return IRQ_HANDLED;
+ }
+
if (!i2c_dev->slave_running) {
u32 mask;
/* Disable interrupts */
@@ -1982,6 +2005,42 @@ static void stm32f7_i2c_disable_smbus_host(struct
stm32f7_i2c_dev *i2c_dev)
}
}
+static int stm32f7_i2c_enable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert;
+ struct i2c_adapter *adap = &i2c_dev->adap;
+ struct device *dev = i2c_dev->dev;
+ void __iomem *base = i2c_dev->base;
+
+ alert = devm_kzalloc(dev, sizeof(*alert), GFP_KERNEL);
+ if (!alert)
+ return -ENOMEM;
+
+ alert->ara = i2c_new_smbus_alert_device(adap, &alert->setup);
+ if (IS_ERR(alert->ara))
+ return PTR_ERR(alert->ara);
+
+ i2c_dev->alert = alert;
+
+ /* Enable SMBus Alert */
+ stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_ALERTEN);
+
+ return 0;
+}
+
+static void stm32f7_i2c_disable_smbus_alert(struct stm32f7_i2c_dev *i2c_dev)
+{
+ struct stm32f7_i2c_alert *alert = i2c_dev->alert;
+ void __iomem *base = i2c_dev->base;
+
+ if (alert) {
+ /* Disable SMBus Alert */
+ stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
+STM32F7_I2C_CR1_ALERTEN);
+ i2c_unregister_device(alert->ara);
+ }
+}
+
static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
{
struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
@@ -2169,6 +2228,16 @@ static int stm32f7_i2c_probe(struct platform_device
*pdev)
}
}
+ if (of_property_read_bool(pdev->dev.of_n
[PATCH v4 1/7] clk: st: clkgen-pll: remove unused variable of struct clkgen_pll
ODF field within the struct clkgen_pll is never used by the driver
and can thus be removed.
Signed-off-by: Alain Volmat
Reviewed-by: Patrice Chotard
---
v3: s/used/unused within the subject
drivers/clk/st/clkgen-pll.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/st/clkgen-pll.c b/drivers/clk/st/clkgen-pll.c
index 119c5b33080c..f6c56ca90c7d 100644
--- a/drivers/clk/st/clkgen-pll.c
+++ b/drivers/clk/st/clkgen-pll.c
@@ -146,7 +146,6 @@ struct clkgen_pll {
u32 ndiv;
u32 idf;
- u32 odf;
u32 cp;
};
--
2.17.1
[PATCH v4 0/7] clk: st: embed clock outputs within drivers
Most of ST clock drivers used by STi platform are updated in order to introduce clock outputs informations within each drivers and thus allow to avoid having to rely on clock-output-names properties within DT clock nodes. For that purpose, drivers are updated to allow handling both modes (with or without clock-output-names). Once all DT will have been updated, the legacy mode could be removed from the drivers. This will also allow, once all STi DT will be corrected, to remove the of_clk_detect_critical API from clk core code since STi clock drivers are the only drivers using this API. Alain Volmat (7): clk: st: clkgen-pll: remove unused variable of struct clkgen_pll clk: st: flexgen: embed soc clock outputs within compatible data dt-bindings: clock: st: flexgen: add new introduced compatible clk: st: clkgen-pll: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-pll: add new introduced compatible clk: st: clkgen-fsyn: embed soc clock outputs within compatible data dt-bindings: clock: st: clkgen-fsyn: add new introduced compatible .../bindings/clock/st/st,clkgen-pll.txt | 3 + .../bindings/clock/st/st,flexgen.txt | 10 + .../bindings/clock/st/st,quadfs.txt | 3 + drivers/clk/st/clk-flexgen.c | 367 +- drivers/clk/st/clkgen-fsyn.c | 113 +- drivers/clk/st/clkgen-pll.c | 121 +- 6 files changed, 576 insertions(+), 41 deletions(-) --- v4: - add an additional CLK_IS_CRITICAL within flexgen driver v3: - removal some useless CLK_IS_CRITICAL and add some comments - only keep clk drivers/binding patches within the serie -- 2.17.1
[PATCH v4 3/7] dt-bindings: clock: st: flexgen: add new introduced compatible
New compatible are added, supporting various kind of flexgen in STiH407, STiH410 and STiH418 Signed-off-by: Alain Volmat Acked-by: Rob Herring --- .../devicetree/bindings/clock/st/st,flexgen.txt| 10 ++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt index 7ff77fc57dff..55a18939bddd 100644 --- a/Documentation/devicetree/bindings/clock/st/st,flexgen.txt +++ b/Documentation/devicetree/bindings/clock/st/st,flexgen.txt @@ -64,6 +64,16 @@ Required properties: audio use case) "st,flexgen-video", "st,flexgen" (enable clock propagation on parent and activate synchronous mode) + "st,flexgen-stih407-a0" + "st,flexgen-stih410-a0" + "st,flexgen-stih407-c0" + "st,flexgen-stih410-c0" + "st,flexgen-stih418-c0" + "st,flexgen-stih407-d0" + "st,flexgen-stih410-d0" + "st,flexgen-stih407-d2" + "st,flexgen-stih418-d2" + "st,flexgen-stih407-d3" - #clock-cells : from common clock binding; shall be set to 1 (multiple clock outputs). -- 2.17.1
[PATCH v4 2/7] clk: st: flexgen: embed soc clock outputs within compatible data
In order to avoid relying on the old style description via the DT
clock-output-names, add compatible data describing the flexgen
outputs clocks for all STiH407/STiH410 and STiH418 SOCs.
In order to ease transition between the two methods, this commit
introduce the new compatible without removing the old method.
Once DTs will be fixed, the method relying on DT clock-output-names
will be removed from this driver as well as old compatibles.
Signed-off-by: Alain Volmat
Reviewed-by: Patrice Chotard
---
v4: for stih410, set the clk-icn-reg-16 as critical
v3: add comments about CLK_IS_CRITICAL reason
don't put clk-proc-stfe as CLK_IS_CRITICAL
v2: add some missing clock as CLK_IS_CRITICAL
drivers/clk/st/clk-flexgen.c | 367 +--
1 file changed, 353 insertions(+), 14 deletions(-)
diff --git a/drivers/clk/st/clk-flexgen.c b/drivers/clk/st/clk-flexgen.c
index 55873d4b7603..7ae4f656191e 100644
--- a/drivers/clk/st/clk-flexgen.c
+++ b/drivers/clk/st/clk-flexgen.c
@@ -16,9 +16,16 @@
#include
#include
+struct clkgen_clk_out {
+ const char *name;
+ unsigned long flags;
+};
+
struct clkgen_data {
unsigned long flags;
bool mode;
+ const struct clkgen_clk_out *outputs;
+ const unsigned int outputs_nb;
};
struct flexgen {
@@ -295,6 +302,290 @@ static const struct clkgen_data clkgen_video = {
.mode = 1,
};
+static const struct clkgen_clk_out clkgen_stih407_a0_clk_out[] = {
+ /* This clk needs to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih407_a0 = {
+ .outputs = clkgen_stih407_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_a0_clk_out[] = {
+ /* Those clks need to be on so that memory interface is accessible */
+ { .name = "clk-ic-lmi0", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-lmi1", .flags = CLK_IS_CRITICAL },
+};
+
+static const struct clkgen_data clkgen_stih410_a0 = {
+ .outputs = clkgen_stih410_a0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih410_a0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih407_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-cpu", .flags = CLK_IS_CRITICAL },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-tx-icn-dmu", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-mmc-0", },
+ { .name = "clk-mmc-1", },
+ { .name = "clk-jpegdec", },
+ /* This clk needs to be on to keep A9 running */
+ { .name = "clk-ext2fa9", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-ic-bdisp-0", },
+ { .name = "clk-ic-bdisp-1", },
+ { .name = "clk-pp-dmu", },
+ { .name = "clk-vid-dmu", },
+ { .name = "clk-dss-lpc", },
+ { .name = "clk-st231-aud-0", },
+ { .name = "clk-st231-gp-1", },
+ { .name = "clk-st231-dmu", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-lmi", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-tx-icn-disp-1", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .name = "clk-icn-sbc", .flags = CLK_IS_CRITICAL },
+ { .name = "clk-stfe-frc2", },
+ { .name = "clk-eth-phy", },
+ { .name = "clk-eth-ref-phyclk", },
+ { .name = "clk-flash-promip", },
+ { .name = "clk-main-disp", },
+ { .name = "clk-aux-disp", },
+ { .name = "clk-compo-dvp", },
+};
+
+static const struct clkgen_data clkgen_stih407_c0 = {
+ .outputs = clkgen_stih407_c0_clk_out,
+ .outputs_nb = ARRAY_SIZE(clkgen_stih407_c0_clk_out),
+};
+
+static const struct clkgen_clk_out clkgen_stih410_c0_clk_out[] = {
+ { .name = "clk-icn-gpu", },
+ { .name = "clk-fdma", },
+ { .name = "clk-nand", },
+ { .name = "clk-hva", },
+ { .name = "clk-proc-stfe", },
+ { .name = "clk-proc-tp", },
+ { .name = "clk-rx-icn-dmu", },
+ { .name = "clk-rx-icn-hva", },
+ /* This clk needs to be on to keep bus interconnect alive */
+ { .nam
