[PATCH 1/3] ARM: imx: enable anatop suspend/resume
anatop module have sereval configurations for user
to reduce the power consumption in suspend, provide
suspend/resume interface for further use and enable
fet_odrive to reduce CORE LDO leakage during suspend.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/Kconfig |4
arch/arm/mach-imx/Makefile |1 +
arch/arm/mach-imx/anatop.c | 50
arch/arm/mach-imx/common.h |3 +++
arch/arm/mach-imx/mach-imx6q.c |1 +
arch/arm/mach-imx/pm-imx6q.c |2 ++
6 files changed, 61 insertions(+)
create mode 100644 arch/arm/mach-imx/anatop.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4c9c6f9..7abaa6e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,9 @@ config HAVE_IMX_MMDC
config HAVE_IMX_SRC
def_bool y if SMP
+config HAVE_IMX_ANATOP
+ bool
+
config IMX_HAVE_IOMUX_V1
bool
@@ -816,6 +819,7 @@ config SOC_IMX6Q
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
+ select HAVE_IMX_ANATOP
select HAVE_SMP
select MFD_SYSCON
select PINCTRL
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c4ce090..f4badaa 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
new file mode 100644
index 000..8f6ab27
--- /dev/null
+++ b/arch/arm/mach-imx/anatop.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include linux/err.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
+
+#define REG_SET0x4
+#define REG_CLR0x8
+#define ANA_REG_CORE 0x140
+
+#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x2000
+
+static struct regmap *anatop;
+
+void imx_anatop_enable_fet_odrive(bool enable)
+{
+ regmap_write(anatop, ANA_REG_CORE + (enable ?
+ REG_SET : REG_CLR), BM_ANADIG_REG_CORE_FET_ODRIVE);
+}
+
+void imx_anatop_pre_suspend(void)
+{
+ imx_anatop_enable_fet_odrive(true);
+}
+
+void imx_anatop_post_resume(void)
+{
+ imx_anatop_enable_fet_odrive(false);
+}
+
+void __init imx_anatop_init(void)
+{
+ anatop = syscon_regmap_lookup_by_compatible(fsl,imx6q-anatop);
+ if (IS_ERR(anatop)) {
+ pr_err(%s: failed to find imx6q-anatop regmap!\n, __func__);
+ return;
+ }
+}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5a800bf..004c2b3 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -129,6 +129,9 @@ extern void imx_src_prepare_restart(void);
extern void imx_gpc_init(void);
extern void imx_gpc_pre_suspend(void);
extern void imx_gpc_post_resume(void);
+extern void imx_anatop_init(void);
+extern void imx_anatop_pre_suspend(void);
+extern void imx_anatop_post_resume(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_set_chicken_bit(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103..aa867db 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -197,6 +197,7 @@ static void __init imx6q_init_machine(void)
of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+ imx_anatop_init();
imx6q_pm_init();
imx6q_usb_init();
imx6q_1588_init();
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 5faba7a..05b26cd 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -34,10 +34,12 @@ static int imx6q_pm_enter(suspend_state_t state)
case PM_SUSPEND_MEM:
imx6q_set_lpm(STOP_POWER_OFF);
imx_gpc_pre_suspend();
+ imx_anatop_pre_suspend();
imx_set_cpu_jump(0, v7_cpu_resume);
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
imx_smp_prepare();
+ imx_anatop_post_resume();
imx_gpc_post_resume();
imx6q_set_lpm(WAIT_CLOCKED);
break;
--
1.7.9.5
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[PATCH 2/3] ARM: imx: enable periphery well bias for suspend
enable periphery charge pump for well biasing
at suspend to reduce periphery leakage.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/clk-imx6q.c | 22 +-
arch/arm/mach-imx/common.h|4 ++--
arch/arm/mach-imx/pm-imx6q.c |4 +++-
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2f9ff93..b365efc 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -23,6 +23,9 @@
#include clk.h
#include common.h
+#define CCR0x0
+#define BM_CCR_WB_COUNT(0x7 16)
+
#define CCGR0 0x68
#define CCGR1 0x6c
#define CCGR2 0x70
@@ -67,6 +70,23 @@ void imx6q_set_chicken_bit(void)
writel_relaxed(val, ccm_base + CGPR);
}
+void imx6q_set_wb(bool enable)
+{
+ u32 val;
+
+ /* configurate well bias enable bit */
+ val = readl_relaxed(ccm_base + CLPCR);
+ val = ~BM_CLPCR_WB_PER_AT_LPM;
+ val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+ writel_relaxed(val, ccm_base + CLPCR);
+
+ /* configurate well bias count */
+ val = readl_relaxed(ccm_base + CCR);
+ val = ~BM_CCR_WB_COUNT;
+ val |= enable ? BM_CCR_WB_COUNT : 0;
+ writel_relaxed(val, ccm_base + CCR);
+}
+
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
u32 val = readl_relaxed(ccm_base + CLPCR);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 004c2b3..b9125cf 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -134,7 +134,7 @@ extern void imx_anatop_pre_suspend(void);
extern void imx_anatop_post_resume(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_set_chicken_bit(void);
-
+extern void imx6q_set_wb(bool enable);
extern void imx_cpu_die(unsigned int cpu);
extern int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 05b26cd..57ca274 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -36,8 +36,10 @@ static int imx6q_pm_enter(suspend_state_t state)
imx_gpc_pre_suspend();
imx_anatop_pre_suspend();
imx_set_cpu_jump(0, v7_cpu_resume);
+ imx6q_set_wb(true);
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
+ imx6q_set_wb(false);
imx_smp_prepare();
imx_anatop_post_resume();
imx_gpc_post_resume();
--
1.7.9.5
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[PATCH 3/3] ARM: imx: enable RBC to support anatop LPM mode
RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:
1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;
As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.
For RBC settings, there are some rules as below
due to hardware designe:
1. All interrupts must be masked during operating
RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
RBC setting is changed.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/anatop.c| 19 +++
arch/arm/mach-imx/clk-imx6q.c | 35 +++
arch/arm/mach-imx/common.h|3 +++
arch/arm/mach-imx/gpc.c | 21 -
arch/arm/mach-imx/pm-imx6q.c |2 ++
5 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 8f6ab27..38b4f44 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -18,12 +18,29 @@
#define REG_SET0x4
#define REG_CLR0x8
+#define ANA_MISC0 0x150
#define ANA_REG_CORE 0x140
+#define ANA_REG_2P50x130
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x4
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x2000
static struct regmap *anatop;
+void imx_anatop_enable_weak2p5(bool enable)
+{
+ u32 val;
+
+ regmap_read(anatop, ANA_MISC0, val);
+
+ /* can only be enabled when stop_mode_config is clear. */
+ regmap_write(anatop, ANA_REG_2P5 + ((enable
+ ((val BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG)
+ == 0)) ? REG_SET : REG_CLR),
+ BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
+}
+
void imx_anatop_enable_fet_odrive(bool enable)
{
regmap_write(anatop, ANA_REG_CORE + (enable ?
@@ -32,12 +49,14 @@ void imx_anatop_enable_fet_odrive(bool enable)
void imx_anatop_pre_suspend(void)
{
+ imx_anatop_enable_weak2p5(true);
imx_anatop_enable_fet_odrive(true);
}
void imx_anatop_post_resume(void)
{
imx_anatop_enable_fet_odrive(false);
+ imx_anatop_enable_weak2p5(false);
}
void __init imx_anatop_init(void)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index b365efc..646ce12 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -14,6 +14,7 @@
#include linux/types.h
#include linux/clk.h
#include linux/clkdev.h
+#include linux/delay.h
#include linux/err.h
#include linux/io.h
#include linux/of.h
@@ -25,6 +26,8 @@
#define CCR0x0
#define BM_CCR_WB_COUNT(0x7 16)
+#define BM_CCR_RBC_BYPASS_COUNT(0x3f 21)
+#define BM_CCR_RBC_EN (0x1 27)
#define CCGR0 0x68
#define CCGR1 0x6c
@@ -70,6 +73,38 @@ void imx6q_set_chicken_bit(void)
writel_relaxed(val, ccm_base + CGPR);
}
+void imx6q_set_rbc(bool enable)
+{
+ u32 val;
+
+ /*
+* need to mask all interrupts in GPC before
+* operating RBC configurations
+*/
+ imx_gpc_mask_all();
+
+ /* configurate RBC enable bit */
+ val = readl_relaxed(ccm_base + CCR);
+ val = ~BM_CCR_RBC_EN;
+ val |= enable ? BM_CCR_RBC_EN : 0;
+ writel_relaxed(val, ccm_base + CCR);
+
+ /* configurate RBC count */
+ val = readl_relaxed(ccm_base + CCR);
+ val = ~BM_CCR_RBC_BYPASS_COUNT;
+ val |= enable ? BM_CCR_RBC_BYPASS_COUNT : 0;
+ writel(val, ccm_base + CCR);
+
+ /*
+* need to delay at least 2 cycles of CKIL(32K)
+* due to hardware design requirement, which is
+* ~61us, here we use 65us for safe
+*/
+ udelay(65);
+ /* restore GPC interrupt mask settings */
+ imx_gpc_restore_all();
+}
+
void imx6q_set_wb(bool enable)
{
u32 val;
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b9125cf..66fe41c 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -129,11 +129,14 @@ extern void imx_src_prepare_restart(void);
extern void imx_gpc_init(void);
extern void imx_gpc_pre_suspend(void);
extern void imx_gpc_post_resume(void);
+extern void imx_gpc_mask_all(void);
+extern void imx_gpc_restore_all(void);
extern void imx_anatop_init(void);
extern void imx_anatop_pre_suspend(void);
extern void imx_anatop_post_resume(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_set_chicken_bit(void);
+extern void imx6q_set_rbc(bool enable);
extern void imx6q_set_wb(bool enable);
extern void imx_cpu_die(unsigned int cpu);
extern int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx
Re: [PATCH 1/3] ARM: imx: enable anatop suspend/resume
On Wed, Mar 20, 2013 at 03:29:33PM +0800, Shawn Guo wrote:
On Wed, Mar 20, 2013 at 01:39:38PM -0400, Anson Huang wrote:
anatop module have sereval configurations for user
to reduce the power consumption in suspend, provide
suspend/resume interface for further use and enable
fet_odrive to reduce CORE LDO leakage during suspend.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/Kconfig |4
arch/arm/mach-imx/Makefile |1 +
arch/arm/mach-imx/anatop.c | 50
I like the idea of having an anatop.c for all those anatop related
setup. Please move those anatop related code in mach-imx6q.c
into there as well. Leaving them out there beats the idea of having
a centralized place for anatop configurations.
will do that in V2.
arch/arm/mach-imx/common.h |3 +++
arch/arm/mach-imx/mach-imx6q.c |1 +
arch/arm/mach-imx/pm-imx6q.c |2 ++
6 files changed, 61 insertions(+)
create mode 100644 arch/arm/mach-imx/anatop.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4c9c6f9..7abaa6e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -74,6 +74,9 @@ config HAVE_IMX_MMDC
config HAVE_IMX_SRC
def_bool y if SMP
+config HAVE_IMX_ANATOP
+ bool
+
Please have it added before config HAVE_IMX_GPC. We are trying to
have them sorted in alphabet.
Accepted
config IMX_HAVE_IOMUX_V1
bool
@@ -816,6 +819,7 @@ config SOC_IMX6Q
select HAVE_IMX_GPC
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
+ select HAVE_IMX_ANATOP
Ditto
Accepted
select HAVE_SMP
select MFD_SYSCON
select PINCTRL
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index c4ce090..f4badaa 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -95,6 +95,7 @@ obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
+obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
Ditto
Accepted
AFLAGS_headsmp.o :=-Wa,-march=armv7-a
obj-$(CONFIG_SMP) += headsmp.o platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
new file mode 100644
index 000..8f6ab27
--- /dev/null
+++ b/arch/arm/mach-imx/anatop.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include linux/err.h
+#include linux/io.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/mfd/syscon.h
+#include linux/regmap.h
+
+#define REG_SET0x4
+#define REG_CLR0x8
+#define ANA_REG_CORE 0x140
The abbreviation ANA is used here ...
+
+#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x2000
... while ANADIG is here. Please be consistent.
Accepted.
+
+static struct regmap *anatop;
+
+void imx_anatop_enable_fet_odrive(bool enable)
static?
Accepted.
+{
+ regmap_write(anatop, ANA_REG_CORE + (enable ?
+ REG_SET : REG_CLR), BM_ANADIG_REG_CORE_FET_ODRIVE);
This is a nit, but I think the following indent is nicer for reading.
regmap_write(anatop, ANA_REG_CORE + (enable ? REG_SET : REG_CLR),
BM_ANADIG_REG_CORE_FET_ODRIVE);
Accepted.
+}
+
+void imx_anatop_pre_suspend(void)
static?
This function will be called outside this file, so we can NOT use static here.
Shawn
+{
+ imx_anatop_enable_fet_odrive(true);
+}
+
+void imx_anatop_post_resume(void)
+{
+ imx_anatop_enable_fet_odrive(false);
+}
+
+void __init imx_anatop_init(void)
+{
+ anatop = syscon_regmap_lookup_by_compatible(fsl,imx6q-anatop);
+ if (IS_ERR(anatop)) {
+ pr_err(%s: failed to find imx6q-anatop regmap!\n, __func__);
+ return;
+ }
+}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5a800bf..004c2b3 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -129,6 +129,9 @@ extern void imx_src_prepare_restart(void);
extern void imx_gpc_init(void);
extern void imx_gpc_pre_suspend(void);
extern void imx_gpc_post_resume(void);
+extern void imx_anatop_init(void);
+extern void imx_anatop_pre_suspend(void);
+extern void imx_anatop_post_resume(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_set_chicken_bit(void);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index 9ffd103
Re: [PATCH 2/3] ARM: imx: enable periphery well bias for suspend
On Wed, Mar 20, 2013 at 03:49:08PM +0800, Shawn Guo wrote:
Forgot mentioning in patch #1, for patches touching arch/arm/, it's
good enough to send them to linux-arm-kernel list. Copying list
linux-kernel isn't so necessary.
Accepted, will pay attention to it.
On Wed, Mar 20, 2013 at 01:39:39PM -0400, Anson Huang wrote:
enable periphery charge pump for well biasing
at suspend to reduce periphery leakage.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/clk-imx6q.c | 22 +-
arch/arm/mach-imx/common.h|4 ++--
arch/arm/mach-imx/pm-imx6q.c |4 +++-
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index 2f9ff93..b365efc 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -23,6 +23,9 @@
#include clk.h
#include common.h
+#define CCR0x0
+#define BM_CCR_WB_COUNT(0x7 16)
+
#define CCGR0 0x68
#define CCGR1 0x6c
#define CCGR2 0x70
@@ -67,6 +70,23 @@ void imx6q_set_chicken_bit(void)
writel_relaxed(val, ccm_base + CGPR);
}
+void imx6q_set_wb(bool enable)
+{
+ u32 val;
+
+ /* configurate well bias enable bit */
s/configurate/configure
Accepted.
+ val = readl_relaxed(ccm_base + CLPCR);
+ val = ~BM_CLPCR_WB_PER_AT_LPM;
+ val |= enable ? BM_CLPCR_WB_PER_AT_LPM : 0;
+ writel_relaxed(val, ccm_base + CLPCR);
+
+ /* configurate well bias count */
Ditto
Accepted.
+ val = readl_relaxed(ccm_base + CCR);
+ val = ~BM_CCR_WB_COUNT;
+ val |= enable ? BM_CCR_WB_COUNT : 0;
+ writel_relaxed(val, ccm_base + CCR);
+}
+
int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
{
u32 val = readl_relaxed(ccm_base + CLPCR);
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 004c2b3..b9125cf 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2013 Freescale Semiconductor, Inc. All Rights Reserved.
*/
/*
@@ -134,7 +134,7 @@ extern void imx_anatop_pre_suspend(void);
extern void imx_anatop_post_resume(void);
extern int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode);
extern void imx6q_set_chicken_bit(void);
-
Unnecessary new line.
Accepted.
+extern void imx6q_set_wb(bool enable);
extern void imx_cpu_die(unsigned int cpu);
extern int imx_cpu_kill(unsigned int cpu);
diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c
index 05b26cd..57ca274 100644
--- a/arch/arm/mach-imx/pm-imx6q.c
+++ b/arch/arm/mach-imx/pm-imx6q.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2011 Freescale Semiconductor, Inc.
+ * Copyright 2011-2013 Freescale Semiconductor, Inc.
* Copyright 2011 Linaro Ltd.
*
* The code contained herein is licensed under the GNU General Public
@@ -36,8 +36,10 @@ static int imx6q_pm_enter(suspend_state_t state)
imx_gpc_pre_suspend();
imx_anatop_pre_suspend();
imx_set_cpu_jump(0, v7_cpu_resume);
+ imx6q_set_wb(true);
Is it possible to have it called inside imx6q_set_lpm()? If so, we can
1) Have imx6q_set_wb() be a static function in clk-imx6q.c
2) Apply the function for both STOP and WAIT mode
Good idea, will move it to imx6q_set_lpm(), but for now, I will only enable
this well bias for stop mode, if we need to enable it in wait mode, will
create another patch, as we are not so confident whether it can be applied
in WAIT mode, many modules are still working in WAIT mode.
Shawn
/* Zzz ... */
cpu_suspend(0, imx6q_suspend_finish);
+ imx6q_set_wb(false);
imx_smp_prepare();
imx_anatop_post_resume();
imx_gpc_post_resume();
--
1.7.9.5
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Re: [PATCH 3/3] ARM: imx: enable RBC to support anatop LPM mode
On Wed, Mar 20, 2013 at 05:01:19PM +0800, Shawn Guo wrote:
On Wed, Mar 20, 2013 at 01:39:40PM -0400, Anson Huang wrote:
RBC is to control whether some ANATOP sub modules
can enter lpm mode when SOC is into STOP mode, if
RBC is enabled and PMIC_VSTBY_REQ is set, ANATOP
will have below behaviors:
1. Digital LDOs(CORE, SOC and PU) are bypassed;
2. Analog LDOs(1P1, 2P5, 3P0) are disabled;
As the 2P5 is necessary for DRAM IO pre-drive in
STOP mode, so we need to enable weak 2P5 in STOP
mode when 2P5 LDO is disabled.
For RBC settings, there are some rules as below
due to hardware designe:
s/designe/design
Accepted.
1. All interrupts must be masked during operating
RBC registers;
2. At least 2 CKIL(32K) cycles is needed after the
RBC setting is changed.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/anatop.c| 19 +++
arch/arm/mach-imx/clk-imx6q.c | 35 +++
arch/arm/mach-imx/common.h|3 +++
arch/arm/mach-imx/gpc.c | 21 -
arch/arm/mach-imx/pm-imx6q.c |2 ++
5 files changed, 79 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 8f6ab27..38b4f44 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -18,12 +18,29 @@
#define REG_SET0x4
#define REG_CLR0x8
+#define ANA_MISC0 0x150
#define ANA_REG_CORE 0x140
+#define ANA_REG_2P50x130
Please put these registers in acceding offset.
Accepted.
+#define BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG 0x4
+#define BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG 0x1000
#define BM_ANADIG_REG_CORE_FET_ODRIVE 0x2000
static struct regmap *anatop;
+void imx_anatop_enable_weak2p5(bool enable)
static
Accepted.
+{
+ u32 val;
+
+ regmap_read(anatop, ANA_MISC0, val);
+
+ /* can only be enabled when stop_mode_config is clear. */
+ regmap_write(anatop, ANA_REG_2P5 + ((enable
+ ((val BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG)
+ == 0)) ? REG_SET : REG_CLR),
+ BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
It's a little difficult to parse the expression even it's on the same
line, not mentioning with indentation. There are so many levels of
parentheses.
((enable ((val BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0)) ? REG_SET
: REG_CLR)
What about rewriting it as below to make it easy for people to read?
reg = ANA_REG_2P5;
reg += (enable (val BM_ANADIG_ANA_MISC0_STOP_MODE_CONFIG) == 0) ?
REG_SET : REG_CLR;
regmap_write(anatop, reg, BM_ANADIG_REG_2P5_ENABLE_WEAK_LINREG);
Accepted.
+}
+
void imx_anatop_enable_fet_odrive(bool enable)
{
regmap_write(anatop, ANA_REG_CORE + (enable ?
@@ -32,12 +49,14 @@ void imx_anatop_enable_fet_odrive(bool enable)
void imx_anatop_pre_suspend(void)
{
+ imx_anatop_enable_weak2p5(true);
imx_anatop_enable_fet_odrive(true);
}
void imx_anatop_post_resume(void)
{
imx_anatop_enable_fet_odrive(false);
+ imx_anatop_enable_weak2p5(false);
}
void __init imx_anatop_init(void)
diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c
index b365efc..646ce12 100644
--- a/arch/arm/mach-imx/clk-imx6q.c
+++ b/arch/arm/mach-imx/clk-imx6q.c
@@ -14,6 +14,7 @@
#include linux/types.h
#include linux/clk.h
#include linux/clkdev.h
+#include linux/delay.h
#include linux/err.h
#include linux/io.h
#include linux/of.h
@@ -25,6 +26,8 @@
#define CCR0x0
#define BM_CCR_WB_COUNT(0x7 16)
+#define BM_CCR_RBC_BYPASS_COUNT(0x3f 21)
+#define BM_CCR_RBC_EN (0x1 27)
#define CCGR0 0x68
#define CCGR1 0x6c
@@ -70,6 +73,38 @@ void imx6q_set_chicken_bit(void)
writel_relaxed(val, ccm_base + CGPR);
}
+void imx6q_set_rbc(bool enable)
Same question as imx6q_set_wb, can we manage to call it in
imx6q_set_lpm()? The intension behind this is we should try to
a centralized place to configure CCM registers/bits for suspend
instead of exporting so many functions to suspend routine to call
individually.
Will do it in the way as well bias did.
+{
+ u32 val;
+
+ /*
+* need to mask all interrupts in GPC before
+* operating RBC configurations
+*/
+ imx_gpc_mask_all();
+
+ /* configurate RBC enable bit */
s/configurate/configure
Accepted.
+ val = readl_relaxed(ccm_base + CCR);
+ val = ~BM_CCR_RBC_EN;
+ val |= enable ? BM_CCR_RBC_EN : 0;
+ writel_relaxed(val, ccm_base + CCR);
+
+ /* configurate RBC count */
Ditto
Accepted.
+ val = readl_relaxed(ccm_base + CCR
[PATCH 2/2] regulators: anatop: add set_voltage_time_sel interface
some of anatop's regulators(vppcpu, vddpu and vddsoc) have
register settings about LDO's step time, which will impact
the LDO ramp up speed, need to use set_voltage_time_sel
interface to add necessary delay everytime LDOs' voltage
is increased.
offset 0x170:
bit [24-25]: vddcpu
bit [26-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/regulator/anatop-regulator.c | 42 ++
1 file changed, 42 insertions(+)
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index 8f39cac..a857b9c 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -31,12 +31,18 @@
#include linux/regulator/driver.h
#include linux/regulator/of_regulator.h
+#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
struct anatop_regulator {
const char *name;
u32 control_reg;
struct regmap *anatop;
int vol_bit_shift;
int vol_bit_width;
+ u32 delay_reg;
+ int delay_bit_shift;
+ int delay_bit_width;
int min_bit_val;
int min_voltage;
int max_voltage;
@@ -55,6 +61,33 @@ static int anatop_regmap_set_voltage_sel(struct
regulator_dev *reg,
return regulator_set_voltage_sel_regmap(reg, selector);
}
+static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
+ unsigned int old_sel,
+ unsigned int new_sel)
+{
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+ u32 val;
+ int ret = 0;
+
+ /* check whether need to care about LDO ramp up speed */
+ if (anatop_reg-delay_reg) {
+ /*
+* the delay for LDO ramp up time is
+* based on the register setting, we need
+* to calculate how many steps LDO need to
+* ramp up, and how much delay needed. (us)
+*/
+ regmap_read(anatop_reg-anatop, anatop_reg-delay_reg, val);
+ val = (val anatop_reg-delay_bit_shift)
+ ((1 anatop_reg-delay_bit_width) - 1);
+ ret = new_sel old_sel ? (new_sel - old_sel) *
+ ((LDO_RAMP_UP_UNIT_IN_CYCLES val) /
+ LDO_RAMP_UP_FREQ_IN_MHZ + 1) : 0;
+ }
+
+ return ret;
+}
+
static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
@@ -67,6 +100,7 @@ static int anatop_regmap_get_voltage_sel(struct
regulator_dev *reg)
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
+ .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
@@ -143,6 +177,14 @@ static int anatop_regulator_probe(struct platform_device
*pdev)
goto anatop_probe_end;
}
+ /* read LDO ramp up setting, only for core reg */
+ of_property_read_u32(np, anatop-delay-reg-offset,
+sreg-delay_reg);
+ of_property_read_u32(np, anatop-delay-bit-width,
+sreg-delay_bit_width);
+ of_property_read_u32(np, anatop-delay-bit-shift,
+sreg-delay_bit_shift);
+
rdesc-n_voltages = (sreg-max_voltage - sreg-min_voltage) / 25000 + 1
+ sreg-min_bit_val;
rdesc-min_uV = sreg-min_voltage;
--
1.7.9.5
--
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[PATCH] regulators: anatop: add set_voltage_time_sel interface
some of anatop's regulators(vppcpu, vddpu and vddsoc) have
register settings about LDO's step time, which will impact
the LDO ramp up speed, need to use set_voltage_time_sel
interface to add necessary delay everytime LDOs' voltage
is increased.
offset 0x170:
bit [24-25]: vddcpu
bit [26-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang b20...@freescale.com
---
.../bindings/regulator/anatop-regulator.txt|6 +++
drivers/regulator/anatop-regulator.c | 42
2 files changed, 48 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
index 357758c..b3a08f8 100644
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -5,6 +5,9 @@ Required properties:
- anatop-reg-offset: Anatop MFD register offset
- anatop-vol-bit-shift: Bit shift for the register
- anatop-vol-bit-width: Number of bits used in the register
+- anatop-delay-reg-offset: Anatop MFD step time register offset
+- anatop-delay-bit-shift: Bit shift for the step time register
+- anatop-delay-bit-width: Number of bits used in the step time register
- anatop-min-bit-val: Minimum value of this register
- anatop-min-voltage: Minimum voltage of this regulator
- anatop-max-voltage: Maximum voltage of this regulator
@@ -23,6 +26,9 @@ Example:
anatop-reg-offset = 0x140;
anatop-vol-bit-shift = 9;
anatop-vol-bit-width = 5;
+ anatop-delay-reg-offset = 0x170;
+ anatop-delay-bit-shift = 24;
+ anatop-delay-bit-width = 2;
anatop-min-bit-val = 1;
anatop-min-voltage = 725000;
anatop-max-voltage = 130;
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index 8f39cac..a857b9c 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -31,12 +31,18 @@
#include linux/regulator/driver.h
#include linux/regulator/of_regulator.h
+#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
struct anatop_regulator {
const char *name;
u32 control_reg;
struct regmap *anatop;
int vol_bit_shift;
int vol_bit_width;
+ u32 delay_reg;
+ int delay_bit_shift;
+ int delay_bit_width;
int min_bit_val;
int min_voltage;
int max_voltage;
@@ -55,6 +61,33 @@ static int anatop_regmap_set_voltage_sel(struct
regulator_dev *reg,
return regulator_set_voltage_sel_regmap(reg, selector);
}
+static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
+ unsigned int old_sel,
+ unsigned int new_sel)
+{
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+ u32 val;
+ int ret = 0;
+
+ /* check whether need to care about LDO ramp up speed */
+ if (anatop_reg-delay_reg) {
+ /*
+* the delay for LDO ramp up time is
+* based on the register setting, we need
+* to calculate how many steps LDO need to
+* ramp up, and how much delay needed. (us)
+*/
+ regmap_read(anatop_reg-anatop, anatop_reg-delay_reg, val);
+ val = (val anatop_reg-delay_bit_shift)
+ ((1 anatop_reg-delay_bit_width) - 1);
+ ret = new_sel old_sel ? (new_sel - old_sel) *
+ ((LDO_RAMP_UP_UNIT_IN_CYCLES val) /
+ LDO_RAMP_UP_FREQ_IN_MHZ + 1) : 0;
+ }
+
+ return ret;
+}
+
static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
@@ -67,6 +100,7 @@ static int anatop_regmap_get_voltage_sel(struct
regulator_dev *reg)
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
+ .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
@@ -143,6 +177,14 @@ static int anatop_regulator_probe(struct platform_device
*pdev)
goto anatop_probe_end;
}
+ /* read LDO ramp up setting, only for core reg */
+ of_property_read_u32(np, anatop-delay-reg-offset,
+sreg-delay_reg);
+ of_property_read_u32(np, anatop-delay-bit-width,
+sreg-delay_bit_width);
+ of_property_read_u32(np, anatop-delay-bit-shift
[PATCH V2] regulators: anatop: add set_voltage_time_sel interface
some of anatop's regulators(cpu, vddpu and vddsoc) have
register settings about LDO's step time, which will impact
the LDO ramp up speed, need to use set_voltage_time_sel
interface to add necessary delay everytime LDOs' voltage
is increased.
offset 0x170:
bit [24-25]: cpu
bit [26-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang b20...@freescale.com
---
.../bindings/regulator/anatop-regulator.txt|8
drivers/regulator/anatop-regulator.c | 42
2 files changed, 50 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
index 357758c..758eae2 100644
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -9,6 +9,11 @@ Required properties:
- anatop-min-voltage: Minimum voltage of this regulator
- anatop-max-voltage: Maximum voltage of this regulator
+Optional properties:
+- anatop-delay-reg-offset: Anatop MFD step time register offset
+- anatop-delay-bit-shift: Bit shift for the step time register
+- anatop-delay-bit-width: Number of bits used in the step time register
+
Any property defined as part of the core regulator
binding, defined in regulator.txt, can also be used.
@@ -23,6 +28,9 @@ Example:
anatop-reg-offset = 0x140;
anatop-vol-bit-shift = 9;
anatop-vol-bit-width = 5;
+ anatop-delay-reg-offset = 0x170;
+ anatop-delay-bit-shift = 24;
+ anatop-delay-bit-width = 2;
anatop-min-bit-val = 1;
anatop-min-voltage = 725000;
anatop-max-voltage = 130;
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index 8f39cac..fe79d24 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -31,12 +31,18 @@
#include linux/regulator/driver.h
#include linux/regulator/of_regulator.h
+#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
struct anatop_regulator {
const char *name;
u32 control_reg;
struct regmap *anatop;
int vol_bit_shift;
int vol_bit_width;
+ u32 delay_reg;
+ int delay_bit_shift;
+ int delay_bit_width;
int min_bit_val;
int min_voltage;
int max_voltage;
@@ -55,6 +61,33 @@ static int anatop_regmap_set_voltage_sel(struct
regulator_dev *reg,
return regulator_set_voltage_sel_regmap(reg, selector);
}
+static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
+ unsigned int old_sel,
+ unsigned int new_sel)
+{
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+ u32 val;
+ int ret = 0;
+
+ /* check whether need to care about LDO ramp up speed */
+ if (anatop_reg-delay_bit_width) {
+ /*
+* the delay for LDO ramp up time is
+* based on the register setting, we need
+* to calculate how many steps LDO need to
+* ramp up, and how much delay needed. (us)
+*/
+ regmap_read(anatop_reg-anatop, anatop_reg-delay_reg, val);
+ val = (val anatop_reg-delay_bit_shift)
+ ((1 anatop_reg-delay_bit_width) - 1);
+ ret = new_sel old_sel ? (new_sel - old_sel) *
+ ((LDO_RAMP_UP_UNIT_IN_CYCLES val) /
+ LDO_RAMP_UP_FREQ_IN_MHZ + 1) : 0;
+ }
+
+ return ret;
+}
+
static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
@@ -67,6 +100,7 @@ static int anatop_regmap_get_voltage_sel(struct
regulator_dev *reg)
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
+ .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
@@ -143,6 +177,14 @@ static int anatop_regulator_probe(struct platform_device
*pdev)
goto anatop_probe_end;
}
+ /* read LDO ramp up setting, only for core reg */
+ of_property_read_u32(np, anatop-delay-reg-offset,
+sreg-delay_reg);
+ of_property_read_u32(np, anatop-delay-bit-width,
+sreg-delay_bit_width);
+ of_property_read_u32(np, anatop-delay-bit-shift,
+sreg-delay_bit_shift);
+
rdesc-n_voltages
[PATCH V3] regulators: anatop: add set_voltage_time_sel interface
some of anatop's regulators(cpu, vddpu and vddsoc) have
register settings about LDO's step time, which will impact
the LDO ramp up speed, need to use set_voltage_time_sel
interface to add necessary delay everytime LDOs' voltage
is increased.
offset 0x170:
bit [24-25]: cpu
bit [26-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang b20...@freescale.com
---
.../bindings/regulator/anatop-regulator.txt|8
drivers/regulator/anatop-regulator.c | 41
2 files changed, 49 insertions(+)
diff --git a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
index 357758c..758eae2 100644
--- a/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
+++ b/Documentation/devicetree/bindings/regulator/anatop-regulator.txt
@@ -9,6 +9,11 @@ Required properties:
- anatop-min-voltage: Minimum voltage of this regulator
- anatop-max-voltage: Maximum voltage of this regulator
+Optional properties:
+- anatop-delay-reg-offset: Anatop MFD step time register offset
+- anatop-delay-bit-shift: Bit shift for the step time register
+- anatop-delay-bit-width: Number of bits used in the step time register
+
Any property defined as part of the core regulator
binding, defined in regulator.txt, can also be used.
@@ -23,6 +28,9 @@ Example:
anatop-reg-offset = 0x140;
anatop-vol-bit-shift = 9;
anatop-vol-bit-width = 5;
+ anatop-delay-reg-offset = 0x170;
+ anatop-delay-bit-shift = 24;
+ anatop-delay-bit-width = 2;
anatop-min-bit-val = 1;
anatop-min-voltage = 725000;
anatop-max-voltage = 130;
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index 8f39cac..0df9c6a 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -31,12 +31,18 @@
#include linux/regulator/driver.h
#include linux/regulator/of_regulator.h
+#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
struct anatop_regulator {
const char *name;
u32 control_reg;
struct regmap *anatop;
int vol_bit_shift;
int vol_bit_width;
+ u32 delay_reg;
+ int delay_bit_shift;
+ int delay_bit_width;
int min_bit_val;
int min_voltage;
int max_voltage;
@@ -55,6 +61,32 @@ static int anatop_regmap_set_voltage_sel(struct
regulator_dev *reg,
return regulator_set_voltage_sel_regmap(reg, selector);
}
+static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
+ unsigned int old_sel,
+ unsigned int new_sel)
+{
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+ u32 val;
+ int ret = 0;
+
+ /* check whether need to care about LDO ramp up speed */
+ if (anatop_reg-delay_bit_width new_sel old_sel) {
+ /*
+* the delay for LDO ramp up time is
+* based on the register setting, we need
+* to calculate how many steps LDO need to
+* ramp up, and how much delay needed. (us)
+*/
+ regmap_read(anatop_reg-anatop, anatop_reg-delay_reg, val);
+ val = (val anatop_reg-delay_bit_shift)
+ ((1 anatop_reg-delay_bit_width) - 1);
+ ret = (new_sel - old_sel) * ((LDO_RAMP_UP_UNIT_IN_CYCLES
+ val) / LDO_RAMP_UP_FREQ_IN_MHZ + 1);
+ }
+
+ return ret;
+}
+
static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
@@ -67,6 +99,7 @@ static int anatop_regmap_get_voltage_sel(struct regulator_dev
*reg)
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
+ .set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
@@ -143,6 +176,14 @@ static int anatop_regulator_probe(struct platform_device
*pdev)
goto anatop_probe_end;
}
+ /* read LDO ramp up setting, only for core reg */
+ of_property_read_u32(np, anatop-delay-reg-offset,
+sreg-delay_reg);
+ of_property_read_u32(np, anatop-delay-bit-width,
+sreg-delay_bit_width);
+ of_property_read_u32(np, anatop-delay-bit-shift,
+sreg-delay_bit_shift);
+
rdesc-n_voltages = (sreg-max_voltage - sreg
Re: [PATCH 2/2] regulators: anatop: add set_voltage_time_sel interface
On Wed, Jan 30, 2013 at 02:30:47PM -0700, Troy Kisky wrote:
On 1/30/2013 3:37 PM, Anson Huang wrote:
some of anatop's regulators(vppcpu, vddpu and vddsoc) have
register settings about LDO's step time, which will impact
the LDO ramp up speed, need to use set_voltage_time_sel
interface to add necessary delay everytime LDOs' voltage
is increased.
offset 0x170:
bit [24-25]: vddcpu
bit [26-27]: vddpu
bit [28-29]: vddsoc
field definition:
0'b00: 64 cycles of 24M clock;
0'b01: 128 cycles of 24M clock;
0'b02: 256 cycles of 24M clock;
0'b03: 512 cycles of 24M clock;
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/regulator/anatop-regulator.c | 42
++
1 file changed, 42 insertions(+)
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index 8f39cac..a857b9c 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -31,12 +31,18 @@
#include linux/regulator/driver.h
#include linux/regulator/of_regulator.h
+#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
+#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
+
struct anatop_regulator {
const char *name;
u32 control_reg;
struct regmap *anatop;
int vol_bit_shift;
int vol_bit_width;
+u32 delay_reg;
+int delay_bit_shift;
+int delay_bit_width;
int min_bit_val;
int min_voltage;
int max_voltage;
@@ -55,6 +61,33 @@ static int anatop_regmap_set_voltage_sel(struct
regulator_dev *reg,
return regulator_set_voltage_sel_regmap(reg, selector);
}
+static int anatop_regmap_set_voltage_time_sel(struct regulator_dev *reg,
+unsigned int old_sel,
+unsigned int new_sel)
+{
+struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+u32 val;
+int ret = 0;
+
+/* check whether need to care about LDO ramp up speed */
+if (anatop_reg-delay_reg) {
+/*
+ * the delay for LDO ramp up time is
+ * based on the register setting, we need
+ * to calculate how many steps LDO need to
+ * ramp up, and how much delay needed. (us)
+ */
+regmap_read(anatop_reg-anatop, anatop_reg-delay_reg, val);
+val = (val anatop_reg-delay_bit_shift)
+((1 anatop_reg-delay_bit_width) - 1);
+ret = new_sel old_sel ? (new_sel - old_sel) *
The (new_sel old_sel) could be part of the above if.
if (anatop_reg-delay_reg new_sel old_sel)
[Anson Huang]Good point, accepted. Please help review my v3 patch,thanks!
+((LDO_RAMP_UP_UNIT_IN_CYCLES val) /
+LDO_RAMP_UP_FREQ_IN_MHZ + 1) : 0;
+}
+
+return ret;
+}
+
static int anatop_regmap_get_voltage_sel(struct regulator_dev *reg)
{
struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
@@ -67,6 +100,7 @@ static int anatop_regmap_get_voltage_sel(struct
regulator_dev *reg)
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
+.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
@@ -143,6 +177,14 @@ static int anatop_regulator_probe(struct
platform_device *pdev)
goto anatop_probe_end;
}
+/* read LDO ramp up setting, only for core reg */
+of_property_read_u32(np, anatop-delay-reg-offset,
+ sreg-delay_reg);
+of_property_read_u32(np, anatop-delay-bit-width,
+ sreg-delay_bit_width);
+of_property_read_u32(np, anatop-delay-bit-shift,
+ sreg-delay_bit_shift);
+
rdesc-n_voltages = (sreg-max_voltage - sreg-min_voltage) / 25000 + 1
+ sreg-min_bit_val;
rdesc-min_uV = sreg-min_voltage;
--
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[PATCH 2/4] regulator: anatop: add is_enabled interface
Add is_enabled interface for anatop regulator in case
some drivers need to know regulator's status.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/regulator/anatop-regulator.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index c734d09..770d836 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -97,10 +97,25 @@ static int anatop_regmap_get_voltage_sel(struct
regulator_dev *reg)
return regulator_get_voltage_sel_regmap(reg);
}
+static int anatop_regmap_is_enabled(struct regulator_dev *reg)
+{
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+ u32 val;
+
+ if (!anatop_reg-control_reg)
+ return -ENOTSUPP;
+
+ regmap_read(anatop_reg-anatop, anatop_reg-control_reg, val);
+
+ return (val anatop_reg-vol_bit_shift)
+ ((1 anatop_reg-vol_bit_width) - 1) ? 1 : 0;
+}
+
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
+ .is_enabled = anatop_regmap_is_enabled,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
};
--
1.7.9.5
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[PATCH] regulator: anatop: add is_enabled interface
Add is_enabled interface for anatop regulator in case
some drivers need to know regulator's status.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/regulator/anatop-regulator.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/drivers/regulator/anatop-regulator.c
b/drivers/regulator/anatop-regulator.c
index c734d09..770d836 100644
--- a/drivers/regulator/anatop-regulator.c
+++ b/drivers/regulator/anatop-regulator.c
@@ -97,10 +97,25 @@ static int anatop_regmap_get_voltage_sel(struct
regulator_dev *reg)
return regulator_get_voltage_sel_regmap(reg);
}
+static int anatop_regmap_is_enabled(struct regulator_dev *reg)
+{
+ struct anatop_regulator *anatop_reg = rdev_get_drvdata(reg);
+ u32 val;
+
+ if (!anatop_reg-control_reg)
+ return -ENOTSUPP;
+
+ regmap_read(anatop_reg-anatop, anatop_reg-control_reg, val);
+
+ return (val anatop_reg-vol_bit_shift)
+ ((1 anatop_reg-vol_bit_width) - 1) ? 1 : 0;
+}
+
static struct regulator_ops anatop_rops = {
.set_voltage_sel = anatop_regmap_set_voltage_sel,
.set_voltage_time_sel = anatop_regmap_set_voltage_time_sel,
.get_voltage_sel = anatop_regmap_get_voltage_sel,
+ .is_enabled = anatop_regmap_is_enabled,
.list_voltage = regulator_list_voltage_linear,
.map_voltage = regulator_map_voltage_linear,
};
--
1.7.9.5
--
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[PATCH] thermal: imx: correct suspend/resume flow
Current imx thermal sensor's suspend function will return fail if
thermal sensor is always enabled, but because alarm function is enabled,
thermal sensor will be always enabled as well, hence break system's suspend,
this patch will disable thermal sensor before suspend and re-enable it
after resume, it fixes the failure of suspend/resume caused by thermal driver.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/thermal/imx_thermal.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index cbb16f3..9a9a6c2 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -510,27 +510,30 @@ static int imx_thermal_suspend(struct device *dev)
{
struct imx_thermal_data *data = dev_get_drvdata(dev);
struct regmap *map = data-tempmon;
- u32 val;
- regmap_read(map, TEMPSENSE0, val);
- if ((val TEMPSENSE0_POWER_DOWN) == 0) {
- /*
-* If a measurement is taking place, wait for a long enough
-* time for it to finish, and then check again. If it still
-* does not finish, something must go wrong.
-*/
- udelay(50);
- regmap_read(map, TEMPSENSE0, val);
- if ((val TEMPSENSE0_POWER_DOWN) == 0)
- return -ETIMEDOUT;
- }
+ /*
+* Need to disable thermal sensor, otherwise, when thermal core
+* try to get temperature before thermal sensor resume, a wrong
+* temperature will be read as the thermal sensor is powered
+* down.
+*/
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
+ data-mode = THERMAL_DEVICE_DISABLED;
return 0;
}
static int imx_thermal_resume(struct device *dev)
{
- /* Nothing to do for now */
+ struct imx_thermal_data *data = dev_get_drvdata(dev);
+ struct regmap *map = data-tempmon;
+
+ /* Enabled thermal sensor after resume */
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+ data-mode = THERMAL_DEVICE_ENABLED;
+
return 0;
}
#endif
--
1.7.9.5
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[PATCH V2] thermal: imx: correct suspend/resume flow
Fixes regression introduced by:
commit 37713a1e8e4c1a1067ad4c99296f78d3c82ed9c4
Author: Philipp Zabel p.za...@pengutronix.de
Date: Thu Aug 1 18:33:12 2013 +0200
thermal: imx: implement thermal alarm interrupt handling
The commit 37713a1e8e4 makes imx thermal sensor always powered up as alarm
function is enabled, but the suspend callback of imx thermal returns
success only if thermal sensor is powered down, so it will always returns
fail hence break system's suspend, this patch disables imx thermal sensor
before suspend and re-enable it after resume.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/thermal/imx_thermal.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index cbb16f3..9a9a6c2 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -510,27 +510,30 @@ static int imx_thermal_suspend(struct device *dev)
{
struct imx_thermal_data *data = dev_get_drvdata(dev);
struct regmap *map = data-tempmon;
- u32 val;
- regmap_read(map, TEMPSENSE0, val);
- if ((val TEMPSENSE0_POWER_DOWN) == 0) {
- /*
-* If a measurement is taking place, wait for a long enough
-* time for it to finish, and then check again. If it still
-* does not finish, something must go wrong.
-*/
- udelay(50);
- regmap_read(map, TEMPSENSE0, val);
- if ((val TEMPSENSE0_POWER_DOWN) == 0)
- return -ETIMEDOUT;
- }
+ /*
+* Need to disable thermal sensor, otherwise, when thermal core
+* try to get temperature before thermal sensor resume, a wrong
+* temperature will be read as the thermal sensor is powered
+* down.
+*/
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN);
+ data-mode = THERMAL_DEVICE_DISABLED;
return 0;
}
static int imx_thermal_resume(struct device *dev)
{
- /* Nothing to do for now */
+ struct imx_thermal_data *data = dev_get_drvdata(dev);
+ struct regmap *map = data-tempmon;
+
+ /* Enabled thermal sensor after resume */
+ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN);
+ regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP);
+ data-mode = THERMAL_DEVICE_ENABLED;
+
return 0;
}
#endif
--
1.7.9.5
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[PATCH] ARM: imx: improve the comment of CCM lpm SW workaround
Improve the comment of SW workaround for CCM lpm issue using hardware errata description to avoid confusion. TKT194736: Chip will enter low power mode before ARM A9 CPU executes WFI when improper low power sequence is used. SW workaround: 1) SW will trigger irq #32(IOMUX) to be always pending manually by setting IOMUX_GPR1_GINT bit, 2) SW should then Unmask it in GPC before setting CCM LPM 3) SW should Mask it right after CCM LPM is set (set bit0-1 of CCM_CLPCR) Signed-off-by: Anson Huang b20...@freescale.com --- arch/arm/mach-imx/pm-imx6q.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index aecd9f8..8da4732 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -156,10 +156,13 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) } /* -* Unmask the always pending IOMUXC interrupt #32 as wakeup source to -* deassert dsm_request signal, so that we can ensure dsm_request -* is not asserted when we're going to write CLPCR register to set LPM. -* After setting up LPM bits, we need to mask this wakeup source. +* TKT194736: +* Chip will enter low power mode before ARM A9 CPU executes WFI when improper low power sequence is used. +* +* SW workaround: +* 1) SW will trigger irq #32(IOMUXC) to be always pending manually by setting IOMUX_GPR1_GINT bit, +* 2) SW should then Unmask it in GPC before setting CCM LPM +* 3) SW should Mask it right after CCM LPM is set (set bit0-1 of CCM_CLPCR) */ iomuxc_irq_desc = irq_to_desc(32); imx_gpc_irq_unmask(iomuxc_irq_desc-irq_data); @@ -219,6 +222,8 @@ void __init imx6q_pm_init(void) WARN_ON(!ccm_base); /* +* This is for SW workaround step #1 of TKT194736, see comments +* in imx6q_set_lpm for details of this errata. * Force IOMUXC irq pending, so that the interrupt to GPC can be * used to deassert dsm_request signal when the signal gets * asserted unexpectedly. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] ARM: imx: add necessary interface for pfd
Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.
PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: Anson Huang b20...@freescale.com
---
arch/arm/mach-imx/clk-pfd.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/mach-imx/clk-pfd.c b/arch/arm/mach-imx/clk-pfd.c
index e2ed416..0b0f6f6 100644
--- a/arch/arm/mach-imx/clk-pfd.c
+++ b/arch/arm/mach-imx/clk-pfd.c
@@ -109,12 +109,23 @@ static int clk_pfd_set_rate(struct clk_hw *hw, unsigned
long rate,
return 0;
}
+static int clk_pfd_is_enabled(struct clk_hw *hw)
+{
+ struct clk_pfd *pfd = to_clk_pfd(hw);
+
+ if (readl_relaxed(pfd-reg) (1 ((pfd-idx + 1) * 8 - 1)))
+ return 0;
+
+ return 1;
+}
+
static const struct clk_ops clk_pfd_ops = {
.enable = clk_pfd_enable,
.disable= clk_pfd_disable,
.recalc_rate= clk_pfd_recalc_rate,
.round_rate = clk_pfd_round_rate,
.set_rate = clk_pfd_set_rate,
+ .is_enabled = clk_pfd_is_enabled,
};
struct clk *imx_clk_pfd(const char *name, const char *parent_name,
--
1.7.9.5
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[PATCH] ARM: imx: improve status check of clock gate
For ccm clock gate, both 2b'11 and 2b'01 should be treated as clock enabled, see below description in CCM, whenver CPU trys to check clock gate's status, system will be in run mode. 2b'00: clock is off during all modes; 2b'01: clock is on in run mode, but off in wait and stop mode; 2b'10: Not applicable; 2b'11: clock is on during all modes, except stop mode. Signed-off-by: Anson Huang b20...@freescale.com --- arch/arm/mach-imx/clk-gate2.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/clk-gate2.c b/arch/arm/mach-imx/clk-gate2.c index a63e415..a2ecc00 100644 --- a/arch/arm/mach-imx/clk-gate2.c +++ b/arch/arm/mach-imx/clk-gate2.c @@ -72,7 +72,7 @@ static int clk_gate2_is_enabled(struct clk_hw *hw) reg = readl(gate-reg); - if (((reg gate-bit_idx) 3) == 3) + if (((reg gate-bit_idx) 1) == 1) return 1; return 0; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH V2] ARM: imx: improve the comment of CCM lpm SW workaround
Improve the comment of SW workaround for CCM lpm issue using hardware errata description to avoid confusion. ERR007265: CCM: When improper low-power sequence is used, the SoC enters low power mode before the ARM core executes WFI. Software workaround: 1) Software should trigger IRQ #32 (IOMUX) to be always pending by setting IOMUX_GPR1_GINT. 2) Software should then unmask IRQ #32 in GPC before setting CCM Low-Power mode. 3) Software should mask IRQ #32 right after CCM Low-Power mode is set (set bits 0-1 of CCM_CLPCR). Signed-off-by: Anson Huang b20...@freescale.com --- arch/arm/mach-imx/pm-imx6q.c | 13 + 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/arm/mach-imx/pm-imx6q.c b/arch/arm/mach-imx/pm-imx6q.c index aecd9f8..31cb9d6 100644 --- a/arch/arm/mach-imx/pm-imx6q.c +++ b/arch/arm/mach-imx/pm-imx6q.c @@ -156,10 +156,13 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode) } /* -* Unmask the always pending IOMUXC interrupt #32 as wakeup source to -* deassert dsm_request signal, so that we can ensure dsm_request -* is not asserted when we're going to write CLPCR register to set LPM. -* After setting up LPM bits, we need to mask this wakeup source. +* ERR007265: +* CCM: When improper low-power sequence is used, the SoC enters low power mode before the ARM core executes WFI. +* +* Software workaround: +* 1) Software should trigger IRQ #32 (IOMUX) to be always pending by setting IOMUX_GPR1_GINT. +* 2) Software should then unmask IRQ #32 in GPC before setting CCM Low-Power mode. +* 3) Software should mask IRQ #32 right after CCM Low-Power mode is set (set bits 0-1 of CCM_CLPCR). */ iomuxc_irq_desc = irq_to_desc(32); imx_gpc_irq_unmask(iomuxc_irq_desc-irq_data); @@ -219,6 +222,8 @@ void __init imx6q_pm_init(void) WARN_ON(!ccm_base); /* +* This is for SW workaround step #1 of ERR007265, see comments +* in imx6q_set_lpm for details of this errata. * Force IOMUXC irq pending, so that the interrupt to GPC can be * used to deassert dsm_request signal when the signal gets * asserted unexpectedly. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] Thermal: imx: add i.mx6sx thermal support
i.MX6SX has some new features of thermal interrupt function,
there are LOW, HIGH and PANIC irq for thermal sensor, so add
platform data to separate different thermal version;
The reset value of LOW ALARM is 0 which means the highest
temp, so the LOW ALARM will be triggered once irq is enabled,
so we need to correct it before enabling thermal irq;
Enable PANIC ALARM as critical trip point, it will trigger
system reset via SRC module once PANIC IRQ is triggered, it
is pure hardware function, so use it instead of software
reset by cooling device.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|2 +-
drivers/thermal/imx_thermal.c | 88 +---
2 files changed, 76 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
index 1f0f672..95c05b1 100644
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -1,7 +1,7 @@
* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
Required properties:
-- compatible : fsl,imx6q-thermal
+- compatible : fsl,imx6q-tempmon for V1, fsl,imx6sx-tempmon for V2.
- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
control registers, e.g. ANATOP on imx6q.
- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 2c516f2..2276e74 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -19,6 +19,7 @@
#include linux/mfd/syscon.h
#include linux/module.h
#include linux/of.h
+#include linux/of_device.h
#include linux/platform_device.h
#include linux/regmap.h
#include linux/slab.h
@@ -31,6 +32,10 @@
#define MISC0 0x0150
#define MISC0_REFTOP_SELBIASOFF(1 3)
+#define MISC1 0x0160
+#define MISC1_IRQ_TEMPHIGH (1 29)
+#define MISC1_IRQ_TEMPLOW (1 28)
+#define MISC1_IRQ_TEMPPANIC(1 27)
#define TEMPSENSE0 0x0180
#define TEMPSENSE0_ALARM_VALUE_SHIFT 20
@@ -43,6 +48,11 @@
#define TEMPSENSE1 0x0190
#define TEMPSENSE1_MEASURE_FREQ0x
+#define TEMPSENSE2 0x0290
+#define TEMPSENSE2_LOW_VALUE_SHIFT 0
+#define TEMPSENSE2_LOW_VALUE_MASK 0xfff
+#define TEMPSENSE2_PANIC_VALUE_SHIFT 16
+#define TEMPSENSE2_PANIC_VALUE_MASK0xfff
#define OCOTP_ANA1 0x04e0
@@ -66,6 +76,21 @@ enum imx_thermal_trip {
#define FACTOR115976
#define FACTOR24297157
+#define TEMPMON_V1 1
+#define TEMPMON_V2 2
+
+struct thermal_soc_data {
+ u32 version;
+};
+
+static struct thermal_soc_data thermal_imx6q_data = {
+ .version = TEMPMON_V1,
+};
+
+static struct thermal_soc_data thermal_imx6sx_data = {
+ .version = TEMPMON_V2,
+};
+
struct imx_thermal_data {
struct thermal_zone_device *tz;
struct thermal_cooling_device *cdev;
@@ -79,8 +104,21 @@ struct imx_thermal_data {
bool irq_enabled;
int irq;
struct clk *thermal_clk;
+ const struct thermal_soc_data *socdata;
};
+static void imx_set_panic_temp(struct imx_thermal_data *data,
+ signed long panic_temp)
+{
+ struct regmap *map = data-tempmon;
+ int critical_value;
+
+ critical_value = (data-c2 - panic_temp) / data-c1;
+ regmap_write(map, TEMPSENSE2 + REG_CLR, TEMPSENSE2_PANIC_VALUE_MASK);
+ regmap_write(map, TEMPSENSE2 + REG_SET, critical_value
+ TEMPSENSE2_PANIC_VALUE_SHIFT);
+}
+
static void imx_set_alarm_temp(struct imx_thermal_data *data,
signed long alarm_temp)
{
@@ -142,13 +180,15 @@ static int imx_get_temp(struct thermal_zone_device *tz,
unsigned long *temp)
/* See imx_get_sensor_data() for formula derivation */
*temp = data-c2 - n_meas * data-c1;
- /* Update alarm value to next higher trip point */
- if (data-alarm_temp == data-temp_passive *temp =
data-temp_passive)
- imx_set_alarm_temp(data, data-temp_critical);
- if (data-alarm_temp == data-temp_critical *temp
data-temp_passive) {
- imx_set_alarm_temp(data, data-temp_passive);
- dev_dbg(tz-device, thermal alarm off: T %lu\n,
- data-alarm_temp / 1000);
+ /* Update alarm value to next higher trip point, only V1 needs it */
+ if (data-socdata-version == TEMPMON_V1) {
+ if (data-alarm_temp == data-temp_passive *temp =
data-temp_passive)
+ imx_set_alarm_temp(data, data-temp_critical);
+ if (data
Re: [PATCH] Thermal: imx: add i.mx6sx thermal support
On Tue, Aug 05, 2014 at 09:25:53AM -0400, Eduardo Valentin wrote:
Hello Anson,
On Tue, Aug 05, 2014 at 05:12:43PM +0800, Anson Huang wrote:
i.MX6SX has some new features of thermal interrupt function,
there are LOW, HIGH and PANIC irq for thermal sensor, so add
platform data to separate different thermal version;
The reset value of LOW ALARM is 0 which means the highest
temp, so the LOW ALARM will be triggered once irq is enabled,
so we need to correct it before enabling thermal irq;
Enable PANIC ALARM as critical trip point, it will trigger
system reset via SRC module once PANIC IRQ is triggered, it
is pure hardware function, so use it instead of software
reset by cooling device.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|2 +-
drivers/thermal/imx_thermal.c | 88
+---
2 files changed, 76 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
index 1f0f672..95c05b1 100644
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -1,7 +1,7 @@
* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
Required properties:
-- compatible : fsl,imx6q-thermal
+- compatible : fsl,imx6q-tempmon for V1, fsl,imx6sx-tempmon for V2.
It would be kind to document the difference between V1 and V2, don't you
think?
Accepted, will add some brief summary about the new feature added on V2.
- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
control registers, e.g. ANATOP on imx6q.
- fsl,tempmon-data : phandle pointer to fuse controller that contains
TEMPMON
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 2c516f2..2276e74 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -19,6 +19,7 @@
#include linux/mfd/syscon.h
#include linux/module.h
#include linux/of.h
+#include linux/of_device.h
#include linux/platform_device.h
#include linux/regmap.h
#include linux/slab.h
@@ -31,6 +32,10 @@
#define MISC0 0x0150
#define MISC0_REFTOP_SELBIASOFF(1 3)
+#define MISC1 0x0160
+#define MISC1_IRQ_TEMPHIGH (1 29)
+#define MISC1_IRQ_TEMPLOW (1 28)
+#define MISC1_IRQ_TEMPPANIC(1 27)
how about using
+#define MISC1_IRQ_TEMPHIGH BIT(29)
+#define MISC1_IRQ_TEMPLOWBIT(28)
+#define MISC1_IRQ_TEMPPANIC BIT(27)
Accepted, will improve it in V2 patch.
#define TEMPSENSE0 0x0180
#define TEMPSENSE0_ALARM_VALUE_SHIFT 20
@@ -43,6 +48,11 @@
#define TEMPSENSE1 0x0190
#define TEMPSENSE1_MEASURE_FREQ0x
+#define TEMPSENSE2 0x0290
+#define TEMPSENSE2_LOW_VALUE_SHIFT 0
+#define TEMPSENSE2_LOW_VALUE_MASK 0xfff
+#define TEMPSENSE2_PANIC_VALUE_SHIFT 16
+#define TEMPSENSE2_PANIC_VALUE_MASK0xfff
Are the above register offsets and (bit) masks applicable to both
versions? do you mind adding a comment to what is specific to V2?
Accepted, will add comments in V2 patch.
#define OCOTP_ANA1 0x04e0
@@ -66,6 +76,21 @@ enum imx_thermal_trip {
#define FACTOR115976
#define FACTOR24297157
+#define TEMPMON_V1 1
+#define TEMPMON_V2 2
+
where does the V1/V2 nomenclature come from? how about:
+#define TEMPMON_IMX6Q1
+#define TEMPMON_IMX6SX 2
OK.
+struct thermal_soc_data {
+ u32 version;
+};
+
+static struct thermal_soc_data thermal_imx6q_data = {
+ .version = TEMPMON_V1,
+};
+
+static struct thermal_soc_data thermal_imx6sx_data = {
+ .version = TEMPMON_V2,
+};
+
struct imx_thermal_data {
struct thermal_zone_device *tz;
struct thermal_cooling_device *cdev;
@@ -79,8 +104,21 @@ struct imx_thermal_data {
bool irq_enabled;
int irq;
struct clk *thermal_clk;
+ const struct thermal_soc_data *socdata;
};
+static void imx_set_panic_temp(struct imx_thermal_data *data,
+ signed long panic_temp)
+{
+ struct regmap *map = data-tempmon;
+ int critical_value;
+
+ critical_value = (data-c2 - panic_temp) / data-c1;
+ regmap_write(map, TEMPSENSE2 + REG_CLR, TEMPSENSE2_PANIC_VALUE_MASK);
+ regmap_write(map, TEMPSENSE2 + REG_SET, critical_value
+ TEMPSENSE2_PANIC_VALUE_SHIFT);
+}
+
static void imx_set_alarm_temp(struct imx_thermal_data *data,
signed long
[PATCH V2] Thermal: imx: add i.mx6sx thermal support
i.MX6SX has some new features of thermal interrupt function,
there are LOW, HIGH and PANIC irq for thermal sensor, so add
platform data to separate different thermal version;
The reset value of LOW ALARM is 0 which means the highest
temp, so the LOW ALARM will be triggered once irq is enabled,
so we need to correct it before enabling thermal irq;
Enable PANIC ALARM as critical trip point, it will trigger
system reset via SRC module once PANIC IRQ is triggered, it
is pure hardware function, so use it instead of software
reset by cooling device.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|5 +-
drivers/thermal/imx_thermal.c | 89 +---
2 files changed, 80 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
index 1f0f672..3c67bd5 100644
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -1,7 +1,10 @@
* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
Required properties:
-- compatible : fsl,imx6q-thermal
+- compatible : fsl,imx6q-tempmon for i.MX6Q, fsl,imx6sx-tempmon for
i.MX6SX.
+ i.MX6SX has two more IRQs than i.MX6Q, one is IRQ_LOW and the other is
IRQ_PANIC,
+ when temperature is below than low threshold, IRQ_LOW will be triggered,
when temperature
+ is higher than panic threshold, system will auto reboot by SRC module.
- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
control registers, e.g. ANATOP on imx6q.
- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 2c516f2..e8940aa 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -19,6 +19,7 @@
#include linux/mfd/syscon.h
#include linux/module.h
#include linux/of.h
+#include linux/of_device.h
#include linux/platform_device.h
#include linux/regmap.h
#include linux/slab.h
@@ -31,6 +32,11 @@
#define MISC0 0x0150
#define MISC0_REFTOP_SELBIASOFF(1 3)
+#define MISC1 0x0160
+#define MISC1_IRQ_TEMPHIGH (1 29)
+/* Below LOW and PANIC bits are only for TEMPMON_IMX6SX */
+#define MISC1_IRQ_TEMPLOW (1 28)
+#define MISC1_IRQ_TEMPPANIC(1 27)
#define TEMPSENSE0 0x0180
#define TEMPSENSE0_ALARM_VALUE_SHIFT 20
@@ -43,6 +49,12 @@
#define TEMPSENSE1 0x0190
#define TEMPSENSE1_MEASURE_FREQ0x
+/* Below TEMPSENSE2 is only for TEMPMON_IMX6SX */
+#define TEMPSENSE2 0x0290
+#define TEMPSENSE2_LOW_VALUE_SHIFT 0
+#define TEMPSENSE2_LOW_VALUE_MASK 0xfff
+#define TEMPSENSE2_PANIC_VALUE_SHIFT 16
+#define TEMPSENSE2_PANIC_VALUE_MASK0xfff
#define OCOTP_ANA1 0x04e0
@@ -66,6 +78,21 @@ enum imx_thermal_trip {
#define FACTOR115976
#define FACTOR24297157
+#define TEMPMON_IMX6Q 1
+#define TEMPMON_IMX6SX 2
+
+struct thermal_soc_data {
+ u32 version;
+};
+
+static struct thermal_soc_data thermal_imx6q_data = {
+ .version = TEMPMON_IMX6Q,
+};
+
+static struct thermal_soc_data thermal_imx6sx_data = {
+ .version = TEMPMON_IMX6SX,
+};
+
struct imx_thermal_data {
struct thermal_zone_device *tz;
struct thermal_cooling_device *cdev;
@@ -79,8 +106,21 @@ struct imx_thermal_data {
bool irq_enabled;
int irq;
struct clk *thermal_clk;
+ const struct thermal_soc_data *socdata;
};
+static void imx_set_panic_temp(struct imx_thermal_data *data,
+ signed long panic_temp)
+{
+ struct regmap *map = data-tempmon;
+ int critical_value;
+
+ critical_value = (data-c2 - panic_temp) / data-c1;
+ regmap_write(map, TEMPSENSE2 + REG_CLR, TEMPSENSE2_PANIC_VALUE_MASK);
+ regmap_write(map, TEMPSENSE2 + REG_SET, critical_value
+ TEMPSENSE2_PANIC_VALUE_SHIFT);
+}
+
static void imx_set_alarm_temp(struct imx_thermal_data *data,
signed long alarm_temp)
{
@@ -142,13 +182,15 @@ static int imx_get_temp(struct thermal_zone_device *tz,
unsigned long *temp)
/* See imx_get_sensor_data() for formula derivation */
*temp = data-c2 - n_meas * data-c1;
- /* Update alarm value to next higher trip point */
- if (data-alarm_temp == data-temp_passive *temp =
data-temp_passive)
- imx_set_alarm_temp(data, data-temp_critical);
- if (data-alarm_temp == data-temp_critical *temp
data-temp_passive) {
- imx_set_alarm_temp(data, data-temp_passive);
- dev_dbg(tz-device, thermal
[PATCH V3] Thermal: imx: add i.mx6sx thermal support
i.MX6SX has some new features of thermal interrupt function,
there are LOW, HIGH and PANIC irq for thermal sensor, so add
platform data to separate different thermal version;
The reset value of LOW ALARM is 0 which means the highest
temp, so the LOW ALARM will be triggered once irq is enabled,
so we need to correct it before enabling thermal irq;
Enable PANIC ALARM as critical trip point, it will trigger
system reset via SRC module once PANIC IRQ is triggered, it
is pure hardware function, so use it instead of software
reset by cooling device.
Signed-off-by: Anson Huang b20...@freescale.com
---
.../devicetree/bindings/thermal/imx-thermal.txt|5 +-
drivers/thermal/imx_thermal.c | 91 +---
2 files changed, 82 insertions(+), 14 deletions(-)
diff --git a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
index 1f0f672..3c67bd5 100644
--- a/Documentation/devicetree/bindings/thermal/imx-thermal.txt
+++ b/Documentation/devicetree/bindings/thermal/imx-thermal.txt
@@ -1,7 +1,10 @@
* Temperature Monitor (TEMPMON) on Freescale i.MX SoCs
Required properties:
-- compatible : fsl,imx6q-thermal
+- compatible : fsl,imx6q-tempmon for i.MX6Q, fsl,imx6sx-tempmon for
i.MX6SX.
+ i.MX6SX has two more IRQs than i.MX6Q, one is IRQ_LOW and the other is
IRQ_PANIC,
+ when temperature is below than low threshold, IRQ_LOW will be triggered,
when temperature
+ is higher than panic threshold, system will auto reboot by SRC module.
- fsl,tempmon : phandle pointer to system controller that contains TEMPMON
control registers, e.g. ANATOP on imx6q.
- fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index 2c516f2..461bf3d 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -19,6 +19,7 @@
#include linux/mfd/syscon.h
#include linux/module.h
#include linux/of.h
+#include linux/of_device.h
#include linux/platform_device.h
#include linux/regmap.h
#include linux/slab.h
@@ -31,6 +32,11 @@
#define MISC0 0x0150
#define MISC0_REFTOP_SELBIASOFF(1 3)
+#define MISC1 0x0160
+#define MISC1_IRQ_TEMPHIGH (1 29)
+/* Below LOW and PANIC bits are only for TEMPMON_IMX6SX */
+#define MISC1_IRQ_TEMPLOW (1 28)
+#define MISC1_IRQ_TEMPPANIC(1 27)
#define TEMPSENSE0 0x0180
#define TEMPSENSE0_ALARM_VALUE_SHIFT 20
@@ -43,6 +49,12 @@
#define TEMPSENSE1 0x0190
#define TEMPSENSE1_MEASURE_FREQ0x
+/* Below TEMPSENSE2 is only for TEMPMON_IMX6SX */
+#define TEMPSENSE2 0x0290
+#define TEMPSENSE2_LOW_VALUE_SHIFT 0
+#define TEMPSENSE2_LOW_VALUE_MASK 0xfff
+#define TEMPSENSE2_PANIC_VALUE_SHIFT 16
+#define TEMPSENSE2_PANIC_VALUE_MASK0xfff
#define OCOTP_ANA1 0x04e0
@@ -66,6 +78,21 @@ enum imx_thermal_trip {
#define FACTOR115976
#define FACTOR24297157
+#define TEMPMON_IMX6Q 1
+#define TEMPMON_IMX6SX 2
+
+struct thermal_soc_data {
+ u32 version;
+};
+
+static struct thermal_soc_data thermal_imx6q_data = {
+ .version = TEMPMON_IMX6Q,
+};
+
+static struct thermal_soc_data thermal_imx6sx_data = {
+ .version = TEMPMON_IMX6SX,
+};
+
struct imx_thermal_data {
struct thermal_zone_device *tz;
struct thermal_cooling_device *cdev;
@@ -79,8 +106,21 @@ struct imx_thermal_data {
bool irq_enabled;
int irq;
struct clk *thermal_clk;
+ const struct thermal_soc_data *socdata;
};
+static void imx_set_panic_temp(struct imx_thermal_data *data,
+ signed long panic_temp)
+{
+ struct regmap *map = data-tempmon;
+ int critical_value;
+
+ critical_value = (data-c2 - panic_temp) / data-c1;
+ regmap_write(map, TEMPSENSE2 + REG_CLR, TEMPSENSE2_PANIC_VALUE_MASK);
+ regmap_write(map, TEMPSENSE2 + REG_SET, critical_value
+ TEMPSENSE2_PANIC_VALUE_SHIFT);
+}
+
static void imx_set_alarm_temp(struct imx_thermal_data *data,
signed long alarm_temp)
{
@@ -142,13 +182,17 @@ static int imx_get_temp(struct thermal_zone_device *tz,
unsigned long *temp)
/* See imx_get_sensor_data() for formula derivation */
*temp = data-c2 - n_meas * data-c1;
- /* Update alarm value to next higher trip point */
- if (data-alarm_temp == data-temp_passive *temp =
data-temp_passive)
- imx_set_alarm_temp(data, data-temp_critical);
- if (data-alarm_temp == data-temp_critical *temp
data-temp_passive) {
- imx_set_alarm_temp(data, data-temp_passive);
- dev_dbg(tz-device, thermal
[PATCH V2] Thermal: imx: add clk disable/enable for suspend/resume
Thermal sensor's clk is from pll3_usb_otg, per hardware design requirement, need to make sure pll3_usb_otg is disabled before STOP mode is entered, otherwise, all PFDs under it may enter incorrect state, this patch disables pll3_usb_otg before suspend and enables it after resume. Signed-off-by: Anson Huang b20...@freescale.com --- drivers/thermal/imx_thermal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 461bf3d..dc8bcd8 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -600,6 +600,7 @@ static int imx_thermal_suspend(struct device *dev) regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP); regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN); data-mode = THERMAL_DEVICE_DISABLED; + clk_disable_unprepare(data-thermal_clk); return 0; } @@ -609,6 +610,7 @@ static int imx_thermal_resume(struct device *dev) struct imx_thermal_data *data = dev_get_drvdata(dev); struct regmap *map = data-tempmon; + clk_prepare_enable(data-thermal_clk); /* Enabled thermal sensor after resume */ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN); regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP); -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] Thermal: imx: add clk disable/enable for suspend/resume
Thermal sensor's clk is from pll3_usb_otg, per hardware design requirement, need to make sure pll3_usb_otg is disabled before STOP mode is entered, otherwise, all PFDs under it may enter incorrect state, this patch disables pll3_usb_otg before suspend and enables it after resume. Signed-off-by: Anson Huang b20...@freescale.com --- drivers/thermal/imx_thermal.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 461bf3d..03894da 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -600,6 +600,8 @@ static int imx_thermal_suspend(struct device *dev) regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_MEASURE_TEMP); regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_POWER_DOWN); data-mode = THERMAL_DEVICE_DISABLED; + if (!IS_ERR(data-thermal_clk)) + clk_disable_unprepare(data-thermal_clk); return 0; } @@ -609,6 +611,8 @@ static int imx_thermal_resume(struct device *dev) struct imx_thermal_data *data = dev_get_drvdata(dev); struct regmap *map = data-tempmon; + if (!IS_ERR(data-thermal_clk)) + clk_prepare_enable(data-thermal_clk); /* Enabled thermal sensor after resume */ regmap_write(map, TEMPSENSE0 + REG_CLR, TEMPSENSE0_POWER_DOWN); regmap_write(map, TEMPSENSE0 + REG_SET, TEMPSENSE0_MEASURE_TEMP); -- 1.9.1 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH] irqchip/gic: restore global interrupts group settings in distributor
In GIC's distributor initializtion, all global interrupts
are set to group 1, however, after suspend/resume with
ARM/GIC power off/on, distributor does NOT restore
these global interrupts group setting, it will cause
system fail to resume.
This patch adds global interrupts group setting restore
for distributor.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/irqchip/irq-gic.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index a530d9a..c8fa6ee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -532,6 +532,16 @@ static void gic_dist_restore(unsigned int gic_nr)
writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
dist_base + GIC_DIST_ENABLE_SET + i * 4);
+ writel_relaxed(GICD_ENABLE_GRP1, dist_base + GIC_DIST_CTRL);
+
+ /*
+* Optionally set all global interrupts to be group 1.
+*/
+ if (readl_relaxed(dist_base + GIC_DIST_CTRL) GICD_ENABLE_GRP1) {
+ for (i = 32; i gic_irqs; i += 32)
+ writel_relaxed(0x, dist_base + GIC_DIST_IGROUP
+ i * 4 / 32);
+ }
+
writel_relaxed(GICD_ENABLE | GICD_ENABLE_GRP1, dist_base +
GIC_DIST_CTRL);
}
--
1.9.1
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Re: [PATCH] irqchip/gic: restore global interrupts group settings in distributor
On Wed, Aug 05, 2015 at 10:12:35AM +0100, Marc Zyngier wrote:
Hi Anson,
On 05/08/15 17:39, Anson Huang wrote:
In GIC's distributor initializtion, all global interrupts
are set to group 1, however, after suspend/resume with
ARM/GIC power off/on, distributor does NOT restore
these global interrupts group setting, it will cause
system fail to resume.
This patch adds global interrupts group setting restore
for distributor.
Signed-off-by: Anson Huang b20...@freescale.com
---
drivers/irqchip/irq-gic.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index a530d9a..c8fa6ee 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -532,6 +532,16 @@ static void gic_dist_restore(unsigned int gic_nr)
writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
dist_base + GIC_DIST_ENABLE_SET + i * 4);
+ writel_relaxed(GICD_ENABLE_GRP1, dist_base + GIC_DIST_CTRL);
+
+ /*
+* Optionally set all global interrupts to be group 1.
+*/
+ if (readl_relaxed(dist_base + GIC_DIST_CTRL) GICD_ENABLE_GRP1) {
+ for (i = 32; i gic_irqs; i += 32)
+ writel_relaxed(0x, dist_base + GIC_DIST_IGROUP
+ i * 4 / 32);
+ }
+
writel_relaxed(GICD_ENABLE | GICD_ENABLE_GRP1, dist_base +
GIC_DIST_CTRL);
}
I'm afraid you'll have to explain a few more things here.
For GICv1/v2, we exclusively use Group0 interrupts when booted in secure
mode (i.e. we don't use FIQ yet, but RMK and Daniel Thompson have
patches for that). When booted in non-secure, the group configuration is
not accessible (it is secure only).
So the first case is not applicable yet, and the second one is not
possible. Which side are you on?
Thanks,
M.
Hi, Marc
I may NOT know the history of enabling secure/non-secure of GIC very
well, will spend
some time look into it later, during the upstream of our i.MX6UL's
suepnd/resume,
I found patch(19bcd001 ARM: cobble together FIQ backtracing) break kernel
resume function. After
looking into the gic driver, I saw the dist_inti set all global interrupts to
GROUP 1(non-secure), but in
dist_restore, it does NOT restore those settings, after restoring them,
suspend/resume works.
Don't we need to make this GIC distributor settings after resume
aligned with before suspend?
Before suspend, global interrupts are set to non-secure, but after resume, it
is by default set to
secure mode, while cpu controller signal secure interrupts to FIQn, so that is
incorrect, not sure
if my understanding is correct, please correct me if I am wrong.
Thanks.
Anson
--
Jazz is not dead. It just smells funny...
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[PATCH] ARM: imx: add cpuidle support for i.mx6ul
This patch enables cpuidle driver for i.MX6UL, it
reuses i.MX6SX's cpuidle driver, 3 levels of cpuidle
supported:
1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.
As i.MX6UL has cortex-A7 CORE with an internal L2
cache, so need to add L2 cache type check to decide
if to flush L2 when entering idle with ARM power off,
this is different from i.MX6SX which has PL310 external
L2 cache.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/mach-imx/cpuidle-imx6sx.c | 10 ++
arch/arm/mach-imx/mach-imx6ul.c| 3 +++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c
b/arch/arm/mach-imx/cpuidle-imx6sx.c
index 41cdce6..b4fcc8ae 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -9,14 +9,21 @@
#include
#include
#include
+#include
+#include
#include
#include
#include "common.h"
#include "cpuidle.h"
+static bool pl310_available;
+
static int imx6sx_idle_finish(unsigned long val)
{
+ /* check if need to flush internal L2 cache */
+ if (!pl310_available)
+ flush_cache_all();
cpu_do_idle();
return 0;
@@ -101,5 +108,8 @@ int __init imx6sx_cpuidle_init(void)
imx_gpc_set_arm_power_up_timing(2, 1);
imx_gpc_set_arm_power_down_timing(1, 1);
+ if (of_find_compatible_node(NULL, NULL, "arm,pl310-cache"))
+ pl310_available = true;
+
return cpuidle_register(_cpuidle_driver, NULL);
}
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index c2cd61c..9c5e8f3 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -16,6 +16,7 @@
#include
#include "common.h"
+#include "cpuidle.h"
static void __init imx6ul_enet_clk_init(void)
{
@@ -80,6 +81,8 @@ static void __init imx6ul_init_irq(void)
static void __init imx6ul_init_late(void)
{
+ imx6sx_cpuidle_init();
+
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) {
imx6_pm_opp_init();
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
--
1.9.1
[PATCH] ARM: imx: build cpuidle-imx6sx.c for imx6ul
Fix build error when CONFIG_SOC_IMX6SX is disabled, as i.MX6UL reuses i.MX6SX's cpuidle driver. arch/arm/mach-imx/built-in.o: In function `imx6ul_init_late': platform-spi_imx.c:(.init.text+0x445c): undefined reference to `imx6sx_cpuidle_init' make: *** [vmlinux] Error 1 Signed-off-by: Anson Huang <anson.hu...@nxp.com> --- arch/arm/mach-imx/Makefile | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index 2636adf..cab1289 100644 --- a/arch/arm/mach-imx/Makefile +++ b/arch/arm/mach-imx/Makefile @@ -27,6 +27,7 @@ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o endif ifdef CONFIG_SND_IMX_SOC -- 1.9.1
RE: [PATCH] ARM: imx: build cpuidle-imx6sx.c for imx6ul
Sorry, please ignore this patch, Arnd Bergmann <a...@arndb.de> has summited a patch to fix this issue. Best Regards! Anson Huang > -Original Message- > From: linux-arm-kernel [mailto:linux-arm-kernel-boun...@lists.infradead.org] > On Behalf Of Anson Huang > Sent: 2016-09-07 6:31 PM > To: linux-arm-ker...@lists.infradead.org; linux-kernel@vger.kernel.org > Cc: Fabio Estevam Estevam <fabio.este...@nxp.com>; shawn...@kernel.org; > li...@armlinux.org.uk; ker...@pengutronix.de > Subject: [PATCH] ARM: imx: build cpuidle-imx6sx.c for imx6ul > > Fix build error when CONFIG_SOC_IMX6SX is disabled, as i.MX6UL reuses > i.MX6SX's cpuidle driver. > > arch/arm/mach-imx/built-in.o: In function `imx6ul_init_late': > platform-spi_imx.c:(.init.text+0x445c): undefined reference to > `imx6sx_cpuidle_init' > make: *** [vmlinux] Error 1 > > Signed-off-by: Anson Huang <anson.hu...@nxp.com> > --- > arch/arm/mach-imx/Makefile | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile index > 2636adf..cab1289 100644 > --- a/arch/arm/mach-imx/Makefile > +++ b/arch/arm/mach-imx/Makefile > @@ -27,6 +27,7 @@ obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o > obj-$(CONFIG_SOC_IMX6Q) += cpuidle-imx6q.o > obj-$(CONFIG_SOC_IMX6SL) += cpuidle-imx6sl.o > obj-$(CONFIG_SOC_IMX6SX) += cpuidle-imx6sx.o > +obj-$(CONFIG_SOC_IMX6UL) += cpuidle-imx6sx.o > endif > > ifdef CONFIG_SND_IMX_SOC > -- > 1.9.1 > > > ___ > linux-arm-kernel mailing list > linux-arm-ker...@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
[PATCH] ARM: imx: use soc type instead of cpu type for i.MX
i.MX is a SoC rather than a CPU, so for those names
of cpu_is_xxx and cpu_type etc., better to use soc_is_xxx
and soc_type etc. instead, this patch improves these names.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/mach-imx/anatop.c | 6 ++---
arch/arm/mach-imx/common.h | 2 +-
arch/arm/mach-imx/cpu-imx31.c | 12 -
arch/arm/mach-imx/cpu.c| 36 +--
arch/arm/mach-imx/mach-imx1.c | 2 +-
arch/arm/mach-imx/mach-imx25.c | 2 +-
arch/arm/mach-imx/mach-imx51.c | 2 +-
arch/arm/mach-imx/mach-imx53.c | 2 +-
arch/arm/mach-imx/mach-imx6q.c | 10
arch/arm/mach-imx/mm-imx21.c | 2 +-
arch/arm/mach-imx/mm-imx27.c | 2 +-
arch/arm/mach-imx/mm-imx3.c| 4 +--
arch/arm/mach-imx/mxc.h| 56 +-
arch/arm/mach-imx/pm-imx6.c| 14 +--
14 files changed, 76 insertions(+), 76 deletions(-)
diff --git a/arch/arm/mach-imx/anatop.c b/arch/arm/mach-imx/anatop.c
index 649a84c..071380c8 100644
--- a/arch/arm/mach-imx/anatop.c
+++ b/arch/arm/mach-imx/anatop.c
@@ -81,7 +81,7 @@ void imx_anatop_pre_suspend(void)
imx_anatop_enable_fet_odrive(true);
- if (cpu_is_imx6sl())
+ if (soc_is_imx6sl())
imx_anatop_disconnect_high_snvs(true);
}
@@ -94,7 +94,7 @@ void imx_anatop_post_resume(void)
imx_anatop_enable_fet_odrive(false);
- if (cpu_is_imx6sl())
+ if (soc_is_imx6sl())
imx_anatop_disconnect_high_snvs(false);
}
@@ -168,7 +168,7 @@ void __init imx_init_revision_from_anatop(void)
revision = digprog & 0xff;
}
- mxc_set_cpu_type(digprog >> 16 & 0xff);
+ mxc_set_soc_type(digprog >> 16 & 0xff);
imx_set_soc_revision(revision);
}
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index bcca481..2130ee0 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -46,7 +46,7 @@ int mx35_clocks_init(void);
int mx31_clocks_init_dt(void);
struct platform_device *mxc_register_gpio(char *name, int id,
resource_size_t iobase, resource_size_t iosize, int irq, int irq_high);
-void mxc_set_cpu_type(unsigned int type);
+void mxc_set_soc_type(unsigned int type);
void mxc_restart(enum reboot_mode, const char *);
void mxc_arch_reset_init(void __iomem *);
void imx1_reset_init(void __iomem *);
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
index 3daf195..33d36d7 100644
--- a/arch/arm/mach-imx/cpu-imx31.c
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -22,7 +22,7 @@ static struct {
u8 srev;
const char *name;
unsigned int rev;
-} mx31_cpu_type[] = {
+} mx31_soc_type[] = {
{ .srev = 0x00, .name = "i.MX31(L)", .rev = IMX_CHIP_REVISION_1_0 },
{ .srev = 0x10, .name = "i.MX31",.rev = IMX_CHIP_REVISION_1_1 },
{ .srev = 0x11, .name = "i.MX31L", .rev = IMX_CHIP_REVISION_1_1 },
@@ -42,11 +42,11 @@ static int mx31_read_cpu_rev(void)
srev = imx_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
srev &= 0xff;
- for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
- if (srev == mx31_cpu_type[i].srev) {
- imx_print_silicon_rev(mx31_cpu_type[i].name,
- mx31_cpu_type[i].rev);
- return mx31_cpu_type[i].rev;
+ for (i = 0; i < ARRAY_SIZE(mx31_soc_type); i++)
+ if (srev == mx31_soc_type[i].srev) {
+ imx_print_silicon_rev(mx31_soc_type[i].name,
+ mx31_soc_type[i].rev);
+ return mx31_soc_type[i].rev;
}
imx_print_silicon_rev("i.MX31", IMX_CHIP_REVISION_UNKNOWN);
diff --git a/arch/arm/mach-imx/cpu.c b/arch/arm/mach-imx/cpu.c
index b3347d3..5519cf4 100644
--- a/arch/arm/mach-imx/cpu.c
+++ b/arch/arm/mach-imx/cpu.c
@@ -9,12 +9,12 @@
#include "hardware.h"
#include "common.h"
-unsigned int __mxc_cpu_type;
+unsigned int __mxc_soc_type;
static unsigned int imx_soc_revision;
-void mxc_set_cpu_type(unsigned int type)
+void mxc_set_soc_type(unsigned int type)
{
- __mxc_cpu_type = type;
+ __mxc_soc_type = type;
}
void imx_set_soc_revision(unsigned int rev)
@@ -91,47 +91,47 @@ struct device * __init imx_soc_device_init(void)
if (ret)
goto free_soc;
- switch (__mxc_cpu_type) {
- case MXC_CPU_MX1:
+ switch (__mxc_soc_type) {
+ case MXC_SOC_MX1:
soc_id = "i.MX1";
break;
- case MXC_CPU_MX21:
+ case MXC_SOC_MX21:
soc_id = "i.MX21";
break;
- case MXC_CPU_MX25:
+ case MXC_SOC_MX25:
soc_id = "i.MX25";
break;
- case MXC_CPU_
[PATCH V2] ARM: imx: add cpuidle support for i.mx6ul
This patch enables cpuidle driver for i.MX6UL, it
reuses i.MX6SX's cpuidle driver, 3 levels of cpuidle
supported:
1. ARM WFI;
2. SOC in WAIT mode;
3. SOC in WAIT mode + ARM power off.
As i.MX6UL has cortex-A7 CORE with an internal L2
cache, so flushing it before powering down ARM platform
is necessary, flush_cache_all() in last step of cpu_suspend
has very small overhead, just call it to avoid cache
type check for different platforms.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V1:
remove L2 cache contional code, just call flush_cache_all
is just fine since it has very small overhead for L1 cache flush.
arch/arm/mach-imx/cpuidle-imx6sx.c | 10 ++
arch/arm/mach-imx/mach-imx6ul.c| 3 +++
2 files changed, 13 insertions(+)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c
b/arch/arm/mach-imx/cpuidle-imx6sx.c
index 261aaa4..c5a5c3a 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
@@ -17,6 +18,15 @@
static int imx6sx_idle_finish(unsigned long val)
{
+ /*
+* for Cortex-A7 which has an internal L2
+* cache, need to flush it before powering
+* down ARM platform, since flushing L1 cache
+* here again has very small overhead, compared
+* to adding conditional code for L2 cache type,
+* just call flush_cache_all() is fine.
+*/
+ flush_cache_all();
cpu_do_idle();
return 0;
diff --git a/arch/arm/mach-imx/mach-imx6ul.c b/arch/arm/mach-imx/mach-imx6ul.c
index 6bb7d9c..58a2b88 100644
--- a/arch/arm/mach-imx/mach-imx6ul.c
+++ b/arch/arm/mach-imx/mach-imx6ul.c
@@ -16,6 +16,7 @@
#include
#include "common.h"
+#include "cpuidle.h"
static void __init imx6ul_enet_clk_init(void)
{
@@ -80,6 +81,8 @@ static void __init imx6ul_init_irq(void)
static void __init imx6ul_init_late(void)
{
+ imx6sx_cpuidle_init();
+
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
}
--
1.9.1
[PATCH V2 1/2] ARM: imx: rename imx6q_set_int_mem_clk_lpm() function
Let's rename the function imx6q_set_int_mem_clk_lpm()
to imx6_set_int_mem_clk_lpm() since it's actually
common for all i.MX6 SoCs.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V1:
This is a new add patch to improve function name.
arch/arm/mach-imx/common.h| 2 +-
arch/arm/mach-imx/cpuidle-imx6q.c | 2 +-
arch/arm/mach-imx/pm-imx6.c | 8
3 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index bcca481..c4436d9 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -104,7 +104,7 @@ void imx_anatop_init(void);
void imx_anatop_pre_suspend(void);
void imx_anatop_post_resume(void);
int imx6_set_lpm(enum mxc_cpu_pwr_mode mode);
-void imx6q_set_int_mem_clk_lpm(bool enable);
+void imx6_set_int_mem_clk_lpm(bool enable);
void imx6sl_set_wait_clk(bool enter);
int imx_mmdc_get_ddr_type(void);
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c
b/arch/arm/mach-imx/cpuidle-imx6q.c
index db0f48c..bfeb25a 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -85,7 +85,7 @@ EXPORT_SYMBOL_GPL(imx6q_cpuidle_fec_irqs_unused);
int __init imx6q_cpuidle_init(void)
{
/* Set INT_MEM_CLK_LPM bit to get a reliable WAIT mode support */
- imx6q_set_int_mem_clk_lpm(true);
+ imx6_set_int_mem_clk_lpm(true);
return cpuidle_register(_cpuidle_driver, NULL);
}
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index 67bab74..70e5bfb 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -217,7 +217,7 @@ struct imx6_cpu_pm_info {
u32 mmdc_io_val[MX6_MAX_MMDC_IO_NUM][2]; /* To save offset and value */
} __aligned(8);
-void imx6q_set_int_mem_clk_lpm(bool enable)
+void imx6_set_int_mem_clk_lpm(bool enable)
{
u32 val = readl_relaxed(ccm_base + CGPR);
@@ -367,7 +367,7 @@ static int imx6q_pm_enter(suspend_state_t state)
switch (state) {
case PM_SUSPEND_STANDBY:
imx6_set_lpm(STOP_POWER_ON);
- imx6q_set_int_mem_clk_lpm(true);
+ imx6_set_int_mem_clk_lpm(true);
imx_gpc_pre_suspend(false);
if (cpu_is_imx6sl())
imx6sl_set_wait_clk(true);
@@ -380,7 +380,7 @@ static int imx6q_pm_enter(suspend_state_t state)
break;
case PM_SUSPEND_MEM:
imx6_set_lpm(STOP_POWER_OFF);
- imx6q_set_int_mem_clk_lpm(false);
+ imx6_set_int_mem_clk_lpm(false);
imx6q_enable_wb(true);
/*
* For suspend into ocram, asm code already take care of
@@ -398,7 +398,7 @@ static int imx6q_pm_enter(suspend_state_t state)
imx_gpc_post_resume();
imx6_enable_rbc(false);
imx6q_enable_wb(false);
- imx6q_set_int_mem_clk_lpm(true);
+ imx6_set_int_mem_clk_lpm(true);
imx6_set_lpm(WAIT_CLOCKED);
break;
default:
--
1.9.1
[PATCH V2 2/2] ARM: imx: enable WAIT mode hardware workaround for imx6sx
Need to enable INT_MEM_CLK_LPM bit in CCM_CGPR for WAIT mode,
without this bit set, if there is pending interrupt during
ARM platform entering WAIT mode without power gating, cache
data will be corrupted, this is a hardware workaround for WAIT
mode and must be enabled.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V1:
function name is changed in 1/2 patch, change it accordingly.
arch/arm/mach-imx/cpuidle-imx6sx.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c
b/arch/arm/mach-imx/cpuidle-imx6sx.c
index 3c6672b..261aaa4 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -90,6 +90,7 @@ static struct cpuidle_driver imx6sx_cpuidle_driver = {
int __init imx6sx_cpuidle_init(void)
{
+ imx6_set_int_mem_clk_lpm(true);
imx6_enable_rbc(false);
/*
* set ARM power up/down timing to the fastest,
--
1.9.1
[PATCH V2] ARM: dts: imx6ul iomuxc syscon is compatible to imx6q
The imx6ul iomuxc syscon is compatible to imx6q,
so let's add compatible string 'fsl,imx6q-iomuxc-gpr'
for imx6ul iomuxc syscon node.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V1:
improve commit message.
arch/arm/boot/dts/imx6ul.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 33b95d7..acc9486 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -644,7 +644,8 @@
};
gpr: iomuxc-gpr@020e4000 {
- compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx6ul-iomuxc-gpr",
+"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>;
};
--
1.9.1
[PATCH] ARM: dts: imx6ul: set GINT to enable IOMUXC irq
Add "fsl,imx6q-iomuxc-gpr" for IOMUXC-GPR to enable
IOMUXC irq which is required for ERR007265 software
workaround.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx6ul.dtsi | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 33b95d7..acc9486 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -644,7 +644,8 @@
};
gpr: iomuxc-gpr@020e4000 {
- compatible = "fsl,imx6ul-iomuxc-gpr", "syscon";
+ compatible = "fsl,imx6ul-iomuxc-gpr",
+"fsl,imx6q-iomuxc-gpr", "syscon";
reg = <0x020e4000 0x4000>;
};
--
1.9.1
[PATCH 2/3] ARM: imx: add gpcv2 support
i.MX7's GPC(general power controller) module is
different from i.MX6, name it as GPCV2 and add
its driver for SMP support, as secondary CPUs
boot up will need GPC to enable power.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/mach-imx/Kconfig | 4 +++
arch/arm/mach-imx/Makefile | 1 +
arch/arm/mach-imx/common.h | 2 ++
arch/arm/mach-imx/gpcv2.c | 66 ++
4 files changed, 73 insertions(+)
create mode 100644 arch/arm/mach-imx/gpcv2.c
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 0ac05a0..13d5952 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -51,6 +51,9 @@ config HAVE_IMX_GPC
bool
select PM_GENERIC_DOMAINS if PM
+config HAVE_IMX_GPCV2
+ bool
+
config HAVE_IMX_MMDC
bool
@@ -537,6 +540,7 @@ config SOC_IMX7D
select HAVE_IMX_ANATOP
select HAVE_IMX_MMDC
select HAVE_IMX_SRC
+ select HAVE_IMX_GPCV2
help
This enables support for Freescale i.MX7 Dual processor.
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index edce8df..6d812f6 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -66,6 +66,7 @@ obj-$(CONFIG_MACH_IMX35_DT) += imx35-dt.o
obj-$(CONFIG_HAVE_IMX_ANATOP) += anatop.o
obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
+obj-$(CONFIG_HAVE_IMX_GPCV2) += gpcv2.o
obj-$(CONFIG_HAVE_IMX_MMDC) += mmdc.o
obj-$(CONFIG_HAVE_IMX_SRC) += src.o
ifneq ($(CONFIG_SOC_IMX6)$(CONFIG_SOC_LS1021A),)
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index b757811..732a19a 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -58,9 +58,11 @@ void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_check_dt(void);
+void imx_gpcv2_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
+void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn);
void imx25_pm_init(void);
void imx27_pm_init(void);
diff --git a/arch/arm/mach-imx/gpcv2.c b/arch/arm/mach-imx/gpcv2.c
new file mode 100644
index 000..98577c4
--- /dev/null
+++ b/arch/arm/mach-imx/gpcv2.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright 2016 Freescale Semiconductor, Inc.
+ *
+ * The code contained herein is licensed under the GNU General Public
+ * License. You may obtain a copy of the GNU General Public License
+ * Version 2 or later at the following locations:
+ *
+ * http://www.opensource.org/licenses/gpl-license.html
+ * http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include "common.h"
+
+#define GPC_CPU_PGC_SW_PUP_REQ 0xf0
+#define GPC_CPU_PGC_SW_PDN_REQ 0xfc
+#define GPC_PGC_C1 0x840
+
+#define BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7 0x2
+#define BM_GPC_PGC_PCG 0x1
+
+static void __iomem *gpcv2_base;
+
+static void imx_gpcv2_set_m_core_pgc(bool enable, u32 offset)
+{
+ u32 val = readl_relaxed(gpcv2_base + offset) & (~BM_GPC_PGC_PCG);
+
+ if (enable)
+ val |= BM_GPC_PGC_PCG;
+
+ writel_relaxed(val, gpcv2_base + offset);
+}
+
+void imx_gpcv2_set_core1_pdn_pup_by_software(bool pdn)
+{
+ u32 val = readl_relaxed(gpcv2_base + (pdn ?
+ GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ));
+
+ imx_gpcv2_set_m_core_pgc(true, GPC_PGC_C1);
+ val |= BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7;
+ writel_relaxed(val, gpcv2_base + (pdn ?
+ GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ));
+
+ while ((readl_relaxed(gpcv2_base + (pdn ?
+ GPC_CPU_PGC_SW_PDN_REQ : GPC_CPU_PGC_SW_PUP_REQ)) &
+ BM_CPU_PGC_SW_PDN_PUP_REQ_CORE1_A7) != 0)
+ ;
+ imx_gpcv2_set_m_core_pgc(false, GPC_PGC_C1);
+}
+
+void __init imx_gpcv2_check_dt(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,imx7d-gpc");
+ if (WARN_ON(!np))
+ return;
+
+ gpcv2_base = of_iomap(np, 0);
+ WARN_ON(!gpcv2_base);
+}
--
1.9.1
[PATCH 0/3] Add SMP support for i.MX7D
i.MX7D has 2 Cortex-A7 ARM cores, and it has a different GPC design than i.MX6, so this patch set adds a new GPCV2 driver for i.MX7D, and also adds runtime check in SMP code to support both Cortex-A9 and Cortex-A7 ARM cores. With this patch set, i.MX7D can boot up SMP kernel with 2 CPUs. Anson Huang (3): ARM: dts: imx7: support SMP boot up ARM: imx: add gpcv2 support ARM: imx: add SMP support for i.MX7D arch/arm/boot/dts/imx7s.dtsi | 8 + arch/arm/mach-imx/Kconfig | 4 +++ arch/arm/mach-imx/Makefile | 1 + arch/arm/mach-imx/common.h | 2 ++ arch/arm/mach-imx/gpcv2.c | 66 ++ arch/arm/mach-imx/headsmp.S| 11 +++ arch/arm/mach-imx/mach-imx7d.c | 2 ++ arch/arm/mach-imx/platsmp.c| 23 ++- arch/arm/mach-imx/src.c| 38 +++- 9 files changed, 146 insertions(+), 9 deletions(-) create mode 100644 arch/arm/mach-imx/gpcv2.c -- 1.9.1
[PATCH 3/3] ARM: imx: add SMP support for i.MX7D
i.MX7D has 2 cortex-a7 ARM core, add support for
booting up SMP kernel with 2 CPUs.
The existing i.MX SMP code is designed for i.MX6
series SoCs which have cortex-a9 ARM core, but i.MX7D
has 2 cortex-a7 ARM core, so we need to add runtime
check for those differences between cortex-a9 and
cortex-a7.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/mach-imx/headsmp.S| 11 +++
arch/arm/mach-imx/mach-imx7d.c | 2 ++
arch/arm/mach-imx/platsmp.c| 19 ++-
arch/arm/mach-imx/src.c| 38 ++
4 files changed, 61 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 6c28d28..a26e459 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -26,7 +26,18 @@ diag_reg_offset:
.endm
ENTRY(v7_secondary_startup)
+ .word 0xc070 @ 0xc07 is cortex-a7 id
+ .word 0xfff0 @ mask for core type
+
ARM_BE8(setend be) @ go BE8 if entered LE
+ mrc p15, 0, r0, c0, c0, 0
+ adr r1, v7_secondary_startup
+ ldr r2, [r1]
+ ldr r3, [r1, #0x4]
+ and r0, r0, r3
+ cmp r0, r2
+ beq secondary_startup
+
set_diag_reg
b secondary_startup
ENDPROC(v7_secondary_startup)
diff --git a/arch/arm/mach-imx/mach-imx7d.c b/arch/arm/mach-imx/mach-imx7d.c
index 26ca744..ef3dce6 100644
--- a/arch/arm/mach-imx/mach-imx7d.c
+++ b/arch/arm/mach-imx/mach-imx7d.c
@@ -99,6 +99,7 @@ static void __init imx7d_init_machine(void)
static void __init imx7d_init_irq(void)
{
+ imx_gpcv2_check_dt();
imx_init_revision_from_anatop();
imx_src_init();
irqchip_init();
@@ -111,6 +112,7 @@ static const char *const imx7d_dt_compat[] __initconst = {
};
DT_MACHINE_START(IMX7D, "Freescale i.MX7 Dual (Device Tree)")
+ .smp= smp_ops(imx_smp_ops),
.init_irq = imx7d_init_irq,
.init_machine = imx7d_init_machine,
.dt_compat = imx7d_dt_compat,
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 711dbbd..63af911 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -60,8 +60,17 @@ static int imx_boot_secondary(unsigned int cpu, struct
task_struct *idle)
static void __init imx_smp_init_cpus(void)
{
int i, ncores;
+ unsigned long val, arch_type;
- ncores = scu_get_core_count(scu_base);
+ asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (arch_type));
+
+ if (((arch_type >> 4) & 0xfff) == 0xc07) {
+ /* cortex-a7 core number is in bit[25:24] of CP15 L2CTLR */
+ asm volatile("mrc p15, 1, %0, c9, c0, 2" : "=r" (val));
+ ncores = ((val >> 24) & 0x3) + 1;
+ } else {
+ ncores = scu_get_core_count(scu_base);
+ }
for (i = ncores; i < NR_CPUS; i++)
set_cpu_possible(i, false);
@@ -74,6 +83,14 @@ void imx_smp_prepare(void)
static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
{
+ unsigned long arch_type;
+
+ asm volatile("mrc p15, 0, %0, c0, c0, 0" : "=r" (arch_type));
+
+ /* no need for cortex-a7 */
+ if (((arch_type >> 4) & 0xfff) == 0xc07)
+ return;
+
imx_smp_prepare();
/*
diff --git a/arch/arm/mach-imx/src.c b/arch/arm/mach-imx/src.c
index 70b083f..1fda72a 100644
--- a/arch/arm/mach-imx/src.c
+++ b/arch/arm/mach-imx/src.c
@@ -18,6 +18,7 @@
#include
#include
#include "common.h"
+#include "hardware.h"
#define SRC_SCR0x000
#define SRC_GPR1 0x020
@@ -30,6 +31,15 @@
#define BP_SRC_SCR_CORE1_RST 14
#define BP_SRC_SCR_CORE1_ENABLE22
+/* below are for i.MX7D */
+#define SRC_GPR1_V2 0x074
+#define SRC_A7RCR0 0x004
+#define SRC_A7RCR1 0x008
+#define SRC_M4RCR 0x00C
+
+#define BP_SRC_A7RCR0_A7_CORE_RESET0 0
+#define BP_SRC_A7RCR1_A7_CORE1_ENABLE 1
+
static void __iomem *src_base;
static DEFINE_SPINLOCK(scr_lock);
@@ -87,12 +97,21 @@ void imx_enable_cpu(int cpu, bool enable)
u32 mask, val;
cpu = cpu_logical_map(cpu);
- mask = 1 << (BP_SRC_SCR_CORE1_ENABLE + cpu - 1);
spin_lock(_lock);
- val = readl_relaxed(src_base + SRC_SCR);
- val = enable ? val | mask : val & ~mask;
- val |= 1 << (BP_SRC_SCR_CORE1_RST + cpu - 1);
- writel_relaxed(val, src_base + SRC_SCR);
+ if (cpu_is_imx7d()) {
+ if (enable)
+ imx_gpcv2_set_core1_pdn_pup_by_software(false);
+ mask = 1 << (BP_SRC_A7RCR1_A7_CORE1_ENABLE + cpu - 1);
+
[PATCH 1/3] ARM: dts: imx7: support SMP boot up
This patch adds GPC module, i.MX7 has a different
design of GPC module from i.MX6, so we call it GPCV2,
booting up secondary CPUs needs to access GPCV2
to enable secondary CPUs' power.
Also, adds "arm,cpu-registers-not-fw-configured"
property, interrupt parent and clock rate to
arch timer.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx7s.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi
index bb7102c..e920436 100644
--- a/arch/arm/boot/dts/imx7s.dtsi
+++ b/arch/arm/boot/dts/imx7s.dtsi
@@ -299,10 +299,13 @@
timer {
compatible = "arm,armv7-timer";
+ arm,cpu-registers-not-fw-configured;
interrupts = ,
,
,
;
+ interrupt-parent = <>;
+ clock-frequency = <800>;
};
aips1: aips-bus@3000 {
@@ -312,6 +315,11 @@
reg = <0x3000 0x40>;
ranges;
+ gpc: gpc@303a {
+ compatible = "fsl,imx7d-gpc";
+ reg = <0x303a 0x1>;
+ };
+
gpio1: gpio@3020 {
compatible = "fsl,imx7d-gpio", "fsl,imx35-gpio";
reg = <0x3020 0x1>;
--
1.9.1
RE: [PATCH] cpufreq: imx6q: Fix imx6sx low frequency support
Best Regards! Anson Huang > -Original Message- > From: Lucas Stach [mailto:l.st...@pengutronix.de] > Sent: 2017-07-19 6:28 PM > To: Leonard Crestez <leonard.cres...@nxp.com> > Cc: Viresh Kumar <viresh.ku...@linaro.org>; Rafael J. Wysocki > <r...@rjwysocki.net>; Shawn Guo <shawn...@kernel.org>; Fabio Estevam > <fabio.este...@nxp.com>; linux...@vger.kernel.org; Octavian Purdila > <octavian.purd...@nxp.com>; Anson Huang <anson.hu...@nxp.com>; Jacky > Bai <ping@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>; > ker...@pengutronix.de; linux-arm-ker...@lists.infradead.org; linux- > ker...@vger.kernel.org > Subject: Re: [PATCH] cpufreq: imx6q: Fix imx6sx low frequency support > > Hi Leonard, > > Am Mittwoch, den 19.07.2017, 12:54 +0300 schrieb Leonard Crestez: > > This patch contains the minimal changes required to support imx6sx OPP > > of > > 198 Mhz. Without this patch cpufreq still reports success but the > > frequency is not changed, the "arm" clock will still be at 39600 in > clk_summary. > > > > In order to do this PLL1 needs to be bypassed but still kept enabled. > > This is required despite the fact that the arm clk is configured to > > come from > > pll2_pfd2 and from the clk framework perspective pll1 and related > > clocks are unused. > > I'm not really an expert for MX6SX, so a little background on why PLL1 needs > to > be kept enabled would help to review this change. Hi, Lucas The PLL1 needs to be enabled is because when ARM_PODF is changed in CCM, we need to check the busy bit of CCM_CDHIPR bit 16 arm_podf_busy, and this bit is sync with PLL1 clock, so if PLL1 NOT enabled, this bit will never get clear. This is hardware requirement. Anson. > > Thanks, > Lucas > > > This patch adds pll1, pll_bypass and pll1_bypass_src clocks to the imx > > cpufreq driver as imx6sx-specific for the bypass logic. > > > > The definition of pll1_sys is changed to imx_clk_fixed_factor so that > > it's never disabled. > > > > Signed-off-by: Leonard Crestez <leonard.cres...@nxp.com> > > --- > > > > Some potential issues: > > > > In theory pll1_sys could be explictly kept enabled from cpufreq. It's > > not clear this would be better since the intention is to never let > > this be disabled. > > > > The new clocks are only added for imx6sx. The frequency changing code > > relies on the fact that the clk API simply does nothing when called > > with a null clk. > > > > Perhaps it might be better to accept ENOENT from clk_get on these new > > clocks instead of checking of_machine_is_compatible. > > > > arch/arm/boot/dts/imx6sx.dtsi | 8 ++-- > > drivers/clk/imx/clk-imx6sx.c| 2 +- > > drivers/cpufreq/imx6q-cpufreq.c | 33 > > + > > 3 files changed, 40 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm/boot/dts/imx6sx.dtsi > > b/arch/arm/boot/dts/imx6sx.dtsi index f16b9df..4394137 100644 > > --- a/arch/arm/boot/dts/imx6sx.dtsi > > +++ b/arch/arm/boot/dts/imx6sx.dtsi > > @@ -87,9 +87,13 @@ > > < IMX6SX_CLK_PLL2_PFD2>, > > < IMX6SX_CLK_STEP>, > > < IMX6SX_CLK_PLL1_SW>, > > -< IMX6SX_CLK_PLL1_SYS>; > > +< IMX6SX_CLK_PLL1_SYS>, > > +< IMX6SX_CLK_PLL1>, > > +< IMX6SX_PLL1_BYPASS>, > > +< IMX6SX_PLL1_BYPASS_SRC>; > > clock-names = "arm", "pll2_pfd2_396m", "step", > > - "pll1_sw", "pll1_sys"; > > + "pll1_sw", "pll1_sys", "pll1", > > + "pll1_bypass", "pll1_bypass_src"; > > arm-supply = <_arm>; > > soc-supply = <_soc>; > > }; > > diff --git a/drivers/clk/imx/clk-imx6sx.c > > b/drivers/clk/imx/clk-imx6sx.c index b5c96de..aa63b92 100644 > > --- a/drivers/clk/imx/clk-imx6sx.c > > +++ b/drivers/clk/imx/clk-imx6sx.c > > @@ -199,7 +199,7 @@ static void __init imx6sx_clocks_init(struct > device_node *ccm_node) > > clk_set_parent(clks[IMX6SX_PLL6_BYPASS], clks[IMX6SX_CLK_PLL6]); > > clk_set_parent(clks[IMX6SX_PLL7_BYPASS], clks[IMX6SX_CLK_PLL7]); > > > > - clk
RE: [PATCH] ARM: imx6ull: Make suspend/resume work like on 6ul
Best Regards! Anson Huang > -Original Message- > From: Shawn Guo [mailto:shawn...@kernel.org] > Sent: 2017-06-07 11:21 AM > To: Anson Huang <anson.hu...@nxp.com> > Cc: Leonard Crestez <leonard.cres...@nxp.com>; Peter Chen > <peter.c...@nxp.com>; linux-kernel@vger.kernel.org; Fabio Estevam > <fabio.este...@nxp.com>; linux-arm-ker...@lists.infradead.org; Lucas Stach > <l.st...@pengutronix.de> > Subject: Re: [PATCH] ARM: imx6ull: Make suspend/resume work like on 6ul > > On Tue, Jun 06, 2017 at 01:51:53PM +0300, Leonard Crestez wrote: > > On Mon, 2017-06-05 at 13:37 +0800, Shawn Guo wrote: > > > On Tue, May 30, 2017 at 07:11:19PM +0300, Leonard Crestez wrote: > > > > > > > > Suspend and resume on imx6ull is currenty not working because of > > > > some missed checks where behavior should match imx6ul. > > > > > > > > Signed-off-by: Leonard Crestez <leonard.cres...@nxp.com> > > > > --- > > > >  arch/arm/mach-imx/mxc.h | 6 ++ > > > >  arch/arm/mach-imx/pm-imx6.c | 6 -- > > > >  2 files changed, 10 insertions(+), 2 deletions(-) > > > > > > > > diff --git a/arch/arm/mach-imx/mxc.h b/arch/arm/mach-imx/mxc.h > > > > index 34f2ff6..e00d626 100644 > > > > --- a/arch/arm/mach-imx/mxc.h > > > > +++ b/arch/arm/mach-imx/mxc.h > > > > @@ -39,6 +39,7 @@ > > > >  #define MXC_CPU_IMX6SX 0x62 > > > >  #define MXC_CPU_IMX6Q 0x63 > > > >  #define MXC_CPU_IMX6UL 0x64 > > > > +#define MXC_CPU_IMX6ULL0x65 > > > Since you are adding a new CPU type, you should probably patch > > > imx_soc_device_init() for it as well. > > > > Ok, I will resend as a 2-patch series. > > > > BTW, it actually seems to me that setting > BM_CLPCR_BYP_MMDC_CH0_LPM_HS > > on imx6sl/sx/ul/ull is not actually needed. That bit (19) is > > documented as "reserved" in the Reference Manual and likely ignored by > hardware. > > > > As far as I understand the MMDC on imx6qdl has two channels and unless > > 2-channel mode is enabled (not currently supported) the handshake with > > CH1 needs to be disabled. Other reduced chips only have one MMDC > > channel and that is CH1 (CH0 was removed) and nothing needs to be done > > from them. The only important thing is to avoid setting > > BM_CLPCR_BYP_MMDC_CH1_LPM_HS. > > > > However perhaps what I am saying is wrong for some early chip versions? > > Because this behavior of setting BM_CLPCR_BYP_MMDC_CH0_LPM_HS has > been > > in the kernel for a long time. As far as I know, since i.MX6SX, we only use MMDC_CH1, but MMDC_CH0 is still there and we need to bypass its handshake when entering low power mode. The bit 19 in DOC is incorrect, I remembered I ever tried it and discuss with design time, they request DOC team to update DOC, but I think doc team forgot to do it. You can try removing this bit 19 setting and see if standby/mem suspend can still work? And try to modify this bit 19 value to see if it can be modified. Anson. > > @Anson, you might be the right person to comment here? > > Shawn
[PATCH V6 5/7] ARM: dts: imx6sx-sabreauto: add wdog external reset
i.MX6SX Sabre Auto board has GPIO1_IO13 pin can be
MUXed as WDOG output to reset PMIC, add this function
support.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx6sx-sabreauto.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 7dda741..13de77b 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -232,6 +232,12 @@
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY0x30b0
+ >;
+ };
};
{
@@ -370,3 +376,9 @@
#gpio-cells = <2>;
};
};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_wdog>;
+ fsl,ext-reset-output;
+};
--
2.7.4
[PATCH V6 3/7] ARM: dts: imx6sx-sabreauto: add IO expander max7310 support
i.MX6SX Sabre Auto board has two max7310 IO expander on I2C3 bus, add
support for them.
Signed-off-by: Dong Aisheng <aisheng.d...@nxp.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V5:
improve pinctrl node name.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index ae253af..4d41b4d 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -73,6 +73,13 @@
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL0x4001b8b1
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
@@ -262,3 +269,24 @@
#gpio-cells = <2>;
};
};
+
+ {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c3>;
+ status = "okay";
+
+ max7310_a: gpio@30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio@32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
--
2.7.4
[PATCH V6 6/7] ARM: dts: imx6sx-sabreauto: add debug LED support
There is a debug LED(D11) connected to GPIO1_IO24,
add support for it.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx6sx-sabreauto.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 13de77b..1dc5b58 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -18,6 +18,18 @@
reg = <0x8000 0x8000>;
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led>;
+
+ user {
+ label = "debug";
+ gpios = < 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
reg_fec: fec_io_supply {
compatible = "regulator-gpio";
regulator-name = "1.8V_1.5V_FEC";
@@ -160,6 +172,12 @@
>;
};
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
--
2.7.4
[PATCH V6 4/7] ARM: dts: imx6sx-sabreauto: add fec support
Add FEC support on i.MX6SX Sabre Auto board.
Signed-off-by: Fugang Duan <fugang.d...@nxp.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V5:
use "gpios" instead of "enable-gpio".
arch/arm/boot/dts/imx6sx-sabreauto.dts | 80 ++
1 file changed, 80 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 4d41b4d..7dda741 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -18,6 +18,17 @@
reg = <0x8000 0x8000>;
};
+ reg_fec: fec_io_supply {
+ compatible = "regulator-gpio";
+ regulator-name = "1.8V_1.5V_FEC";
+ regulator-min-microvolt = <150>;
+ regulator-max-microvolt = <180>;
+ states = <150 0x0 180 0x1>;
+ gpios = < 0 GPIO_ACTIVE_HIGH>;
+ vin-supply = <_reg>;
+ enable-active-high;
+ };
+
vcc_sd3: regulator-vcc-sd3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -34,6 +45,39 @@
clock-frequency = <24576000>;
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_enet1>;
+ phy-mode = "rgmii";
+ phy-handle = <>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_enet2>;
+ phy-mode = "rgmii";
+ phy-handle = <>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_uart1>;
@@ -66,6 +110,42 @@
};
{
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO0xa0b1
+ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN0xa0b1
+ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
+ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN0x3081
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN0xa0b1
+ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
+ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN0x3081
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
--
2.7.4
[PATCH V6 1/7] ARM: dts: imx6sx-sabreauto: add PMIC support
Add pfuze100 support on i.MX6SX Sabre Auto board.
Signed-off-by: Robin Gong <yibin.g...@nxp.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V5:
improve node name and unit-address format.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 116 +
1 file changed, 116 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 87ffe2c..1d8cf0f 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -66,6 +66,13 @@
};
{
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
@@ -139,3 +146,112 @@
>;
};
};
+
+ {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c2>;
+ status = "okay";
+
+ pfuze100: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <30>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <30>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <40>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <40>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <515>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <300>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <155>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <155>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <180>;
+
[PATCH V6 2/7] ARM: dts: imx6sx-sabreauto: add max7322 IO expander support
Add MAX7322 IO expander support.
Signed-off-by: Fugang Duan <fugang.d...@nxp.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx6sx-sabreauto.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 1d8cf0f..ae253af 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -254,4 +254,11 @@
};
};
};
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
--
2.7.4
[PATCH V6 7/7] ARM: dts: imx6sx-sabreauto: add egalax touch screen support
Add egalax touch screen support on i2c2 bus.
Signed-off-by: Haibo Chen <haibo.c...@freescale.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V5:
improve pinctrl node name and touchscreen node name.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 1dc5b58..3fe41d3 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -122,6 +122,12 @@
};
{
+ pinctrl_egalax_int: egalax-intgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x8000
+ >;
+ };
+
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO0xa0b1
@@ -264,6 +270,16 @@
pinctrl-0 = <_i2c2>;
status = "okay";
+ egalax_touchscreen@4 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_egalax_int>;
+ interrupt-parent = <>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = < 22 GPIO_ACTIVE_HIGH>;
+ };
+
pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
--
2.7.4
[PATCH 3/3] ARM: dts: imx: add cooling-cells for cpufreq cooling device
Add #cooling-cells for i.MX6/7 SoCs for cpufreq
cooling device usage.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx6dl.dtsi | 1 +
arch/arm/boot/dts/imx6q.dtsi | 1 +
arch/arm/boot/dts/imx6sl.dtsi | 1 +
arch/arm/boot/dts/imx6sx.dtsi | 1 +
arch/arm/boot/dts/imx6ul.dtsi | 1 +
arch/arm/boot/dts/imx7d.dtsi | 1 +
6 files changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/imx6dl.dtsi b/arch/arm/boot/dts/imx6dl.dtsi
index 558bce8..b830dfd 100644
--- a/arch/arm/boot/dts/imx6dl.dtsi
+++ b/arch/arm/boot/dts/imx6dl.dtsi
@@ -39,6 +39,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = < IMX6QDL_CLK_ARM>,
< IMX6QDL_CLK_PLL2_PFD2_396M>,
< IMX6QDL_CLK_STEP>,
diff --git a/arch/arm/boot/dts/imx6q.dtsi b/arch/arm/boot/dts/imx6q.dtsi
index ae7b3f1..ac9f5cb 100644
--- a/arch/arm/boot/dts/imx6q.dtsi
+++ b/arch/arm/boot/dts/imx6q.dtsi
@@ -44,6 +44,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = < IMX6QDL_CLK_ARM>,
< IMX6QDL_CLK_PLL2_PFD2_396M>,
< IMX6QDL_CLK_STEP>,
diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index ab6a7e2..d35d4e9 100644
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -65,6 +65,7 @@
396000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = < IMX6SL_CLK_ARM>, <
IMX6SL_CLK_PLL2_PFD2>,
< IMX6SL_CLK_STEP>, <
IMX6SL_CLK_PLL1_SW>,
< IMX6SL_CLK_PLL1_SYS>;
diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index 49c7205..966e39a 100644
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -83,6 +83,7 @@
198000 1175000
>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
clocks = < IMX6SX_CLK_ARM>,
< IMX6SX_CLK_PLL2_PFD2>,
< IMX6SX_CLK_STEP>,
diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi
index 1241972..14b6ac7 100644
--- a/arch/arm/boot/dts/imx6ul.dtsi
+++ b/arch/arm/boot/dts/imx6ul.dtsi
@@ -66,6 +66,7 @@
device_type = "cpu";
reg = <0>;
clock-latency = <61036>; /* two CLK32 periods */
+ #cooling-cells = <2>;
operating-points = <
/* kHz uV */
696000 1275000
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 200714e..49913717 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -53,6 +53,7 @@
792000 975000
>;
clock-frequency = <99600>;
+ #cooling-cells = <2>;
};
cpu1: cpu@1 {
--
2.7.4
[PATCH 1/3] thermal: imx: remove cpufreq cooling registration
This patch removes cpufreq cooling registration in
thermal .probe function, cpufreq cooling should be
done in cpufreq driver when it is ready.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/thermal/imx_thermal.c | 16
1 file changed, 16 deletions(-)
diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c
index c30dc21..8eedb97 100644
--- a/drivers/thermal/imx_thermal.c
+++ b/drivers/thermal/imx_thermal.c
@@ -9,7 +9,6 @@
#include
#include
-#include
#include
#include
#include
@@ -207,7 +206,6 @@ static struct thermal_soc_data thermal_imx7d_data = {
struct imx_thermal_data {
struct cpufreq_policy *policy;
struct thermal_zone_device *tz;
- struct thermal_cooling_device *cdev;
enum thermal_device_mode mode;
struct regmap *tempmon;
u32 c1, c2; /* See formula in imx_init_calib() */
@@ -729,22 +727,12 @@ static int imx_thermal_probe(struct platform_device *pdev)
return -EPROBE_DEFER;
}
- data->cdev = cpufreq_cooling_register(data->policy);
- if (IS_ERR(data->cdev)) {
- ret = PTR_ERR(data->cdev);
- dev_err(>dev,
- "failed to register cpufreq cooling device: %d\n", ret);
- cpufreq_cpu_put(data->policy);
- return ret;
- }
-
data->thermal_clk = devm_clk_get(>dev, NULL);
if (IS_ERR(data->thermal_clk)) {
ret = PTR_ERR(data->thermal_clk);
if (ret != -EPROBE_DEFER)
dev_err(>dev,
"failed to get thermal clk: %d\n", ret);
- cpufreq_cooling_unregister(data->cdev);
cpufreq_cpu_put(data->policy);
return ret;
}
@@ -759,7 +747,6 @@ static int imx_thermal_probe(struct platform_device *pdev)
ret = clk_prepare_enable(data->thermal_clk);
if (ret) {
dev_err(>dev, "failed to enable thermal clk: %d\n", ret);
- cpufreq_cooling_unregister(data->cdev);
cpufreq_cpu_put(data->policy);
return ret;
}
@@ -775,7 +762,6 @@ static int imx_thermal_probe(struct platform_device *pdev)
dev_err(>dev,
"failed to register thermal zone device %d\n", ret);
clk_disable_unprepare(data->thermal_clk);
- cpufreq_cooling_unregister(data->cdev);
cpufreq_cpu_put(data->policy);
return ret;
}
@@ -811,7 +797,6 @@ static int imx_thermal_probe(struct platform_device *pdev)
dev_err(>dev, "failed to request alarm irq: %d\n", ret);
clk_disable_unprepare(data->thermal_clk);
thermal_zone_device_unregister(data->tz);
- cpufreq_cooling_unregister(data->cdev);
cpufreq_cpu_put(data->policy);
return ret;
}
@@ -831,7 +816,6 @@ static int imx_thermal_remove(struct platform_device *pdev)
clk_disable_unprepare(data->thermal_clk);
thermal_zone_device_unregister(data->tz);
- cpufreq_cooling_unregister(data->cdev);
cpufreq_cpu_put(data->policy);
return 0;
--
2.7.4
RE: [PATCH 1/3] thermal: imx: remove cpufreq cooling registration
Anson Huang
Best Regards!
> -Original Message-
> From: Bastian Stender [mailto:b...@pengutronix.de]
> Sent: Monday, May 14, 2018 4:37 PM
> To: Anson Huang <anson.hu...@nxp.com>; shawn...@kernel.org;
> s.ha...@pengutronix.de; ker...@pengutronix.de; Fabio Estevam
> <fabio.este...@nxp.com>; robh...@kernel.org; mark.rutl...@arm.com;
> r...@rjwysocki.net; viresh.ku...@linaro.org; rui.zh...@intel.com;
> edubez...@gmail.com
> Cc: devicet...@vger.kernel.org; linux...@vger.kernel.org; dl-linux-imx
> <linux-...@nxp.com>; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: Re: [PATCH 1/3] thermal: imx: remove cpufreq cooling registration
>
> Hi,
>
> On 05/14/2018 10:09 AM, Anson Huang wrote:
> > This patch removes cpufreq cooling registration in thermal .probe
> > function, cpufreq cooling should be done in cpufreq driver when it is
> > ready.
> >
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
>
> It seems you are trying to achieve something similar to a patch I sent a
> couple
> of month ago. Unfortunately I did not have the time to rework it yet:
>
>
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.kernel.org%2Fpatch%2F10059085%2F=02%7C01%7Canson.huang
> %40nxp.com%7C179da3635cab4a14deef08d5b975ecb6%7C686ea1d3bc2b4c6f
> a92cd99c5c301635%7C0%7C0%7C636618838508978629=BcQ9tc%2BE
> CZ%2Fk4AsZFxshgmvSsPg7eRN0ASzP8LO8yBI%3D=0
>
> Some of the comments might apply here too.
Ah, I did NOT notice this thread, so how to proceed, will you continue to
finish your patch?
If yes, then you can just ignore/skip my patch, thanks.
Anson.
>
> Regards,
> Bastian
>
> > ---
> > drivers/thermal/imx_thermal.c | 16
> > 1 file changed, 16 deletions(-)
> >
> > diff --git a/drivers/thermal/imx_thermal.c
> > b/drivers/thermal/imx_thermal.c index c30dc21..8eedb97 100644
> > --- a/drivers/thermal/imx_thermal.c
> > +++ b/drivers/thermal/imx_thermal.c
> > @@ -9,7 +9,6 @@
> >
> > #include
> > #include
> > -#include
> > #include
> > #include
> > #include
> > @@ -207,7 +206,6 @@ static struct thermal_soc_data thermal_imx7d_data
> = {
> > struct imx_thermal_data {
> > struct cpufreq_policy *policy;
> > struct thermal_zone_device *tz;
> > - struct thermal_cooling_device *cdev;
> > enum thermal_device_mode mode;
> > struct regmap *tempmon;
> > u32 c1, c2; /* See formula in imx_init_calib() */ @@ -729,22
> > +727,12 @@ static int imx_thermal_probe(struct platform_device *pdev)
> > return -EPROBE_DEFER;
> > }
> >
> > - data->cdev = cpufreq_cooling_register(data->policy);
> > - if (IS_ERR(data->cdev)) {
> > - ret = PTR_ERR(data->cdev);
> > - dev_err(>dev,
> > - "failed to register cpufreq cooling device: %d\n", ret);
> > - cpufreq_cpu_put(data->policy);
> > - return ret;
> > - }
> > -
> > data->thermal_clk = devm_clk_get(>dev, NULL);
> > if (IS_ERR(data->thermal_clk)) {
> > ret = PTR_ERR(data->thermal_clk);
> > if (ret != -EPROBE_DEFER)
> > dev_err(>dev,
> > "failed to get thermal clk: %d\n", ret);
> > - cpufreq_cooling_unregister(data->cdev);
> > cpufreq_cpu_put(data->policy);
> > return ret;
> > }
> > @@ -759,7 +747,6 @@ static int imx_thermal_probe(struct platform_device
> *pdev)
> > ret = clk_prepare_enable(data->thermal_clk);
> > if (ret) {
> > dev_err(>dev, "failed to enable thermal clk: %d\n", ret);
> > - cpufreq_cooling_unregister(data->cdev);
> > cpufreq_cpu_put(data->policy);
> > return ret;
> > }
> > @@ -775,7 +762,6 @@ static int imx_thermal_probe(struct platform_device
> *pdev)
> > dev_err(>dev,
> > "failed to register thermal zone device %d\n", ret);
> > clk_disable_unprepare(data->thermal_clk);
> > - cpufreq_cooling_unregister(data->cdev);
> > cpufreq_cpu_put(data->policy);
> > return ret;
> > }
> > @@ -811,7 +797,6 @@ static int imx_thermal_probe(struct platform_device
> *pdev)
> > dev_err(>dev, "failed to request alarm irq: %d\n", ret);
> > clk_disable_unprepare(data
[PATCH 2/3] cpufreq: imx6q: add cpufreq cooling device based on device tree
Register the imx6q cpufreq driver as a cooling device
based on the thermal device tree framework.
When temperature exceeds the passive trip point, cpufreq
driver will be used to throttle CPUs.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/cpufreq/imx6q-cpufreq.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/cpufreq/imx6q-cpufreq.c b/drivers/cpufreq/imx6q-cpufreq.c
index 83cf631..27ce84d 100644
--- a/drivers/cpufreq/imx6q-cpufreq.c
+++ b/drivers/cpufreq/imx6q-cpufreq.c
@@ -9,6 +9,7 @@
#include
#include
#include
+#include
#include
#include
#include
@@ -50,6 +51,7 @@ static struct clk_bulk_data clks[] = {
};
static struct device *cpu_dev;
+struct thermal_cooling_device *cdev;
static bool free_opp;
static struct cpufreq_frequency_table *freq_table;
static unsigned int max_freq;
@@ -202,6 +204,11 @@ static int imx6q_cpufreq_init(struct cpufreq_policy
*policy)
return ret;
}
+static void imx6q_cpufreq_ready(struct cpufreq_policy *policy)
+{
+ cdev = of_cpufreq_cooling_register(policy);
+}
+
static struct cpufreq_driver imx6q_cpufreq_driver = {
.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK,
.verify = cpufreq_generic_frequency_table_verify,
@@ -210,6 +217,7 @@ static struct cpufreq_driver imx6q_cpufreq_driver = {
.init = imx6q_cpufreq_init,
.name = "imx6q-cpufreq",
.attr = cpufreq_generic_attr,
+ .ready = imx6q_cpufreq_ready,
.suspend = cpufreq_generic_suspend,
};
@@ -482,6 +490,7 @@ static int imx6q_cpufreq_probe(struct platform_device *pdev)
static int imx6q_cpufreq_remove(struct platform_device *pdev)
{
+ cpufreq_cooling_unregister(cdev);
cpufreq_unregister_driver(_cpufreq_driver);
dev_pm_opp_free_cpufreq_table(cpu_dev, _table);
if (free_opp)
--
2.7.4
[PATCH] cpufreq: add imx8mq-cpufreq driver
Add imx8mq-cpufreq driver for NXP i.MX8MQ SoC to support the
hardware specific frequency and voltage scaling requirements.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/cpufreq/Kconfig.arm | 8 ++
drivers/cpufreq/Makefile | 1 +
drivers/cpufreq/imx8mq-cpufreq.c | 234 +++
3 files changed, 243 insertions(+)
create mode 100644 drivers/cpufreq/imx8mq-cpufreq.c
diff --git a/drivers/cpufreq/Kconfig.arm b/drivers/cpufreq/Kconfig.arm
index 96b35b8..ea8e2b6 100644
--- a/drivers/cpufreq/Kconfig.arm
+++ b/drivers/cpufreq/Kconfig.arm
@@ -105,6 +105,14 @@ config ARM_IMX6Q_CPUFREQ
If in doubt, say N.
+config ARM_IMX8MQ_CPUFREQ
+ tristate "NXP i.MX8MQ cpufreq support"
+ select PM_OPP
+ help
+ This adds cpufreq driver support for NXP i.MX8MQ SoC.
+
+ If in doubt, say N.
+
config ARM_KIRKWOOD_CPUFREQ
def_bool MACH_KIRKWOOD
help
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index 8d24ade..a3bc61c 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -59,6 +59,7 @@ obj-$(CONFIG_ARCH_DAVINCI)+= davinci-cpufreq.o
obj-$(CONFIG_ARM_EXYNOS5440_CPUFREQ) += exynos5440-cpufreq.o
obj-$(CONFIG_ARM_HIGHBANK_CPUFREQ) += highbank-cpufreq.o
obj-$(CONFIG_ARM_IMX6Q_CPUFREQ)+= imx6q-cpufreq.o
+obj-$(CONFIG_ARM_IMX8MQ_CPUFREQ) += imx8mq-cpufreq.o
obj-$(CONFIG_ARM_KIRKWOOD_CPUFREQ) += kirkwood-cpufreq.o
obj-$(CONFIG_ARM_MEDIATEK_CPUFREQ) += mediatek-cpufreq.o
obj-$(CONFIG_MACH_MVEBU_V7)+= mvebu-cpufreq.o
diff --git a/drivers/cpufreq/imx8mq-cpufreq.c b/drivers/cpufreq/imx8mq-cpufreq.c
new file mode 100644
index 000..2aee6049
--- /dev/null
+++ b/drivers/cpufreq/imx8mq-cpufreq.c
@@ -0,0 +1,234 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018 NXP
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+static struct device *cpu_dev;
+static bool free_opp;
+static struct cpufreq_frequency_table *freq_table;
+static unsigned int transition_latency;
+static struct thermal_cooling_device *cdev;
+static struct regulator *arm_reg;
+static unsigned int max_freq;
+
+#define IMX8MQ_CPUFREQ_CLK_NUM 5
+
+enum IMX8MQ_CPUFREQ_CLKS {
+ A53,
+ A53_SRC,
+ ARM_PLL,
+ ARM_PLL_OUT,
+ SYS1_PLL_800M,
+};
+
+static struct clk_bulk_data clks[] = {
+ { .id = "a53" },
+ { .id = "a53_src" },
+ { .id = "arm_pll" },
+ { .id = "arm_pll_out" },
+ { .id = "sys1_pll_800m" },
+};
+
+static int imx8mq_set_target(struct cpufreq_policy *policy, unsigned int index)
+{
+ struct dev_pm_opp *opp;
+ unsigned long freq_hz, volt;
+ unsigned int old_freq, new_freq;
+ int ret;
+
+ new_freq = freq_table[index].frequency;
+ freq_hz = new_freq * 1000;
+ old_freq = policy->cur;
+
+ opp = dev_pm_opp_find_freq_ceil(cpu_dev, _hz);
+ if (IS_ERR(opp)) {
+ dev_err(cpu_dev, "failed to find OPP for %ld\n", freq_hz);
+ return PTR_ERR(opp);
+ }
+ volt = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ dev_dbg(cpu_dev, "%u MHz --> %u MHz\n",
+ old_freq / 1000, new_freq / 1000);
+
+ if (new_freq > old_freq) {
+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+ if (ret) {
+ dev_err(cpu_dev, "failed to scale arm_reg up: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ clk_set_parent(clks[A53_SRC].clk, clks[SYS1_PLL_800M].clk);
+ clk_set_rate(clks[ARM_PLL].clk, new_freq * 1000);
+ clk_set_parent(clks[A53_SRC].clk, clks[ARM_PLL_OUT].clk);
+
+ /* Ensure the arm clock divider is what we expect */
+ ret = clk_set_rate(clks[A53].clk, new_freq * 1000);
+ if (ret)
+ dev_err(cpu_dev, "failed to set clock rate: %d\n", ret);
+
+ if (new_freq < old_freq) {
+ ret = regulator_set_voltage_tol(arm_reg, volt, 0);
+ if (ret) {
+ dev_err(cpu_dev, "failed to scale arm_reg down: %d\n",
+ ret);
+ return ret;
+ }
+ }
+
+ return ret;
+}
+
+static void imx8mq_cpufreq_ready(struct cpufreq_policy *policy)
+{
+ cdev = of_cpufreq_cooling_register(policy);
+}
+
+static int imx8mq_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int ret;
+
+ policy->clk =
[PATCH] ARM: dts: imx6sx-sabreauto: add debug LED support
There is a debug LED(D11) connected to GPIO1_IO24, add
support for it.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
this patch is based on patch series (ARM: dts: imx6sx-sabreauto: add wdog
external reset support).
arch/arm/boot/dts/imx6sx-sabreauto.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index eb1452c..6b94f24 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -18,6 +18,18 @@
reg = <0x8000 0x8000>;
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led>;
+
+ user {
+ label = "debug";
+ gpios = < 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
regulators {
compatible = "simple-bus";
#address-cells = <1>;
@@ -119,6 +131,12 @@
{
imx6x-sabreauto {
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
+ >;
+ };
+
pinctrl_enet1_1: enet1grp-1 {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO0xa0b1
--
2.7.4
[PATCH] ARM: dts: imx6sx-sabreauto: add egalax touch screen support
From: Haibo Chen <haibo.c...@nxp.com>
Add egalax touch screen support on i2c2 bus.
Signed-off-by: Haibo Chen <haibo.c...@freescale.com>
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
this patch is based on patch (ARM: dts: imx6sx-sabreauto: add debug LED
support) I sent out for review.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 6b94f24..2f6e474 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -131,6 +131,12 @@
{
imx6x-sabreauto {
+ pinctrl_egalax_int: egalax_intgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22
0x8000
+ >;
+ };
+
pinctrl_led: ledgrp {
fsl,pins = <
MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
@@ -274,6 +280,16 @@
pinctrl-0 = <_i2c2_1>;
status = "okay";
+ egalax_ts@04 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_egalax_int>;
+ interrupt-parent = <>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = < 22 GPIO_ACTIVE_HIGH>;
+ };
+
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
--
2.7.4
RE: [PATCH V6 4/7] ARM: dts: imx6sx-sabreauto: add fec support
Hi, Fabio
Anson Huang
Best Regards!
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Saturday, May 5, 2018 8:11 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: Shawn Guo <shawn...@kernel.org>; Sascha Hauer
> <ker...@pengutronix.de>; Fabio Estevam <fabio.este...@nxp.com>; Rob
> Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>;
> Haibo Chen <haibo.c...@freescale.com>; Andy Duan
> <fugang.d...@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>; Robin Gong
> <yibin.g...@nxp.com>; dl-linux-imx <linux-...@nxp.com>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-ker...@lists.infradead.org>; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS <devicet...@vger.kernel.org>; linux-kernel
> <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH V6 4/7] ARM: dts: imx6sx-sabreauto: add fec support
>
> On Sat, May 5, 2018 at 5:29 AM, Anson Huang <anson.hu...@nxp.com>
> wrote:
> > Add FEC support on i.MX6SX Sabre Auto board.
> >
> > Signed-off-by: Fugang Duan <fugang.d...@nxp.com>
>
> Again, it is not clear who is the author here. Is it Fugang or yourself?
Same story explained in patch V6 7/7.
>
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > ---
> > changes since V5:
> > use "gpios" instead of "enable-gpio".
> > arch/arm/boot/dts/imx6sx-sabreauto.dts | 80
> > ++
> > 1 file changed, 80 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > b/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > index 4d41b4d..7dda741 100644
> > --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > @@ -18,6 +18,17 @@
> > reg = <0x8000 0x8000>;
> > };
> >
> > + reg_fec: fec_io_supply {
> > + compatible = "regulator-gpio";
> > + regulator-name = "1.8V_1.5V_FEC";
> > + regulator-min-microvolt = <150>;
> > + regulator-max-microvolt = <180>;
> > + states = <150 0x0 180 0x1>;
> > + gpios = < 0 GPIO_ACTIVE_HIGH>;
> > + vin-supply = <_reg>;
> > + enable-active-high;
> > + };
>
> I still find this confusing.
>
> There is no consumer for reg_fec in, so it seems you are relying on the fact
> that
> the kernel regulator core will disable reg_fec to put the regulator in the
> state
> you require.
Adding consumer for reg_fec in NOT available in this patch, as FEC driver itself
does NOT support setting IO voltage based on setting of dtb, so if want to add
consumer, need to patch FEC driver as well.
As I explained before, this reg is for adjusting IO voltage between 1.5V and
1.8V,
and FEC driver can work on both of them, current FEC driver can work well no
matter
if it is 1.5V or 1.8V, to avoid confusion, I think I can remove this reg_fec in
this patch series,
let FEC driver work with default setting of this GPIO regulator, we can add
reg_fec support
after FEC driver supports adjusting IO voltage. Thanks.
Anson.
RE: [PATCH V6 7/7] ARM: dts: imx6sx-sabreauto: add egalax touch screen support
Hi, Fabio
Anson Huang
Best Regards!
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Saturday, May 5, 2018 11:18 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: Shawn Guo <shawn...@kernel.org>; Sascha Hauer
> <ker...@pengutronix.de>; Fabio Estevam <fabio.este...@nxp.com>; Rob
> Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>;
> Haibo Chen <haibo.c...@freescale.com>; Andy Duan
> <fugang.d...@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>; Robin Gong
> <yibin.g...@nxp.com>; dl-linux-imx <linux-...@nxp.com>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-ker...@lists.infradead.org>; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS <devicet...@vger.kernel.org>; linux-kernel
> <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH V6 7/7] ARM: dts: imx6sx-sabreauto: add egalax touch
> screen support
>
> On Sat, May 5, 2018 at 5:29 AM, Anson Huang <anson.hu...@nxp.com>
> wrote:
>
> > {
> > + pinctrl_egalax_int: egalax-intgrp {
> > + fsl,pins = <
> > + MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22
> 0x8000
>
> Please avoid using 0x8000 and use the real IOMUX value instead.
Will use the expected pad settings in next version. Thanks.
Anson.
RE: [PATCH V6 7/7] ARM: dts: imx6sx-sabreauto: add egalax touch screen support
Hi, Fabio
Anson Huang
Best Regards!
> -Original Message-
> From: Fabio Estevam [mailto:feste...@gmail.com]
> Sent: Saturday, May 5, 2018 7:56 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: Shawn Guo <shawn...@kernel.org>; Sascha Hauer
> <ker...@pengutronix.de>; Fabio Estevam <fabio.este...@nxp.com>; Rob
> Herring <robh...@kernel.org>; Mark Rutland <mark.rutl...@arm.com>;
> Haibo Chen <haibo.c...@freescale.com>; Andy Duan
> <fugang.d...@nxp.com>; A.s. Dong <aisheng.d...@nxp.com>; Robin Gong
> <yibin.g...@nxp.com>; dl-linux-imx <linux-...@nxp.com>; moderated
> list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE
> <linux-arm-ker...@lists.infradead.org>; open list:OPEN FIRMWARE AND
> FLATTENED DEVICE TREE BINDINGS <devicet...@vger.kernel.org>; linux-kernel
> <linux-kernel@vger.kernel.org>
> Subject: Re: [PATCH V6 7/7] ARM: dts: imx6sx-sabreauto: add egalax touch
> screen support
>
> Hi Anson,
>
> On Sat, May 5, 2018 at 5:29 AM, Anson Huang <anson.hu...@nxp.com>
> wrote:
> > Add egalax touch screen support on i2c2 bus.
> >
> > Signed-off-by: Haibo Chen <haibo.c...@freescale.com>
>
> Is Haibo the author of this patch? If so, his name should appear in the From
> field.
I made this patch based on NXP kernel tree, Haibo is the original author of this
feature, but the original patch can NOT be applied directly, I have to refine
the patch
to meet the upstream requirement, so I added him as another signed-off tag,
to avoid confuse, I can remove this sign-off in next patch version. Same story
for other patches in this series.
>
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > ---
> > changes since V5:
> > improve pinctrl node name and touchscreen node name.
> > arch/arm/boot/dts/imx6sx-sabreauto.dts | 16
> > 1 file changed, 16 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > b/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > index 1dc5b58..3fe41d3 100644
> > --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
> > @@ -122,6 +122,12 @@
> > };
> >
> > {
> > + pinctrl_egalax_int: egalax-intgrp {
> > + fsl,pins = <
> > + MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22
> 0x8000
> > + >;
> > + };
> > +
> > pinctrl_enet1: enet1grp {
> > fsl,pins = <
> > MX6SX_PAD_ENET1_MDIO__ENET1_MDIO
> 0xa0b1
> > @@ -264,6 +270,16 @@
> > pinctrl-0 = <_i2c2>;
> > status = "okay";
> >
> > + egalax_touchscreen@4 {
>
> Should be touchscreen@4.
Will improve it in next patch version.
Anson.
[PATCH V7 5/7] ARM: dts: imx6sx-sabreauto: add wdog external reset
i.MX6SX Sabre Auto board has GPIO1_IO13 pin can be
MUXed as WDOG output to reset PMIC, add this function
support.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
no change.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index fff0081..146d5ab 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -221,6 +221,12 @@
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
+
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO13__WDOG1_WDOG_ANY0x30b0
+ >;
+ };
};
{
@@ -359,3 +365,9 @@
#gpio-cells = <2>;
};
};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_wdog>;
+ fsl,ext-reset-output;
+};
--
2.7.4
[PATCH V7 1/7] ARM: dts: imx6sx-sabreauto: add PMIC support
Add pfuze100 support on i.MX6SX Sabre Auto board.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V6:
remove unnecessary sign-off.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 116 +
1 file changed, 116 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 87ffe2c..1d8cf0f 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -66,6 +66,13 @@
};
{
+ pinctrl_i2c2: i2c2grp {
+ fsl,pins = <
+ MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
+ MX6SX_PAD_GPIO1_IO02__I2C2_SCL 0x4001b8b1
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
@@ -139,3 +146,112 @@
>;
};
};
+
+ {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c2>;
+ status = "okay";
+
+ pfuze100: pmic@8 {
+ compatible = "fsl,pfuze100";
+ reg = <0x08>;
+
+ regulators {
+ sw1a_reg: sw1ab {
+ regulator-min-microvolt = <30>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw1c_reg: sw1c {
+ regulator-min-microvolt = <30>;
+ regulator-max-microvolt = <1875000>;
+ regulator-boot-on;
+ regulator-always-on;
+ regulator-ramp-delay = <6250>;
+ };
+
+ sw2_reg: sw2 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <330>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3a_reg: sw3a {
+ regulator-min-microvolt = <40>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw3b_reg: sw3b {
+ regulator-min-microvolt = <40>;
+ regulator-max-microvolt = <1975000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ sw4_reg: sw4 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ swbst_reg: swbst {
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <515>;
+ };
+
+ snvs_reg: vsnvs {
+ regulator-min-microvolt = <100>;
+ regulator-max-microvolt = <300>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vref_reg: vrefddr {
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ vgen1_reg: vgen1 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <155>;
+ regulator-always-on;
+ };
+
+ vgen2_reg: vgen2 {
+ regulator-min-microvolt = <80>;
+ regulator-max-microvolt = <155>;
+ };
+
+ vgen3_reg: vgen3 {
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <330>;
+ regulator-always-on;
+ };
+
+ vgen4_reg: vgen4 {
+ regulator-min-microvolt = <180>;
+ regulator-ma
[PATCH V7 7/7] ARM: dts: imx6sx-sabreauto: add egalax touch screen support
Add egalax touch screen support on i2c2 bus.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V6:
remove unnecessary sign-off, improve node name and add PAD setting
value.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 8e6bd9d..bfbcf70 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -111,6 +111,12 @@
};
{
+ pinctrl_egalax_int: egalax-intgrp {
+ fsl,pins = <
+ MX6SX_PAD_SD4_RESET_B__GPIO6_IO_22 0x10b0
+ >;
+ };
+
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO0xa0b1
@@ -253,6 +259,16 @@
pinctrl-0 = <_i2c2>;
status = "okay";
+ touchscreen@4 {
+ compatible = "eeti,egalax_ts";
+ reg = <0x04>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_egalax_int>;
+ interrupt-parent = <>;
+ interrupts = <22 IRQ_TYPE_EDGE_FALLING>;
+ wakeup-gpios = < 22 GPIO_ACTIVE_HIGH>;
+ };
+
pfuze100: pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x08>;
--
2.7.4
[PATCH V7 3/7] ARM: dts: imx6sx-sabreauto: add IO expander max7310 support
i.MX6SX Sabre Auto board has two max7310 IO expander on I2C3 bus, add
support for them.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V6:
remove unnecessary sign-off.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 28
1 file changed, 28 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index ae253af..4d41b4d 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -73,6 +73,13 @@
>;
};
+ pinctrl_i2c3: i2c3grp {
+ fsl,pins = <
+ MX6SX_PAD_KEY_ROW4__I2C3_SDA0x4001b8b1
+ MX6SX_PAD_KEY_COL4__I2C3_SCL0x4001b8b1
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
@@ -262,3 +269,24 @@
#gpio-cells = <2>;
};
};
+
+ {
+ clock-frequency = <10>;
+ pinctrl-names = "default";
+ pinctrl-0 = <_i2c3>;
+ status = "okay";
+
+ max7310_a: gpio@30 {
+ compatible = "maxim,max7310";
+ reg = <0x30>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+
+ max7310_b: gpio@32 {
+ compatible = "maxim,max7310";
+ reg = <0x32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+};
--
2.7.4
[PATCH V7 6/7] ARM: dts: imx6sx-sabreauto: add debug LED support
There is a debug LED(D11) connected to GPIO1_IO24,
add support for it.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
no change.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 18 ++
1 file changed, 18 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 146d5ab..8e6bd9d 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -18,6 +18,18 @@
reg = <0x8000 0x8000>;
};
+ leds {
+ compatible = "gpio-leds";
+ pinctrl-names = "default";
+ pinctrl-0 = <_led>;
+
+ user {
+ label = "debug";
+ gpios = < 24 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ };
+ };
+
vcc_sd3: regulator-vcc-sd3 {
compatible = "regulator-fixed";
pinctrl-names = "default";
@@ -149,6 +161,12 @@
>;
};
+ pinctrl_led: ledgrp {
+ fsl,pins = <
+ MX6SX_PAD_CSI_PIXCLK__GPIO1_IO_24 0x17059
+ >;
+ };
+
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
--
2.7.4
[PATCH V7 4/7] ARM: dts: imx6sx-sabreauto: add fec support
Add FEC support on i.MX6SX Sabre Auto board.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V6:
remove unnecessary sign-off and remove unused regulator for adjusting
fec IO voltage.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 69 ++
1 file changed, 69 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 4d41b4d..fff0081 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -34,6 +34,39 @@
clock-frequency = <24576000>;
};
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_enet1>;
+ phy-mode = "rgmii";
+ phy-handle = <>;
+ fsl,magic-packet;
+ status = "okay";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ };
+
+ ethphy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+ };
+ };
+};
+
+ {
+ pinctrl-names = "default";
+ pinctrl-0 = <_enet2>;
+ phy-mode = "rgmii";
+ phy-handle = <>;
+ fsl,magic-packet;
+ status = "okay";
+};
+
{
pinctrl-names = "default";
pinctrl-0 = <_uart1>;
@@ -66,6 +99,42 @@
};
{
+ pinctrl_enet1: enet1grp {
+ fsl,pins = <
+ MX6SX_PAD_ENET1_MDIO__ENET1_MDIO0xa0b1
+ MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
+ MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN0xa0b1
+ MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
+ MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN0x3081
+ >;
+ };
+
+ pinctrl_enet2: enet2grp {
+ fsl,pins = <
+ MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
+ MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
+ MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
+ MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
+ MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
+ MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN0xa0b1
+ MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
+ MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
+ MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
+ MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
+ MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
+ MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN0x3081
+ >;
+ };
+
pinctrl_i2c2: i2c2grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO03__I2C2_SDA 0x4001b8b1
--
2.7.4
[PATCH V7 2/7] ARM: dts: imx6sx-sabreauto: add max7322 IO expander support
Add MAX7322 IO expander support.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V6:
remove unnecessary sign-off.
arch/arm/boot/dts/imx6sx-sabreauto.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts
b/arch/arm/boot/dts/imx6sx-sabreauto.dts
index 1d8cf0f..ae253af 100644
--- a/arch/arm/boot/dts/imx6sx-sabreauto.dts
+++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts
@@ -254,4 +254,11 @@
};
};
};
+
+ max7322: gpio@68 {
+ compatible = "maxim,max7322";
+ reg = <0x68>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
};
--
2.7.4
[PATCH 2/2] ARM: dts: imx7: correct enet clock settings
This patch corrects ENET "ipg" and "enet_out" clock settings according to clock driver's changes. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by: Anson Huang <anson.hu...@nxp.com> --- arch/arm/boot/dts/imx7d.dtsi | 4 ++-- arch/arm/boot/dts/imx7s.dtsi | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 200714e..92022ea 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -120,11 +120,11 @@ , , ; - clocks = < IMX7D_ENET_AXI_ROOT_CLK>, + clocks = < IMX7D_ENET2_IPG_ROOT_CLK>, < IMX7D_ENET_AXI_ROOT_CLK>, < IMX7D_ENET2_TIME_ROOT_CLK>, < IMX7D_PLL_ENET_MAIN_125M_CLK>, - < IMX7D_ENET_PHY_REF_ROOT_CLK>; + < IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 4d42335..cf4ba53 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1091,11 +1091,11 @@ , , ; - clocks = < IMX7D_ENET_AXI_ROOT_CLK>, + clocks = < IMX7D_ENET1_IPG_ROOT_CLK>, < IMX7D_ENET_AXI_ROOT_CLK>, < IMX7D_ENET1_TIME_ROOT_CLK>, < IMX7D_PLL_ENET_MAIN_125M_CLK>, - < IMX7D_ENET_PHY_REF_ROOT_CLK>; + < IMX7D_ENET_PHY_REF_ROOT_DIV>; clock-names = "ipg", "ahb", "ptp", "enet_clk_ref", "enet_out"; fsl,num-tx-queues=<3>; -- 2.7.4
[PATCH 1/2] clk: imx7d: correct enet clock CCGR register offset
Correct enet clock CCGR register offset.
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY,
no gate after this clock, its parent clock root has gate.
IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supplies clocks
for enet IPG_CLK_RMII, no gate after the clock, its parent
clock root has gate.
IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supplies clock for
enet RGMII tx_clk.
Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 11 ++-
include/dt-bindings/clock/imx7d-clock.h | 4 +++-
2 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 975a20d..485ab49 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -26,6 +26,8 @@ static u32 share_count_sai1;
static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_nand;
+static u32 share_count_enet1;
+static u32 share_count_enet2;
static const struct clk_div_table test_div_table[] = {
{ .val = 3, .div = 1, },
@@ -805,6 +807,10 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk",
"mipi_dsi_post_div", base + 0x4650, 0);
clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk",
"mipi_csi_post_div", base + 0x4640, 0);
clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk",
"mipi_dphy_post_div", base + 0x4660, 0);
+ clks[IMX7D_ENET1_IPG_ROOT_CLK] =
imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700,
0, _count_enet1);
+ clks[IMX7D_ENET1_TIME_ROOT_CLK] =
imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base +
0x4700, 0, _count_enet1);
+ clks[IMX7D_ENET2_IPG_ROOT_CLK] =
imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710,
0, _count_enet2);
+ clks[IMX7D_ENET2_TIME_ROOT_CLK] =
imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base +
0x4710, 0, _count_enet2);
clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk",
"sai1_post_div", base + 0x48c0, 0, _count_sai1);
clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk",
"ipg_root_clk", base + 0x48c0, 0, _count_sai1);
clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk",
"sai2_post_div", base + 0x48d0, 0, _count_sai2);
@@ -812,11 +818,6 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk",
"sai3_post_div", base + 0x48e0, 0, _count_sai3);
clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk",
"ipg_root_clk", base + 0x48e0, 0, _count_sai3);
clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk",
"spdif_post_div", base + 0x44d0, 0);
- clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk",
"enet1_ref_post_div", base + 0x44e0, 0);
- clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk",
"enet1_time_post_div", base + 0x44f0, 0);
- clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk",
"enet2_ref_post_div", base + 0x4500, 0);
- clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk",
"enet2_time_post_div", base + 0x4510, 0);
- clks[IMX7D_ENET_PHY_REF_ROOT_CLK] =
imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520,
0);
clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk",
"eim_post_div", base + 0x4160, 0);
clks[IMX7D_NAND_RAWNAND_CLK] =
imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0,
_count_nand);
clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] =
imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base +
0x4140, 0, _count_nand);
diff --git a/include/dt-bindings/clock/imx7d-clock.h
b/include/dt-bindings/clock/imx7d-clock.h
index b2325d3e2..fef0647 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -455,5 +455,7 @@
#define IMX7D_SNVS_CLK 442
#define IMX7D_CAAM_CLK 443
#define IMX7D_KPP_ROOT_CLK 444
-#define IMX7D_CLK_END 445
+#define IMX7D_ENET1_IPG_ROOT_CLK445
+#define IMX7D_ENET2_IPG_ROOT_CLK446
+#define IMX7D_CLK_END 447
#endif /* __DT_BINDINGS_CLOCK_IMX7D_H */
--
2.7.4
[PATCH 2/2] regulator: pfuze100: add .is_enable() for pfuze100_swb_regulator_ops
If is_enabled() is not defined, regulator core will assume
this regulator is already enabled, then it can NOT be really
enabled after disabled.
Based on Li Jun's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/regulator/pfuze100-regulator.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/regulator/pfuze100-regulator.c
b/drivers/regulator/pfuze100-regulator.c
index 053eb1e..677a070 100644
--- a/drivers/regulator/pfuze100-regulator.c
+++ b/drivers/regulator/pfuze100-regulator.c
@@ -168,6 +168,7 @@ static const struct regulator_ops pfuze100_sw_regulator_ops
= {
static const struct regulator_ops pfuze100_swb_regulator_ops = {
.enable = regulator_enable_regmap,
.disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
.list_voltage = regulator_list_voltage_table,
.map_voltage = regulator_map_voltage_ascend,
.set_voltage_sel = regulator_set_voltage_sel_regmap,
--
2.7.4
[PATCH 1/2] regulator: pfuze100: add enable/disable for switch
Add enable/disable support for switch regulator on pfuze100.
Based on Robin Gong's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/regulator/pfuze100-regulator.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/regulator/pfuze100-regulator.c
b/drivers/regulator/pfuze100-regulator.c
index 680f076..053eb1e 100644
--- a/drivers/regulator/pfuze100-regulator.c
+++ b/drivers/regulator/pfuze100-regulator.c
@@ -155,6 +155,9 @@ static const struct regulator_ops
pfuze100_fixed_regulator_ops = {
};
static const struct regulator_ops pfuze100_sw_regulator_ops = {
+ .enable = regulator_enable_regmap,
+ .disable = regulator_disable_regmap,
+ .is_enabled = regulator_is_enabled_regmap,
.list_voltage = regulator_list_voltage_linear,
.set_voltage_sel = regulator_set_voltage_sel_regmap,
.get_voltage_sel = regulator_get_voltage_sel_regmap,
@@ -200,6 +203,11 @@ static const struct regulator_ops
pfuze100_swb_regulator_ops = {
.uV_step = (step), \
.vsel_reg = (base) + PFUZE100_VOL_OFFSET, \
.vsel_mask = 0x3f, \
+ .enable_reg = (base) + PFUZE100_MODE_OFFSET,\
+ .enable_val = 0xc, \
+ .disable_val = 0x0, \
+ .enable_mask = 0xf, \
+ .enable_time = 500, \
}, \
.stby_reg = (base) + PFUZE100_STANDBY_OFFSET, \
.stby_mask = 0x3f, \
--
2.7.4
[PATCH] ARM: dts: imx7d: correct cpu supply name for voltage scaling
Correct CPU supply name to meet cpufreq-dt driver's
requirement for voltage scaling.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 4 ++--
arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +-
arch/arm/boot/dts/imx7d-sdb.dts | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 7f64568..60deaf9 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -33,7 +33,7 @@
};
{
- arm-supply = <_reg>;
+ cpu-supply = <_reg>;
};
{
@@ -284,4 +284,4 @@
MX7D_PAD_LPSR_GPIO1_IO05__GPIO1_IO5 0x14 /* OTG
PWREN */
>;
};
-};
\ No newline at end of file
+};
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts
b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index b8e73b4..70c53e5 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -144,7 +144,7 @@
};
{
- arm-supply = <_reg>;
+ cpu-supply = <_reg>;
};
{
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 722a45a..9408491 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -141,7 +141,7 @@
};
{
- arm-supply = <_reg>;
+ cpu-supply = <_reg>;
};
{
--
2.7.4
[PATCH] ARM: dts: imx7s-warp: remove unnecessary cpu regulator supply
i.MX7S does NOT support CPU frequency scaling, so no
need to specify the CPU regulator supply.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx7s-warp.dts | 4
1 file changed, 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx7s-warp.dts b/arch/arm/boot/dts/imx7s-warp.dts
index 8a30b14..fa390da 100644
--- a/arch/arm/boot/dts/imx7s-warp.dts
+++ b/arch/arm/boot/dts/imx7s-warp.dts
@@ -113,10 +113,6 @@
assigned-clock-rates = <884736000>;
};
- {
- arm-supply = <_reg>;
-};
-
{
pinctrl-names = "default";
pinctrl-0 = <_i2c1>;
--
2.7.4
[PATCH] gpio: mxc: add clock operation
i.MX6SLL has GPIO clock gates in CCM CCGR, need
to enable them before accessing registers, add
optional clock operation for GPIO driver.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/gpio/gpio-mxc.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 11ec722..8fc37c4 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -60,6 +60,7 @@ struct mxc_gpio_hwdata {
struct mxc_gpio_port {
struct list_head node;
void __iomem *base;
+ struct clk *clk;
int irq;
int irq_high;
struct irq_domain *domain;
@@ -434,6 +435,17 @@ static int mxc_gpio_probe(struct platform_device *pdev)
if (port->irq < 0)
return port->irq;
+ /* the controller clock is optional */
+ port->clk = devm_clk_get(>dev, NULL);
+ if (IS_ERR(port->clk))
+ port->clk = NULL;
+
+ err = clk_prepare_enable(port->clk);
+ if (err) {
+ dev_err(>dev, "Unable to enable clock.\n");
+ return err;
+ }
+
/* disable the interrupt and clear the status */
writel(0, port->base + GPIO_IMR);
writel(~0, port->base + GPIO_ISR);
@@ -502,6 +514,7 @@ static int mxc_gpio_probe(struct platform_device *pdev)
out_irqdomain_remove:
irq_domain_remove(port->domain);
out_bgio:
+ clk_disable_unprepare(port->clk);
dev_info(>dev, "%s failed with errno %d\n", __func__, err);
return err;
}
--
2.7.4
[PATCH V2] gpio: mxc: add clock operation
Some i.MX SoCs have GPIO clock gates in CCM CCGR, such as
i.MX6SLL, need to enable clocks before accessing GPIO
registers, add optional clock operation for GPIO driver.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V1:
add missing clk header;
remove FSF addresses in copyright to avoid check patch ERROR.
drivers/gpio/gpio-mxc.c | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 11ec722..2026f94 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -14,12 +14,9 @@
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301,
USA.
*/
+#include
#include
#include
#include
@@ -60,6 +57,7 @@ struct mxc_gpio_hwdata {
struct mxc_gpio_port {
struct list_head node;
void __iomem *base;
+ struct clk *clk;
int irq;
int irq_high;
struct irq_domain *domain;
@@ -434,6 +432,17 @@ static int mxc_gpio_probe(struct platform_device *pdev)
if (port->irq < 0)
return port->irq;
+ /* the controller clock is optional */
+ port->clk = devm_clk_get(>dev, NULL);
+ if (IS_ERR(port->clk))
+ port->clk = NULL;
+
+ err = clk_prepare_enable(port->clk);
+ if (err) {
+ dev_err(>dev, "Unable to enable clock.\n");
+ return err;
+ }
+
/* disable the interrupt and clear the status */
writel(0, port->base + GPIO_IMR);
writel(~0, port->base + GPIO_ISR);
@@ -502,6 +511,7 @@ static int mxc_gpio_probe(struct platform_device *pdev)
out_irqdomain_remove:
irq_domain_remove(port->domain);
out_bgio:
+ clk_disable_unprepare(port->clk);
dev_info(>dev, "%s failed with errno %d\n", __func__, err);
return err;
}
--
2.7.4
RE: [PATCH V2] gpio: mxc: add clock operation
Hi, Fabio Anson Huang Best Regards! > -Original Message- > From: Fabio Estevam [mailto:feste...@gmail.com] > Sent: Tuesday, May 22, 2018 10:28 AM > To: Anson Huang <anson.hu...@nxp.com> > Cc: Linus Walleij <linus.wall...@linaro.org>; dl-linux-imx > <linux-...@nxp.com>; > linux-g...@vger.kernel.org; linux-kernel <linux-kernel@vger.kernel.org> > Subject: Re: [PATCH V2] gpio: mxc: add clock operation > > Hi Anson, > > On Mon, May 21, 2018 at 10:15 PM, Anson Huang <anson.hu...@nxp.com> > wrote: > > Some i.MX SoCs have GPIO clock gates in CCM CCGR, such as i.MX6SLL, > > need to enable clocks before accessing GPIO registers, add optional > > clock operation for GPIO driver. > > > > Signed-off-by: Anson Huang <anson.hu...@nxp.com> > > --- > > changes since V1: > > add missing clk header; > > remove FSF addresses in copyright to avoid check patch ERROR. > > drivers/gpio/gpio-mxc.c | 18 ++ > > 1 file changed, 14 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c index > > 11ec722..2026f94 100644 > > --- a/drivers/gpio/gpio-mxc.c > > +++ b/drivers/gpio/gpio-mxc.c > > @@ -14,12 +14,9 @@ > > * but WITHOUT ANY WARRANTY; without even the implied warranty of > > * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > > * GNU General Public License for more details. > > - * > > - * You should have received a copy of the GNU General Public License > > - * along with this program; if not, write to the Free Software > > - * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA > > 02110-1301, > USA. > > */ > > This is an unrelated change and should be part of a different patch. > > A patch that converts this driver to use SPDX would get rid of the FSF > address. Thanks, I will rework it into 2 patches, using SPDX. Anson.
RE: [PATCH V2] gpio: mxc: add clock operation
Anson Huang Best Regards! > -Original Message- > From: Fabio Estevam [mailto:feste...@gmail.com] > Sent: Tuesday, May 22, 2018 10:34 AM > To: Anson Huang <anson.hu...@nxp.com> > Cc: Linus Walleij <linus.wall...@linaro.org>; dl-linux-imx > <linux-...@nxp.com>; > linux-g...@vger.kernel.org; linux-kernel <linux-kernel@vger.kernel.org> > Subject: Re: [PATCH V2] gpio: mxc: add clock operation > > Hi Anson, > > On Mon, May 21, 2018 at 11:29 PM, Anson Huang <anson.hu...@nxp.com> > wrote: > > > Thanks, I will rework it into 2 patches, using SPDX. > > I have just sent a series that converts gpio-mxc and gpio-mxs to use SPDX > identifier and put you on Cc. > > You can base your change on top of mine. > > Thanks OK, thanks.
[PATCH V3] gpio: mxc: add clock operation
Some i.MX SoCs have GPIO clock gates in CCM CCGR, such as
i.MX6SLL, need to enable clocks before accessing GPIO
registers, add optional clock operation for GPIO driver.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
changes since V2:
remove the copyright change, since the change is already done by
Fabio's patch [1/2] gpio: mxc: Switch to SPDX identifier, I redo
the patch on top of it.
drivers/gpio/gpio-mxc.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 6a9dc61..2f28299 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -7,6 +7,7 @@
// Authors: Daniel Mack, Juergen Beisert.
// Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
+#include
#include
#include
#include
@@ -47,6 +48,7 @@ struct mxc_gpio_hwdata {
struct mxc_gpio_port {
struct list_head node;
void __iomem *base;
+ struct clk *clk;
int irq;
int irq_high;
struct irq_domain *domain;
@@ -421,6 +423,17 @@ static int mxc_gpio_probe(struct platform_device *pdev)
if (port->irq < 0)
return port->irq;
+ /* the controller clock is optional */
+ port->clk = devm_clk_get(>dev, NULL);
+ if (IS_ERR(port->clk))
+ port->clk = NULL;
+
+ err = clk_prepare_enable(port->clk);
+ if (err) {
+ dev_err(>dev, "Unable to enable clock.\n");
+ return err;
+ }
+
/* disable the interrupt and clear the status */
writel(0, port->base + GPIO_IMR);
writel(~0, port->base + GPIO_ISR);
@@ -489,6 +502,7 @@ static int mxc_gpio_probe(struct platform_device *pdev)
out_irqdomain_remove:
irq_domain_remove(port->domain);
out_bgio:
+ clk_disable_unprepare(port->clk);
dev_info(>dev, "%s failed with errno %d\n", __func__, err);
return err;
}
--
2.7.4
[PATCH 2/2] ARM: dts: imx6ul: add GPIO clocks
i.MX6UL has GPIO clock gates in CCM CCGR, add clock property for GPIO driver to make sure all GPIO banks work as expected. Signed-off-by: Anson Huang <anson.hu...@nxp.com> --- arch/arm/boot/dts/imx6ul.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 1241972..405e068 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -437,6 +437,7 @@ reg = <0x0209c000 0x4000>; interrupts = , ; + clocks = < IMX6UL_CLK_GPIO1>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -450,6 +451,7 @@ reg = <0x020a 0x4000>; interrupts = , ; + clocks = < IMX6UL_CLK_GPIO2>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -462,6 +464,7 @@ reg = <0x020a4000 0x4000>; interrupts = , ; + clocks = < IMX6UL_CLK_GPIO3>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -474,6 +477,7 @@ reg = <0x020a8000 0x4000>; interrupts = , ; + clocks = < IMX6UL_CLK_GPIO4>; gpio-controller; #gpio-cells = <2>; interrupt-controller; @@ -486,6 +490,7 @@ reg = <0x020ac000 0x4000>; interrupts = , ; + clocks = < IMX6UL_CLK_GPIO5>; gpio-controller; #gpio-cells = <2>; interrupt-controller; -- 2.7.4
[PATCH 1/2] clk: imx6ul: add GPIO clock gates
i.MX6UL has GPIO clock gates in CCM CCGR, add
them into clock tree for clock management.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx6ul.c | 5 +
include/dt-bindings/clock/imx6ul-clock.h | 31 ++-
2 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6ul.c b/drivers/clk/imx/clk-imx6ul.c
index ba563ba..3ea2d97 100644
--- a/drivers/clk/imx/clk-imx6ul.c
+++ b/drivers/clk/imx/clk-imx6ul.c
@@ -360,6 +360,7 @@ static void __init imx6ul_clocks_init(struct device_node
*ccm_node)
clks[IMX6UL_CLK_UART2_SERIAL] = imx_clk_gate2("uart2_serial",
"uart_podf",base + 0x68,28);
if (clk_on_imx6ull())
clks[IMX6UL_CLK_AIPSTZ3]= imx_clk_gate2("aips_tz3",
"ahb", base + 0x80, 18);
+ clks[IMX6UL_CLK_GPIO2] = imx_clk_gate2("gpio2","ipg",
base + 0x68,30);
/* CCGR1 */
clks[IMX6UL_CLK_ECSPI1] = imx_clk_gate2("ecspi1",
"ecspi_podf", base + 0x6c,0);
@@ -376,6 +377,8 @@ static void __init imx6ul_clocks_init(struct device_node
*ccm_node)
clks[IMX6UL_CLK_GPT1_SERIAL]= imx_clk_gate2("gpt1_serial",
"perclk", base + 0x6c,22);
clks[IMX6UL_CLK_UART4_IPG] = imx_clk_gate2("uart4_ipg","ipg",
base + 0x6c,24);
clks[IMX6UL_CLK_UART4_SERIAL] = imx_clk_gate2("uart4_serial",
"uart_podf",base + 0x6c,24);
+ clks[IMX6UL_CLK_GPIO1] = imx_clk_gate2("gpio1","ipg",
base + 0x6c,26);
+ clks[IMX6UL_CLK_GPIO5] = imx_clk_gate2("gpio5","ipg",
base + 0x6c,30);
/* CCGR2 */
if (clk_on_imx6ull()) {
@@ -389,6 +392,7 @@ static void __init imx6ul_clocks_init(struct device_node
*ccm_node)
clks[IMX6UL_CLK_I2C3] = imx_clk_gate2("i2c3",
"perclk", base + 0x70,10);
clks[IMX6UL_CLK_OCOTP] = imx_clk_gate2("ocotp","ipg",
base + 0x70,12);
clks[IMX6UL_CLK_IOMUXC] = imx_clk_gate2("iomuxc",
"lcdif_podf", base + 0x70,14);
+ clks[IMX6UL_CLK_GPIO3] = imx_clk_gate2("gpio3","ipg",
base + 0x70,26);
clks[IMX6UL_CLK_LCDIF_APB] = imx_clk_gate2("lcdif_apb","axi",
base + 0x70,28);
clks[IMX6UL_CLK_PXP]= imx_clk_gate2("pxp", "axi",
base + 0x70,30);
@@ -405,6 +409,7 @@ static void __init imx6ul_clocks_init(struct device_node
*ccm_node)
clks[IMX6UL_CLK_UART6_IPG] = imx_clk_gate2("uart6_ipg","ipg",
base + 0x74,6);
clks[IMX6UL_CLK_UART6_SERIAL] = imx_clk_gate2("uart6_serial",
"uart_podf",base + 0x74,6);
clks[IMX6UL_CLK_LCDIF_PIX] = imx_clk_gate2("lcdif_pix",
"lcdif_podf", base + 0x74,10);
+ clks[IMX6UL_CLK_GPIO4] = imx_clk_gate2("gpio4","ipg",
base + 0x74,12);
clks[IMX6UL_CLK_QSPI] = imx_clk_gate2("qspi1",
"qspi1_podf", base + 0x74,14);
clks[IMX6UL_CLK_WDOG1] = imx_clk_gate2("wdog1","ipg",
base + 0x74,16);
clks[IMX6UL_CLK_MMDC_P0_FAST] = imx_clk_gate("mmdc_p0_fast",
"mmdc_podf", base + 0x74,20);
diff --git a/include/dt-bindings/clock/imx6ul-clock.h
b/include/dt-bindings/clock/imx6ul-clock.h
index 9564597..1291328 100644
--- a/include/dt-bindings/clock/imx6ul-clock.h
+++ b/include/dt-bindings/clock/imx6ul-clock.h
@@ -242,20 +242,25 @@
#define IMX6UL_CLK_CKO2_PODF 229
#define IMX6UL_CLK_CKO2230
#define IMX6UL_CLK_CKO 231
+#define IMX6UL_CLK_GPIO1 232
+#define IMX6UL_CLK_GPIO2 233
+#define IMX6UL_CLK_GPIO3 234
+#define IMX6UL_CLK_GPIO4 235
+#define IMX6UL_CLK_GPIO5 236
/* For i.MX6ULL */
-#define IMX6ULL_CLK_ESAI_PRED 232
-#define IMX6ULL_CLK_ESAI_PODF 233
-#define IMX6ULL_CLK_ESAI_EXTAL 234
-#define IMX6ULL_CLK_ESAI_MEM 235
-#define IMX6ULL_CLK_ESAI_IPG 236
-#define IMX6ULL_CLK_DCP_CLK237
-#define IMX6ULL_CLK_EPDC_PRE_SEL 238
-#define IMX6ULL_CLK_EPDC_SEL 239
-#define IMX6ULL_CLK_EPDC_PODF 240
-#define IMX6ULL_CLK_EPDC_ACLK 241
-#define IMX6ULL_CLK_EPDC_PIX 242
-#define IMX6ULL_CLK_ESAI_SEL 243
-#
RE: [PATCH] irqchip: gpcv2: remove unnecessary functions
Hi, Marc
Anson Huang
Best Regards!
> -Original Message-
> From: Marc Zyngier [mailto:marc.zyng...@arm.com]
> Sent: Wednesday, May 23, 2018 3:23 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: t...@linutronix.de; ja...@lakedaemon.net; dl-linux-imx
> <linux-...@nxp.com>; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] irqchip: gpcv2: remove unnecessary functions
>
> On Wed, 23 May 2018 07:23:00 +0100,
> Anson Huang wrote:
> >
> > GPC is in always-on domain, it never lost its content during
> > suspend/resume, so no need to do save/restore for it during
> > suspend/resume.
> >
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > ---
> > drivers/irqchip/irq-imx-gpcv2.c | 41
> > -
> > 1 file changed, 41 deletions(-)
> >
> > diff --git a/drivers/irqchip/irq-imx-gpcv2.c
> > b/drivers/irqchip/irq-imx-gpcv2.c index 4760307..e6025d9 100644
> > --- a/drivers/irqchip/irq-imx-gpcv2.c
> > +++ b/drivers/irqchip/irq-imx-gpcv2.c
> > @@ -28,46 +28,6 @@ struct gpcv2_irqchip_data {
> >
> > static struct gpcv2_irqchip_data *imx_gpcv2_instance;
> >
> > -static int gpcv2_wakeup_source_save(void) -{
> > - struct gpcv2_irqchip_data *cd;
> > - void __iomem *reg;
> > - int i;
> > -
> > - cd = imx_gpcv2_instance;
> > - if (!cd)
> > - return 0;
> > -
> > - for (i = 0; i < IMR_NUM; i++) {
> > - reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
> > - cd->saved_irq_mask[i] = readl_relaxed(reg);
> > - writel_relaxed(cd->wakeup_sources[i], reg);
> > - }
>
> If you're removing that code, what's the purpose of keeping saved_irq_mask?
>
> Also, who is now programming the wake-up_source? For good or bad reasons,
> this drivers uses the save/restore hooks to program the wake-up state.
> Removing this code seem to simply kill the feature.
>
> What am I missing?
>
> Thanks,
I made a mistake here, forgot to program the wakeup source into GPC IMR register
In imx_gpcv2_irq_set_wake function.
And I think we can remove the saved_irq_mask as well, will do it in V2.
The wake-up source is programmed by module driver calling "enable_irq_wake" if
device wakeup capability is enabled, and I miss to program into GPC IMR
register. Will
fix it later. Thanks.
Anson.
>
> M.
>
> --
> Jazz is not dead, it just smell funny.
[PATCH] irqchip: gpcv2: remove unnecessary functions
GPC is in always-on domain, it never lost its
content during suspend/resume, so no need to
do save/restore for it during suspend/resume.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/irqchip/irq-imx-gpcv2.c | 41 -
1 file changed, 41 deletions(-)
diff --git a/drivers/irqchip/irq-imx-gpcv2.c b/drivers/irqchip/irq-imx-gpcv2.c
index 4760307..e6025d9 100644
--- a/drivers/irqchip/irq-imx-gpcv2.c
+++ b/drivers/irqchip/irq-imx-gpcv2.c
@@ -28,46 +28,6 @@ struct gpcv2_irqchip_data {
static struct gpcv2_irqchip_data *imx_gpcv2_instance;
-static int gpcv2_wakeup_source_save(void)
-{
- struct gpcv2_irqchip_data *cd;
- void __iomem *reg;
- int i;
-
- cd = imx_gpcv2_instance;
- if (!cd)
- return 0;
-
- for (i = 0; i < IMR_NUM; i++) {
- reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
- cd->saved_irq_mask[i] = readl_relaxed(reg);
- writel_relaxed(cd->wakeup_sources[i], reg);
- }
-
- return 0;
-}
-
-static void gpcv2_wakeup_source_restore(void)
-{
- struct gpcv2_irqchip_data *cd;
- void __iomem *reg;
- int i;
-
- cd = imx_gpcv2_instance;
- if (!cd)
- return;
-
- for (i = 0; i < IMR_NUM; i++) {
- reg = cd->gpc_base + cd->cpu2wakeup + i * 4;
- writel_relaxed(cd->saved_irq_mask[i], reg);
- }
-}
-
-static struct syscore_ops imx_gpcv2_syscore_ops = {
- .suspend= gpcv2_wakeup_source_save,
- .resume = gpcv2_wakeup_source_restore,
-};
-
static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on)
{
struct gpcv2_irqchip_data *cd = d->chip_data;
@@ -252,7 +212,6 @@ static int __init imx_gpcv2_irqchip_init(struct device_node
*node,
writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup);
imx_gpcv2_instance = cd;
- register_syscore_ops(_gpcv2_syscore_ops);
/*
* Clear the OF_POPULATED flag set in of_irq_init so that
--
2.7.4
RE: [PATCH] gpio: mxc: add clock operation
Hi, Linus Anson Huang Best Regards! > -Original Message- > From: Linus Walleij [mailto:linus.wall...@linaro.org] > Sent: Thursday, May 24, 2018 4:13 PM > To: Anson Huang <anson.hu...@nxp.com> > Cc: dl-linux-imx <linux-...@nxp.com>; open list:GPIO SUBSYSTEM > <linux-g...@vger.kernel.org>; linux-kernel@vger.kernel.org > Subject: Re: [PATCH] gpio: mxc: add clock operation > > On Mon, May 21, 2018 at 12:06 PM, Anson Huang <anson.hu...@nxp.com> > wrote: > > > i.MX6SLL has GPIO clock gates in CCM CCGR, need to enable them before > > accessing registers, add optional clock operation for GPIO driver. > > > > Signed-off-by: Anson Huang <anson.hu...@nxp.com> > > Some warnings from the build robot, seem like a missing #include > or something. Please ignore this patch, the "[PATCH V3] gpio: mxc: add clock operation" is to fix this build warning. Thanks. Anson. > > Yours, > Linus Walleij
[PATCH V2] ARM: dts: imx7d: correct cpu supply name for voltage scaling
Correct CPU supply name to meet cpufreq-dt driver's
requirement for voltage scaling.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
Reviewed-by: Fabio Estevam <fabio.este...@nxp.com>
---
changes since V1:
fix the "No newline at end of file" caused by vim editor.
arch/arm/boot/dts/imx7d-cl-som-imx7.dts | 2 +-
arch/arm/boot/dts/imx7d-nitrogen7.dts | 2 +-
arch/arm/boot/dts/imx7d-sdb.dts | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
index 7f64568..8bf365d 100644
--- a/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
+++ b/arch/arm/boot/dts/imx7d-cl-som-imx7.dts
@@ -33,7 +33,7 @@
};
{
- arm-supply = <_reg>;
+ cpu-supply = <_reg>;
};
{
diff --git a/arch/arm/boot/dts/imx7d-nitrogen7.dts
b/arch/arm/boot/dts/imx7d-nitrogen7.dts
index b8e73b4..70c53e5 100644
--- a/arch/arm/boot/dts/imx7d-nitrogen7.dts
+++ b/arch/arm/boot/dts/imx7d-nitrogen7.dts
@@ -144,7 +144,7 @@
};
{
- arm-supply = <_reg>;
+ cpu-supply = <_reg>;
};
{
diff --git a/arch/arm/boot/dts/imx7d-sdb.dts b/arch/arm/boot/dts/imx7d-sdb.dts
index 722a45a..9408491 100644
--- a/arch/arm/boot/dts/imx7d-sdb.dts
+++ b/arch/arm/boot/dts/imx7d-sdb.dts
@@ -141,7 +141,7 @@
};
{
- arm-supply = <_reg>;
+ cpu-supply = <_reg>;
};
{
--
2.7.4
[PATCH] clk: imx6sl: correct ocram_podf clock type
IMX6SL_CLK_OCRAM_PODF is a busy divider, its name in
CCM_CDHIPR register of Reference Manual CCM chapter
is axi_podf_busy, correct its clock type.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx6sl.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/imx/clk-imx6sl.c b/drivers/clk/imx/clk-imx6sl.c
index 9642cdf..66b1dd1 100644
--- a/drivers/clk/imx/clk-imx6sl.c
+++ b/drivers/clk/imx/clk-imx6sl.c
@@ -330,7 +330,7 @@ static void __init imx6sl_clocks_init(struct device_node
*ccm_node)
clks[IMX6SL_CLK_PERIPH2] = imx_clk_busy_mux("periph2", base + 0x14, 26,
1, base + 0x48, 3, periph2_sels, ARRAY_SIZE(periph2_sels));
/* name
parent_name reg shift width */
- clks[IMX6SL_CLK_OCRAM_PODF]= imx_clk_divider("ocram_podf",
"ocram_sel", base + 0x14, 16, 3);
+ clks[IMX6SL_CLK_OCRAM_PODF]= imx_clk_busy_divider("ocram_podf",
"ocram_sel", base + 0x14, 16, 3, base + 0x48, 0);
clks[IMX6SL_CLK_PERIPH_CLK2_PODF] =
imx_clk_divider("periph_clk2_podf", "periph_clk2_sel", base + 0x14, 27, 3);
clks[IMX6SL_CLK_PERIPH2_CLK2_PODF] =
imx_clk_divider("periph2_clk2_podf", "periph2_clk2_sel", base + 0x14, 0, 3);
clks[IMX6SL_CLK_IPG] = imx_clk_divider("ipg",
"ahb", base + 0x14, 8, 2);
--
2.7.4
[PATCH] clk: imx6sx: disable unnecessary clocks during clock initialization
Disable those unnecessary clocks during kernel boot up to save power,
those modules clock should be managed by modules driver in runtime.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx6sx.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/clk/imx/clk-imx6sx.c b/drivers/clk/imx/clk-imx6sx.c
index 0178ee2..10c771b 100644
--- a/drivers/clk/imx/clk-imx6sx.c
+++ b/drivers/clk/imx/clk-imx6sx.c
@@ -97,12 +97,7 @@ static int const clks_init_on[] __initconst = {
IMX6SX_CLK_IPMUX1, IMX6SX_CLK_IPMUX2, IMX6SX_CLK_IPMUX3,
IMX6SX_CLK_WAKEUP, IMX6SX_CLK_MMDC_P0_FAST, IMX6SX_CLK_MMDC_P0_IPG,
IMX6SX_CLK_ROM, IMX6SX_CLK_ARM, IMX6SX_CLK_IPG, IMX6SX_CLK_OCRAM,
- IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_M4,
- IMX6SX_CLK_QSPI1, IMX6SX_CLK_QSPI2, IMX6SX_CLK_UART_IPG,
- IMX6SX_CLK_UART_SERIAL, IMX6SX_CLK_I2C3, IMX6SX_CLK_ECSPI5,
- IMX6SX_CLK_CAN1_IPG, IMX6SX_CLK_CAN1_SERIAL, IMX6SX_CLK_CAN2_IPG,
- IMX6SX_CLK_CAN2_SERIAL, IMX6SX_CLK_CANFD, IMX6SX_CLK_EPIT1,
- IMX6SX_CLK_EPIT2,
+ IMX6SX_CLK_PER2_MAIN, IMX6SX_CLK_PERCLK, IMX6SX_CLK_TZASC1,
};
static const struct clk_div_table clk_enet_ref_table[] = {
--
2.7.4
[PATCH] ARM: dts: imx7d: use operating-points-v2 for cpu
This patch uses "operating-points-v2" instead of
"operating-points" to be more fit with cpufreq-dt
driver.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
arch/arm/boot/dts/imx7d.dtsi | 24 +++-
1 file changed, 19 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi
index 4c9877e..28980c8 100644
--- a/arch/arm/boot/dts/imx7d.dtsi
+++ b/arch/arm/boot/dts/imx7d.dtsi
@@ -9,12 +9,8 @@
/ {
cpus {
cpu0: cpu@0 {
- operating-points = <
- /* KHz uV */
- 996000 1075000
- 792000 975000
- >;
clock-frequency = <99600>;
+ operating-points-v2 = <_opp_table>;
};
cpu1: cpu@1 {
@@ -22,6 +18,24 @@
device_type = "cpu";
reg = <1>;
clock-frequency = <99600>;
+ operating-points-v2 = <_opp_table>;
+ };
+ };
+
+ cpu0_opp_table: opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-79200 {
+ opp-hz = /bits/ 64 <79200>;
+ opp-microvolt = <975000>;
+ clock-latency-ns = <15>;
+ };
+ opp-99600 {
+ opp-hz = /bits/ 64 <99600>;
+ opp-microvolt = <1075000>;
+ clock-latency-ns = <15>;
+ opp-suspend;
};
};
--
2.7.4
RE: [PATCH] ARM: dts: imx7d: use operating-points-v2 for cpu
Anson Huang
Best Regards!
> -Original Message-
> From: Shawn Guo [mailto:shawn...@kernel.org]
> Sent: Sunday, May 20, 2018 8:51 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: ker...@pengutronix.de; Fabio Estevam <fabio.este...@nxp.com>;
> robh...@kernel.org; mark.rutl...@arm.com; dl-linux-imx
> <linux-...@nxp.com>; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH] ARM: dts: imx7d: use operating-points-v2 for cpu
>
> On Wed, May 16, 2018 at 12:48:17PM +0800, Anson Huang wrote:
> > This patch uses "operating-points-v2" instead of "operating-points" to
> > be more fit with cpufreq-dt driver.
> >
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > ---
> > arch/arm/boot/dts/imx7d.dtsi | 24 +++-
> > 1 file changed, 19 insertions(+), 5 deletions(-)
> >
> > diff --git a/arch/arm/boot/dts/imx7d.dtsi
> > b/arch/arm/boot/dts/imx7d.dtsi index 4c9877e..28980c8 100644
> > --- a/arch/arm/boot/dts/imx7d.dtsi
> > +++ b/arch/arm/boot/dts/imx7d.dtsi
> > @@ -9,12 +9,8 @@
> > / {
> > cpus {
> > cpu0: cpu@0 {
> > - operating-points = <
> > - /* KHz uV */
> > - 996000 1075000
> > - 792000 975000
> > - >;
> > clock-frequency = <99600>;
> > + operating-points-v2 = <_opp_table>;
> > };
> >
> > cpu1: cpu@1 {
> > @@ -22,6 +18,24 @@
> > device_type = "cpu";
> > reg = <1>;
> > clock-frequency = <99600>;
> > + operating-points-v2 = <_opp_table>;
> > + };
> > + };
> > +
> > + cpu0_opp_table: opp_table0 {
>
> Hyphen is recommended in node name. Also the suffix 0 doesn't mean too
> much here. That said, a better node name would be 'opp-table'.
>
> > + compatible = "operating-points-v2";
> > + opp-shared;
> > +
> > + opp-79200 {
> > + opp-hz = /bits/ 64 <79200>;
> > + opp-microvolt = <975000>;
> > + clock-latency-ns = <15>;
> > + };
>
> We recommend to have a newline between nodes.
>
> I fixed them all and applied the patch.
>
> Shawn
Thanks Shawn.
Anson.
>
> > + opp-99600 {
> > + opp-hz = /bits/ 64 <99600>;
> > + opp-microvolt = <1075000>;
> > + clock-latency-ns = <15>;
> > + opp-suspend;
> > };
> > };
> >
> > --
> > 2.7.4
> >
RE: [PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers
Hi, Stefan
Anson Huang
Best Regards!
> -Original Message-
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: Friday, May 18, 2018 9:02 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: shawn...@kernel.org; ker...@pengutronix.de; Fabio Estevam
> <fabio.este...@nxp.com>; robh...@kernel.org; mark.rutl...@arm.com;
> mturque...@baylibre.com; sb...@kernel.org; Adriana Reus
> <adriana.r...@nxp.com>; rui.si...@linaro.org; dl-linux-imx
> <linux-...@nxp.com>; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-...@vger.kernel.org
> Subject: Re: [PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers
>
> On 18.05.2018 03:01, Anson Huang wrote:
> > Correct enet clock gates as below:
> >
> > CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
> > CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
> > CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
> >
> > Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
> > IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.
>
> Are you sure that IMX7D_ENETx_REF_ROOT_CLK are not used?
>
> I understand that the reference manual does not a gate at 0x44e0...
>
> But in a earlier revision of our Colibri iMX7 we actually used clock out, and
> referenced this clock to enable the reference clock (see also:
> https://emea01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatch
> work.kernel.org%2Fpatch%2F9211371%2F=02%7C01%7CAnson.Huang%
> 40nxp.com%7Cea0856a68d8e4b921ba608d5bcbf9c02%7C686ea1d3bc2b4c6fa
> 92cd99c5c301635%7C0%7C1%7C63662245350330=rEhwj0innLDc
> AEgxJyqd5vtG3SNVS05r2hEFvSc%2BQQs%3D=0).
>
> I guess if the gate really does not exist, then we should/would have to set
> IMX7D_ENET1_REF_ROOT_DIV to use the SoC provided ref clock.
>
> --
> Stefan
I looked into the RTL and also checked with our design team, they confirm that
there is no CCGR78(0x44e0) and CCGR80(0x4500) on i.MX7D, the register offset
are there, but no hardware wire connection for them. That is why they did NOT
list them in Reference Manual. So I think we can remove them.
For your case of using them as clock input, maybe clock tree auto use its parent
IMX7D_ENETx_REF_ROOT_DIV which is existing, so it works.
Anson.
>
> >
> > Based on Andy Duan's patch from the NXP kernel tree.
> >
> > Signed-off-by: Anson Huang <anson.hu...@nxp.com>
> > ---
> > drivers/clk/imx/clk-imx7d.c | 10 ++
> > include/dt-bindings/clock/imx7d-clock.h | 4 ++--
> > 2 files changed, 8 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
> > index 23d5090a..d4936b9 100644
> > --- a/drivers/clk/imx/clk-imx7d.c
> > +++ b/drivers/clk/imx/clk-imx7d.c
> > @@ -26,6 +26,8 @@ static u32 share_count_sai1; static u32
> > share_count_sai2; static u32 share_count_sai3; static u32
> > share_count_nand;
> > +static u32 share_count_enet1;
> > +static u32 share_count_enet2;
> >
> > static const struct clk_div_table test_div_table[] = {
> > { .val = 3, .div = 1, },
> > @@ -805,6 +807,10 @@ static void __init imx7d_clocks_init(struct
> > device_node *ccm_node)
> > clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk",
> > "mipi_dsi_post_div", base + 0x4650, 0);
> > clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk",
> > "mipi_csi_post_div", base + 0x4640, 0);
> > clks[IMX7D_MIPI_DPHY_ROOT_CLK] =
> imx_clk_gate4("mipi_dphy_root_clk",
> > "mipi_dphy_post_div", base + 0x4660, 0);
> > + clks[IMX7D_ENET1_IPG_ROOT_CLK] =
> > imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base
> > + 0x4700, 0, _count_enet1);
> > + clks[IMX7D_ENET1_TIME_ROOT_CLK] =
> > imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div",
> > base + 0x4700, 0, _count_enet1);
> > + clks[IMX7D_ENET2_IPG_ROOT_CLK] =
> > imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base
> > + 0x4710, 0, _count_enet2);
> > + clks[IMX7D_ENET2_TIME_ROOT_CLK] =
> > imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div",
> > base + 0x4710, 0, _count_enet2);
> > clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk",
> > "sai1_post_div", base + 0x48c0, 0, _count_sai1);
> > clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk",
> > "ipg_root_clk", bas
[PATCH V2 3/3] ARM: dts: imx7: correct enet ipg clock
ENET "ipg" clock should be IMX7D_ENETx_IPG_ROOT_CLK rather than IMX7D_ENET_AXI_ROOT_CLK which is for ENET bus clock. Based on Andy Duan's patch from the NXP kernel tree. Signed-off-by: Anson Huang <anson.hu...@nxp.com> --- arch/arm/boot/dts/imx7d.dtsi | 2 +- arch/arm/boot/dts/imx7s.dtsi | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index 200714e..d74dd7f 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -120,7 +120,7 @@ , , ; - clocks = < IMX7D_ENET_AXI_ROOT_CLK>, + clocks = < IMX7D_ENET2_IPG_ROOT_CLK>, < IMX7D_ENET_AXI_ROOT_CLK>, < IMX7D_ENET2_TIME_ROOT_CLK>, < IMX7D_PLL_ENET_MAIN_125M_CLK>, diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 4d42335..b90769d 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -1091,7 +1091,7 @@ , , ; - clocks = < IMX7D_ENET_AXI_ROOT_CLK>, + clocks = < IMX7D_ENET1_IPG_ROOT_CLK>, < IMX7D_ENET_AXI_ROOT_CLK>, < IMX7D_ENET1_TIME_ROOT_CLK>, < IMX7D_PLL_ENET_MAIN_125M_CLK>, -- 2.7.4
[PATCH V2 2/3] clk: imx7d: correct enet clock CCGR registers
Correct enet clock gates as below:
CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
Just rename unused IMX7D_ENETx_REF_ROOT_CLK for
IMX7D_ENETx_IPG_ROOT_CLK instead of adding new clocks.
Based on Andy Duan's patch from the NXP kernel tree.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 10 ++
include/dt-bindings/clock/imx7d-clock.h | 4 ++--
2 files changed, 8 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 23d5090a..d4936b9 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -26,6 +26,8 @@ static u32 share_count_sai1;
static u32 share_count_sai2;
static u32 share_count_sai3;
static u32 share_count_nand;
+static u32 share_count_enet1;
+static u32 share_count_enet2;
static const struct clk_div_table test_div_table[] = {
{ .val = 3, .div = 1, },
@@ -805,6 +807,10 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_MIPI_DSI_ROOT_CLK] = imx_clk_gate4("mipi_dsi_root_clk",
"mipi_dsi_post_div", base + 0x4650, 0);
clks[IMX7D_MIPI_CSI_ROOT_CLK] = imx_clk_gate4("mipi_csi_root_clk",
"mipi_csi_post_div", base + 0x4640, 0);
clks[IMX7D_MIPI_DPHY_ROOT_CLK] = imx_clk_gate4("mipi_dphy_root_clk",
"mipi_dphy_post_div", base + 0x4660, 0);
+ clks[IMX7D_ENET1_IPG_ROOT_CLK] =
imx_clk_gate2_shared2("enet1_ipg_root_clk", "enet_axi_post_div", base + 0x4700,
0, _count_enet1);
+ clks[IMX7D_ENET1_TIME_ROOT_CLK] =
imx_clk_gate2_shared2("enet1_time_root_clk", "enet1_time_post_div", base +
0x4700, 0, _count_enet1);
+ clks[IMX7D_ENET2_IPG_ROOT_CLK] =
imx_clk_gate2_shared2("enet2_ipg_root_clk", "enet_axi_post_div", base + 0x4710,
0, _count_enet2);
+ clks[IMX7D_ENET2_TIME_ROOT_CLK] =
imx_clk_gate2_shared2("enet2_time_root_clk", "enet2_time_post_div", base +
0x4710, 0, _count_enet2);
clks[IMX7D_SAI1_ROOT_CLK] = imx_clk_gate2_shared2("sai1_root_clk",
"sai1_post_div", base + 0x48c0, 0, _count_sai1);
clks[IMX7D_SAI1_IPG_CLK] = imx_clk_gate2_shared2("sai1_ipg_clk",
"ipg_root_clk", base + 0x48c0, 0, _count_sai1);
clks[IMX7D_SAI2_ROOT_CLK] = imx_clk_gate2_shared2("sai2_root_clk",
"sai2_post_div", base + 0x48d0, 0, _count_sai2);
@@ -812,10 +818,6 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_SAI3_ROOT_CLK] = imx_clk_gate2_shared2("sai3_root_clk",
"sai3_post_div", base + 0x48e0, 0, _count_sai3);
clks[IMX7D_SAI3_IPG_CLK] = imx_clk_gate2_shared2("sai3_ipg_clk",
"ipg_root_clk", base + 0x48e0, 0, _count_sai3);
clks[IMX7D_SPDIF_ROOT_CLK] = imx_clk_gate4("spdif_root_clk",
"spdif_post_div", base + 0x44d0, 0);
- clks[IMX7D_ENET1_REF_ROOT_CLK] = imx_clk_gate4("enet1_ref_root_clk",
"enet1_ref_post_div", base + 0x44e0, 0);
- clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk",
"enet1_time_post_div", base + 0x44f0, 0);
- clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk",
"enet2_ref_post_div", base + 0x4500, 0);
- clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk",
"enet2_time_post_div", base + 0x4510, 0);
clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk",
"eim_post_div", base + 0x4160, 0);
clks[IMX7D_NAND_RAWNAND_CLK] =
imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0,
_count_nand);
clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] =
imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base +
0x4140, 0, _count_nand);
diff --git a/include/dt-bindings/clock/imx7d-clock.h
b/include/dt-bindings/clock/imx7d-clock.h
index b2325d3e2..0d67f53 100644
--- a/include/dt-bindings/clock/imx7d-clock.h
+++ b/include/dt-bindings/clock/imx7d-clock.h
@@ -168,7 +168,7 @@
#define IMX7D_SPDIF_ROOT_SRC 155
#define IMX7D_SPDIF_ROOT_CG156
#define IMX7D_SPDIF_ROOT_DIV 157
-#define IMX7D_ENET1_REF_ROOT_CLK 158
+#define IMX7D_ENET1_IPG_ROOT_CLK158
#define IMX7D_ENET1_REF_ROOT_SRC 159
#define IMX7D_ENET1_REF_ROOT_CG160
#define IMX7D_ENET1_REF_ROOT_DIV 161
@@ -176,7 +176,7 @@
#define IMX7D_ENET1_TIME_ROOT_SRC 163
#define IMX7D_ENET1_TIME_ROOT_CG 164
#define IMX7D_ENET1_TIME_ROOT_DIV 165
-#define IMX7D_ENET2_REF_ROOT_CLK 166
+#define IMX7D_ENET2_IPG_ROOT_CLK166
#define IMX7D_ENET2_REF_ROOT_SRC 167
#define IMX7D_ENET2_REF_ROOT_CG168
#define IMX7D_ENET2_REF_ROOT_DIV 169
--
2.7.4
[PATCH V2 1/3] clk: imx7d: correct enet phy ref clock gates
IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY directly,
there is no clock gate after it, rename it to
IMX7D_ENET_PHY_REF_ROOT_CLK to avoid device tree change.
Signed-off-by: Anson Huang <anson.hu...@nxp.com>
---
drivers/clk/imx/clk-imx7d.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/clk/imx/clk-imx7d.c b/drivers/clk/imx/clk-imx7d.c
index 975a20d..23d5090a 100644
--- a/drivers/clk/imx/clk-imx7d.c
+++ b/drivers/clk/imx/clk-imx7d.c
@@ -738,7 +738,7 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_ENET1_TIME_ROOT_DIV] =
imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base + 0xa780, 0,
6);
clks[IMX7D_ENET2_REF_ROOT_DIV] = imx_clk_divider2("enet2_ref_post_div",
"enet2_ref_pre_div", base + 0xa800, 0, 6);
clks[IMX7D_ENET2_TIME_ROOT_DIV] =
imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base + 0xa880, 0,
6);
- clks[IMX7D_ENET_PHY_REF_ROOT_DIV] =
imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base +
0xa900, 0, 6);
+ clks[IMX7D_ENET_PHY_REF_ROOT_CLK] =
imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base +
0xa900, 0, 6);
clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div",
"eim_pre_div", base + 0xa980, 0, 6);
clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk",
"nand_pre_div", base + 0xaa00, 0, 6);
clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div",
"qspi_pre_div", base + 0xaa80, 0, 6);
@@ -816,7 +816,6 @@ static void __init imx7d_clocks_init(struct device_node
*ccm_node)
clks[IMX7D_ENET1_TIME_ROOT_CLK] = imx_clk_gate4("enet1_time_root_clk",
"enet1_time_post_div", base + 0x44f0, 0);
clks[IMX7D_ENET2_REF_ROOT_CLK] = imx_clk_gate4("enet2_ref_root_clk",
"enet2_ref_post_div", base + 0x4500, 0);
clks[IMX7D_ENET2_TIME_ROOT_CLK] = imx_clk_gate4("enet2_time_root_clk",
"enet2_time_post_div", base + 0x4510, 0);
- clks[IMX7D_ENET_PHY_REF_ROOT_CLK] =
imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base + 0x4520,
0);
clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk",
"eim_post_div", base + 0x4160, 0);
clks[IMX7D_NAND_RAWNAND_CLK] =
imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140, 0,
_count_nand);
clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] =
imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk", base +
0x4140, 0, _count_nand);
--
2.7.4
RE: [PATCH 1/2] clk: imx7d: correct enet clock CCGR register offset
Hi, Stefan
Anson Huang
Best Regards!
> -Original Message-
> From: Stefan Agner [mailto:ste...@agner.ch]
> Sent: Thursday, May 17, 2018 7:22 PM
> To: Anson Huang <anson.hu...@nxp.com>
> Cc: shawn...@kernel.org; ker...@pengutronix.de; Fabio Estevam
> <fabio.este...@nxp.com>; robh...@kernel.org; mark.rutl...@arm.com;
> mturque...@baylibre.com; sb...@kernel.org; Adriana Reus
> <adriana.r...@nxp.com>; rui.si...@linaro.org; dl-linux-imx
> <linux-...@nxp.com>; linux-arm-ker...@lists.infradead.org;
> devicet...@vger.kernel.org; linux-kernel@vger.kernel.org;
> linux-...@vger.kernel.org
> Subject: Re: [PATCH 1/2] clk: imx7d: correct enet clock CCGR register offset
>
> On 17.05.2018 10:40, Anson Huang wrote:
> > Correct enet clock CCGR register offset.
> >
> > CCGR6: IMX7D_ENET_AXI_ROOT_CLK (enet1 and enet2 bus clocks)
> > CCGR112: IMX7D_ENET1_TIME_ROOT_CLK, IMX7D_ENET1_IPG_ROOT_CLK
> > CCGR113: IMX7D_ENET2_TIME_ROOT_CLK, IMX7D_ENET2_IPG_ROOT_CLK
> >
> > IMX7D_ENET_PHY_REF_ROOT_DIV supplies clock for PHY, no gate after this
> > clock, its parent clock root has gate.
> > IMX7D_ENET1_REF_ROOT_DIV/IMX7D_ENET2_REF_ROOT_DIV supplies
> clocks for
> > enet IPG_CLK_RMII, no gate after the clock, its parent clock root has
> > gate.
> >
> > IMX7D_PLL_ENET_MAIN_125M_CLK (anatop pll) supplies clock for enet
> > RGMII tx_clk.
>
> As far as I can tell there are two changes here in one patch:
>
> 1. The non existing IMX7D_ENET_PHY_REF_ROOT_CLK gate is removed
>
> 2. Shared clock gate for the enet time/ipg clock is taken into account.
>
>
> I would rather prefer to have separate patches. The device tree change also
> does two things, so this would lead to 4 patches total.
>
> We can avoid the device tree change for the PHY clk and even maintain
> backward compatibility for that part by renaming
> IMX7D_ENET_PHY_REF_ROOT_DIV to IMX7D_ENET_PHY_REF_ROOT_CLK.
>
>
> So this would end up with the following first patch to address the PHY_ROOT
> clock issue:
>
> --- a/drivers/clk/imx/clk-imx7d.c
> +++ b/drivers/clk/imx/clk-imx7d.c
> @@ -738,7 +738,7 @@ static void __init imx7d_clocks_init(struct device_node
> *ccm_node)
> clks[IMX7D_ENET1_TIME_ROOT_DIV] =
> imx_clk_divider2("enet1_time_post_div", "enet1_time_pre_div", base +
> 0xa780, 0, 6);
> clks[IMX7D_ENET2_REF_ROOT_DIV] =
> imx_clk_divider2("enet2_ref_post_div", "enet2_ref_pre_div", base + 0xa800, 0,
> 6);
> clks[IMX7D_ENET2_TIME_ROOT_DIV] =
> imx_clk_divider2("enet2_time_post_div", "enet2_time_pre_div", base +
> 0xa880, 0, 6);
> - clks[IMX7D_ENET_PHY_REF_ROOT_DIV] =
> imx_clk_divider2("enet_phy_ref_post_div", "enet_phy_ref_pre_div", base +
> 0xa900, 0, 6);
> + clks[IMX7D_ENET_PHY_REF_ROOT_CLK] =
> imx_clk_divider2("enet_phy_ref_root_clk", "enet_phy_ref_pre_div", base +
> 0xa900, 0, 6);
> clks[IMX7D_EIM_ROOT_DIV] = imx_clk_divider2("eim_post_div",
> "eim_pre_div", base + 0xa980, 0, 6);
> clks[IMX7D_NAND_ROOT_CLK] = imx_clk_divider2("nand_root_clk",
> "nand_pre_div", base + 0xaa00, 0, 6);
> clks[IMX7D_QSPI_ROOT_DIV] = imx_clk_divider2("qspi_post_div",
> "qspi_pre_div", base + 0xaa80, 0, 6); @@ -816,7 +816,6 @@ static void __init
> imx7d_clocks_init(struct device_node *ccm_node)
> clks[IMX7D_ENET1_TIME_ROOT_CLK] =
> imx_clk_gate4("enet1_time_root_clk", "enet1_time_post_div", base + 0x44f0,
> 0);
> clks[IMX7D_ENET2_REF_ROOT_CLK] =
> imx_clk_gate4("enet2_ref_root_clk", "enet2_ref_post_div", base + 0x4500, 0);
> clks[IMX7D_ENET2_TIME_ROOT_CLK] =
> imx_clk_gate4("enet2_time_root_clk", "enet2_time_post_div", base + 0x4510,
> 0);
> - clks[IMX7D_ENET_PHY_REF_ROOT_CLK] =
> imx_clk_gate4("enet_phy_ref_root_clk", "enet_phy_ref_post_div", base +
> 0x4520, 0);
> clks[IMX7D_EIM_ROOT_CLK] = imx_clk_gate4("eim_root_clk",
> "eim_post_div", base + 0x4160, 0);
> clks[IMX7D_NAND_RAWNAND_CLK] =
> imx_clk_gate2_shared2("nand_rawnand_clk", "nand_root_clk", base + 0x4140,
> 0, _count_nand);
> clks[IMX7D_NAND_USDHC_BUS_RAWNAND_CLK] =
> imx_clk_gate2_shared2("nand_usdhc_rawnand_clk", "nand_usdhc_root_clk",
> base + 0x4140, 0, _count_nand);
>
>
> A second patch would then fix the clock gate issue and the third the
> unavoidable device tree change for the ipg clock.
>
> --
> Stefan
I follow your suggestion and re-st
RE: [PATCH 3/3] ARM: imx: remove i.MX6SLL support in i.MX6SL cpu idle driver
Hi, Fabio Anson Huang Best Regards! > -Original Message- > From: Fabio Estevam [mailto:feste...@gmail.com] > Sent: Thursday, May 31, 2018 8:57 AM > To: Anson Huang > Cc: Shawn Guo ; Sascha Hauer > ; Sascha Hauer ; Fabio > Estevam ; Russell King - ARM Linux > ; dl-linux-imx ; moderated > list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE > ; linux-kernel > > Subject: Re: [PATCH 3/3] ARM: imx: remove i.MX6SLL support in i.MX6SL cpu > idle driver > > Hi Anson, > > On Wed, May 30, 2018 at 9:52 PM, Anson Huang > wrote: > > >> The removal of this header file seems to be an unrelated change. > > > > This header file is no longer needed since no " cpu_is_imx6sl()" used in > > this > file. > > cpu_is_imx6sl() is not defined inside arch/arm/mach-imx/hardware.h header > file. It is in arch/arm/mach-imx/mxc.h included by hardware.h, it is added by commit (dee5dee ARM: imx: Add basic msl support for imx6sll), so I removed it since we no longer need it. Anson.
RE: [PATCH 3/3] ARM: imx: remove i.MX6SLL support in i.MX6SL cpu idle driver
Hi, Fabio Anson Huang Best Regards! > -Original Message- > From: Fabio Estevam [mailto:feste...@gmail.com] > Sent: Wednesday, May 30, 2018 8:34 PM > To: Anson Huang > Cc: Shawn Guo ; Sascha Hauer > ; Sascha Hauer ; Fabio > Estevam ; Russell King - ARM Linux > ; dl-linux-imx ; moderated > list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE > ; linux-kernel > > Subject: Re: [PATCH 3/3] ARM: imx: remove i.MX6SLL support in i.MX6SL cpu > idle driver > > Hi Anson, > > On Wed, May 30, 2018 at 4:12 AM, Anson Huang > wrote: > > i.MX6SLL supports ARM power off in cpu idle, better to reuse i.MX6SX > > cpu idle driver instead of i.MX6SL which does NOT support ARM power > > off. > > > > Signed-off-by: Anson Huang > > --- > > arch/arm/mach-imx/cpuidle-imx6sl.c | 7 ++- > > 1 file changed, 2 insertions(+), 5 deletions(-) > > > > diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c > > b/arch/arm/mach-imx/cpuidle-imx6sl.c > > index fa8ead1..8d866fb 100644 > > --- a/arch/arm/mach-imx/cpuidle-imx6sl.c > > +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c > > @@ -12,7 +12,6 @@ > > > > #include "common.h" > > #include "cpuidle.h" > > -#include "hardware.h" > > The removal of this header file seems to be an unrelated change. This header file is no longer needed since no " cpu_is_imx6sl()" used in this file. Anson.
[PATCH 2/2] ARM: imx: add mem mode suspend for i.MX6SLL
Add mem mode suspend for i.MX6SLL, when linux
kernel suspend, SoC will enter STOP mode,
ARM core will be power gated and MMDC IO
will be set to low power mode.
Signed-off-by: Anson Huang
---
arch/arm/mach-imx/pm-imx6.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c
index d319b20..791e1fd 100644
--- a/arch/arm/mach-imx/pm-imx6.c
+++ b/arch/arm/mach-imx/pm-imx6.c
@@ -130,6 +130,13 @@ static const u32 imx6sl_mmdc_io_offset[] __initconst = {
0x330, 0x334, 0x320,/* SDCKE0, SDCKE1, RESET */
};
+static const u32 imx6sll_mmdc_io_offset[] __initconst = {
+ 0x294, 0x298, 0x29c, 0x2a0, /* DQM0 ~ DQM3 */
+ 0x544, 0x54c, 0x554, 0x558, /* GPR_B0DS ~ GPR_B3DS */
+ 0x530, 0x540, 0x2ac, 0x52c, /* MODE_CTL, MODE, SDCLK_0, GPR_ADDDS */
+ 0x2a4, 0x2a8, /* SDCKE0, SDCKE1*/
+};
+
static const u32 imx6sx_mmdc_io_offset[] __initconst = {
0x2ec, 0x2f0, 0x2f4, 0x2f8, /* DQM0 ~ DQM3 */
0x60c, 0x610, 0x61c, 0x620, /* GPR_B0DS ~ GPR_B3DS */
@@ -175,6 +182,16 @@ static const struct imx6_pm_socdata imx6sl_pm_data
__initconst = {
.mmdc_io_offset = imx6sl_mmdc_io_offset,
};
+static const struct imx6_pm_socdata imx6sll_pm_data __initconst = {
+ .mmdc_compat = "fsl,imx6sll-mmdc",
+ .src_compat = "fsl,imx6sll-src",
+ .iomuxc_compat = "fsl,imx6sll-iomuxc",
+ .gpc_compat = "fsl,imx6sll-gpc",
+ .pl310_compat = "arm,pl310-cache",
+ .mmdc_io_num = ARRAY_SIZE(imx6sll_mmdc_io_offset),
+ .mmdc_io_offset = imx6sll_mmdc_io_offset,
+};
+
static const struct imx6_pm_socdata imx6sx_pm_data __initconst = {
.mmdc_compat = "fsl,imx6sx-mmdc",
.src_compat = "fsl,imx6sx-src",
@@ -314,7 +331,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode)
if (cpu_is_imx6sl() || cpu_is_imx6sx())
val |= BM_CLPCR_BYPASS_PMIC_READY;
if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() ||
- cpu_is_imx6ull())
+ cpu_is_imx6ull() || cpu_is_imx6sll())
val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS;
else
val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS;
@@ -631,7 +648,10 @@ void __init imx6dl_pm_init(void)
void __init imx6sl_pm_init(void)
{
- imx6_pm_common_init(_pm_data);
+ if (cpu_is_imx6sl())
+ imx6_pm_common_init(_pm_data);
+ else
+ imx6_pm_common_init(_pm_data);
}
void __init imx6sx_pm_init(void)
--
2.7.4
[PATCH 1/2] ARM: imx: add standby mode suspend for i.MX6SLL
Add standby mode suspend for i.MX6SLL, when linux kernel suspend, SoC will enter STOP mode with ARM core power on. Signed-off-by: Anson Huang --- arch/arm/mach-imx/pm-imx6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/mach-imx/pm-imx6.c b/arch/arm/mach-imx/pm-imx6.c index 017539d..d319b20 100644 --- a/arch/arm/mach-imx/pm-imx6.c +++ b/arch/arm/mach-imx/pm-imx6.c @@ -296,7 +296,7 @@ int imx6_set_lpm(enum mxc_cpu_pwr_mode mode) if (cpu_is_imx6sl()) val |= BM_CLPCR_BYPASS_PMIC_READY; if (cpu_is_imx6sl() || cpu_is_imx6sx() || cpu_is_imx6ul() || - cpu_is_imx6ull()) + cpu_is_imx6ull() || cpu_is_imx6sll()) val |= BM_CLPCR_BYP_MMDC_CH0_LPM_HS; else val |= BM_CLPCR_BYP_MMDC_CH1_LPM_HS; -- 2.7.4
RE: [PATCH] soc: imx: gpcv2: correct PGC offset
Hi, Andrey Anson Huang Best Regards! > -Original Message- > From: Andrey Smirnov [mailto:andrew.smir...@gmail.com] > Sent: Wednesday, May 30, 2018 7:11 AM > To: Anson Huang > Cc: Shawn Guo ; Sascha Hauer > ; Sascha Hauer ; Fabio > Estevam ; dl-linux-imx ; > linux-arm-kernel ; linux-kernel > > Subject: Re: [PATCH] soc: imx: gpcv2: correct PGC offset > > On Tue, May 29, 2018 at 1:02 AM, Anson Huang > wrote: > > Correct MIPI/PCIe/USB_HSIC's PGC offset based on design RTL, the value > > on Reference Manual are incorrect. > > > > Nit: I'd s/the value on/the values in the/ here. > > > The correct offset should be as below: > > > > 0x800 ~ 0x83F: PGC for core0 of A7 platform; > > 0x840 ~ 0x87F: PGC for core1 of A7 platform; > > 0x880 ~ 0x8BF: PGC for SCU of A7 platform; > > 0xA00 ~ 0xA3F: PGC for fastmix/megamix; > > 0xC00 ~ 0xC3F: PGC for MIPI PHY; > > 0xC40 ~ 0xC7F: PGC for PCIe_PHY; > > 0xC80 ~ 0xCBF: PGC for USB OTG1 PHY; > > 0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY; > > 0xD00 ~ 0xD3F: PGC for USB HSIC PHY; > > > > Signed-off-by: Anson Huang > > --- > > drivers/soc/imx/gpcv2.c | 6 +++--- > > 1 file changed, 3 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index > > afc7ecc..132c946 100644 > > --- a/drivers/soc/imx/gpcv2.c > > +++ b/drivers/soc/imx/gpcv2.c > > @@ -40,9 +40,9 @@ > > #define GPC_M4_PU_PDN_FLG 0x1bc > > > > > > -#define PGC_MIPI 4 > > -#define PGC_PCIE 5 > > -#define PGC_USB_HSIC 8 > > +#define PGC_MIPI 16 > > +#define PGC_PCIE 17 > > +#define PGC_USB_HSIC 20 > > As a suggestion, please add a comment explicitly saying that those values > might differ from what some version of the RM might specify. > Explanation in commit message is great, but seeing a note in the code might > save quite a bit of digging for someone who is reading the code, double > checking those values and thinking that they might be wrong. > > Other than that: > > Acked-by: Andrey Smirnov > > Thanks, > Andrey Smirnov Thanks, I will improve them in V2 patch. Anson.
[PATCH] soc: imx: gpcv2: correct PGC offset
Correct MIPI/PCIe/USB_HSIC's PGC offset based on design RTL, the value on Reference Manual are incorrect. The correct offset should be as below: 0x800 ~ 0x83F: PGC for core0 of A7 platform; 0x840 ~ 0x87F: PGC for core1 of A7 platform; 0x880 ~ 0x8BF: PGC for SCU of A7 platform; 0xA00 ~ 0xA3F: PGC for fastmix/megamix; 0xC00 ~ 0xC3F: PGC for MIPI PHY; 0xC40 ~ 0xC7F: PGC for PCIe_PHY; 0xC80 ~ 0xCBF: PGC for USB OTG1 PHY; 0xCC0 ~ 0xCFF: PGC for USB OTG2 PHY; 0xD00 ~ 0xD3F: PGC for USB HSIC PHY; Signed-off-by: Anson Huang --- drivers/soc/imx/gpcv2.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c index afc7ecc..132c946 100644 --- a/drivers/soc/imx/gpcv2.c +++ b/drivers/soc/imx/gpcv2.c @@ -40,9 +40,9 @@ #define GPC_M4_PU_PDN_FLG 0x1bc -#define PGC_MIPI 4 -#define PGC_PCIE 5 -#define PGC_USB_HSIC 8 +#define PGC_MIPI 16 +#define PGC_PCIE 17 +#define PGC_USB_HSIC 20 #define GPC_PGC_CTRL(n)(0x800 + (n) * 0x40) #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc) -- 2.7.4
[PATCH 2/3] ARM: imx: add cpu idle support for i.MX6SLL
i.MX6SLL supports cpu idle with ARM power gated,
it can reuse i.MX6SX's cpu idle driver to support
below 3 states of cpu idle:
state0: WFI;
state1: WAIT mode with ARM power on;
state2: WAIT mode with ARM power off.
L2_PGE in GPC_CNTR needs to be cleared to support
state2 cpu idle.
Signed-off-by: Anson Huang
---
arch/arm/mach-imx/cpuidle-imx6sx.c | 1 +
arch/arm/mach-imx/mach-imx6sl.c| 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/cpuidle-imx6sx.c
b/arch/arm/mach-imx/cpuidle-imx6sx.c
index d0f14b7..243a108 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sx.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sx.c
@@ -103,6 +103,7 @@ int __init imx6sx_cpuidle_init(void)
{
imx6_set_int_mem_clk_lpm(true);
imx6_enable_rbc(false);
+ imx_gpc_set_l2_mem_power_in_lpm(false);
/*
* set ARM power up/down timing to the fastest,
* sw2iso and sw can be set to one 32K cycle = 31us
diff --git a/arch/arm/mach-imx/mach-imx6sl.c b/arch/arm/mach-imx/mach-imx6sl.c
index c7a1ef1..183540e 100644
--- a/arch/arm/mach-imx/mach-imx6sl.c
+++ b/arch/arm/mach-imx/mach-imx6sl.c
@@ -42,7 +42,10 @@ static void __init imx6sl_init_late(void)
if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ))
platform_device_register_simple("imx6q-cpufreq", -1, NULL, 0);
- imx6sl_cpuidle_init();
+ if (cpu_is_imx6sl())
+ imx6sl_cpuidle_init();
+ else
+ imx6sx_cpuidle_init();
}
static void __init imx6sl_init_machine(void)
--
2.7.4
[PATCH 3/3] ARM: imx: remove i.MX6SLL support in i.MX6SL cpu idle driver
i.MX6SLL supports ARM power off in cpu idle, better to reuse i.MX6SX cpu idle driver instead of i.MX6SL which does NOT support ARM power off. Signed-off-by: Anson Huang --- arch/arm/mach-imx/cpuidle-imx6sl.c | 7 ++- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c index fa8ead1..8d866fb 100644 --- a/arch/arm/mach-imx/cpuidle-imx6sl.c +++ b/arch/arm/mach-imx/cpuidle-imx6sl.c @@ -12,7 +12,6 @@ #include "common.h" #include "cpuidle.h" -#include "hardware.h" static int imx6sl_enter_wait(struct cpuidle_device *dev, struct cpuidle_driver *drv, int index) @@ -22,11 +21,9 @@ static int imx6sl_enter_wait(struct cpuidle_device *dev, * Software workaround for ERR005311, see function * description for details. */ - if (cpu_is_imx6sl()) - imx6sl_set_wait_clk(true); + imx6sl_set_wait_clk(true); cpu_do_idle(); - if (cpu_is_imx6sl()) - imx6sl_set_wait_clk(false); + imx6sl_set_wait_clk(false); imx6_set_lpm(WAIT_CLOCKED); return index; -- 2.7.4
