The scause is already part of pt_regs so no need to pass
scause as separate arg to do_IRQ().
Reviewed-by: Christoph Hellwig
Signed-off-by: Anup Patel
---
arch/riscv/kernel/entry.S | 1 -
arch/riscv/kernel/irq.c | 4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch
m IRQCHIP drivers.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 1 -
arch/riscv/include/asm/smp.h | 3 +++
arch/riscv/kernel/irq.c | 16 ++--
arch/riscv/kernel/smp.c | 11 +--
4 files changed, 22 insertions(+), 9 deletions(-)
diff --git a/arch/riscv/
On Mon, Sep 10, 2018 at 9:41 PM, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 06:07:12PM +0200, Thomas Gleixner wrote:
>> > Considering above, it is better to have a distinct irqchip and
>> > irq_domain for all local interrupts (just like this patch).
>>
>> If that's the future usage
>
>
On Mon, Sep 10, 2018 at 10:05 PM, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 10:02:09PM +0530, Anup Patel wrote:
>> You are thinking very much in-context of SiFive CPUs only.
>
> No. I think in terms of the RISC-V spec. I could care less about
> SiFive to be hones
On Mon, Sep 10, 2018 at 7:19 PM, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 03:45:42PM +0200, Thomas Gleixner wrote:
>> > He has an irqchip that is called from the RISC-V exception handler
>> > when the interrupt flag is set in scause and then dispatches to one
>> > of: IPI, timer,
On Mon, Sep 10, 2018 at 9:43 PM, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 07:59:15PM +0530, Anup Patel wrote:
>> > Yes. external is chained and IPI is still handled explicitly.
>>
>> On riscv64, there are 64 local interrupts (i.e. per-CPU interrupts).
>
&
On Mon, Sep 10, 2018 at 10:09 PM, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 10:05:42PM +0530, Anup Patel wrote:
>> I am quite sure RISC-V spec does not restrict the use of other
>> local interrupts. Different CPU implementations can have their
>> own local interr
On Mon, Sep 10, 2018 at 7:04 PM, Christoph Hellwig wrote:
> On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
>> This patch is doing two things:
>> 1. Allow IRQCHIP driver to provide IPI trigger mechanism
>
> And the big questions is why do we want that? The
On Tue, Sep 11, 2018 at 3:49 AM, Christoph Hellwig wrote:
> On Mon, Sep 10, 2018 at 09:37:59PM +0200, Thomas Gleixner wrote:
>> Processor local interrupts really should be architected and there are
>> really not that many of them.
>
> And that is what they are.
>
>> But well, RISC-V decided
Instead of directly calling RISC-V timer interrupt handler from
RISC-V local interrupt conntroller driver, this patch implements
RISC-V timer interrupt as a per-CPU interrupt using per-CPU APIs
of Linux IRQ subsystem.
Signed-off-by: Anup Patel
---
arch/riscv/include/asm/irq.h | 2
On Wed, Sep 5, 2018 at 12:26 AM, Christoph Hellwig wrote:
> On Tue, Sep 04, 2018 at 06:15:12PM +0530, Anup Patel wrote:
>> This patch selects following GENERIC_IRQ kconfig options:
>> GENERIC_IRQ_MULTI_HANDLER
>
> This is already selected by arch/riscv/Kconfig.
&
On Wed, Sep 5, 2018 at 12:27 AM, Christoph Hellwig wrote:
> On Tue, Sep 04, 2018 at 06:15:13PM +0530, Anup Patel wrote:
>> Few advantages of this new driver over previous one are:
>> 1. It registers all local interrupts as per-CPU interrupts
>
> Please explain why
On Wed, Jan 10, 2018 at 6:46 PM, Anup Patel <a...@brainfault.org> wrote:
> When virtio-rpmsg device is provided via virtio-mmio transport, the
> dma_alloc_coherent() (called by rpmsg_probe()) fails on ARM/ARM64
> systems because "vdev->dev.parent->parent&qu
On Wed, Jan 10, 2018 at 6:47 PM, Anup Patel <a...@brainfault.org> wrote:
> This patch adds "driver_override" device attribute for rpmsg_device which
> will allow users to explicitly specify the rpmsg_driver to be used via
> sysfs entry.
>
> The "driver_overrid
On Mon, Sep 10, 2018 at 7:16 PM, Christoph Hellwig wrote:
> On Fri, Sep 07, 2018 at 06:14:29PM +0530, Anup Patel wrote:
>> This patch provides arch_show_interrupts() implementation to
>> show IPI stats via /proc/interrupts.
>>
>> Now the contents of /proc/inter
On Mon, Mar 19, 2018 at 4:17 AM, Bjorn Andersson
<bjorn.anders...@linaro.org> wrote:
> On Wed 10 Jan 05:16 PST 2018, Anup Patel wrote:
>> diff --git a/drivers/rpmsg/virtio_rpmsg_bus.c
>> b/drivers/rpmsg/virtio_rpmsg_bus.c
> [..]
>> @@ -924,9 +925,16 @@ static int rp
On Mon, Mar 19, 2018 at 4:17 AM, Bjorn Andersson
<bjorn.anders...@linaro.org> wrote:
> On Wed 10 Jan 05:17 PST 2018, Anup Patel wrote:
>
>> This patch adds "driver_override" device attribute for rpmsg_device which
>> will allow users to explicitly specify the rp
or platform, pci, and amba bus types.
One important use-case of "driver_override" device attribute is to force
use of rpmsg_chrdev driver for certain rpmsg_device instances.
Signed-off-by: Anup Patel <a...@brainfault.org>
Changes since v1:
- Removed un-related c
693 77410 Rescheduling interrupts
IPI1: 0 2 3 16 Function call interrupts
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/driv
We explicitly differentiate between PLIC handler and context because
PLIC context is for given mode of HART whereas PLIC handler is per-CPU
software construct meant to handling interrupts from a particular
PLIC context.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 21
We make plic_irq_toggle() more generic so that we can enable/disable
hwirq for given cpumask. This generic plic_irq_toggle() will be
eventually used to implement set_affinity for PLIC driver.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 89 ---
1
.
The patchset is tested on QEMU virt machine. It is based on Linux-4.19-rc2
and can be found at riscv_plic_irq_affinity_v1 branch of:
https://github.com/avpatel/linux.git
Anup Patel (4):
irqchip: sifive-plic: Pre-compute context hart base and enable base
irqchip: sifive-plic: More flexible
This patch does following optimizations:
1. Pre-compute hart base for each context handler
2. Pre-compute enable base for each context handler
3. Have enable lock for each context handler instead
of global plic_toggle_lock
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 51
On Wed, Oct 31, 2018 at 4:06 PM Vincent Chen wrote:
>
> RISC-V permits each vendor to develop respective extension ISA based
> on RISC-V standard ISA. This means that these vendor-specific features
> may be compatible to their compiler and CPU. Therefore, each vendor may
> be considered a
On Thu, Nov 1, 2018 at 4:20 AM Olof Johansson wrote:
>
> On Wed, Oct 31, 2018 at 1:42 PM Palmer Dabbelt wrote:
> >
> > On Wed, 31 Oct 2018 12:20:40 PDT (-0700), Olof Johansson wrote:
> > > On Tue, Oct 30, 2018 at 5:37 AM Anup Patel wrote:
> > >>
>
such as x86_64, arm64, etc).
Signed-off-by: Anup Patel
Acked-by: Olof Johansson
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 07fa9ea75fea..ef4f15df9adf 100644
--- a/arch/riscv/configs
This patch updates defconfig using savedefconfig on Linux-4.19.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 36473d7dbaac
such as x86_64, arm64, etc).
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig
index 36473d7dbaac..ef4f15df9adf 100644
--- a/arch/riscv
or Image.gz is achieved using bootm command.
The flat and uncompressed kernel image (i.e. Image) is very useful
in pre-silicon developent and testing because we can create back-door
HEX files for RAM on FPGAs from Image.
Signed-off-by: Anup Patel
---
arch/riscv/Makefile | 15
On Fri, Nov 9, 2018 at 2:12 PM Christoph Hellwig wrote:
>
> On Mon, Oct 22, 2018 at 05:15:14PM +0530, Anup Patel wrote:
> > This patch does following optimizations:
> > 1. Pre-compute hart base for each context handler
> > 2. Pre-compute enable base for each
On Fri, Nov 9, 2018 at 2:13 PM Christoph Hellwig wrote:
>
> > -
> > struct plic_handler {
> > boolpresent;
> > - int ctxid;
> > void __iomem*hart_base;
> > raw_spinlock_t enable_lock;
> > void __iomem
ce,
> + dma_free_coherent(vdev->dev.parent, total_buf_space,
> vrp->rbufs, vrp->bufs_dma);
>
> kfree(vrp);
> --
> 1.9.1
>
Reviewed-by: Anup Patel
Also, tried this patch on Linux running inside Guest/VM on
Xvisor ARM/ARM64.
Tested-by: Anup Patel
Regards,
Anup
On Wed, Sep 26, 2018 at 9:31 PM Loic PALLARDY wrote:
>
> Hi Anup,
>
> > -Original Message-
> > From: Anup Patel
> > Sent: Friday, September 21, 2018 8:05 AM
> > To: Loic PALLARDY
> > Cc: Bjorn Andersson ; Ohad Ben-Cohen
> > ; lin
On Tue, Oct 2, 2018 at 8:45 AM Atish Patra wrote:
>
> On 9/28/18 11:26 PM, Anup Patel wrote:
> > This patch provides arch_show_interrupts() implementation to
> > show IPI stats via /proc/interrupts.
> >
> > Now the contents of /proc/interrupts" will lo
On Sat, Sep 29, 2018 at 7:15 AM Palmer Dabbelt wrote:
>
> On Mon, 10 Sep 2018 06:46:59 PDT (-0700), Christoph Hellwig wrote:
> > On Fri, Sep 07, 2018 at 06:14:29PM +0530, Anup Patel wrote:
> >> This patch provides arch_show_interrupts() implementation to
> >> show
gt; mmu : sv48
> >
> > cpu : 2
> > hart : 3
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > cpu : 3
> > hart : 2
> > isa : rv64imafdcsu
> > mmu : sv48
> >
> > Signed-off-by: Anup Patel
> > ---
> > arc
10 10 9 11 SiFive PLIC 10 ttyS0
IPI0: 170673251 79 Rescheduling interrupts
IPI1: 1 12 27 1 Function call interrupts
Signed-off-by: Anup Patel
Changes since v2:
- Remove use of IPI_CALL_WAKEUP because
On Sat, Sep 29, 2018 at 7:15 AM Palmer Dabbelt wrote:
>
> On Mon, 10 Sep 2018 06:34:18 PDT (-0700), Christoph Hellwig wrote:
> > On Thu, Sep 06, 2018 at 04:15:14PM +0530, Anup Patel wrote:
> >> This patch is doing two things:
> >> 1. Allow IRQCHIP driver to
On Thu, Aug 30, 2018 at 10:11 AM, Christoph Hellwig wrote:
> On Thu, Aug 30, 2018 at 09:53:50AM -0400, Anup Patel wrote:
>> > Atish Patra (3):
>> > RISC-V: Add logical CPU indexing for RISC-V
>> > RISC-V: Use Linux logical cpu number instead of hartid
>
ra (3):
> RISC-V: Add logical CPU indexing for RISC-V
> RISC-V: Use Linux logical cpu number instead of hartid
> RISC-V: Support cpu hotplug.
>
This series looks good to me.
FWIW,
Reviewed-by: Anup Patel
Regards,
Anup
On Thu, Aug 30, 2018 at 10:11 AM, Christoph Hellwig wrote:
> On Thu, Aug 30, 2018 at 09:53:50AM -0400, Anup Patel wrote:
>> > Atish Patra (3):
>> > RISC-V: Add logical CPU indexing for RISC-V
>> > RISC-V: Use Linux logical cpu number instead of hartid
>
Hi Loic/Bjorn,
Can we consider this series for v4.20?
I am interested in for patch "rpmsg: virtio: allocate buffer
from parent". This patch allows me to used VirtIO
RPMSG driver inside Guest/VM.
Regards,
Anup
On Mon, Sep 17, 2018 at 7:58 PM Anup Patel wrote:
>
> On Mon, Sep 17, 2018 at 7:44 PM Christoph Hellwig wrote:
> >
> > On Mon, Sep 10, 2018 at 10:08:58PM +0530, Anup Patel wrote:
> > > > They could in theory IFF someone actually get the use case through
> > &
On Tue, Sep 25, 2018 at 11:29 PM Atish Patra wrote:
>
> On 9/23/18 6:37 AM, Anup Patel wrote:
> > Currently, /proc/cpuinfo show logical CPU ID as Hart ID which
> > is in-correct. This patch shows CPU ID and Hart ID separately
> > in /proc/cpuinfo using cpuid_to_hardi
On Mon, Sep 17, 2018 at 7:40 PM Christoph Hellwig wrote:
>
> On Wed, Sep 12, 2018 at 09:47:55AM -0700, Atish Patra wrote:
> > The extra hart information will not be parsed by lscpu which will make the
> > cpu information inconsistent between lscpu & /proc/cpuinfo.
> >
> > Should we patch lscpu as
: sv48
Signed-off-by: Anup Patel
---
Changes since v1:
- Show logical CPU ID as "processor" attribute in /proc/cpuinfo
arch/riscv/kernel/cpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 36
On Fri, Nov 30, 2018 at 6:05 AM Atish Patra wrote:
>
> On 11/27/18 2:03 AM, Anup Patel wrote:
> > This patch does following optimizations:
> > 1. Pre-compute hart base for each context handler
> > 2. Pre-compute enable base for each context handler
> > 3. Have enable
On Fri, Nov 30, 2018 at 7:27 AM Atish Patra wrote:
>
> On 11/27/18 2:04 AM, Anup Patel wrote:
> > We explicitly differentiate between PLIC handler and context because
> > PLIC context is for given mode of HART whereas PLIC handler is per-CPU
> > software construct meant
On Fri, Nov 30, 2018 at 7:09 AM Atish Patra wrote:
>
> On 11/27/18 2:03 AM, Anup Patel wrote:
> > We make plic_irq_toggle() more generic so that we can enable/disable
> > hwirq for given cpumask. This generic plic_irq_toggle() will be
> > eventually used to implement set_
to select GENERIC_SCHED_CLOCK for RISC-V
- Kconfig RISCV_TIMER depends on GENERIC_SCHED_CLOCK
Anup Patel (2):
RISC-V: Select GENERIC_SCHED_CLOCK for clocksource drivers
clocksource: riscv_timer: Provide sched_clock
arch/riscv/Kconfig| 1 +
drivers/clocksource/Kconfig | 2
The riscv_timer driver can provide sched_clock using "rdtime"
instruction but to achieve this we require generic sched_clock
framework hence this patch selects GENERIC_SCHED_CLOCK for RISCV.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig | 1 +
1 file changed, 1 insertion(+)
-by: Anup Patel
---
drivers/clocksource/Kconfig | 2 +-
drivers/clocksource/riscv_timer.c | 9 +
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 55c77e44bb2d..19649abd7c75 100644
--- a/drivers/clocksource/Kconfig
This patch enables RISC-V SBI earlycon support in default defconfig
so that we can use "earlycon=sbi" in kernel parameters for early
debug prints.
Signed-off-by: Anup Patel
---
arch/riscv/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/configs/defcon
The EARLY_PRINTK using SBI console calls is not required
any more because we now have RISC-V SBI support in generic
earlycon framework.
Signed-off-by: Anup Patel
---
arch/riscv/Kconfig.debug | 2 --
arch/riscv/kernel/setup.c | 28
2 files changed, 30 deletions
In RISC-V, the M-mode runtime firmware provide SBI calls for
debug prints. This patch adds earlycon support using RISC-V
SBI console calls. To enable it, just pass "earlycon=sbi" in
kernel parameters.
Signed-off-by: Anup Patel
---
drivers/tty/serial/Kconfig
QEMU virt machine. It is based on Linux-4.20-rc5
and can be found at riscv_earlycon_v1 branch of:
https://github.com/avpatel/linux.git
Anup Patel (3):
tty/serial: Add RISC-V SBI earlycon support
RISC-V: defconfig: Enable RISC-V SBI earlycon support
RISC-V: Remove EARLY_PRINTK support
-by: Anup Patel
---
drivers/clocksource/riscv_timer.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/drivers/clocksource/riscv_timer.c
b/drivers/clocksource/riscv_timer.c
index 084e97dc10ed..431892200a08 100644
--- a/drivers/clocksource/riscv_timer.c
+++ b/drivers/clocksource/riscv_timer.c
On Mon, Dec 3, 2018 at 6:29 PM Daniel Lezcano wrote:
>
> On 03/12/2018 13:35, Anup Patel wrote:
> > Currently, we don't have a sched_clock registered for RISC-V systems.
> > This means Linux time keeping will use jiffies (running at HZ) as the
> > default sched_clock.
&
> default sched_clock.
> >
> > To avoid this, we explicity provide sched_clock using RISC-V rdtime
> > instruction (similar to riscv_timer clocksource).
> >
> > Signed-off-by: Anup Patel
> > ---
> > drivers/clocksource/riscv_timer.c | 9 +
On Fri, Nov 30, 2018 at 11:29 AM Atish Patra wrote:
>
> On 11/27/18 2:04 AM, Anup Patel wrote:
> > Currently on SMP host, all CPUs take external interrupts routed via
> > PLIC. All CPUs will try to claim a given external interrupt but only
> > one of them will succee
away after use in plic_init().
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 59 +--
1 file changed, 33 insertions(+), 26 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
index c23a293a2aae..48bee877e0f1
We make plic_irq_toggle() more generic so that we can enable/disable
hwirq for given cpumask. This generic plic_irq_toggle() will be
eventually used to implement set_affinity for PLIC driver.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 15 +++
1 file changed, 7
This patch does following optimizations:
1. Pre-compute hart base for each context handler
2. Pre-compute enable base for each context handler
3. Have enable lock for each context handler instead
of global plic_toggle_lock
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 47
uot;nr_contexts"
and "nr_mapped" to "nr_handlers" in struct plic_hw.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqc
693 77410 Rescheduling interrupts
IPI1: 0 2 3 16 Function call interrupts
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/driv
updated interrupts-extended DT property.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/irqchip/irq-sifive-plic.c
b/drivers/irqchip/irq-sifive-plic.c
index d4433399eb89..3d4f205f8abe 100644
--- a/drivers/irqchip/irq
for locking in PATCH1
- Split PATCH2 into two patches
- Split PATCH3 into two patches
- Minor fix in commit description of PATCH4
Changes since v1:
- Removed few whitspace changes from PATCH1
- Keep use of DEFINE_PER_CPU() as it is
Anup Patel (6):
irqchip: sifive-plic: Pre-compute context hart
.
The flat kernel Image size of Linux-4.20-rc4 using GCC 8.2.0 is
8819980 bytes with current RISC-V vmlinux.lds.S and it reduces to
7991740 bytes with this patch applied using GCC 8.2.0. In summary,
this patch reduces Linux-4.20-rc4 flat kernel Image size by 809 KB.
Signed-off-by: Anup Patel
---
arch
kernel image (i.e. Image) is very useful
> > in pre-silicon developent and testing because we can create back-door
> > HEX files for RAM on FPGAs from Image.
> >
> > Signed-off-by: Anup Patel
> > ---
> > arch/riscv/Makefile | 15
We make plic_irq_toggle() more generic so that we can enable/disable
hwirq for given cpumask. This generic plic_irq_toggle() will be
eventually used to implement set_affinity for PLIC driver.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 79 +++
1
This patch does following optimizations:
1. Pre-compute hart base for each context handler
2. Pre-compute enable base for each context handler
3. Have enable lock for each context handler instead
of global plic_toggle_lock
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 41
.
The patchset is tested on QEMU virt machine. It is based on Linux-4.20-rc4
and can be found at riscv_plic_irq_affinity_v2 branch of:
https://github.com/avpatel/linux.git
Changes since v1:
- Removed few whitspace changes from PATCH1
- Keep use of DEFINE_PER_CPU() as it is
Anup Patel (4
693 77410 Rescheduling interrupts
IPI1: 0 2 3 16 Function call interrupts
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 35 +--
1 file changed, 33 insertions(+), 2 deletions(-)
diff --git a/driv
We explicitly differentiate between PLIC handler and context because
PLIC context is for given mode of HART whereas PLIC handler is per-CPU
software construct meant for handling interrupts from a particular
PLIC context.
Signed-off-by: Anup Patel
---
drivers/irqchip/irq-sifive-plic.c | 21
On Wed, Sep 12, 2018 at 10:17 PM Atish Patra wrote:
>
> On 9/12/18 7:38 AM, Anup Patel wrote:
> > Currently, /proc/cpuinfo show logical CPU ID as Hart ID which
> > is in-correct. This patch shows CPU ID and Hart ID separately
> > in /proc/cpuinfo u
On Mon, Sep 17, 2018 at 8:35 PM Thomas Gleixner wrote:
>
> On Mon, 17 Sep 2018, Christoph Hellwig wrote:
> > > Just for the record, this would be the first (architected) timer ever
> > > which
> > > just works. I'm having a hard time to believe this, but I'd certainly
> > > welcome it.
> >
> >
: 1
hart: 0
isa : rv64imafdcsu
mmu : sv48
cpu : 2
hart: 3
isa : rv64imafdcsu
mmu : sv48
cpu : 3
hart: 2
isa : rv64imafdcsu
mmu : sv48
Signed-off-by: Anup Patel
---
arch/riscv/kernel/cpu.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion
10 10 9 11 SiFive PLIC 10 ttyS0
IPI0: 170673251 79 Rescheduling interrupts
IPI1: 1 12 27 1 Function call interrupts
IPI2: 0 0 0 0 CPU wake-up interrupts
Signed-off-by:
On Mon, Sep 17, 2018 at 7:44 PM Christoph Hellwig wrote:
>
> On Mon, Sep 10, 2018 at 10:08:58PM +0530, Anup Patel wrote:
> > > They could in theory IFF someone actually get the use case through
> > > the riscv privileged spec working group.
> >
> > Their
On Wed, Nov 20, 2013 at 4:28 PM, Marc Zyngier wrote:
> [dropping from the CC list, as someone seems to have
> tripped on the config file, and I'm tired of getting bounces]
>
> Feng,
>
> On 19/11/13 21:42, Feng Kan wrote:
>> The GIC-400 implementation allows for FIQ and IRQ bypass. In the
>>
On Sat, Nov 23, 2013 at 2:11 PM, Anup Patel wrote:
> On Wed, Nov 20, 2013 at 4:28 PM, Marc Zyngier wrote:
>> [dropping from the CC list, as someone seems to have
>> tripped on the config file, and I'm tired of getting bounces]
>>
>> Feng,
>>
>> On 19/1
(Adding correct "Kumar Sankaran" to CC. My mistake.)
(Adding back patc...@apm.com. It is fixed now).
On Mon, Nov 25, 2013 at 2:52 PM, Marc Zyngier wrote:
> On 23/11/13 08:41, Anup Patel wrote:
>> On Wed, Nov 20, 2013 at 4:28 PM, Marc Zyngier wrote:
>>> [dropping
On Mon, Nov 25, 2013 at 9:13 PM, Rob Herring wrote:
> On Sat, Nov 23, 2013 at 2:41 AM, Anup Patel wrote:
>> On Wed, Nov 20, 2013 at 4:28 PM, Marc Zyngier wrote:
>>> [dropping from the CC list, as someone seems to have
>>> tripped on the config file, and I
On Tue, Nov 26, 2013 at 9:05 PM, Rob Herring wrote:
> On Mon, Nov 25, 2013 at 10:00 AM, Anup Patel wrote:
>> On Mon, Nov 25, 2013 at 9:13 PM, Rob Herring wrote:
>>> On Sat, Nov 23, 2013 at 2:41 AM, Anup Patel wrote:
>>>> On Wed, Nov 20, 2013 at 4:28 PM, Marc Z
On 22 April 2013 06:51, Rusty Russell wrote:
>
> Pranavkumar Sawargaonkar writes:
> > On 18 April 2013 12:21, Rusty Russell wrote:
> >>
> >> PranavkumarSawargaonkar writes:
> >> > From: Pranavkumar Sawargaonkar
> >> >
> >> > This patch implements early printk support for virtio-mmio console
>
On Wed, May 1, 2013 at 5:56 AM, Alexander Graf wrote:
>
> On 30.04.2013, at 02:32, Rusty Russell wrote:
>
>> Alexander Graf writes:
>>> Am 29.04.2013 um 05:09 schrieb Rusty Russell :
>>>
Alexander Graf writes:
> On 26.04.2013, at 13:04, Pranavkumar Sawargaonkar wrote:
>
>> This
On Wed, May 1, 2013 at 7:37 AM, Rusty Russell wrote:
> Alexander Graf writes:
>> There are not device specific registers in
>> virtio-console. Virtio-console lives behind a virtio bus which doesn't
>> know what these registers are.
>
> You're not going to make coherent arguments without reading
On 26 April 2013 17:03, Peter Maydell wrote:
> On 26 April 2013 12:19, Alexander Graf wrote:
>> MMIO registers are handled by a different layer than the virtio
>> console itself. After the virtio refactoring in QEMU, they will
>> be completely separate drivers.
>
> Good point -- we don't really
On 26 April 2013 18:03, Arnd Bergmann wrote:
> On Friday 26 April 2013 17:36:16 Anup Patel wrote:
>> On 26 April 2013 17:03, Peter Maydell wrote:
>> > On 26 April 2013 12:19, Alexander Graf wrote:
>> >> MMIO registers are handled by a different layer than the virt
On Fri, May 9, 2014 at 6:15 PM, Eric Auger wrote:
> This patch enables irqfd and irq routing on ARM.
>
> It turns on CONFIG_HAVE_KVM_EVENTFD and CONFIG_HAVE_KVM_IRQ_ROUTING
>
> irqfd framework enables to assign physical IRQs to guests.
>
> 1) user-side uses KVM_IRQFD VM ioctl to pass KVM a
Hi Marc,
On Wed, Jun 25, 2014 at 2:58 PM, Marc Zyngier wrote:
> So far, GICv2 has been used in with EOImode == 0. The effect of this
> mode is to perform the priority drop and the deactivation of the
> interrupt at the same time.
>
> While this works perfectly for Linux (we only have a single
dma_contiguous_reserve(dma_phys_limit);
>
> memblock_allow_resize();
>
> ___
> linux-arm-kernel mailing list
> linux-arm-ker...@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
Linux-3.16-
or platform, pci, and amba bus types.
One important use-case of "driver_override" device attribute is to force
use of rpmsg_chrdev driver for certain rpmsg_device instances.
Signed-off-by: Anup Patel
Changes since v1:
- Removed un-related changes from patch
- Renamed "path"
On Mon, Mar 19, 2018 at 4:17 AM, Bjorn Andersson
wrote:
> On Wed 10 Jan 05:17 PST 2018, Anup Patel wrote:
>
>> This patch adds "driver_override" device attribute for rpmsg_device which
>> will allow users to explicitly specify the rpmsg_driver t
On Mon, Mar 19, 2018 at 4:17 AM, Bjorn Andersson
wrote:
> On Wed 10 Jan 05:16 PST 2018, Anup Patel wrote:
>> diff --git a/drivers/rpmsg/virtio_rpmsg_bus.c
>> b/drivers/rpmsg/virtio_rpmsg_bus.c
> [..]
>> @@ -924,9 +925,16 @@ static int rpmsg_probe(st
On Wed, Jan 10, 2018 at 6:47 PM, Anup Patel wrote:
> This patch adds "driver_override" device attribute for rpmsg_device which
> will allow users to explicitly specify the rpmsg_driver to be used via
> sysfs entry.
>
> The "driver_override" device attribu
On Wed, Jan 10, 2018 at 6:46 PM, Anup Patel wrote:
> When virtio-rpmsg device is provided via virtio-mmio transport, the
> dma_alloc_coherent() (called by rpmsg_probe()) fails on ARM/ARM64
> systems because "vdev->dev.parent->parent" device is used as paramete
On Fri, Aug 11, 2017 at 12:53 AM, Alex Williamson
wrote:
> On Wed, 2 Aug 2017 11:08:30 +0530
> Anup Patel wrote:
>
>> This patch adds Broadcom FlexRM low-level reset for
>> VFIO platform.
>>
>> It will do the following:
>> 1. Disable/Deactivate each F
On Thu, Aug 17, 2017 at 9:14 AM, Vinod Koul wrote:
> On Tue, Aug 01, 2017 at 04:07:45PM +0530, Anup Patel wrote:
>> Make section comments consistent across the Broadcom SBA RAID driver
>> by avoiding " SBA " in some of the comments.
>
> and you add more comments..
On Thu, Aug 17, 2017 at 9:15 AM, Vinod Koul wrote:
> On Tue, Aug 01, 2017 at 04:07:47PM +0530, Anup Patel wrote:
>> This patch merges sba_request state and fence into common
>> sba_request flags. Also, in-future we can extend sba_request
>> flags as required.
>
> a
501 - 600 of 2147 matches
Mail list logo
