c-msm8974: remove ocmemcx_ahb_clk
commit: 471e2875f8904539985e62220afd6c88e70779fa
Best regards,
--
Bjorn Andersson
b57059e2592c7c99b424965374
[3/3] remoteproc: qcom: pas: Add SM6375 MPSS
commit: 93f875645c9da9c788224964499e68fa9664e80f
Best regards,
--
Bjorn Andersson
!
[2/2] hwspinlock: qcom: Remove IPQ6018 SOC specific compatible
commit: 823313068617bf2414c6067504b4e2ce5768e601
Best regards,
--
Bjorn Andersson
On Mon, 14 Aug 2023 15:21:41 +0530, MD Danish Anwar wrote:
> Add interrupts and interrupt-names protperties for PRU and RTU cores.
>
>
Applied, thanks!
[1/1] dt-bindings: remoteproc: pru: Add Interrupt property
commit: d93f191b95bec3c913978eb18c6297e797915993
Best regards,
[1/2] arm64: dts: qcom: ipq6018: Fix tcsr_mutex register size
commit: 72fc3d58b87b0d622039c6299b89024fbb7b420f
Best regards,
--
Bjorn Andersson
commit: 018c949b32df9f17f52bf0e70f976719811db233
Best regards,
--
Bjorn Andersson
commit: 7d65d4b7d70fb9560ce9baaf4219fb24646bd578
Best regards,
--
Bjorn Andersson
7da4fd325c371e1ddbb4fc46629e2caf8f73f07
Best regards,
--
Bjorn Andersson
commit: 7d65d4b7d70fb9560ce9baaf4219fb24646bd578
Best regards,
--
Bjorn Andersson
commit: 09f1642eca6eb6d25a630214098350dc02917954
Best regards,
--
Bjorn Andersson
: qcom: socinfo: Add SoC ID for QCM6490
commit: 59872d59d164ec67f295d6f96fe818b92973ee40
Best regards,
--
Bjorn Andersson
24be2254fa645f8dd8257a9e0
[4/7] dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles
commit: de37ca2dc98607e74522d8f243aa7feac74577c5
[5/7] clk: qcom: hfpll: Add MSM8976 PLL data
commit: 1fa2d1a887c763246662a88e203d69b36052770c
Best regards,
--
Bjorn Andersson
On Sat, Aug 12, 2023 at 01:24:44PM +0200, Adam Skladowski wrote:
Please drop the "drivers:" prefix in $subject, and resubmit this with
patch (alone should be fine) with the new maintainer, and appropriate
mailing list, included.
Thanks,
Bjorn
> Downstream kernel parses resource names based on
On Mon 19 Apr 15:59 CDT 2021, AngeloGioacchino Del Regno wrote:
> Il 19/04/21 20:52, Bjorn Andersson ha scritto:
> > On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
[..]
> > > +static int qcom_cpufreq_hw_acd_init(struct device *cpu_dev,
> > > +
On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
> In order to fine-tune the frequency scaling from various governors,
> allow to set a maximum transition latency from OPPs, which may be
> different depending on the SoC.
>
Acked-by: Bjorn Andersson
Regards,
Bjorn
On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
> Add the MSM8998 to the blacklist since the CPU scaling is handled
> out of this.
>
Reviewed-by: Bjorn Andersson
Although I presume this could be squashed with the previous patch...
Regards,
Bjorn
>
On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
> Add the SDM630, SDM636 and SDM660 to the blacklist since the CPU
> scaling is handled out of this.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: AngeloGioacchino Del Regno
>
> ---
> drivers/cpufreq/cpu
On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
[..]
> diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml
> new file mode 100644
> index ..bc81b6203e27
> --- /dev/null
> +++
On Wed 14 Apr 20:31 CDT 2021, Taniya Das wrote:
>
> On 4/13/2021 9:19 AM, Viresh Kumar wrote:
> > On 12-04-21, 15:01, Taniya Das wrote:
> > > Technically the HW we are trying to program here differs in terms of
> > > clocking, the LUT definitions and many more. It will definitely make
> > >
On Tue 19 Jan 11:45 CST 2021, AngeloGioacchino Del Regno wrote:
> On new SoCs (SDM845 onwards) the Operating State Manager (OSM) is
> being programmed in the bootloader and write-protected by the
> hypervisor, leaving to the OS read-only access to some of its
> registers (in order to read the
> Suggested-by: Akhil P Oommen
> Signed-off-by: Sai Prakash Ranjan
Sorry for taking my time thinking about this.
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 12 +---
> 1 file changed, 9 insertions(+), 3 deletions
On Mon 19 Apr 05:32 CDT 2021, schow...@codeaurora.org wrote:
> On 2021-04-15 12:01, Felipe Balbi wrote:
> > Hi,
> >
> > Souradeep Chowdhury writes:
> > > diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
> > > index ad675a6..e7f0ccb 100644
> > > --- a/drivers/soc/qcom/Makefile
On Sat 17 Apr 08:25 CDT 2021, Thara Gopinath wrote:
> Add register programming sequence for enabling AEAD
> algorithms on the Qualcomm crypto engine.
>
> Signed-off-by: Thara Gopinath
> ---
>
> v1->v2:
> - Minor fixes like removing not needed initializing of variables
> and using
On Sat 17 Apr 08:24 CDT 2021, Thara Gopinath wrote:
> rf4309 is the specification that uses aes ccm algorithms with IPsec
> security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
> in the crypto driver.
>
Reviewed-by: Bjorn Andersson
> Signed-off-by:
On Sat 17 Apr 08:24 CDT 2021, Thara Gopinath wrote:
> MAC_FAILED gets set in the status register if authenthication fails
> for ccm algorithms(during decryption). Add support to catch and flag
> this error.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by:
On Wed 14 Apr 02:23 CDT 2021, Arnaud POULIQUEN wrote:
> On 4/13/21 11:34 PM, Bjorn Andersson wrote:
> > On Wed 31 Mar 02:33 CDT 2021, Arnaud Pouliquen wrote:
[..]
> >> + err = mbox_send_message(ddata->mb[idx].chan,
> >> + _dat
; - PINCTRL_MSM [=y] && PINCTRL [=y] && (ARCH_QCOM || COMPILE_TEST [=y])
>
> This is because PINCTRL_MSM selects GPIOLIB_IRQCHIP,
> without selecting or depending on GPIOLIB, despite
> GPIOLIB_IRQCHIP depending on GPIOLIB. Having PINCTRL_MSM
> select GPIOLIB will cause
On Sat 10 Apr 03:05 CDT 2021, Nikita Travkin wrote:
> Hi, sorry for a late reply but I couldn't answer earlier.
>
> 30.03.2021 19:40, Rob Herring ??:
> > On Fri, Mar 19, 2021 at 10:23:20PM +0500, nikitos...@gmail.com wrote:
> >> From: Nikita Travkin
> >>
> >> Add DT bindings for
ile ago:
> commit 82bcd087029f ("firmware: qcom: scm: Fix interrupted SCM calls")
>
> Without this change, the Qualcomm ARM32 platforms like SDX55 will return
> -EINVAL for SMC calls used for modem firmware loading and validation.
>
> Signed-off-by: Manivannan
GPIOLIB
> > >
> > > instead?
> > >
> > > The driver needs the library so...
> > >
> > > Yours,
> > > Linus Walleij
> > >
> >
> > Hi Linus,
> >
> > Looks like I confused this patch with another one when
> &g
On Tue 13 Apr 17:44 CDT 2021, Thara Gopinath wrote:
>
>
> On 4/13/21 6:20 PM, Bjorn Andersson wrote:
> > On Tue 13 Apr 16:31 CDT 2021, Thara Gopinath wrote:
> >
> > >
> > > Hi Bjorn,
> > >
> > > On 4/5/21 6:18 PM, Bjorn Andersson wr
On Mon 12 Apr 18:16 CDT 2021, Doug Anderson wrote:
> Bjorn,
>
> On Mon, Mar 15, 2021 at 1:39 PM Douglas Anderson
> wrote:
> >
> > This was present downstream. Add upstream too. NOTE: upstream I
> > managed to get some sort of halfway state and got one pinctrl entry in
> > the coachz-r1 device
On Tue 13 Apr 17:27 CDT 2021, Thara Gopinath wrote:
>
>
> On 4/5/21 6:18 PM, Bjorn Andersson wrote:
> > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> >
> > > Add register programming sequence for enabling AEAD
> > > algorithms on the Qualcomm
On Tue 13 Apr 16:31 CDT 2021, Thara Gopinath wrote:
>
> Hi Bjorn,
>
> On 4/5/21 6:18 PM, Bjorn Andersson wrote:
> > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> >
> > > Add register programming sequence for enabling AEAD
> > >
On Wed 31 Mar 02:33 CDT 2021, Arnaud Pouliquen wrote:
> A mechanism similar to the shutdown mailbox signal is implemented to
> detach a remote processor.
>
> Upon detachment, a signal is sent to the remote firmware, allowing it
> to perform specific actions such as stopping rpmsg communication.
On Thu 08 Apr 23:39 CDT 2021, Deepak Kumar Singh wrote:
[..]
> +/**
> + * qmp_get() - get a qmp handle from a device
> + * @dev: client device pointer
> + *
> + * Return: handle to qmp device on success, ERR_PTR() on failure
> + */
> +struct qmp *qmp_get(struct device *dev)
> +{
> + struct
On Tue 23 Mar 17:02 CDT 2021, Martin Blumenstingl wrote:
> Hi Bjorn,
>
> On Thu, Mar 18, 2021 at 3:55 AM Bjorn Andersson
> wrote:
> [...]
> > > +examples:
> > > + - |
> > > +remoteproc@1c {
> > > + compatible= "amlogic,mes
On Thu 18 Mar 09:59 CDT 2021, Arnaud Pouliquen wrote:
> From: Arnaud Pouliquen
>
> A mechanism similar to the shutdown mailbox signal is implemented to
> detach a remote processor.
>
> Upon detachment, a signal is sent to the remote firmware, allowing it
> to perform specific actions such as
On Tue 13 Apr 14:30 CDT 2021, Thara Gopinath wrote:
>
>
> On 4/5/21 6:32 PM, Bjorn Andersson wrote:
> > On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> >
> > > rf4309 is the specification that uses aes ccm algorithms with IPsec
> > > security pac
to only receiving PON interrupts.
>
> Add support for the PMK8350 PON_HLOS peripheral so that its
> KPDPWR_N and RESIN_N interrupts can be used to detect key
> presses.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: David Collins
> Signed-off-by: satya priya
On Mon 12 Apr 00:11 CDT 2021, Viresh Kumar wrote:
> On 19-01-21, 18:45, AngeloGioacchino Del Regno wrote:
> > **
> > ** NOTE: To "view the full picture", please look at the following
> > ** patch series:
> > ** https://patchwork.kernel.org/project/linux-arm-msm/list/?series=413355
> >
On Mon 12 Apr 13:52 CDT 2021, Arnd Bergmann wrote:
> On Mon, Apr 12, 2021 at 6:01 PM Bjorn Andersson
> wrote:
> > On Mon 12 Apr 08:14 CDT 2021, Arnd Bergmann wrote:
> > > On Mon, Apr 12, 2021 at 1:32 PM Geert Uytterhoeven
> > > wrote:
> > > > On Thu, A
On Fri 09 Apr 02:31 CDT 2021, Manivannan Sadhasivam wrote:
> On Sun, Apr 04, 2021 at 12:17:52PM -0500, Bjorn Andersson wrote:
> > On Fri 02 Apr 01:17 CDT 2021, Deepak Kumar Singh wrote:
> >
> > > Not all upcoming usecases will have an interface to allow the aoss
> >
On Thu 08 Apr 22:07 CDT 2021, Chunfeng Yun wrote:
> There is error log in clk_bulk_prepare/enable()
>
Reviewed-by: Bjorn Andersson
> Signed-off-by: Chunfeng Yun
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 8 ++--
> 1 file changed, 2 insertions(+), 6 deletions(
On Tue 06 Apr 05:27 CDT 2021, Maulik Shah wrote:
> From: Mahesh Sivasubramanian
>
> Let's add a driver to read the stats from remote processor and
> export to debugfs.
>
> The driver creates "qcom_sleep_stats" directory in debugfs and
> adds files for various low power mode available. Below is
On Mon 12 Apr 08:14 CDT 2021, Arnd Bergmann wrote:
> On Mon, Apr 12, 2021 at 1:32 PM Geert Uytterhoeven
> wrote:
> > On Thu, Apr 8, 2021 at 5:08 PM Arnd Bergmann wrote:
>
> > >
> > > For this merge window, I don't think any of them are show-stoppers (Rob,
> > > let me
> > > know if you
On Fri 09 Apr 06:46 CDT 2021, Dikshita Agarwal wrote:
> Fill fw version info into smem to be printed as part of
> soc info.
>
> Signed-off-by: Dikshita Agarwal
> Reported-by: kernel test robot
Why/how did kernel test robot tell you that you should write the
firmware version in SMEM?
>
>
The following changes since commit a38fd8748464831584a19438cbb3082b5a2dab15:
Linux 5.12-rc2 (2021-03-05 17:33:41 -0800)
are available in the Git repository at:
https://git.kernel.org/pub/scm/linux/kernel/git/andersson/remoteproc.git
tags/rproc-v5.12-fixes
for you to fetch changes up to
> Change-Id: I13fb096da54458f2882e8d853a3ad9c379e7d5a9
Please remember to drop the Change-Id when posting to the mailing lists.
We typically don't have defines for the IRQ numbers, but I don't mind.
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Guru Das Srinagesh
> ---
> include/dt-binding
On Fri 09 Apr 08:59 CDT 2021, satya priya wrote:
> Add binding doc for qcom pm8xxx rtc device.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: satya priya
> ---
> Changes in V2:
> - Added this in V2 to have separate binding for rtc node.
>
> ...
er Management ICs are used to provide regulated
> + voltages and other various functionality to Qualcomm SoCs.
> +
> +properties:
> + compatible:
> +enum:
> + - qcom,pm8058
> + - qcom,pm8821
> + - qcom,pm8921
> +
> + reg:
> +maxItems: 1
> +
ke sure the "snps,dwc3"-compatible nodes are correctly
> named.
>
> Signed-off-by: Serge Semin
> Acked-by: Krzysztof Kozlowski
> Reviewed-by: Bjorn Andersson
As mentioned previously, I would like to merge this through the qcom soc
tree to avoid conflicts with other activit
gt; Qcom-specific code to detect the DWC3 sub-node just by checking its
> compatible string to match the "snps,dwc3". The semantic of the code
> won't change seeing all the DWC USB3 nodes are supposed to have the
> compatible property with any of those strings set.
>
Reviewed-by: Bj
.data = (void *) 2 },
As with the binding, please keep these sorted alphabetically.
With that:
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> { },
> };
>
> --
> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
> a Linux Foundation Collaborative Project
>
n/devicetree/bindings/pinctrl/qcom,pmic-gpio.txt
> @@ -36,6 +36,7 @@ PMIC's from Qualcomm.
> "qcom,pm6150-gpio"
> "qcom,pm6150l-gpio"
> "qcom,pmx55-gpio"
> + "qcom,pm8008-gpio"
On Wed 07 Apr 10:37 CDT 2021, ska...@codeaurora.org wrote:
> Hi Bjorn,
>
> On 2021-03-11 22:33, Bjorn Andersson wrote:
> > On Thu 11 Mar 01:29 CST 2021, satya priya wrote:
[..]
> > > +patternProperties:
> > > + "rtc@[0-9a-f]+$":
> >
> &
use new header.
> Though for time being include new header back to kernel.h to avoid twisted
> indirected includes for existing users.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> rf4309 is the specification that uses aes ccm algorithms with IPsec
> security packets. Add a submode to identify rfc4309 ccm(aes) algorithm
> in the crypto driver.
>
> Signed-off-by: Thara Gopinath
> ---
> drivers/crypto/qce/common.h | 7
S_DUMP field optional so that algorithms can choose
> whether or not to enable the option.
> Note that in this patch, the enabled algorithms always choose
> RESULTS_DUMP to be enabled. But later with the introduction of ccm
> algorithms, this changes.
>
> Signed-off-by: Thara Gopinath
Rev
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> Add register programming sequence for enabling AEAD
> algorithms on the Qualcomm crypto engine.
>
> Signed-off-by: Thara Gopinath
> ---
> drivers/crypto/qce/common.c | 155 +++-
> 1 file changed, 153
On Thu 25 Feb 12:27 CST 2021, Thara Gopinath wrote:
> MAC_FAILED gets set in the status register if authenthication fails
> for ccm algorithms(during decryption). Add support to catch and flag
> this error.
>
> Signed-off-by: Thara Gopinath
> ---
> drivers/crypto/qce/common.c | 11 ---
On Mon 22 Mar 11:16 CDT 2021, Jami Kettunen wrote:
[..]
> diff --git a/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
> b/arch/arm64/boot/dts/qcom/msm8998-oneplus-cheeseburger.dts
> new file mode 100644
> index ..13b6b8ad4679
> --- /dev/null
> +++
On Thu 01 Apr 04:13 CDT 2021, satya priya wrote:
> Changes in V2:
> - As per Matthias's comments:
> - I've Split the patch into per-PMIC patches and one sc7280 patch
> - Removed 2nd critical point, thermal-governer property
> - s/pm8325_tz/pm7325_temp_alarm and
On Fri 02 Apr 01:17 CDT 2021, Deepak Kumar Singh wrote:
> [Change from V0]
It's typical that the first patchset, without a version specified, is
considered "version 1", and as such the second submission would be
"v2".
> Update qmp_get to parse qmp handle with binding qcom,qmp
>
I won't be
On Fri 02 Apr 01:17 CDT 2021, Deepak Kumar Singh wrote:
> Not all upcoming usecases will have an interface to allow the aoss
> driver to hook onto. Expose the send api and create a get function to
> enable drivers to send their own messages to aoss.
>
> Signed-off-by: Chris Lew
> Signed-off-by:
On Fri 02 Apr 01:17 CDT 2021, Deepak Kumar Singh wrote:
> It can be useful to control the different power states of various
> parts of hardware for device testing. Add a debugfs node for qmp so
> messages can be sent to aoss for debugging and testing purposes.
>
> Signed-off-by: Chris Lew
>
within this function.
>
> Fixes: a7ff82976122 ("drivers: thermal: tsens: Merge tsens-common.c into
> tsens.c")
>
> Signed-off-by: Guangqing Zhu
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> v2:
> - Fix a error(missing a bracket) in v1.
>
> ---
&g
On Thu 01 Apr 09:58 CDT 2021, nitir...@codeaurora.org wrote:
> On 2021-03-31 23:49, Bjorn Andersson wrote:
> > On Wed 24 Mar 16:55 CDT 2021, nitir...@codeaurora.org wrote:
> >
> > > On 2021-03-23 20:58, Bjorn Andersson wrote:
> > > > On Sun 21 M
On Thu 01 Apr 07:35 CDT 2021, satya priya wrote:
> Add PM7325, PM8350c, PMK8350 and PMR735A compatibles for GPIO
> support.
>
> Signed-off-by: satya priya
> Acked-by: Bjorn Andersson
> ---
> Changes in V2:
> - No change.
>
> drivers/pinctrl/qcom/pinctrl-
On Thu 01 Apr 07:35 CDT 2021, satya priya wrote:
> Update the binding to add PM7325, PM8350C, PMK8350 and PMR735A GPIO support.
>
> Signed-off-by: satya priya
> ---
> Changes in V2:
> - Placed this patch before conversion patch and updated commit text
>to be more clear.
>
>
man
> Cc: Brian Masney
> Cc: Stephan Gerhold
> Cc: Jeffrey Hugo
> Cc: Douglas Anderson
> Signed-off-by: Stephen Boyd
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
>
> Followup to v1
> (https://lore.kernel.org/r/20210223214539.1336155-7-swb...@chromiu
re is no
> need to iniitialize devnum with zero as this value is no read, so
> remove the redundant assignment.
>
> Addresses-Coverity: ("Unsigned compared against 0")
> Fixes: c7d49c76d1d5 ("soundwire: qcom: add support to new interrupts")
> Signed-
On Wed 24 Mar 16:55 CDT 2021, nitir...@codeaurora.org wrote:
> On 2021-03-23 20:58, Bjorn Andersson wrote:
> > On Sun 21 Mar 16:57 CDT 2021, Nitin Rawat wrote:
> >
> > > As a part of vops handler, VCC voltage is updated
> > > as per the ufs device probed after re
.
>
> While at it, drop the superfluous initialization as well
>
> drivers/soundwire/qcom.c: qcom_swrm_irq_handler() warn: impossible
> condition '(devnum < 0) => (0-255 < 0)'
>
> Reported-by: kernel test robot
> Signed-off-by: Vinod Koul
Reviewed-by: Bjorn Ande
On Wed 31 Mar 02:21 CDT 2021, Vinod Koul wrote:
> We get warning for using a unsigned variable being compared to less than
> zero. The comparison is correct as it checks for errors from previous
> call to qcom_swrm_get_alert_slave_dev_num(), so we should use a signed
> variable instead.
>
>
On Fri 26 Mar 01:33 CDT 2021, Dikshita Agarwal wrote:
> Fill fw version info into smem to be printed as part of
> soc info.
>
> Signed-off-by: Dikshita Agarwal
>
> Changes since v1:
> adressed comments from stephen.
> removed unwanted code.
> ---
>
On Wed 24 Mar 07:43 CDT 2021, Robert Foss wrote:
> Add tsens bindings for sm8350.
>
> Signed-off-by: Robert Foss
> Reviewed-by: Vinod Koul
Reviewed-by: Bjorn Andersson
@Daniel, I presume it's better that you take this patch (1/2) through
your tree. I've picked patch 2.
Re
On Fri 26 Mar 09:58 CDT 2021, Bartosz Dudziak wrote:
> This patch adds basic device tree support for MSM8226 SoC which belongs
> to the Snapdragon 400 family. For now, this file adds the basic nodes
> like gcc, pinctrl and other required configuration for booting up to
> the serial console.
>
>
On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:
> Plug dp_phy-provided clocks to display clock controller.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Dmitry Baryshkov
> ---
> arch/arm64/boot/dts/qcom/sm8250.dtsi | 8
> 1 file changed,
On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:
> USB1 QMP PHY is not just a USB3 PHY, but USB3+DP PHY. Change device tree
> nodes accordingly.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
@Vinod, will you let me know when you've picked the driver chan
On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:
> Add support for QMP V4 Combo USB3+DP PHY (for SM8250 platform).
>
> Signed-off-by: Dmitry Baryshkov
Acked-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/phy/qualcomm/phy-qcom-qmp.c | 388 ++--
On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:
> A plenty of DP PHY registers are common between V3 and V4. To simplify
> V4 code, rename all common registers.
>
> Signed-off-by: Dmitry Baryshkov
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
> drivers/phy/qualc
On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:
> In preparation to adding support for V4 DP PHY move DP functions to
> callbacks at struct qmp_phy_cfg.
>
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> Signed-off-by: Dmitry Baryshkov
> ---
> drivers/phy/qualcomm/ph
On Sun 28 Mar 15:52 CDT 2021, Dmitry Baryshkov wrote:
> Add compatible for SM8250 in QMP USB3 DP PHY bindings.
>
> Signed-off-by: Dmitry Baryshkov
> Acked-by: Rob Herring
Reviewed-by: Bjorn Andersson
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.ya
-usb3-dp-phy.yaml to describe only real "combo" USB3+DP device nodes.
>
> Fixes: 724fabf5df13 ("dt-bindings: phy: qcom,qmp-usb3-dp: Add DP phy
> information")
> Cc: Stephen Boyd
> Cc: Sandeep Maheswaram
> Signed-off-by: Dmitry Baryshkov
> Acked-
On Fri 26 Mar 18:13 CDT 2021, Eric Anholt wrote:
> This enables the adreno-specific SMMU path that sets HUPCF so
> (user-managed) page faults don't wedge the GPU.
>
> Signed-off-by: Eric Anholt
Acked-by: Bjorn Andersson
@Will, can you pick this together with the drive
all the way to the TTBR1 path.
>
> Signed-off-by: Eric Anholt
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
> ---
>
> We've been seeing a flaky test per day or so in Mesa CI where the
> kernel gets wedged after an iommu fault turns into CP errors. With
> this patch, the C
On Fri 26 Mar 10:24 CDT 2021, Rob Clark wrote:
> On Fri, Mar 26, 2021 at 8:18 AM Rob Clark wrote:
> >
> > On Fri, Mar 26, 2021 at 5:38 AM Thierry Reding
> > wrote:
> > >
> > > On Wed, Mar 17, 2021 at 06:53:04PM -0700, Rob Clark wrote:
> > > > On Wed, Mar 17, 2021 at 4:27 PM Matthias Kaehlcke
On Fri 12 Mar 20:35 CST 2021, Konrad Dybcio wrote:
> Hi,
>
>
> I'm not sure I can agree. Especially for regions like IPA and
> TZ-reserved, which seem the same on (almost?) all..
>
Thanks Konrad, I appreciate that.
>
> Sure, the configuration for various remoteprocs *can* differ based on
>
On Tue 23 Mar 13:27 CDT 2021, Elliot Berman wrote:
> On 3/22/2021 8:36 PM, Stephen Boyd wrote:
> > Quoting Bjorn Andersson (2021-03-07 09:42:45)
> > > On Sat 06 Mar 00:18 CST 2021, Stephen Boyd wrote:
> > >
> > > > Quoting Elliot Berman (2021-03-05 1
On Sun 21 Mar 16:57 CDT 2021, Nitin Rawat wrote:
> As a part of vops handler, VCC voltage is updated
> as per the ufs device probed after reading the device
> descriptor. We follow below steps to configure voltage
> level.
>
> 1. Set the device to SLEEP state.
> 2. Disable the Vcc Regulator.
>
o22",
>^
> Add the missing comma that must have accidentally been removed.
That's certainly a useful warning! Thanks Arnd.
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
>
> Fixes: ac43c44a7a37 ("pinctrl: qcom
On Thu 18 Mar 11:56 CDT 2021, Jeffrey Hugo wrote:
> form -> from in the subject?
>
Seems like I only failed in the cover letter, right?
Regards,
Bjorn
> On Thu, Mar 11, 2021 at 5:34 PM Bjorn Andersson
> wrote:
> >
> > The wireless subsystem found in Qualcomm MSM89
On Mon 15 Mar 07:01 CDT 2021, Bryan O'Donoghue wrote:
> On 12/03/2021 00:33, Bjorn Andersson wrote:
> > Enable the modem and WiFi subsystems and specify msm8916 specific
> > firmware path for these and the WCNSS control service.
> >
> > Signed-off-by: Bjorn Andersso
On Tue 29 Dec 19:27 CST 2020, Martin Blumenstingl wrote:
> Amlogic Meson6, Meson8, Meson8b and Meson8m2 SoCs embed an ARC EM4
> controller for always-on operations, typically used for managing system
> suspend.
>
> Signed-off-by: Martin Blumenstingl
> ---
>
On Tue 29 Dec 19:27 CST 2020, Martin Blumenstingl wrote:
> Amlogic Meson6, Meson8, Meson8b and Meson8m2 embed an ARC core in the
> Always-On (AO) power-domain. This is typically used for waking up the
> ARM cores after system suspend.
>
> The configuration is spread across three different
On Fri 29 Jan 11:11 CST 2021, Gokul Sriram Palanisamy wrote:
> Populate hardcoded param using driver data for IPQ6018 SoCs.
>
> Signed-off-by: Gokul Sriram Palanisamy
> ---
> drivers/remoteproc/qcom_q6v5_wcss.c | 19 +--
> 1 file changed, 17 insertions(+), 2 deletions(-)
>
>
On Fri 29 Jan 23:20 CST 2021, Gokul Sriram Palanisamy wrote:
> IPQ8074 uses secure PIL. Hence, adding the support for the same.
>
Sorry for not giving this a proper review before Gokul, I've look at it
but been uncertain about what feedback to offer.
> Signed-off-by: Gokul Sriram Palanisamy
>
On Wed 17 Mar 09:02 CDT 2021, Marc Zyngier wrote:
> On Wed, 17 Mar 2021 09:48:09 +,
> Maulik Shah wrote:
> >
> > Hi Marc,
> >
> > On 3/17/2021 2:47 PM, Marc Zyngier wrote:
> > > On Wed, 17 Mar 2021 05:29:54 +,
> > > Maulik Shah wrote:
> > >> PDC interrupt controller driver do not use
des the DPU platform_device.
Replace the open coded test for compatibles with a check against the
match data of the mdss device to save others this trouble in the future.
Signed-off-by: Bjorn Andersson
---
drivers/gpu/drm/msm/msm_drv.c | 15 +--
1 file changed, 9 insertions(+)
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