On Mon, 27 Aug 2018 20:52:34 -0500
Rob Herring wrote:
> In preparation to remove the node name pointer from struct device_node,
> convert printf users to use the %pOFn format specifier.
>
> Cc: Boris Brezillon
> Cc: Miquel Raynal
> Cc: Richard Weinberger
> Cc: David W
On Mon, 27 Aug 2018 16:01:41 +0900
Masahiro Yamada wrote:
> Commit 49aa76b16676 ("mtd: rawnand: do not execute nand_scan_ident()
> if maxchips is zero") gave a new meaning for calling nand_scan_ident()
> with maxchips=0.
>
> It is a special usage for some drivers such as docg4, but actually
> th
On Thu, 23 Aug 2018 23:43:45 +0200
Geert Uytterhoeven wrote:
> If gcc (e.g. 4.1.2) decides not to inline init_mtd_structs() and
> read_id_reg(), this will cause section mismatches, and crashes:
>
> WARNING: drivers/mtd/nand/raw/docg4.o(.text+0xc10): Section mismatch in
> reference from the
On Mon, 27 Aug 2018 23:02:29 +0800 (CST)
liuxiang wrote:
> Fixes:e46ecda764dc37f9fc6279d95ea2c007daef1a71("mtd: spi-nor: Add Freescale
> QuadSPI driver")
12 digits should be enough for the commit-id.
> Cc: sta...@vger.kernel.org
>
> Should I send a V2 patch that adds these above？
Yes please
On Mon, 27 Aug 2018 10:44:14 +0200
Johan Hovold wrote:
> On Mon, Aug 27, 2018 at 10:28:20AM +0200, Boris Brezillon wrote:
> > Hi Johan
> >
> > On Mon, 27 Aug 2018 10:21:49 +0200
> > Johan Hovold wrote:
> >
> > > Use the new of_get_compatible_child()
> Fixes: f88fc122cc34 ("mtd: nand: Cleanup/rework the atmel_nand driver")
> Cc: stable # 4.11
> Cc: Nicolas Ferre
> Cc: Josh Wu
> Cc: Boris Brezillon
> Signed-off-by: Johan Hovold
Acked-by: Boris Brezillon
I'll let Miquel queue this patch to the nand/next b
On Sat, 18 Aug 2018 17:14:23 +0800
Liu Xiang wrote:
> If the size of spi-nor flash is larger than 16MB, the read_opcode
> is set to SPINOR_OP_READ_1_1_4_4B, and fsl_qspi_get_seqid() will
> return -EINVAL when cmd is SPINOR_OP_READ_1_1_4_4B. This can
> cause read operation fail.
>
> Signed-off-by
Hi Gustavo,
On Thu, 23 Aug 2018 20:09:38 -0500
"Gustavo A. R. Silva" wrote:
> One of the more common cases of allocation size calculations is finding
> the size of a structure that has a zero-sized array at the end, along
> with memory for some number of elements for that array. For example:
>
On Mon, 27 Aug 2018 16:01:41 +0900
Masahiro Yamada wrote:
> Commit 49aa76b16676 ("mtd: rawnand: do not execute nand_scan_ident()
> if maxchips is zero") gave a new meaning for calling nand_scan_ident()
> with maxchips=0.
>
> It is a special usage for some drivers such as docg4, but actually
> th
On Sat, 25 Aug 2018 00:04:43 +0900
Masahiro Yamada wrote:
> Hi Boris,
>
> 2018-08-24 21:55 GMT+09:00 Boris Brezillon :
> > Hi Masahiro,
> >
> > On Tue, 21 Aug 2018 17:23:19 +0900
> > Masahiro Yamada wrote:
> >
> >> Commit 49aa76b16676 ("m
d.
>
> This optimisation will become particularly important as soon as
> planned conversion of the driver to GPIO API for data I/O will be
> implemented.
>
> Signed-off-by: Janusz Krzysztofik
Reviewed-by: Boris Brezillon
> ---
> d
Hi Masahiro,
On Tue, 21 Aug 2018 17:23:19 +0900
Masahiro Yamada wrote:
> Commit 49aa76b16676 ("mtd: rawnand: do not execute nand_scan_ident()
> if maxchips is zero") gave a new meaning for calling nand_scan_ident()
> with maxchips=0.
>
> It is a special usage for some drivers such as docg4, but
On Wed, 22 Aug 2018 22:08:42 +0800
Liang Yang wrote:
> > You have to wait tWB, that's for sure.
> >
> we have a maximum 32 commands fifo. when command is written into
> NFC_REG_CMD, it doesn't mean that command is executing right now, maybe
> it is buffering on the queue.Assume one ERASE ope
ruct_size() helper:
>
> instance = devm_kzalloc(dev, struct_size(instance, entry, count), GFP_KERNEL);
Oh, I didn't know about that one. That's nice!
>
> Signed-off-by: Gustavo A. R. Silva
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/jz4780_nand.c | 2 +
On Tue, 21 Aug 2018 09:22:07 +
Naga Sureshkumar Relli wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Tuesday, August 21, 2018 11:30 AM
> > To: Naga Sureshkumar Relli
> >
On Tue, 21 Aug 2018 10:44:54 +
Naga Sureshkumar Relli wrote:
> Hi Miquel,
>
> > -Original Message-
> > From: Miquel Raynal [mailto:miquel.ray...@bootlin.com]
> > Sent: Tuesday, August 21, 2018 3:23 PM
> > To: Naga Sureshkumar Relli
> > Cc: Boris
On Tue, 21 Aug 2018 05:47:18 +
Naga Sureshkumar Relli wrote:
> > > +Required properties:
> > > +- compatible:Should be "xlnx,zynqmp-nand" or
> > > "arasan,nfc-v3p10"
> >
> > In your example it's not an "or" since both are defined.
> In our previous discussion (https://lore.k
Hi Naga,
On Fri, 17 Aug 2018 18:49:24 +0530
Naga Sureshkumar Relli wrote:
>
> +config MTD_NAND_ARASAN
> + tristate "Support for Arasan Nand Flash controller"
> + depends on HAS_IOMEM
> + depends on HAS_DMA
Just nitpicking, but you can place them on the same line:
depends
On Mon, 20 Aug 2018 13:01:13 +
David Laight wrote:
> From: Chuanhua Han
> > Sent: 20 August 2018 13:44
> >
Still no message here, and the subject prefix is still wrong.
Fixes and Cc-stable tags should be placed here...
> > Signed-off-by: Chuanhua Han
> > ---
> > Changes in v3:
> > R
On Fri, 17 Aug 2018 18:49:23 +0530
Naga Sureshkumar Relli wrote:
> This patch adds the dts binding document for arasan nand flash
> controller.
>
> Signed-off-by: Naga Sureshkumar Relli
> ---
> Changes in v10:
> - None
> Changes in v9:
> - None
> Changes in v8:
> - Updated compatible and clock-
On Mon, 20 Aug 2018 12:21:12 +
Naga Sureshkumar Relli wrote:
> Hi Boris,
>
> > -Original Message-
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Monday, August 20, 2018 5:40 PM
> > To: Naga Sureshkumar Relli
> > Cc: r
On Mon, 20 Aug 2018 10:49:38 +
Naga Sureshkumar Relli wrote:
>
> Thanks for your suggestion and are you saying something like Marvell parser
> patterns for nfcv1 as below?
>
> static const struct nand_op_parser marvell_nfcv1_op_parser = NAND_OP_PARSER(
> /* Naked commands not support
Hi Chuanhua,
On Mon, 20 Aug 2018 17:43:26 +0800
Chuanhua Han wrote:
Subject prefix should be "spi: spi-mem: " not "mtd: m25p80: ", and you
need a commit message explaining what this patch does and why it's
needed.
> Signed-off-by: Chuanhua Han
Fixes: c36ff266dc82 ("spi: Extend the core to eas
On Sat, 18 Aug 2018 05:49:32 +
Naga Sureshkumar Relli wrote:
> Hi Boris,
>
> Thanks for the review.
>
> > -Original Message-----
> > From: Boris Brezillon [mailto:boris.brezil...@bootlin.com]
> > Sent: Friday, August 17, 2018 11:29 PM
> > To: Naga S
Hi Naga,
On Fri, 17 Aug 2018 18:49:24 +0530
Naga Sureshkumar Relli wrote:
> +static int anfc_exec_op_cmd(struct nand_chip *chip,
> +const struct nand_subop *subop)
> +{
> + const struct nand_op_instr *instr;
> + struct anfc_op nfc_op = {};
> + struct a
On Fri, 17 Aug 2018 15:56:23 +
"Luck, Tony" wrote:
> >> - Some targets don't have any support for I/O space on their PCI bus and
> >> just
> >>want to get things to compile by setting PCI_IOBASE to zero, this still
> >> opens
> >> up some of the same problems as above, but doesn't r
On Fri, 17 Aug 2018 21:03:59 +0800
Liang Yang wrote:
> Hi Boris,
> On 2018/8/2 5:50, Boris Brezillon wrote:
>
> > Hi Yixun,
> >
> > On Thu, 19 Jul 2018 17:46:12 +0800
> > Yixun Lan wrote:
> >
> > I haven't finished reviewing the driver ye
On Fri, 17 Aug 2018 18:07:05 +0800
Chuanhua Han wrote:
> The length of the transmitted data needs to be adjusted due to the maximum
> length limit for espi transmission messages
>
> Signed-off-by: Chuanhua Han
> ---
> drivers/spi/spi-fsl-espi.c | 25 +
> 1 file changed
On Fri, 17 Aug 2018 10:47:34 +0200
Arnd Bergmann wrote:
> On Fri, Aug 17, 2018 at 1:27 AM Luck, Tony wrote:
> >
> > On Thu, Aug 16, 2018 at 11:10:33PM +0200, Arnd Bergmann wrote:
> > > Another way would be to add
> > >
> > > #include
> > > +#undef PCI_IOBASE
> > >
> > > in your asm/io.h. Thi
Hi Yixun,
I know I said I would finish reviewing the driver, but I didn't have
time to do it, so feel free to send a new version addressing the
comments I already made.
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
> +static void meson_nfc_select_chip(struct mtd_info *mtd, int chip)
> +{
On Tue, 14 Aug 2018 00:34:48 +0200
Janusz Krzysztofik wrote:
> Don't readw()/writew() data directly from/to GPIO port which is under
> control of gpio-omap driver, use GPIO API instead.
>
> Degrade of performance on Amstrad Delta is significant, can be
> recognized as a regression, that's why I'
On Tue, 14 Aug 2018 00:34:46 +0200
Janusz Krzysztofik wrote:
> In its current shape, the driver sets data port direction before each
> byte read/write operation, even during multi-byte transfers. Improve
> performance of the driver by setting the port direction only when
> needed.
>
> This opti
Hi Chuanhua,
On Wed, 15 Aug 2018 14:33:43 +0800
Chuanhua Han wrote:
> Consider a message size limit when calculating the maximum amount
> of data that can be read.
>
> Signed-off-by: Chuanhua Han
> ---
> drivers/mtd/devices/m25p80.c | 7 ++-
> 1 file changed, 6 insertions(+), 1 deletion(-
Hi Randy,
On Fri, 10 Aug 2018 08:37:01 -0700
Randy Dunlap wrote:
> On 08/09/2018 08:11 PM, a...@linux-foundation.org wrote:
> > The mm-of-the-moment snapshot 2018-08-09-20-10 has been uploaded to
> >
> >http://www.ozlabs.org/~akpm/mmotm/
> >
> > mmotm-readme.txt says
> >
> > README for mm
On Tue, 7 Aug 2018 00:29:13 +0200
Janusz Krzysztofik wrote:
> In its current shape, the driver sets data port direction before each
> byte read/write operation, even during multi-byte transfers. Since
> performance of the driver is completely not acceptable on Amstrad Delta
> after it has been
On Mon, 6 Aug 2018 15:01:37 +0300
Dan Carpenter wrote:
> On Mon, Aug 06, 2018 at 01:46:48PM +0200, Boris Brezillon wrote:
> > Hi Dan,
> >
> > On Wed, 1 Aug 2018 15:05:51 +0300
> > Dan Carpenter wrote:
> >
> > > On Wed, Aug 01, 2018 at 11:24:19AM
Hi Dan,
On Wed, 1 Aug 2018 15:05:51 +0300
Dan Carpenter wrote:
> On Wed, Aug 01, 2018 at 11:24:19AM +0800, Jheng-Jhong Wu wrote:
> > For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> > are necessary to address the correct page. The driver sets the address for
> > more
AYASHI Yoshitake
With the commit message adjusted as suggested above,
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_toshiba.c | 53
> -
> 1 file changed, 52 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw
command only knows whether there was bitflips above the
> threshold and can not get accurate bitflips. For now, I set
> max_bitflips mtd->bitflip_threshold.
>
> Signed-off-by: KOBAYASHI Yoshitake
Reviewed-by: Boris Brezillon
> ---
> drivers
D to the SPI layer.
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Frieder Schrempf
Acked-by: Boris Brezillon
> ---
> drivers/mtd/devices/m25p80.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/mtd/devices/m25p80.c b/drivers/mtd/devices/m25p8
new driver without spi_mem_get_name: spi4.0
>
> Suggested-by: Boris Brezillon
> Signed-off-by: Frieder Schrempf
Reviewed-by: Boris Brezillon
> ---
> drivers/spi/spi-mem.c | 28
> include/linux/spi/spi-mem.h | 12
> 2 files ch
On Thu, 2 Aug 2018 14:53:52 +0200
Frieder Schrempf wrote:
We usually try to avoid empty commit message, even if this one is
pretty obvious, I'd suggest adding something here.
"
Fix a typo in the @drvpriv description.
"
?
> Signed-off-by: Frieder Schrempf
Acked-b
On Thu, 2 Aug 2018 12:46:36 +0200
Frieder Schrempf wrote:
> Hi Mark,
>
> On 02.08.2018 12:17, Mark Brown wrote:
> > On Wed, Aug 01, 2018 at 09:57:33PM +0200, Boris Brezillon wrote:
> >> Mark Brown wrote:
> >
> >> 2/ Getting this patch [1] merged
Hi Yixun,
On Thu, 19 Jul 2018 17:46:12 +0800
Yixun Lan wrote:
I haven't finished reviewing the driver yet (I'll try to do that later
this week), but I already pointed a few things to fix/improve.
> +
> +static int meson_nfc_exec_op(struct nand_chip *chip,
> + const stru
Hi Mark,
On Wed, 1 Aug 2018 18:27:47 +0100
Mark Brown wrote:
> On Wed, Jun 27, 2018 at 03:16:08PM +0200, Piotr Bugalski wrote:
> > Kernel contains QSPI driver strongly tied to MTD and nor-flash memory.
> > New spi-mem interface allows usage also other memory types, especially
> > much larger NAN
Hi Jheng-Jhong,
On Wed, 1 Aug 2018 11:24:19 +0800
Jheng-Jhong Wu wrote:
> For NAND flash chips with more than 1Gbit (e.g. MT29F2G) more than 16 bits
> are necessary to address the correct page. The driver sets the address for
> more than 16 bits, but it uses 16-bit arguments and variables (thes
On Sun, 29 Jul 2018 22:36:49 +0200
Linus Walleij wrote:
> On Thu, Jul 19, 2018 at 8:44 AM Boris Brezillon
> wrote:
>
> > I guess you'd prefer to have the pin values in a bitmap instead of an
> > array of integers. That's probably something you can discuss with
&g
On Fri, 27 Jul 2018 05:21:49 +
Nicholas Mc Guire wrote:
> On Thu, Jul 26, 2018 at 10:09:28PM +0200, Boris Brezillon wrote:
> > On Wed, 25 Jul 2018 06:31:37 +
> > Nicholas Mc Guire wrote:
> >
> > > On Tue, Jul 24, 2018 at 10:46:26PM +0200, Boris Brezill
On Wed, 25 Jul 2018 06:31:37 +
Nicholas Mc Guire wrote:
> On Tue, Jul 24, 2018 at 10:46:26PM +0200, Boris Brezillon wrote:
> > On Sat, 21 Jul 2018 18:08:13 +0200
> > Nicholas Mc Guire wrote:
> >
> > > wait_for_completion_timeout returns an unsigned long not
;} [-Wformat=]
> ../drivers/mtd/maps/solutionengine.c:62:72: note: format string is defined
> here
> printk(KERN_NOTICE "Solution Engine: Flash at 0x%08lx, EPROM at 0x%08lx\n",
> ^
> %08x
On Sun, 22 Jul 2018 08:44:32 +0200
Boris Brezillon wrote:
> On Fri, 20 Jul 2018 17:15:19 +0200
> Miquel Raynal wrote:
>
> > Two helpers have been added to the core to make ECC-related
> > configuration between the detection phase and the final NAND scan. Use
> >
On Thu, 26 Jul 2018 14:06:41 +0800
xiaolei li wrote:
> On Sat, 2018-07-21 at 19:10 +0200, Boris Brezillon wrote:
> > On Fri, 20 Jul 2018 17:15:06 +0200
> > Miquel Raynal wrote:
> >
> > > Two helpers have been added to the core to make ECC-related
> > &
On Wed, 25 Jul 2018 16:56:28 +0200
Miquel Raynal wrote:
> Mails to wenyou.y...@microchip.com are not deliverable.
> Drop him as Microchip/Atmel NAND controller driver maintainer.
>
> Signed-off-by: Miquel Raynal
> ---
> MAINTAINERS | 1 -
> 1 file changed, 1 deletion(-)
>
> diff --git a/MAINT
On Wed, 25 Jul 2018 16:56:28 +0200
Miquel Raynal wrote:
> Mails to wenyou.y...@microchip.com are not deliverable.
> Drop him as Microchip/Atmel NAND controller driver maintainer.
>
> Signed-off-by: Miquel Raynal
Acked-by: Boris Brezillon
> ---
> MAINTAINERS | 1 -
&g
On Wed, 25 Jul 2018 18:42:44 +0900
Masahiro Yamada wrote:
>
> You need to remove kfree(denali->buf)
> from denali_remove(), right?
Absolutely.
>
> void denali_remove(struct denali_nand_info *denali)
> {
> struct mtd_info *mtd = nand_to_mtd(&denali->nand);
>
> nand_release(mtd
On Sat, 21 Jul 2018 18:08:13 +0200
Nicholas Mc Guire wrote:
> wait_for_completion_timeout returns an unsigned long not int. declare a
> suitably type timeout and fix up assignment and check.
>
> Signed-off-by: Nicholas Mc Guire
> Reported-by: Vignesh R
> Fixes: 140623410536 ("mtd: spi-nor: Add
On Tue, 24 Jul 2018 12:52:02 -0700
Brian Norris wrote:
> > > Or even better: put this hack behind a DT flag, so that one has to
> > > admit that their board design is broken before it will even do
> > > anything. Proposal: "linux,badly-designed-flash-reset".
> >
> > I think we can remove the "
x27;} [-Wformat=]
> ../drivers/mtd/maps/solutionengine.c:62:72: note: format string is defined
> here
> printk(KERN_NOTICE "Solution Engine: Flash at 0x%08lx, EPROM at 0x%08lx\n",
> ^
>
On Tue, 24 Jul 2018 08:46:33 +1000
NeilBrown wrote:
> On Mon, Jul 23 2018, Brian Norris wrote:
>
> > Hi Boris,
> >
> > On Mon, Jul 23, 2018 at 1:10 PM, Boris Brezillon
> > wrote:
> >> On Mon, 23 Jul 2018 11:13:50 -0700
> >> Brian Norris wrote:
+Neil
On Mon, 23 Jul 2018 15:06:43 -0700
Brian Norris wrote:
> Hi Boris,
>
> On Mon, Jul 23, 2018 at 1:10 PM, Boris Brezillon
> wrote:
> > On Mon, 23 Jul 2018 11:13:50 -0700
> > Brian Norris wrote:
> >> I noticed this got merged, but I wanted to put my 2 ce
Hi Brian,
On Mon, 23 Jul 2018 11:13:50 -0700
Brian Norris wrote:
> Hello,
>
> I noticed this got merged, but I wanted to put my 2 cents in here:
I wish you had replied to this thread when it was posted (more than
6 months ago). Reverting the patch now implies making some people
unhappy because
On Mon, 23 Jul 2018 18:04:52 +0200
Arnd Bergmann wrote:
> On Mon, Jul 23, 2018 at 5:40 PM, Arnd Bergmann wrote:
> > On Mon, Jul 23, 2018 at 11:41 AM, Boris Brezillon
> > wrote:
> >> On Mon, 23 Jul 2018 11:34:43 +0200
> >> Arnd Bergmann wrote:
> >&g
On Mon, 23 Jul 2018 17:40:29 +0200
Arnd Bergmann wrote:
> On Mon, Jul 23, 2018 at 11:41 AM, Boris Brezillon
> wrote:
> > On Mon, 23 Jul 2018 11:34:43 +0200
> > Arnd Bergmann wrote:
> >
> >> On Sun, Jul 22, 2018 at 8:29 AM, Boris Brezillon
> >>
On Mon, 23 Jul 2018 11:34:43 +0200
Arnd Bergmann wrote:
> On Sun, Jul 22, 2018 at 8:29 AM, Boris Brezillon
> wrote:
> > +Arnd, Rob and the DT ML.
> >
> > On Sat, 21 Jul 2018 14:53:47 -0700
> > Randy Dunlap wrote:
> >
> >> On 07/21/2018 01:00
and/raw/nand_micron.c
> @@ -88,9 +88,9 @@ static int micron_nand_setup_read_retry(struct mtd_info
> *mtd, int retry_mode)
> static int micron_nand_onfi_init(struct nand_chip *chip)
> {
> struct nand_parameters *p = &chip->parameters;
> - struct nand_onfi_vend
ed in nand_detect().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nand_base.c | 52
> +++-
> include/linux/mtd/rawnand.h | 2 +-
> 2 files changed, 42 insertions(+), 12 deletions(-)
On Fri, 20 Jul 2018 17:15:25 +0200
Miquel Raynal wrote:
> Both nand_scan_ident() and nand_scan_tail() helpers used to be called
> directly from controller drivers that needed to tweak some ECC-related
> parameters before nand_scan_tail(). This separation prevented dynamic
> allocations during the
On Fri, 20 Jul 2018 17:15:24 +0200
Miquel Raynal wrote:
> + chip = &nand->chip;
> + chip->controller = &ctrl->controller;
> + chip->controller->ops = &tegra_nand_controller_ops;
Should be moved next to the controller initialization.
On Fri, 20 Jul 2018 17:15:23 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
com_nandc_ops;
This assignment should be moved here [1].
Once fixed you can add
Reviewed-by: Boris Brezillon
[1]https://elixir.bootlin.com/linux/v4.18-rc5/source/drivers/mtd/nand/raw/qcom_nandc.c#L2574
On Fri, 20 Jul 2018 17:15:21 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
On Fri, 20 Jul 2018 17:15:20 +0200
Miquel Raynal wrote:
> Some driver (eg. docg4) will need to handle themselves the
> identification phase. As part of the migration to use nand_scan()
> everywhere (which will unconditionnaly call nand_scan_ident()), we add
> a condition at the start of nand_scan
d_scan() for passing a flash IDs table) instead of
> both nand_scan_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/sm_common.c | 39 +--
> 1 file changed, 25 insertions
On Fri, 20 Jul 2018 17:15:18 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
+Arnd, Rob and the DT ML.
On Sat, 21 Jul 2018 14:53:47 -0700
Randy Dunlap wrote:
> On 07/21/2018 01:00 PM, Anders Roxell wrote:
> > JZ4780_NEMC doesn't depend on OF, and if OF isn't enabled we get this
> > error:
> > drivers/memory/jz4780-nemc.c: In function ‘jz4780_nemc_num_banks’:
> > drivers/
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/vf610_nfc.c | 127
> ---
> 1 file changed, 66 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/mtd/nand/r
On Fri, 20 Jul 2018 17:15:16 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/txx9ndfmc.c | 29 +++--
> 1 file changed, 15 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/txx9ndfmc.c
>
On Fri, 20 Jul 2018 17:15:15 +0200
Miquel Raynal wrote:
> As already done in the core, calling a struct nand_controller
> 'hw_control' is misleading. Use the same name as in nand_base.c:
> 'controller'.
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Br
582,14 @@ static int chip_init(struct device *dev, struct
> device_node *np)
> NAND_NO_SUBPAGE_WRITE |
> NAND_WAIT_TCCS;
> chip->controller = &nfc->hw;
> + chip->controller->ops = &tango_control
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/sunxi_nand.c | 43
> +--
> 1 file changed, 19 insertions(+), 24 deletions(-)
>
> diff --git a/drivers/mtd/nand/ra
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/sh_flctl.c | 19 ---
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/sh_flctl.c b/driver
On Fri, 20 Jul 2018 17:15:11 +0200
Miquel Raynal wrote:
> @@ -1007,6 +1007,16 @@ static int flctl_chip_init_tail(struct mtd_info *mtd)
> struct sh_flctl *flctl = mtd_to_flctl(mtd);
> struct nand_chip *chip = &flctl->chip;
>
> + if (chip->options & NAND_BUSWIDTH_16) {
> +
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/s3c2410.c | 30 +-
> 1 file changed, 13 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/s3c2410.c b/drive
On Fri, 20 Jul 2018 17:15:09 +0200
Miquel Raynal wrote:
> static int omap_nand_probe(struct platform_device *pdev)
> {
> struct omap_nand_info *info;
> struct mtd_info *mtd;
> struct nand_chip*nand_chip;
> int
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/nandsim.c | 82
> +++---
> 1 file changed, 45 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/mtd/nand/
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/mxc_nand.c | 136
> +---
> 1 file changed, 71 insertions(+), 65 deletions(-)
>
> diff --git a/drivers/mtd/nand/r
2 tmp;
> int ret;
> int i;
> @@ -1287,6 +1328,7 @@ static int mtk_nfc_nand_chip_init(struct device *dev,
> struct mtk_nfc *nfc,
>
> nand = &chip->nand;
> nand->controller = &nfc->controller;
> + nand->controller->ops =
th that fixed, you can add
Reviewed-by: Boris Brezillon
> + ret = nand_scan(mtd, marvell_nand->nsels);
> if (ret) {
> - dev_err(dev, "nand_scan_tail failed: %d\n", ret);
> + dev_err(dev, "could not scan the nand chip\n");
> return ret;
> }
>
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/lpc32xx_slc.c | 77
> +-
> 1 file changed, 42 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw
On Fri, 20 Jul 2018 17:15:03 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
> Acked-by: Harvey Hunt
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/jz4780_nand.c | 34 --
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/dri
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/hisi504_nand.c | 78
> +
> 1 file changed, 44 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c | 56
> ++
> 1 file changed, 33 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/mtd/nand/ra
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/fsmc_nand.c | 148
> +--
> 1 file changed, 78 insertions(+), 70 deletions(-)
>
> diff --git a/drivers/mtd/nand/r
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/fsl_ifc_nand.c | 19 ---
> 1 file changed, 8 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/mtd/nand/raw/fsl_ifc_nand.c
> b
_mtd *priv = nand_get_controller_data(chip);
> struct fsl_lbc_ctrl *ctrl = priv->ctrl;
> struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
> @@ -706,6 +706,10 @@ static int fsl_elbc_chip_init_tail(struct mtd_info *mtd)
Looks like fsl_elbc_chip_init_tail() was retur
_ident() and nand_scan_tail().
>
> Signed-off-by: Miquel Raynal
Reviewed-by: Boris Brezillon
> ---
> drivers/mtd/nand/raw/denali.c | 138
> +++---
> 1 file changed, 77 insertions(+), 61 deletions(-)
>
> diff --git a/drivers/mtd/nand
can use to get
a platform_device object from a device one, so this change was not
really needed. Actually, you should not even need a ->dev field here
because it can be retrieved from mtd->dev.parent. Anyway, if you
patched all places using davinci->dev to now use &davinci->pdev->dev
On Fri, 20 Jul 2018 17:14:54 +0200
Miquel Raynal wrote:
> Two helpers have been added to the core to make ECC-related
> configuration between the detection phase and the final NAND scan. Use
> these hooks and convert the driver to just use nand_scan() instead of
> both nand_scan_ident() and nand_
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