On some architectures, the ioread routines are still using a non-const
argument for the address parameter. Let's change that to be consistent
with the others and fix compile testing (ARM drivers on Intel for
instance).
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
I am not sure
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
drivers/char/ipmi/Kconfig |1 +
1 file changed, 1 insertion(+)
Index: linux.git/drivers/char/ipmi/Kconfig
===
--- linux.git.orig/drivers/char/ipmi/Kconfig
+++ linux.git/d
On 09/21/2016 12:05 PM, Joel Stanley wrote:
> devm_ioremap_resource returns ERR_PTR so we can't check for NULL.
Thanks for spotting this.
Acked-by: Cédric Le Goater <c...@kaod.org>
C.
> Signed-off-by: Joel Stanley <j...@jms.id.au>
> ---
> drivers/char/ipmi/bt-bmc.c |
-off-by: Andrew Jeffery <and...@aj.id.au>
It would be nice to have an example of the associated binding.
I did not see it. A part from that :
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
> ---
> drivers/char/ipmi/Kconfig | 1 +
> drivers/char/ipmi/bt-bmc.c | 82
rebooting and powering down the host.
>
> Signed-off-by: Andrew Jeffery <and...@aj.id.au>
It would be nice to have an example of the associated binding.
I did not see it. A part from that :
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
> ---
> drivers/char/ipmi/Kconfig
On 03/22/2017 03:01 PM, Joel Stanley wrote:
> The ast2500 SoCs contain the same IPMI BT device.
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
> ---
> Documentation/devicetree/bindings/ipmi/asp
On 03/23/2017 08:10 PM, Cyrille Pitchen wrote:
> Hi Cédic,
>
> Le 23/03/2017 à 16:13, Cédric Le Goater a écrit :
>> On 03/23/2017 12:33 AM, Cyrille Pitchen wrote:
>>> This patch changes the prototype of spi_nor_scan(): its 3rd parameter
>>> is replaced by a 'stru
On 03/23/2017 12:33 AM, Cyrille Pitchen wrote:
> This patch changes the prototype of spi_nor_scan(): its 3rd parameter
> is replaced by a 'struct spi_nor_hwcaps' pointer, which tells the spi-nor
> framework about the actual hardware capabilities supported by the SPI
> controller and its driver.
>
htonl was used instead of ntohl. Surely a typo.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
net/ncsi/ncsi-rsp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/net/ncsi/ncsi-rsp.c b/net/ncsi/ncsi-rsp.c
index 087db775b3dc..d375286b79f2 100644
--- a/net/ncsi/ncsi
Hello Shilpasri,
On 04/21/2017 06:31 AM, Shilpasri G Bhat wrote:
> Add support for adding min/max values for the inband sensors copied by
> OCC to main memory. And also add current(mA) sensors to the list.
>
> Signed-off-by: Shilpasri G Bhat
> ---
>
On 04/18/2017 02:06 AM, Gavin Shan wrote:
> On Mon, Apr 17, 2017 at 01:36:19PM -0400, David Miller wrote:
>> From: Cédric Le Goater <c...@kaod.org>
>> Date: Fri, 14 Apr 2017 10:56:37 +0200
>>
>>> htonl was used instead of ntohl. Surely a typo.
>>>
>&
On 08/16/2017 08:59 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2017-08-16 at 08:53 +0200, Cédric Le Goater wrote:
>>>> divisor = DIV_ROUND_UP(bus->parent_clk_frequency,
>>>> bus->bus_frequency);
>>>> - clk_reg_val = bus->get_clk_re
On 08/16/2017 08:49 AM, Joel Stanley wrote:
> On Tue, Aug 15, 2017 at 4:51 PM, Andrew Jeffery wrote:
>> In addition to the base, low and high clock configuration, the AC timing
>> register #1 on the AST2400 houses fields controlling:
>>
>> 1. tBUF: Minimum delay between Stop and
On 08/10/2017 04:31 AM, Jeremy Kerr wrote:
> Hi Brendan,
>
>> The driver was handling interaction with userspace on its own. This
>> patch changes it to use the functionality of the ipmi_bmc framework
>> instead.
>>
>> Note that this removes the ability for the BMC to set SMS_ATN by making
>> an
On 04/22/2017 08:11 AM, Michael Ellerman wrote:
> Shilpasri G Bhat <shilpa.b...@linux.vnet.ibm.com> writes:
>> On 04/21/2017 05:17 PM, Cédric Le Goater wrote:
>>> On 04/21/2017 06:31 AM, Shilpasri G Bhat wrote:
>>>> diff --git a/drivers/hwmon/ibmpowernv.c b/d
...
> + sdata[count].id = sensor_id;
> + sdata[count].type = type;
> + sdata[count].hwmon_index = sdata[count - 1].hwmon_index;
> + create_hwmon_attr([count], attr_name,
> +
On 04/25/2017 04:28 PM, Cédric Le Goater wrote:
> On 04/22/2017 08:11 AM, Michael Ellerman wrote:
>> Shilpasri G Bhat <shilpa.b...@linux.vnet.ibm.com> writes:
>>> On 04/21/2017 05:17 PM, Cédric Le Goater wrote:
>>>> On 04/21/2017 06:31 AM, Shilpasri G Bhat wro
Hello Brendan,
[ ... ]
> +static bool aspeed_i2c_master_irq(struct aspeed_i2c_bus *bus)
> +{
> + u32 irq_status, status_ack = 0, command = 0;
> + struct i2c_msg *msg;
> + u8 recv_byte;
> +
> + spin_lock(>lock);
> + irq_status = readl(bus->base + ASPEED_I2C_INTR_STS_REG);
> +
On 06/20/2017 09:15 AM, Shilpasri G Bhat wrote:
>
>
> On 06/20/2017 11:36 AM, Cédric Le Goater wrote:
>> On 06/20/2017 07:08 AM, Shilpasri G Bhat wrote:
>>> From: Cédric Le Goater <c...@kaod.org>
>>>
>>> Today, the type of a PowerNV sensor system
On 06/20/2017 07:08 AM, Shilpasri G Bhat wrote:
> From: Cédric Le Goater <c...@kaod.org>
>
> Today, the type of a PowerNV sensor system is determined with the
> "compatible" property for legacy Firmwares and with the "sensor-type"
> for newer ones. The sam
On 06/20/2017 07:08 AM, Shilpasri G Bhat wrote:
> This patch exports current(A) sensors in inband sensors copied to
> main memory by OCC.
>
> Signed-off-by: Shilpasri G Bhat <shilpa.b...@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
hy you are doing that but that is the old (cr?@#!y) way to
define sensor types. we should try to improve thing a little more
and use the "sensor-type" property only.
I think the patch below should help you adding new types without
too much changes to your skiboot patchset. Could
>> As an aside, we have a pretty decent model for the Aspeed SoCs in
>> Qemu. If you want to use it to smoketest your rework:
>>
>> $ qemu-system-arm -m 512 -M ast2500-evb -nodefaults -nographic
>> -serial stdio -kernel arch/arm/boot/zImage -dtb
>> arch/arm/boot/dts/aspeed-ast2500-evb.dtb
>>
>> I
On 05/18/2017 10:20 PM, Linus Walleij wrote:
> On Thu, May 18, 2017 at 2:43 PM, Linus Walleij
> wrote:
>> On Thu, May 18, 2017 at 9:22 AM, Joel Stanley wrote:
>>> On Wed, May 17, 2017 at 10:05 PM, Linus Walleij
>>> wrote:
On 05/18/2017 11:09 PM, Cédric Le Goater wrote:
> On 05/18/2017 10:20 PM, Linus Walleij wrote:
>> On Thu, May 18, 2017 at 2:43 PM, Linus Walleij <linus.wall...@linaro.org>
>> wrote:
>>> On Thu, May 18, 2017 at 9:22 AM, Joel Stanley <j...@jms.id.au> wrote:
&
On 10/17/2017 09:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
> Dear all,
>
> I'm working on an iMX6 based board with a PCA9555 which is used both to drive
> LEDs and manage some GPIOs.
The PCA9555 chip and the PCA955[0-3] chips have different control
registers. You need a different led
On 10/17/2017 10:20 AM, Andrea Scian - DAVE Embedded Systems wrote:
>
> Il 17/10/2017 10:18, Cédric Le Goater ha scritto:
>> On 10/17/2017 09:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
>>> Dear all,
>>>
>>> I'm working on an iMX6 based board with a P
VALIDATE_DESC(desc);
> if (test_bit(FLAG_ACTIVE_LOW, >flags))
>value = !value;
> else
>value = !!value;
> return _gpiod_direction_output_raw(desc, value);
> }
>
On 09/04/2017 10:53 AM, Stephen Rothwell wrote:
> Hi all,
>
> After merging the powerpc tree, today's linux-next build (powerpc
> allyesconfig) produced this warning:
>
> WARNING: vmlinux.o(.text+0xa7cb8): Section mismatch in reference from the
> function .xive_spapr_init() to the function
On 10/17/2017 11:16 AM, Andrea Scian - DAVE Embedded Systems wrote:
>
>> On 10/17/2017 10:20 AM, Andrea Scian - DAVE Embedded Systems wrote:
>>>
>>> Il 17/10/2017 10:18, Cédric Le Goater ha scritto:
>>>> On 10/17/2017 09:36 AM, Andrea Scian - DAVE
tions.
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-opp-rom
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> In preperation for adding more boards.
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
> arch/arm/boot/dts/Makefile | 7 ---
> 1 file changed, 4 insertions(+),
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
> arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
> 2 files changed, 5 insertions(+)
d,ast2500-lpc-snoop";
it should be :
aspeed,ast2400-lpc-snoop
a part from that :
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> + reg = <0x0 0x80>;
> +
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
> arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
> 2 files changed, 5 insertions(+)
reg = <0x0 0x80>;
> + status = "disabled";
> + };
> +
> + lhc: lhc@20 {
> +
Some comments below,
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> - Fix incorrect RAM size
> - Remove alias; these are now specified in the dtsi
> - Add newly upstreamed devices
> - Include OpenBMC flash layout
>
> Signed-off-by: Joel Stanley
> ---
>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> The OpenBMC flash layout is used by Palmetto systems.
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 1 +
>
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> We don't require it for any of the ASPEED systems.
Reviewed-by: Cédric Le Goater <c...@kaod.org>
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 1 -
> arch/arm/boot/dts/a
On 12/15/2017 06:33 AM, Joel Stanley wrote:
> This should have always been 8.
>
> Fixes: db4d6d9d80fa ("ARM: dts: aspeed: Correctly order UART nodes")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goat
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> This is a layout used by OpenBMC systems. It describes the fixed flash
> layout of a 32MB mtd device.
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
> ---
> a
On 12/20/2017 04:23 AM, Joel Stanley wrote:
> - Fix incorrect RAM size
> - Remove alias; these are now specified in the dtsi
> - Add newly upstreamed devices
> - Include OpenBMC flash layout
>
> Signed-off-by: Joel Stanley <j...@jms.id.au>
Reviewed-by: Cédric
On 10/25/2017 12:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
>
> Il 24/10/2017 07:51, Cédric Le Goater ha scritto:
>> On 10/17/2017 11:16 AM, Andrea Scian - DAVE Embedded Systems wrote:
>>>
>>>> On 10/17/2017 10:20 AM, Andrea Scian - DAVE Embedded Systems
gt; extern inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
> ^
>
> Signed-off-by: Mathieu Malaterre <ma...@debian.org>
Reviewed-by: Cédric Le Goater <c...@kaod.org>
Thanks,
C.
> ---
> arch/powerpc/include/asm/xive.h | 2 +-
On 12/19/2017 04:05 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2017-12-18 at 16:21 +0100, Frederic Barrat wrote:
>> Add user APIs through ioctl to allocate, free, and be notified of an
>> AFU interrupt.
>>
>> For opencapi, an AFU can trigger an interrupt on the host by sending a
>> specific
with the I2C aspeed driver. I can not find
the thread anymore but we had to move up the ack of the interrupts.
QEMU tends to be much faster to fire interrupts than real HW.
> conditions (because additional interrupts may have arrived while handling
> the existing interrupts, or bec
On 09/12/2018 10:30 PM, Guenter Roeck wrote:
> On Wed, Sep 12, 2018 at 01:10:45PM -0700, Jae Hyun Yoo wrote:
>> On 9/12/2018 12:58 PM, Guenter Roeck wrote:
>>> On Wed, Sep 12, 2018 at 09:54:51AM -0700, Jae Hyun Yoo wrote:
On 9/11/2018 6:34 PM, Guenter Roeck wrote:
> On Tue, Sep 11, 2018
On 09/12/2018 06:54 PM, Jae Hyun Yoo wrote:
> On 9/11/2018 6:34 PM, Guenter Roeck wrote:
>> On Tue, Sep 11, 2018 at 04:58:44PM -0700, Jae Hyun Yoo wrote:
>>> On 9/11/2018 4:33 PM, Guenter Roeck wrote:
Looking into the patch, clearing the interrupt status at the end of an
interrupt
>>> That seems to suggest that none of the status bits auto-clears, and that
>>> the above code clearing intr_status should be removed entirely.
>>> Am I missing something ?
>>
>> You are right. I just pushed another version of the previous patch with this
>> new hunk :
>>
>> @@ -188,7 +200,6 @@
On 09/11/2018 08:37 PM, Guenter Roeck wrote:
> Hi,
>
> On Thu, Aug 23, 2018 at 03:57:31PM -0700, Jae Hyun Yoo wrote:
>> In most of cases, interrupt bits are set one by one but there are
>> also a lot of other cases that Aspeed I2C IP sends multiple
>> interrupt bits with combining master and
Hello !
On 09/13/2018 06:31 PM, Jae Hyun Yoo wrote:
> Hi Cédric,
>
> On 9/12/2018 10:47 PM, Cédric Le Goater wrote:
>> On 09/12/2018 06:54 PM, Jae Hyun Yoo wrote:
>>> On 9/11/2018 6:34 PM, Guenter Roeck wrote:
>>>> On Tue, Sep 11, 2018 at 04:58:44PM -0700, Ja
On 09/13/2018 05:57 PM, Guenter Roeck wrote:
> On Thu, Sep 13, 2018 at 05:48:59PM +0200, Cédric Le Goater wrote:
>> On 09/13/2018 03:33 PM, Guenter Roeck wrote:
> [ ... ]
>>>>> /*
>>>>> * The state machine needs some refinement. It is only used
On 09/13/2018 03:33 PM, Guenter Roeck wrote:
> On 09/12/2018 10:45 PM, Cédric Le Goater wrote
>
> [ ... ]
>
>>> ---
>>> qemu:
>>>
>>> diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c
>>> index c762c73..0d4aa08 100644
>>> ---
On 10/17/2017 10:20 AM, Andrea Scian - DAVE Embedded Systems wrote:
>
> Il 17/10/2017 10:18, Cédric Le Goater ha scritto:
>> On 10/17/2017 09:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
>>> Dear all,
>>>
>>> I'm working on an iMX6 based board with a P
On 10/17/2017 09:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
> Dear all,
>
> I'm working on an iMX6 based board with a PCA9555 which is used both to drive
> LEDs and manage some GPIOs.
The PCA9555 chip and the PCA955[0-3] chips have different control
registers. You need a different led
On 12/20/2017 04:23 AM, Joel Stanley wrote:
> - Fix incorrect RAM size
> - Remove alias; these are now specified in the dtsi
> - Add newly upstreamed devices
> - Include OpenBMC flash layout
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> v3
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> In preperation for adding more boards.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> arch/arm/boot/dts/Makefile | 7 ---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/arch
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
> arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dt
tions.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> arch/arm/boot/dts/aspeed-ast2500-evb.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 2 +-
> arch/arm/boot/dts/aspeed-bmc-opp-romulus.dts | 2 +-
> arch/arm/boot/dts/aspeed-g4.dt
t;;
it should be :
aspeed,ast2400-lpc-snoop
a part from that :
Reviewed-by: Cédric Le Goater
> + reg = <0x0 0x80>;
> +
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> The OpenBMC flash layout is used by Palmetto systems.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> arch/arm/boot/dts/aspeed-bmc-opp-palmetto.dts | 1 +
> 1 file changed, 1 insertion(+)
>
> di
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> We don't require it for any of the ASPEED systems.
Reviewed-by: Cédric Le Goater
>
> Signed-off-by: Joel Stanley
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 1 -
> arch/arm/boot/dts/aspeed-g5.dtsi | 1 -
> 2 files
On 12/15/2017 06:33 AM, Joel Stanley wrote:
> This should have always been 8.
>
> Fixes: db4d6d9d80fa ("ARM: dts: aspeed: Correctly order UART nodes")
> Cc: sta...@vger.kernel.org
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> ARM maint
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> This is a layout used by OpenBMC systems. It describes the fixed flash
> layout of a 32MB mtd device.
>
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> arch/arm/boot/dts/openbmc-flas
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> Signed-off-by: Joel Stanley
Reviewed-by: Cédric Le Goater
> ---
> arch/arm/boot/dts/aspeed-g4.dtsi | 2 ++
> arch/arm/boot/dts/aspeed-g5.dtsi | 3 +++
> 2 files changed, 5 insertions(+)
>
> diff --git a/arch/arm/boot/dt
status = "disabled";
> + };
> +
> + lhc: lhc@20 {
> +
Some comments below,
On 12/15/2017 07:24 AM, Joel Stanley wrote:
> - Fix incorrect RAM size
> - Remove alias; these are now specified in the dtsi
> - Add newly upstreamed devices
> - Include OpenBMC flash layout
>
> Signed-off-by: Joel Stanley
> ---
>
On 08/10/2017 04:31 AM, Jeremy Kerr wrote:
> Hi Brendan,
>
>> The driver was handling interaction with userspace on its own. This
>> patch changes it to use the functionality of the ipmi_bmc framework
>> instead.
>>
>> Note that this removes the ability for the BMC to set SMS_ATN by making
>> an
VALIDATE_DESC(desc);
> if (test_bit(FLAG_ACTIVE_LOW, >flags))
>value = !value;
> else
>value = !!value;
> return _gpiod_direction_output_raw(desc, value);
>
On 09/04/2017 10:53 AM, Stephen Rothwell wrote:
> Hi all,
>
> After merging the powerpc tree, today's linux-next build (powerpc
> allyesconfig) produced this warning:
>
> WARNING: vmlinux.o(.text+0xa7cb8): Section mismatch in reference from the
> function .xive_spapr_init() to the function
On 08/16/2017 08:59 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2017-08-16 at 08:53 +0200, Cédric Le Goater wrote:
>>>> divisor = DIV_ROUND_UP(bus->parent_clk_frequency,
>>>> bus->bus_frequency);
>>>> - clk_reg_val = bus->get_clk_re
On 08/16/2017 08:49 AM, Joel Stanley wrote:
> On Tue, Aug 15, 2017 at 4:51 PM, Andrew Jeffery wrote:
>> In addition to the base, low and high clock configuration, the AC timing
>> register #1 on the AST2400 houses fields controlling:
>>
>> 1. tBUF: Minimum delay between Stop and Start conditions
gt; extern inline int xive_smp_prepare_cpu(unsigned int cpu) { return -EINVAL; }
> ^
>
> Signed-off-by: Mathieu Malaterre
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> arch/powerpc/include/asm/xive.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deleti
anks Bert!
Yes. I was starting to add bfpt-fixups for all chips we use on Aspeed
based system.
Reviewed-by: Cédric Le Goater
Tested-by: Cédric Le Goater
Thanks,
C.
> Cheers,
>
> Joel
>
>> ---
>> drivers/mtd/spi-nor/core.c | 8 +---
>> 1 file change
On 9/19/20 3:29 AM, Qinglang Miao wrote:
> Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
>
> Signed-off-by: Qinglang Miao
Reviewed-by: Cédric Le Goater
> ---
> v2: based on linux-next(20200917), and can be applied to
> mainline cleanly now.
>
s in the Linux interrupt number space but these are never
> removed.
>
> This problem can be fixed by adding the corresponding unmap operation when
> the device is removed. There's no pcibios_* hook for the remove case, but
> the same effect can be achieved using a bus notifier.
>
>
ng. Except (at least) PPC/pseries
> which needs https://lkml.org/lkml/2020/10/27/259
>
> Cc: Cédric Le Goater
> Cc: Marc Zyngier
> Cc: Michael Ellerman
> Cc: Qian Cai
> Cc: Rob Herring
> Cc: Frederic Barrat
> Cc: Michal Suchánek
> Cc: Thomas Gleixner
> Sig
place.
>
> Fix kvmppc_xive_vcpu_id_valid() so that it checks the packed
> vCPU id is below xive->nr_servers, which is explicitly what we
> want.
>
> Fixes: 062cfab7069f ("KVM: PPC: Book3S HV: XIVE: Make VP block size
> configurable")
> Cc: sta...@vger.kernel.org
On 11/24/20 7:17 AM, Alexey Kardashevskiy wrote:
> __irq_domain_alloc_irqs() can already handle virq==-1 and free
> descriptors if it failed allocating hardware interrupts so let's skip
> this extra step.
>
> Signed-off-by: Alexey Kardashevskiy
LGTM,
Reviewed-by: Cédric Le G
Hello,
On 7/8/20 5:24 PM, Christoph Hellwig wrote:
> Use the DMA API bypass mechanism for direct window mappings. This uses
> common code and speed up the direct mapping case by avoiding indirect
> calls just when not using dma ops at all. It also fixes a problem where
> the sync_* methods were
On 8/31/20 8:40 AM, Christoph Hellwig wrote:
> On Sun, Aug 30, 2020 at 11:04:21AM +0200, Cédric Le Goater wrote:
>> Hello,
>>
>> On 7/8/20 5:24 PM, Christoph Hellwig wrote:
>>> Use the DMA API bypass mechanism for direct window mappings. This uses
>>> comm
On 9/24/20 7:11 AM, Alexey Kardashevskiy wrote:
>
>
> On 23/09/2020 17:06, Cédric Le Goater wrote:
>> On 9/23/20 2:33 AM, Qian Cai wrote:
>>> On Fri, 2020-08-07 at 12:18 +0200, Cédric Le Goater wrote:
>>>> When a passthrough IO adapter is removed from a
Hello Chin-Ting,
Thanks for this driver. It's much cleaner than the previous and we should
try adding support for the AST2500 SoC also. I guess we can keep the old
driver for the AST2400 which has a different register layout.
On the patchset, I think we should split this patch in three :
-
On 9/23/20 2:33 AM, Qian Cai wrote:
> On Fri, 2020-08-07 at 12:18 +0200, Cédric Le Goater wrote:
>> When a passthrough IO adapter is removed from a pseries machine using
>> hash MMU and the XIVE interrupt mode, the POWER hypervisor expects the
>> guest OS to clear all page
On 10/14/20 4:55 AM, Alexey Kardashevskiy wrote:
>
>
> On 23/09/2020 17:06, Cédric Le Goater wrote:
>> On 9/23/20 2:33 AM, Qian Cai wrote:
>>> On Fri, 2020-08-07 at 12:18 +0200, Cédric Le Goater wrote:
>>>> When a passthrough IO adapter is removed from a
On 1/26/21 5:54 AM, Nicholas Piggin wrote:
> iounmap will remove ptes.
>
> Cc: "Cédric Le Goater"
> Cc: linuxppc-...@lists.ozlabs.org
> Signed-off-by: Nicholas Piggin
Looks good.
Acked-by: Cédric Le Goater
Thanks,
C.
> ---
> arch/powerpc/sysdev/xive/comm
round anyway to support older skiboots already
> on the field.
>
> Internally convert 0x to OPAL_RESOURCE which is the usual error
> returned upon resource exhaustion.
>
> Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Thanks,
C.
> ---
> arch/powerpc/sysdev/xiv
round anyway to support older skiboots already
> in the field.
>
> Internally convert 0x to OPAL_RESOURCE which is the usual error
> returned upon resource exhaustion.
>
> Cc: sta...@vger.kernel.org # v4.12+
> Signed-off-by: Greg Kurz
Reviewed-by: Cédric Le Goater
Thanks,
On 12/19/2017 04:05 AM, Benjamin Herrenschmidt wrote:
> On Mon, 2017-12-18 at 16:21 +0100, Frederic Barrat wrote:
>> Add user APIs through ioctl to allocate, free, and be notified of an
>> AFU interrupt.
>>
>> For opencapi, an AFU can trigger an interrupt on the host by sending a
>> specific
On 10/17/2017 11:16 AM, Andrea Scian - DAVE Embedded Systems wrote:
>
>> On 10/17/2017 10:20 AM, Andrea Scian - DAVE Embedded Systems wrote:
>>>
>>> Il 17/10/2017 10:18, Cédric Le Goater ha scritto:
>>>> On 10/17/2017 09:36 AM, Andrea Scian - DAVE
On 10/25/2017 12:36 AM, Andrea Scian - DAVE Embedded Systems wrote:
>
> Il 24/10/2017 07:51, Cédric Le Goater ha scritto:
>> On 10/17/2017 11:16 AM, Andrea Scian - DAVE Embedded Systems wrote:
>>>
>>>> On 10/17/2017 10:20 AM, Andrea Scian - DAVE Embedded Systems
On 01/08/2019 10:32, Christophe JAILLET wrote:
> There is no need to use GFP_ATOMIC here. GFP_KERNEL should be enough.
> GFP_KERNEL is also already used for another allocation just a few lines
> below.
This is correct.
> Signed-off-by: Christophe JAILLET
Reviewed-by: Cédr
On 01/08/2019 13:09, Christophe JAILLET wrote:
> 'xive_irq_bitmap_add()' can return -ENOMEM.
> In this case, we should free the memory already allocated and return
> 'false' to the caller.
>
> Also add an error path which undoes the 'tima = ioremap(...)'
>
> Signed-off-by: Christophe JAILLET
>
Hello Christoph,
On 25/06/2019 10:15, Christoph Hellwig wrote:
> This function has never been used anywhere in the kernel tree since it
> was added to the tree. We also now have proper PCIe P2P APIs in the core
> kernel, and any new P2P support should be using those.
>
> Signed-off-by:
o not do
> this.
yes. Looks good to me.
Reviewed-by: Cédric Le Goater
Thanks,
C.
> -corey
>
>>
>> Signed-off-by: YueHaibing
>> ---
>> drivers/char/ipmi/bt-bmc.c | 4 +---
>> 1 file changed, 1 insertion(+), 3 deletions(-)
>>
>> diff --git a/
On 5/2/19 4:35 AM, Alexey Kardashevskiy wrote:
>
>
> On 02/05/2019 00:42, Colin Ian King wrote:
>> Hi,
>>
>> Static analysis with Coverity picked up an issue in the following commit:
>>
>> commit 2bde9b3ec8bdf60788e9e2ce8c07a2f8d6003dbd
>> Author: Céd
during CAS, and ignore xive=off if the hypervisor only supports
> XIVE.
>
> Fixes: eac1e731b59e ("powerpc/xive: guest exploitation of the XIVE interrupt
> controller")
> Cc: sta...@vger.kernel.org # v4.20
> Reported-by: Pavithra R. Prakash
> Signed-off-by: Greg Kurz
On 09/11/2018 08:37 PM, Guenter Roeck wrote:
> Hi,
>
> On Thu, Aug 23, 2018 at 03:57:31PM -0700, Jae Hyun Yoo wrote:
>> In most of cases, interrupt bits are set one by one but there are
>> also a lot of other cases that Aspeed I2C IP sends multiple
>> interrupt bits with combining master and
with the I2C aspeed driver. I can not find
the thread anymore but we had to move up the ack of the interrupts.
QEMU tends to be much faster to fire interrupts than real HW.
> conditions (because additional interrupts may have arrived while handling
> the existing interrupts, or bec
On 09/12/2018 10:30 PM, Guenter Roeck wrote:
> On Wed, Sep 12, 2018 at 01:10:45PM -0700, Jae Hyun Yoo wrote:
>> On 9/12/2018 12:58 PM, Guenter Roeck wrote:
>>> On Wed, Sep 12, 2018 at 09:54:51AM -0700, Jae Hyun Yoo wrote:
On 9/11/2018 6:34 PM, Guenter Roeck wrote:
> On Tue, Sep 11, 2018
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