the source directory without needing to add CFLAGS for
the sources that happen to include linux/libfdt.h.
Signed-off-by: Chris Packham chris.pack...@alliedtelesis.co.nz
---
Hi,
This probably should come via git://git.jdl.com/software/dtc.git however
this appears to be inaccessible at the moment
On Thu, 29 Jan 2015, Grant Likely wrote:
On Tue, 16 Dec 2014 15:13:24 +1300
, Chris Packham chris.pack...@alliedtelesis.co.nz
wrote:
Currently in arch and driver code that needs early access to the
flattened device tree it is necessary to add specific CFLAGS so that
when scripts/dtc/libfdt
Hi Florian,
On 07/31/2015 01:51 PM, Florian Fainelli wrote:
On 30/07/15 15:51, David Miller wrote:
From: David Miller da...@davemloft.net
Date: Thu, 30 Jul 2015 14:19:35 -0700 (PDT)
This looks fine, series applied, thanks.
I think your control block is too large, you'll need to rework this
as per the CPU datasheet.
Signed-off-by: Chris Packham judge.pack...@gmail.com
---
This has come up via u-boot[1] which sync's asm/mipsregs.h with the
kernel. In u-boots case the value read from read_c0_count() is assigned
to an unsigned long [2] which triggers a sign extension and causes a
bug.
U
The assignment of rth->dst.output in vrf_rt6_create() and
vrf_rtable_create() used a hard tab before the '='. The neighboring
assignments did not. Make the assignment of rth->dst.output consistent
with the surrounding code.
Signed-off-by: Chris Packham <chris.pack...@alliedtele
The Marvell 98DX1135 is a switch chip with an integrated CPU,
similar to the MV98DX4122. From a pinctrl point of view the only
difference is that NF_REN, NF_WEN, NF_ALE and NF_CEN lines are
MPP pins instead of dedicated ones.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co
The l2-cache controller on the T2080 SoC has similar capabilities to the
others already supported by the mpc85xx_edac driver. Add it to the list
of compatible devices.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Johannes Thumshirn <j...@k
On 02/02/17 12:28, Borislav Petkov wrote:
> On Thu, Feb 02, 2017 at 12:16:24PM +1300, Chris Packham wrote:
>> The l2-cache controller on the T2080 SoC has similar capabilities to the
>> others already supported by the mpc85xx_edac driver. Add it to the list
>> of compatible
On 03/02/17 12:55, Michael Ellerman wrote:
> Chris if you want to send a patch to add the compatible string to the
> l2cache.txt I would merge that, but honestly it doesn't achieve much
> other than possibly catching a typo in the compatible name.
I think catching a typo might be worthwhile. It's
Rather than having a separate node for the dfx server add a reg property
to the parent node. This give somes compatibility with the Marvell
supplied SDK.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Documentation/devicetree/bindings/net/marvell,prestera.tx
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.
Signed-off-by: Chr
don't have to disable nodes for blocks that only exist on
the Armada-XP.
Patch 3/4 and 4/4 are ported from the Marvell Linux kernel. I've tested
them on the hardware I have access to and things look pretty good.
Chris Packham (4):
ARM: dts: armada-xp-98dx3236: combine dfx server nodes
ARM: dts
The DFX server on the 98dx3236 and compatible SoCs has an ID register
that provides revision information that the PCI based ID register
doesn't have. Use this if it's available.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
.../bindings/arm/marvell/mv98dx3236-soc-
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.
Signed-off-by: Chr
As was done with Armada XP, add node labels to Armada 38x common and SoC
specific nodes to make them easier to reference in board device trees.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
arch/arm/boot/dts/armada-385.dtsi | 20 +---
arch/arm/bo
On 07/02/17 14:13, Chris Packham wrote:
> On 07/02/17 14:03, Stephen Boyd wrote:
>> On 02/06, Chris Packham wrote:
>>> On 07/02/17 12:14, Stephen Boyd wrote:
>>>> On 02/03, Chris Packham wrote:
>>>>> The initial implementation in commit e120c17a70e5
On 07/02/17 14:03, Stephen Boyd wrote:
> On 02/06, Chris Packham wrote:
>> On 07/02/17 12:14, Stephen Boyd wrote:
>>> On 02/03, Chris Packham wrote:
>>>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>>>> for 98DX3236
On 07/02/17 14:25, Chris Packham wrote:
> On 07/02/17 14:13, Chris Packham wrote:
>> On 07/02/17 14:03, Stephen Boyd wrote:
>>> On 02/06, Chris Packham wrote:
>>>> On 07/02/17 12:14, Stephen Boyd wrote:
>>>>> On 02/03, Chris Packham wrote:
>>>
On 07/02/17 12:14, Stephen Boyd wrote:
> On 02/03, Chris Packham wrote:
>> The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
>> for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
>> Port code from the Marvell supplied Li
need to use the coreclk label on a different node. It
also means I don't have to disable nodes for blocks that only exist on
the Armada-XP.
Patch 4/6, 5/6 and 6/6 are ported from the Marvell Linux kernel. I've tested
them on the hardware I have access to and things look pretty good.
Chris Packham (6
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.
Signed-off-by: Chr
This moves the coreclk binding for the 98dx3236 SoC to the DFX block
where the sampled at reset register is located and switches to using the
correct gating clock compatible string.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- New.
The initial implementation in commit e120c17a70e5 ("clk: mvebu: support
for 98DX3236 SoC") hardcoded a fixed value for the main PLL frequency.
Port code from the Marvell supplied Linux kernel to support different
PLL frequencies and provide clock gating support.
Signed-off-by: Chr
Rather than having a separate node for the dfx server add a reg property
to the parent node. This give somes compatibility with the Marvell
supplied SDK.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- none
Documentation/devicetree/bi
The compatible should be 98dx4251 not 98dx4521.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2
- new
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/arm
The DFX server on the 98dx3236 and compatible SoCs has an ID register
that provides revision information that the PCI based ID register
doesn't have. Use this if it's available.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
On 08/02/17 23:53, Arnd Bergmann wrote:
> On Tuesday, February 7, 2017 3:07:37 AM CET Chris Packham wrote:
>>>
>>> Actually I wonder if I can try a bit harder to keep a system booting.
>>> The following might work
>>> 1) add the compatible strings to t
List all the current valid compatible strings for the l2cache binding.
This should stop checkpatch.pl from complaining and will hopefully save
someone from having to debug a typo in their dts.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
.../devicetree/bindings/p
On 21/01/17 13:48, Stephen Boyd wrote:
> On 01/13, Chris Packham wrote:
>> @@ -158,6 +170,14 @@ static const struct coreclk_soc_desc axp_coreclks = {
>> .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
>> };
>>
>> +static const struct cor
On 20/01/17 10:10, Chris Packham wrote:
> On 19/01/17 23:03, Russell King - ARM Linux wrote:
>> On Fri, Jan 13, 2017 at 10:12:18PM +1300, Chris Packham wrote:
>>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
>>> + MPP_FUNC_CTRL(0, 3
On 27/01/17 04:10, Gregory CLEMENT wrote:
> Hi Chris,
>
> On ven., janv. 06 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz>
> wrote:
>
>> The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
>> with integrated CPUs. They are simil
On 27/01/17 04:10, Gregory CLEMENT wrote:
>> +internal-regs {
[snip]
>> +
>> +dfx-registers {
> node label
>
[snip]
>> +switch {
> node label
>
These are peers to the internal-regs, i.e. parts of the SoC with
mappable windows in the address space. Do they
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
package as the switch.
I've rebased this series against linux-pinctrl/devel to get access to
mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to v4.10.0-rc5.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
Changes in v2:
- Update devicetree binding documentation for new
tree if it is set in the machine definition.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
C
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v5:
- update license text
- use node labels
arch/arm/boot/dts/db-dxbc2.dts
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz
Hi Gregory,
On 31/01/17 03:29, Gregory CLEMENT wrote:
> Hi Chris,
>
> On lun., janv. 30 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz>
> wrote:
>
>> These boards are Marvell's evaluation boards for the 98DX4251 and
>> 98DX3336 SoCs.
>>
>
On 31/01/17 03:40, Gregory CLEMENT wrote:
> Hi Chris,
>
> The 5 patches should be available soon (if it is not already the case),
> in the linux-next branch.
>
> The clk patch is already there, the 3 arm patch have been merged in my
> mvebu/for-next branch, and the pinctrl patch is about to be
Change sequences of 8 spaces to hard-tabs.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
I think this crept in during review and I didn't notice. The file is new enough
that we shouldn't lose any useful history.
arch/arm/boot/dts/armada-xp-98dx3236.dts
On 28/01/17 07:47, Stephen Boyd wrote:
> On 01/27, Gregory CLEMENT wrote:
>> Hi all,
>>
>> On ven., janv. 27 2017, Chris Packham <chris.pack...@alliedtelesis.co.nz>
>> wrote:
>>
>>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs wi
package as the switch.
I've rebased this series against linux-pinctrl/devel to get access to
mvebu_mmio_mpp_ctrl. Everything else still applies cleanly to v4.10.0-rc5.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
Changes in v2:
- Update devicetree binding documentation for new
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris
tree if it is set in the machine definition.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
C
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v5:
- update license text
- use node labels
Changes in v6:
- Rename dts files to include 'armada-xp-'
On 27/01/17 09:24, Chris Packham wrote:
> On 27/01/17 04:10, Gregory CLEMENT wrote:
>>> + internal-regs {
>
> [snip]
>
>>> +
>>> + dfx-registers {
>> node label
>>
>
> [snip]
>
>>> + switch {
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Documentation/hwmon/tc654 | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/hwmon/tc654 b/Documentation/hwmon/tc654
index 91a2843f5f98..47636a8077b4 100644
--- a/Documentation/hwmon/tc654
On 18/02/17 05:17, Arnd Bergmann wrote:
> On Fri, Feb 17, 2017 at 5:22 AM, Chris Packham
> <chris.pack...@alliedtelesis.co.nz> wrote:
>> Hi Arnd,
>> On 17/02/17 02:28, Arnd Bergmann wrote:
>>> On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote:
&g
to retain a backwards compatible binding.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- none
Changes in v3:
- update commit message to indicate backwards incompatible change and
why it's OK
- retain dfx-server compatible
The compatible should be 98dx4251 not 98dx4521.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- new
Changes in v3:
- none
arch/arm/boot/dts/armada-xp-98dx4251.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
The DFX server on the 98dx3236 and compatible SoCs has an ID register
that provides revision information that the PCI based ID register
doesn't have. Use this if it's available.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- none
C
to the DFX block enables support for different clock
strapping options in hardware.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v2:
- New. Split out from "clk: mvebu: Expand mv98dx3236-core-clock support"
Changes in v3:
need to use the coreclk label on a different node. It
also means I don't have to disable nodes for blocks that only exist on
the Armada-XP.
Patch 4/6, 5/6 are split from the previous versions.
Patch 6/6 is the device tree portion of a change already in clk-next.
Chris Packham (6):
ARM: dts: Fix
The Marvell datasheets refer to the integrated CPU as "Armada-XP". In
reality there are a number of differences to the actual Armada-XP so
rather than including armada-xp.dtsi and disabling many of the IP
blocks. Include armada-370-xp.dtsi and add the required nodes.
Signed-off-by: Chr
The DFX server on the 98dx3236 and compatible SoCs has an ID register.
Add documentation and a binding for this.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Notes:
Changes in v3:
- new, split from driver
.../devicetree/bindings/arm/marvell/mv98dx3236-soc-
Hi Arnd,
On 17/02/17 02:28, Arnd Bergmann wrote:
> On Thursday, February 16, 2017 9:50:39 PM CET Chris Packham wrote:
>> The DFX server on the 98dx3236 and compatible SoCs has an ID register
>> that provides revision information that the PCI based ID register
>> doesn't h
On 19/01/17 11:25, Rob Herring wrote:
> On Fri, Jan 13, 2017 at 10:12:16PM +1300, Chris Packham wrote:
>> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
>> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>>
>> The clock
On 19/01/17 13:48, Stephen Boyd wrote:
> On 01/13, Chris Packham wrote:
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> index 46c742d3bd41..59be3ca0464f 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/pla
On 19/01/17 23:03, Russell King - ARM Linux wrote:
> On Fri, Jan 13, 2017 at 10:12:18PM +1300, Chris Packham wrote:
>> +static struct mvebu_mpp_ctrl mv98dx3236_mpp_controls[] = {
>> +MPP_FUNC_CTRL(0, 32, NULL, armada_xp_mpp_ctrl),
>> +};
>
> As Linus has ta
On 14/01/17 20:50, Chris Packham wrote:
> On 13/01/17 22:54, Sebastian Hesselbarth wrote:
>> On 13.01.2017 10:12, Chris Packham wrote:
>>> From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
>>>
>>> This pinctrl driver supports the 98DX3236, 9
On 20/01/17 12:19, Sebastian Hesselbarth wrote:
> On 19.01.2017 22:12, Chris Packham wrote:
>> On 14/01/17 20:50, Chris Packham wrote:
>>> On 13/01/17 22:54, Sebastian Hesselbarth wrote:
>>>> On 13.01.2017 10:12, Chris Packham wrote:
>>>>> From: Kalyan
Hi Guenter,
On 10/05/2016 11:10 AM, Guenter Roeck wrote:
> On Tue, Oct 04, 2016 at 09:09:10PM +0000, Chris Packham wrote:
>>
>>>
>>> Of course, all that doesn't solve the real problem in this driver, which is
>>> that it ignores error codes from the smbus fun
of a signed 16-bit value. When presenting this in sysfs the
value is shifted and scaled appropriately.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v2:
- Simplify as per feedback from Guenter.
- Re-word commit message.
drivers/hwmon/adm9240.c | 4 ++--
1 file c
On 10/05/2016 09:54 AM, Guenter Roeck wrote:
> On Tue, Oct 04, 2016 at 05:08:00PM +1300, Chris Packham wrote:
>> Unlike the temperature thresholds the temperature data is a 9-bit signed
>> value. This allows and additional 0.5 degrees of precision on the
>> reading but means
Unlike the temperature thresholds the temperature data is a 9-bit signed
value. This allows and additional 0.5 degrees of precision on the
reading but means we can't rely on sign-extension to handle negative
values.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
d
Add support for the tc654 and tc655 fan controllers from Microchip.
http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Hi Gunter,
I realise this isn't using the new hwmon registration API. This is
essen
Add support for the tc654 and tc655 fan controllers from Microchip.
http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v2:
- Add Documentation/hwmon/tc654
- Incorporate most of the review comment
On 10/07/2016 11:57 AM, Guenter Roeck wrote:
> On Fri, Oct 07, 2016 at 10:36:47AM +1300, Chris Packham wrote:
>> Add support for the tc654 and tc655 fan controllers from Microchip.
>>
>> http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf
>>
>> Signed-
Add pin control information for the NAND flash interface. This interface
is multiplexed with the device bus interface to the function is "dev"
not "nand" as one might expect.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
arch/arm/boot/dts/armada
Add support for the tc654 and tc655 fan controllers from Microchip.
http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v4:
- tab-align values in #defines
- ensure locking in set_pwm covers updating
On 10/11/2016 02:22 AM, Guenter Roeck wrote:
>> +if (val)
>> > + data->config |= TC654_REG_CONFIG_DUTYC;
>> > + else
>> > + data->config &= ~TC654_REG_CONFIG_DUTYC;
> I just realized that this won't work as intended. Problem is that you
> only fill data->config when reading
The actual frequency was updated in commit ae142bd99765 ("ARM: mvebu:
Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
comment was not updated. Update it now.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
arch/arm/boot/dts/armada-375.d
The l2-cache controller on the T2080 SoC has similar capabilities to the
others already supported by the mpc85xx_edac driver. Add it to the list
of compatible devices.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
arch/powerpc/boot/dts/fsl/t2081si-post.dtsi | 1 +
d
On 10/13/2016 02:03 AM, Guenter Roeck wrote:
> On Tue, Oct 11, 2016 at 10:26:31AM +1300, Chris Packham wrote:
>> > Add support for the tc654 and tc655 fan controllers from Microchip.
>> >
>> > http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf
>>
Hi Gunter,
Thanks for the review. v3 on it's way some responses below.
On 10/08/2016 07:29 AM, Guenter Roeck wrote:
> On Fri, Oct 07, 2016 at 02:38:44PM +1300, Chris Packham wrote:
>> Add support for the tc654 and tc655 fan controllers from Microchip.
>>
>> http://ww1.micro
Add support for the tc654 and tc655 fan controllers from Microchip.
http://ww1.microchip.com/downloads/en/DeviceDoc/20001734C.pdf
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v3:
- typofix in documentation
- add missing value to tc654_pwm_map, re-generate
On 13/01/17 22:54, Sebastian Hesselbarth wrote:
> On 13.01.2017 10:12, Chris Packham wrote:
>> From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
>>
>> This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
>> from Marvell.
>>
>>
On 12/01/17 09:56, Sebastian Hesselbarth wrote:
> On 01/11/2017 03:44 PM, Linus Walleij wrote:
>> On Fri, Jan 6, 2017 at 5:15 AM, Chris Packham
>> <chris.pack...@alliedtelesis.co.nz> wrote:
>>
>>> From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.n
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris
package as the switch.
This series is starting to settle down now. The only major change is in
"arm: mvebu: support for SMP on 98DX3336 SoC" the other changes are
generally cosmetic or collecting acks.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
Changes in v2:
- Update
tree if it is set in the machine definition.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
C
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
arch/arm/boot/dts/db-dxbc2.dts | 159
arch/arm/boot/dts/db-xc3-24g4xg.dts
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
Acked-by: Rob Herring <r...@kernel.org>
---
Notes:
On 06/01/17 19:44, Stephen Boyd wrote:
> On 01/06, Chris Packham wrote:
>> diff --git a/arch/arm/mach-mvebu/platsmp.c b/arch/arm/mach-mvebu/platsmp.c
>> index 46c742d3bd41..3c9ab9a008ad 100644
>> --- a/arch/arm/mach-mvebu/platsmp.c
>> +++ b/arch/arm/mach-mvebu/pla
On 06/01/17 02:10, Andrew Lunn wrote:
>> I'd love to see a switchdev driver but it's a huge task (and no I'm not
>> committing to writing it). As it stands Marvell ship a switch SDK
>> largely executes in userspace with a small kernel module providing some
>> linkage to the underlying hardware.
>
quot;, V_98DX4251),
MPP_VAR_FUNCTION(0x4, "dev", "ready0",
V_98DX3236_PLUS)),
MPP_MODE(10,
MPP_VAR_FUNCTION(0x0, "gpio", NULL,
V_98DX3236_PLUS),
+MPP_VAR_FUNCTION(0x2, "sd0", "d3&quo
On 05/01/17 17:46, Chris Packham wrote:
> On 05/01/17 17:04, Florian Fainelli wrote:
>> Le 01/04/17 à 19:36, Chris Packham a écrit :
>>> +}
>>> +
>>> +static int __init mv98dx3236_resume_init(void)
>>> +{
>>> + struct device_node
On 06/01/17 02:59, Mark Rutland wrote:
> On Thu, Jan 05, 2017 at 04:36:40PM +1300, Chris Packham wrote:
>> +internal-regs {
>> +coreclk: mvebu-sar@18230 {
>> +compatible = "mar
On 06/01/17 03:01, Mark Rutland wrote:
> On Thu, Jan 05, 2017 at 04:36:37PM +1300, Chris Packham wrote:
>> The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
>> the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
>>
>&g
From: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
This pinctrl driver supports the 98DX3236, 98DX3336 and 98DX4251 SoCs
from Marvell.
Signed-off-by: Kalyan Kinthada <kalyan.kinth...@alliedtelesis.co.nz>
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
The 98DX3236, 98DX3336, 98DX4521 and variants have a different TCLK from
the Armada XP (200MHz vs 250MHz). The CPU core clock is fixed at 800MHz.
The clock gating options are a subset of those on the Armada XP.
The core clock divider is different to the Armada XP also.
Signed-off-by: Chris
package as the switch.
Chris Packham (4):
clk: mvebu: support for 98DX3236 SoC
arm: mvebu: support for SMP on 98DX3336 SoC
arm: mvebu: Add device tree for 98DX3236 SoCs
arm: mvebu: Add device tree for db-dxbc2 and db-xc3-24g4xg boards
Kalyan Kinthada (1):
pinctrl: mvebu: pinctrl driver
tree if it is set in the machine definition.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v2:
- Document new enable-method value
- Correct some references from 98DX4521 to 98DX3236
Documentation/devicetree/bindings/arm/cpus.txt | 1 +
.../bindings/arm/m
On 05/01/17 17:07, Florian Fainelli wrote:
> Le 01/04/17 à 19:36, Chris Packham a écrit :
>> The 98DX3236, 98DX3336 and 98DX4251 are a set of switch ASICs with
>> integrated CPUs. They CPU block is common within these product lines and
>> (as far as I can tell/hav
The Marvell 98DX3236, 98DX3336, 98DX4521 and variants are switch ASICs
with integrated CPUs. They are similar to the Armada XP SoCs but have
different I/O interfaces.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Changes in v2:
- Update devicetree binding documen
These boards are Marvell's evaluation boards for the 98DX4251 and
98DX3336 SoCs.
Signed-off-by: Chris Packham <chris.pack...@alliedtelesis.co.nz>
---
Chaqnges in v2:
- None
arch/arm/boot/dts/db-dxbc2.dts | 159
arch/arm/boot/dts/db-xc3-24g4xg.dts
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