Hi Jonas,
On 07.10.2018 15:57, Jonas Danielsson wrote:
> From: Jonas Danielsson
>
> This fixes a bug where our embedded system (AT91SAM9260 based) would
> hang at reboot. At the most we managed 16 boot loops without a hang.
>
> With this patch applied the problem has not been observed and the
On 17.10.2018 15:17, Jonas Danielsson wrote:
> On Tue, Oct 16, 2018 at 4:52 PM Alexander Stein
> wrote:
>>
>> On Tuesday, October 16, 2018, 3:30:24 PM CEST claudiu.bez...@microchip.com
>> wrote:
>>> Hi Jonas,
>>>
>>> On 07.10.2018 15:57, Jonas Danielsson wrote:
From: Jonas Danielsson
This series implements PM functionality for act8945 and use that support
on sama5d2_xplained board.
Boris Brezillon (2):
regulator: act8945: Implement PM functionalities
ARM: dts: at91: sama5d2_xplained: Add proper regulator states for
suspend-to-mem
From: Boris Brezillon
The regulator supports a dedicated suspend mode.
Implement the appropriate ->set_suspend_xx() hooks, add support for
->set_mode(), and provide basic PM ops functionalities to setup the
regulator in a suspend state when the system is entering suspend.
We also implement the
From: Boris Brezillon
When entering suspend-to-mem, all PMIC outputs are disabled except
VDDIODDR which is put in power saving mode, and whose voltage is
increased (probably to counter the poor accuracy of power saving mode).
Signed-off-by: Boris Brezillon
[claudiu.bez...@microchip.com: use
Check at91_shdwc before continuing with probe since we want only one instance of
this driver. Inspired from commit 9f1e44774be5 ("power: reset: at91-poweroff:
do not procede if at91_shdwc is allocated").
Signed-off-by: Claudiu Beznea
---
drivers/power/reset/at91-poweroff.c | 3 +++
1 file
Move SHDWC realted data to only one structure to have them grouped.
Inspired from commit 9be74f0d39c1 ("power: reset: at91-poweroff: make
mpddrc_base part of struct shdwc").
Signed-off-by: Claudiu Beznea
---
drivers/power/reset/at91-poweroff.c | 60 +++--
1 file
Use only one poweroff function and adapt it to work for both scenarios
(with LPDDR or not). The assignement of pm_power_off was moved at the
end of probe after all initializations are OK. This patch adapt the idea
from commit 4e018c1e9b05 ("power: reset: at91-poweroff: use only one
poweroff
Hi,
This series includes cleanups for at91-poweroff.c similar to the one did for
SAMA5D2 Xplained SHDWC on series at [1].
Changes were tested on SAMA5D3 Xplained, SAMA5D4 Xplained and AT91SAM9G35-EK
boards.
Thank you,
Claudiu Beznea
[1] https://www.spinics.net/lists/arm-kernel/msg673559.html
Remove at91_ramc_of_match[] since it is not used anywhere in this code.
Signed-off-by: Claudiu Beznea
---
drivers/power/reset/at91-poweroff.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/drivers/power/reset/at91-poweroff.c
b/drivers/power/reset/at91-poweroff.c
index
On 19.10.2018 13:30, Jonas Danielsson wrote:
> On Wed, Oct 17, 2018 at 3:10 PM wrote:
>>
>>>
>>> We take the normal path of sys_reboot => kernel_restart => machine_restart
>>> ...
>>>
>>> I added code to print the c1 register in different paths. And I-cache
>>> is enabled.
>>> So now I am
Hi Alexandre,
On 06.11.2018 23:09, Alexandre Belloni wrote:
> Hi Claudiu,
>
> On 05/11/2018 11:14:26+, claudiu.bez...@microchip.com wrote:
>> static int __init at91_poweroff_probe(struct platform_device *pdev)
>> @@ -154,16 +160,22 @@ static int __init at91_poweroff_probe(struct
>>
On 07.11.2018 16:53, Mark Brown wrote:
> On Fri, Oct 26, 2018 at 04:19:48PM +, claudiu.bez...@microchip.com wrote:
>
>> +static unsigned int act8945a_of_map_mode(unsigned int mode)
>> +{
>> +if (mode == ACT8945A_DCDC_MODE_POWER_SAVING)
>> +return REGULATOR_MODE_STANDBY;
>>
Hi Sebastian,
On 06.12.2018 00:40, Sebastian Reichel wrote:
> Hi,
>
> On Wed, Nov 07, 2018 at 06:23:40PM +0100, Alexandre Belloni wrote:
>> On 07/11/2018 14:54:17+, claudiu.bez...@microchip.com wrote:
>>> Hi Alexandre,
>>>
>>> On 06.11.2018 23:09, Alexandre Belloni wrote:
Hi Claudiu,
On 28.11.2018 23:09, Brandon Streiff wrote:
> On 11/23/2018 3:59 AM, Harini Katakam wrote:
>> +/* Errata mask bits */
>> +#define MACB_ERRATA_RXLOCKUP0x0001
>> +
>> /* LSO settings */
>> #define MACB_LSO_UFO_ENABLE 0x01
>> #define
From: Claudiu Beznea
Move SHDWC realted data to only one structure to have them grouped.
Inspired from commit 9be74f0d39c1 ("power: reset: at91-poweroff: make
mpddrc_base part of struct shdwc").
Signed-off-by: Claudiu Beznea
---
Changes in v2:
- avoid allocate at91_shdwc and keep it static
From: Boris Brezillon
The regulator supports a dedicated suspend mode.
Implement the appropriate ->set_suspend_xx() hooks, add support for
->set_mode(), and provide basic PM ops functionalities to setup the
regulator in a suspend state when the system is entering suspend.
Signed-off-by: Boris
From: Claudiu Beznea
Implement shutdown method to make sure the PMIC will not enter the suspend
state when the system is shutdown.
This work is based on work done by Borris Brezillon on [1].
[1] https://www.spinics.net/lists/kernel/msg2942960.html
Signed-off-by: Claudiu Beznea
---
From: Boris Brezillon
When entering suspend-to-mem, all PMIC outputs are disabled except
VDDIODDR which is put in power saving mode, and whose voltage is
increased (probably to counter the poor accuracy of power saving mode).
Signed-off-by: Boris Brezillon
[claudiu.bez...@microchip.com: use
From: Claudiu Beznea
This series implements PM functionality for act8945a PMIC and use that support
on SAMA5D2 Xplained board.
Changes in v2:
- split patch 1/1 from previous series in 3 patches: one adding regmap,
one adding pm functionality, one adding shutdown functionality
- use dev_pm_ops
From: Claudiu Beznea
Fix line over 80 chars checkpatch.pl warning.
Signed-off-by: Claudiu Beznea
---
drivers/regulator/act8945a-regulator.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/regulator/act8945a-regulator.c
b/drivers/regulator/act8945a-regulator.c
From: Claudiu Beznea
Add documentation for regulator modes and suspend states.
Signed-off-by: Claudiu Beznea
---
.../bindings/regulator/act8945a-regulator.txt | 34 ++
1 file changed, 34 insertions(+)
diff --git
Hi Michael,
On 20.01.2021 21:43, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> If the MII interface is used, the PHY is the clock master, thus don't
> set the clock rate. On Zynq-7000, this will prevent the following
>
On 14.01.2021 12:25, Russell King - ARM Linux admin wrote:
>
> As I've said, if phylib/PHY driver is not restoring the state of the
> PHY on resume from suspend-to-ram, then that's an issue with phylib
> and/or the phy driver.
In the patch I proposed in this thread the restoring is done in PHY
Hi, Rafael, Pavel,
I recently posted a patch for re-configuring an ethernet PHY on its
.resume() callback as this PHY is in a setup with SAMA7G5 SoC that supports
a power saving mode (called backup). In this power saving mode most of the
SoC devices' power is cut of (except the RAM + its
On 21.01.2021 11:41, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi Claudiu,
>
> Am 2021-01-21 10:19, schrieb claudiu.bez...@microchip.com:
>> On 20.01.2021 21:43, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click
On 22.01.2021 13:20, Michael Walle wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Am 2021-01-22 10:10, schrieb claudiu.bez...@microchip.com:
>> On 21.01.2021 11:41, Michael Walle wrote:
>>> EXTERNAL EMAIL: Do not click links or open
On 04.08.2020 14:42, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hello,
>
> On 04/08/2020 14:07:37+0300, Claudiu Beznea wrote:
>> void __init at91rm9200_pm_init(void)
>> {
>> + static const int modes[]
On 04.08.2020 18:08, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 04/08/2020 15:00:38+, claudiu.bez...@microchip.com wrote:
>>
>>
>> On 04.08.2020 14:42, Alexandre Belloni wrote:
>>> EXTERNAL EMAIL: Do not
On 04.08.2020 14:56, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> cpu_do_idle() is already the default action for arm_pm_idle, there is no
> need to open code it.
>
> Signed-off-by: Alexandre Belloni
Reviewed-by:
On 03.08.2020 11:34, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 03/08/2020 10:25:16+0300, Claudiu Beznea wrote:
>> Not all SoCs supports all the PM mode. User may end up settings,
>> e.g. backup mode, on a non
On 03.08.2020 11:18, Codrin Ciubotariu wrote:
> The new SPDIF TX controller is a serial port compliant with the IEC-
> 60958 standard. It also supports programmable User Data and Channel
> Status fields.
>
> This IP is embedded in Microchip's sama7g5 SoC.
>
> Signed-off-by: Codrin Ciubotariu
On 03.08.2020 19:11, Codrin Ciubotariu - M19940 wrote:
> On 03.08.2020 16:06, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 03.08.2020 11:18, Codrin Ciubotariu wrote:
>>> The new SPDIF TX controller is a serial port compliant with the IEC-
>>> 60958 standard. It also supports programmable User Data
On 03.08.2020 19:11, Codrin Ciubotariu - M19940 wrote:
> On 03.08.2020 16:06, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 03.08.2020 11:18, Codrin Ciubotariu wrote:
>>> The new SPDIF TX controller is a serial port compliant with the IEC-
>>> 60958 standard. It also supports programmable User Data
Hi Charles,
On 04.01.2021 12:38, Charles Keepax wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> A new flag MACB_CAPS_CLK_HW_CHG was added and all callers of
> macb_set_tx_clk were gated on the presence of this flag.
>
> - if (!clk)
>
On 05.01.2021 12:44, Viresh Kumar wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 05-01-21, 12:22, Claudiu Beznea wrote:
>> Microchip SAMA7G5 devices supports runtime changes of CPU frequency.
>> This is doable by changing CPUPLL
On 16.12.2020 15:45, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote:
>> Add support for SAMA7G5 by adding proper struct reg_config structure
>> and since SAMA7G5 is
On 16.12.2020 15:45, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 16/12/2020 14:57:33+0200, Claudiu Beznea wrote:
>> Add support for SAMA7G5 by adding proper struct reg_config structure
>> and since SAMA7G5 is
On 18.11.2020 03:49, Stephen Boyd wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Quoting claudiu.bez...@microchip.com (2020-11-16 03:24:54)
>>
>>
>> On 14.11.2020 23:14, Stephen Boyd wrote:
>>> EXTERNAL EMAIL: Do not click links or
On 14.11.2020 23:14, Stephen Boyd wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Quoting Claudiu Beznea (2020-11-06 01:46:23)
>> diff --git a/drivers/clk/at91/clk-sam9x60-pll.c
>> b/drivers/clk/at91/clk-sam9x60-pll.c
>> index
Hi Jon,
On 24.11.2020 11:36, Jon Hunter wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 13/11/2020 15:21, Claudiu Beznea wrote:
>> There are regulators who's min selector is not zero. Selectors loops
>> (looping b/w zero and
On 02.12.2020 14:58, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> The sam9x60 doesn't have the MOSCXTBY bit to enable the crystal oscillator
> bypass.
>
> Fixes: 01e2113de9a5 ("clk: at91: add sam9x60 pmc driver")
>
I have just noticed that the title of this cover letter is wrong.
It should have been:
"clk: at91: adapt for dvfs"
Please let me know if you want me to send a new version for this update.
Thank you,
Claudiu
On 19.11.2020 17:43, Claudiu Beznea wrote:
> Hi,
>
> SAMA7G5 is capable of DVFS. The
On 24.11.2020 15:41, Jon Hunter wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 24/11/2020 11:14, claudiu.bez...@microchip.com wrote:
>
> ...
>
>> I would say that a solution would be to have a new helper to retrieve the
>>
Hi Lars,
On 23.08.2019 13:06, Lars Poeschel wrote:
> External E-Mail
>
>
> On Thu, Aug 22, 2019 at 10:09:09AM +, claudiu.bez...@microchip.com wrote:
>> Hi Lars,
>>
>> On 20.08.2019 15:03, Lars Poeschel wrote:
>>> This adds the UART phy interface for the pn533 driver.
>>> The pn533 driver
From: Claudiu Beznea
Add support to free slow rc oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index c1d7edd33416..492b139a7c15 100644
---
From: Claudiu Beznea
Add support to free slow clock oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 492b139a7c15..2a677c56f901 100644
---
From: Claudiu Beznea
Improve error path for sama5d4 sck registration.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 43 ---
1 file changed, 28 insertions(+), 15 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
From: Claudiu Beznea
Improve error path for sam9x5 slow clock registration.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 50 +++--
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/drivers/clk/at91/sckc.c
From: Claudiu Beznea
Add support to free slow oscillator resources.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 8
1 file changed, 8 insertions(+)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index 2c410f41b413..c1d7edd33416 100644
---
From: Claudiu Beznea
Remove unnecessary line.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index a2b905c91085..c61b6c9ddb94 100644
--- a/drivers/clk/at91/sckc.c
+++
From: Claudiu Beznea
Hi,
This series tries to improve error path for slow clock registrations
by adding functions to free resources and using them on failures.
It is created on top of patch series at [1].
Thank you,
Claudiu Beznea
[1]
From: Claudiu Beznea
Use at91 specific functions to free all resources in case of error.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index
On 20.08.2020 08:48, Dinghao Liu wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> When devm_clk_get() returns -EPROBE_DEFER, sdio_priv
> should be freed just like when wilc_cfg80211_init()
> fails.
>
> Fixes: 8692b047e86cf ("staging:
Hi Dinghao,
On 20.08.2020 08:52, Dinghao Liu wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> When devm_clk_get() returns -EPROBE_DEFER, spi_priv
> should be freed just like when wilc_cfg80211_init()
> fails.
>
> Fixes: 854d66df74aed
Hi,
Please ignore this series for the moment as I will have to run few more
tests on it. Sorry for the noise!
Thank you,
Claudiu Beznea
On 04.11.2020 19:45, Claudiu Beznea wrote:
> Hi,
>
> SAMA7G5 is capable of DVFS. The supported CPU clock frequencies could be
> obtained from CPU PLL. The
On 13.01.2021 13:09, Heiner Kallweit wrote:
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> content is safe
>
> On 13.01.2021 10:29, claudiu.bez...@microchip.com wrote:
>> Hi Heiner,
>>
>> On 08.01.2021 18:31, Heiner Kallweit wrote:
>>> EXTERNAL EMAIL: Do not
Hi Heiner,
On 08.01.2021 18:31, Heiner Kallweit wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 08.01.2021 16:45, Claudiu Beznea wrote:
>> KSZ9131 is used in setups with SAMA7G5. SAMA7G5 supports a special
>> power saving mode (backup
On 18.09.2019 17:57, Kamel Bouhara wrote:
> Since commit 26202873bb51 ("avr32: remove support for AVR32
> architecture") there is no more user of platform_device_id and we
> should only use dt bindings
>
> Signed-off-by: Kamel Bouhara
Acked-by: Claudiu Beznea
> ---
> Changelog:
> v1->v2
>
On 18.05.2019 00:13, Alexandre Belloni wrote:
> External E-Mail
>
>
> On 16/05/2019 08:10:34+, claudiu.bez...@microchip.com wrote:
@@ -69,10 +80,11 @@ static int clk_slow_osc_prepare(struct clk_hw *hw)
void __iomem *sckcr = osc->sckcr;
u32 tmp = readl(sckcr);
From: Claudiu Beznea
Add bindings for SAM9X60's slow clock controller.
Signed-off-by: Claudiu Beznea
Reviewed-by: Alexandre Belloni
Reviewed-by: Rob Herring
---
Documentation/devicetree/bindings/clock/at91-clock.txt | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git
From: Claudiu Beznea
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.
Signed-off-by: Claudiu Beznea
---
drivers/clk/at91/sckc.c | 93 -
1 file changed, 61 insertions(+), 32
From: Claudiu Beznea
The slow clock of SAMA5D4 has no bypass support thus remove it.
Signed-off-by: Claudiu Beznea
Acked-by: Alexandre Belloni
---
drivers/clk/at91/sckc.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/drivers/clk/at91/sckc.c b/drivers/clk/at91/sckc.c
index
From: Claudiu Beznea
Hi,
This series add slow clock support for SAM9X60. Apart from previous IPs, this
one uses different offsets in control register for different functionalities.
The series adapt current driver to work for all IPs using per IP
configurations initialized at probe.
Thank you,
From: Claudiu Beznea
Add support for SAM9X60's slow clock.
Signed-off-by: Claudiu Beznea
Acked-by: Alexandre Belloni
---
drivers/clk/at91/sckc.c | 74 +
1 file changed, 74 insertions(+)
diff --git a/drivers/clk/at91/sckc.c
From: Claudiu Beznea
SAMA5D2 SoC has a suspend mode where SoC's power is cut off. Due to this
the registers content is lost after a suspend/resume cycle. The current
suspend/resume implementation covers some of these registers. However
there are few which were not treated (e.g. SCRT2 and USRIO).
Hi Daniel,
Taking into account the discussion on this tread and the fact that we have
no answer from Rob on this topic (I'm talking about [1]), what do you think
it would be best for this driver to be accepted the soonest? Would it be OK
for you to mimic the approach done by:
On 25.09.2019 20:19, Daniel Lezcano wrote:
> External E-Mail
>
>
> Hi Claudiu,
>
> On 10/09/2019 15:47, Claudiu Beznea wrote:
>> Hi,
>>
>> This series adds support to permit the selection of clocksource/clockevent
>> via DT.
>
> Thanks for the proposal and taking care of making some progress
On 11.09.2019 12:58, Codrin Ciubotariu wrote:
> External E-Mail
>
>
> After a transfer timeout, some faulty I2C slave devices might hold down
> the SCL or the SDA pins. We can generate a bus clear command, hoping that
> the slave might release the pins.
>
> Signed-off-by: Codrin Ciubotariu
Hi Daniel,
Taking into account that Rob doesn't agree with the solution proposed in
this series do you think there is a chance to merge this driver as is?
If you have other suggestion I am open to try it.
Thank you,
Claudiu Beznea
On 26.09.2019 11:42, Claudiu Beznea wrote:
>
>
> On
On 02.10.2019 16:35, Claudiu Beznea wrote:
> Hi Daniel,
>
> Taking into account that Rob doesn't agree with the solution proposed in
> this series do you think there is a chance to merge this driver as is?
Sorry, I was talking here about the driver at [1].
[1]
Hi Kamel,
On 02.10.2019 17:46, Kamel Bouhara wrote:
> +static int at91_init_twi_recovery_info(struct platform_device *pdev,
> +struct at91_twi_dev *dev)
> +{
> + struct i2c_bus_recovery_info *rinfo = >rinfo;
> +
> + dev->pinctrl =
On 20.08.2019 15:03, Lars Poeschel wrote:
> There is a problem in the initialisation and setup of the pn533: It
> registers with nfc too early. It could happen, that it finished
> registering with nfc and someone starts using it. But setup of the pn533
> is not yet finished. Bad or at least
Hi Lars,
On 20.08.2019 15:03, Lars Poeschel wrote:
> This adds the UART phy interface for the pn533 driver.
> The pn533 driver can be used through UART interface this way.
> It is implemented as a serdev device.
>
> Cc: Johan Hovold
> Signed-off-by: Lars Poeschel
> ---
> Changes in v6:
> -
On 04.10.2019 23:39, Uwe Kleine-König wrote:
> External E-Mail
>
>
> On Fri, Oct 04, 2019 at 09:35:23AM +, claudiu.bez...@microchip.com wrote:
>> Hi Kamel,
>>
>> On 02.10.2019 17:46, Kamel Bouhara wrote:
>>> +static int at91_init_twi_recovery_info(struct platform_device *pdev,
>>> +
Hi,
On 08.10.2019 19:54, Alexandre Belloni wrote:
> Hi,
>
> On 08/10/2019 19:46:26+0300, Claudiu Beznea wrote:
>> Add compatible for SAM9X60's PMC.
>
> I think the commit log could be clearer and mention why this is needed
> and the compatible string in sam9x60 is not sufficient.
I had issues
Hi Daniel,
On 13.10.2019 21:16, Daniel Lezcano wrote:
> Hi Claudiu,
>
> sorry for the delay, I was OoO again.
No problem, thank you for your reply.
>
> On 03/10/2019 12:43, claudiu.bez...@microchip.com wrote:
>>
>>
>> On 02.10.2019 16:35, Claudiu Beznea wrote:
>>> Hi Daniel,
>>>
>>> Taking
On 05.09.2019 17:13, Alexandre Belloni wrote:
> + pr_err("ABE: %d %08x\n", bank, bits[word]);
Is this needed?
Please ignore this one!
I'll send a v2.
On 24.06.2020 10:26, Claudiu Beznea wrote:
> DMA buffers were not freed on failure path of at91ether_open().
> Along with changes for freeing the DMA buffers the enable/disable
> interrupt instructions were moved to at91ether_start()/at91ether_stop()
>
On 15.07.2020 14:24, Claudiu Beznea wrote:
> Register slow rc with accuracy option.
>
> Fixes: 04bcc4275e601 ("clk: at91: sckc: add support for SAM9X60")
> Signed-off-by: Claudiu Beznea
> ---
> drivers/clk/at91/sckc.c | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff
On 17.07.2020 12:12, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 15/07/2020 14:24:15+0300, Claudiu Beznea wrote:
>> In commit a436c2a447e59 ("clk: at91: add sam9x60 PLL driver")
>> the fractional part of PLL
On 17.07.2020 18:07, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> Hi,
>
> On 15/07/2020 14:24:18+0300, Claudiu Beznea wrote:
>> Replace conditional operator with double logical not.
>
> I think you need to
On 22.07.2020 17:43, claudiu.bez...@microchip.com wrote:
>
>
> On 22.07.2020 16:44, cristian.bir...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Instead of trying to match every possible compatible use
>> of_find_matching_node_and_match() and pass the compatible array.
>>
>>
On 23.07.2020 21:59, Florian Fainelli wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 7/21/20 10:13 AM, Codrin Ciubotariu wrote:
>> The MACB embeds an MDIO bus controller. For this reason, the PHY nodes
>> were represented as
On 21.07.2020 20:13, Codrin Ciubotariu wrote:
> Adding the PHY nodes directly under the Ethernet node became deprecated,
> so the aim of this patch series is to make MACB use an MDIO node as
> container for MDIO devices.
> This patch series starts with a small patch to use the device-managed
>
On 22.07.2020 16:44, cristian.bir...@microchip.com wrote:
> From: Claudiu Beznea
>
> Instead of trying to match every possible compatible use
> of_find_matching_node_and_match() and pass the compatible array.
>
> Signed-off-by: Claudiu Beznea
> ---
> drivers/usb/gadget/udc/atmel_usba_udc.c
On 22.07.2020 14:38, Codrin Ciubotariu - M19940 wrote:
> On 22.07.2020 13:32, Claudiu Beznea - M18063 wrote:
>>
>>
>> On 21.07.2020 20:13, Codrin Ciubotariu wrote:
>>> Adding the PHY nodes directly under the Ethernet node became deprecated,
>>> so the aim of this patch series is to make MACB use
Hi Daniel,
On 20.06.2019 11:53, Daniel Lezcano wrote:
> Hi Claudiu,
>
> sorry for the late reply.
No problem, I understand.
>
>
> On 13/06/2019 16:12, claudiu.bez...@microchip.com wrote:
>> Hi Daniel,
>>
>> On 31.05.2019 13:41, Daniel Lezcano wrote:
>>>
>>> Hi Claudiu,
>>>
>>>
>>> On
On 26.06.2019 21:36, Stephen Boyd wrote:
> Quoting claudiu.bez...@microchip.com (2019-05-21 03:11:33)
>> From: Claudiu Beznea
>>
>> Add support for SAM9X60's slow clock.
>>
>> Signed-off-by: Claudiu Beznea
>> Acked-by: Alexandre Belloni
>> ---
>
> FYI, this patch is base64 encoded and causes
On 27.06.2019 18:03, Stephen Boyd wrote:
> External E-Mail
>
>
> Quoting claudiu.bez...@microchip.com (2019-06-13 08:37:06)
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> This series tries to improve error path for slow clock registrations
>> by adding functions to free resources and using them on
From: Claudiu Beznea
Add compatible string for SAM9X60 HLCDC's PWM.
Signed-off-by: Claudiu Beznea
Acked-by: Thierry Reding
---
Hi Thierry,
This patch was initially part of series at [1]. The rest of the patches in
that series were taken though drm-misc-next. Only this one remained.
[1]
Hi Daniel,
On 31.05.2019 13:41, Daniel Lezcano wrote:
>
> Hi Claudiu,
>
>
> On 30/05/2019 09:46, claudiu.bez...@microchip.com wrote:
>> Hi Daniel,
>>
>> Taking into account the discussion on this tread and the fact that we have
>> no answer from Rob on this topic (I'm talking about [1]), what
Hi,
On 18.06.2019 12:55, Alexandre Belloni wrote:
> On 13/06/2019 15:37:06+, claudiu.bez...@microchip.com wrote:
>> From: Claudiu Beznea
>>
>> Hi,
>>
>> This series tries to improve error path for slow clock registrations
>> by adding functions to free resources and using them on failures.
Hi Daniel,
On 18.10.2019 23:24, Daniel Lezcano wrote:
> Hi Claudiu,
>
> On 15/10/2019 11:23, claudiu.bez...@microchip.com wrote:
>
> [ ... ]
>
>> The timer clock source could be divided by MR.PRES + 1.
>>
>> So, I used the clock-frequency DT binding to let user choose the timer's
>> frequency.
Hi Nicolas,
On 13.07.2020 13:05, nicolas.fe...@microchip.com wrote:
> From: Nicolas Ferre
>
> Adapt the Wake-on-Lan feature to the Cadence GEM Ethernet controller.
> This controller has different register layout and cannot be handled by
> previous code.
> We disable completely interrupts on
Hi Andrew, Florian,
On 30.06.2020 06:35, Florian Fainelli wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 6/29/2020 5:45 PM, Andrew Lunn wrote:
>> On Mon, Jun 29, 2020 at 10:26:36AM +0300, Claudiu Beznea wrote:
>>> In case
On 27.06.2020 00:03, Alexandre Belloni wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the
> content is safe
>
> On 25/06/2020 13:09:28+0300, Claudiu Beznea wrote:
>> Return in clk_main_osc_prepare()/clk_main_rc_osc_prepare() if
>> oscillators are already
On 06.02.2019 00:49, Thierry Reding wrote:
> On Sat, Jan 05, 2019 at 10:05:22PM +0100, Uwe Kleine-König wrote:
>> Hello,
>>
>> On Thu, Jan 03, 2019 at 01:29:44PM +, claudiu.bez...@microchip.com wrote:
>>> From: Claudiu Beznea
>>>
>>> Add basic PWM modes: normal and complementary. These
On 06.02.2019 10:24, Uwe Kleine-König wrote:
> Hello Thierry,
>
> On Wed, Feb 06, 2019 at 12:01:26AM +0100, Thierry Reding wrote:
>> On Mon, Jan 07, 2019 at 11:10:40PM +0100, Uwe Kleine-König wrote:
>>> On Mon, Jan 07, 2019 at 09:30:55AM +, claudiu.bez...@microchip.com
>>> wrote:
On
From: Claudiu Beznea
Hi,
This series add slow clock support for SAM9X60. Apart from previous IPs, this
one uses different offsets in control register for different functionalities.
The series adapt current driver to work for all IPs using per IP
configurations initialized at probe.
Thank you,
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