On Fri, Jan 13, 2017 at 1:52 PM, Dawei Chien <dawei.ch...@mediatek.com> wrote:
>
> From: "dawei.ch...@mediatek.com" <dawei.ch...@mediatek.com>
>
> Add this for supporting thermal calibration by e-fuse data.
>
> Signed-off-by: Dawei Chien <dawei.ch...@med
On Fri, Jan 13, 2017 at 1:52 PM, Dawei Chien wrote:
>
> From: "dawei.ch...@mediatek.com"
>
> Add this for supporting thermal calibration by e-fuse data.
>
> Signed-off-by: Dawei Chien
Reviewed-by: Daniel Kurtz
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dts
-device cpu1) is around 3:1 (3072:1024).
Signed-off-by: Daniel Kurtz <djku...@chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
-device cpu1) is around 3:1 (3072:1024).
Signed-off-by: Daniel Kurtz
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 12e702771f5c
perty with the higher VENCPLL frequency the board
> supports HDMI 4K resolution.
>
> Signed-off-by: Bibby Hsieh <bibby.hs...@mediatek.com>
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
It looks like this patch was lost. It is actually a prerequisite for
MTK 4k HDMI support, wh
uency the board
> supports HDMI 4K resolution.
>
> Signed-off-by: Bibby Hsieh
Reviewed-by: Daniel Kurtz
It looks like this patch was lost. It is actually a prerequisite for
MTK 4k HDMI support, which already landed in v4.9.
See the email thread entitled:
[PATCH v5 0/3] MT8173 HDMI 4K s
On Fri, Dec 30, 2016 at 2:26 PM, Bibby Hsieh <bibby.hs...@mediatek.com> wrote:
>
> MT8173 overlay can support UYVY and YUYV format,
> we add the format in DRM driver.
>
> Signed-off-by: Bibby Hsieh <bibby.hs...@mediatek.com>
> Reviewed-by: Daniel Kurtz <djku...@c
On Fri, Dec 30, 2016 at 2:26 PM, Bibby Hsieh wrote:
>
> MT8173 overlay can support UYVY and YUYV format,
> we add the format in DRM driver.
>
> Signed-off-by: Bibby Hsieh
> Reviewed-by: Daniel Kurtz
> ---
> drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 21
/mediatek/mtk_drm_plane.c
> @@ -28,6 +28,8 @@
> DRM_FORMAT_XRGB,
> DRM_FORMAT_ARGB8888,
> DRM_FORMAT_RGB565,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_UYVY,
nit: probably better to alphabetize these.
Other than that,
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
>
> };
>
> static void mtk_plane_reset(struct drm_plane *plane)
> --
> 1.9.1
>
RM_FORMAT_XRGB,
> DRM_FORMAT_ARGB,
> DRM_FORMAT_RGB565,
> + DRM_FORMAT_YUYV,
> + DRM_FORMAT_UYVY,
nit: probably better to alphabetize these.
Other than that,
Reviewed-by: Daniel Kurtz
>
> };
>
> static void mtk_plane_reset(struct drm_plane *plane)
> --
> 1.9.1
>
Hi YT,
On Fri, Nov 25, 2016 at 6:34 PM, YT Shen wrote:
>
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR offset changed.
> MIPI_TX pll
Hi YT,
On Fri, Nov 25, 2016 at 6:34 PM, YT Shen wrote:
>
> There are some hardware settings changed, between MT8173 & MT2701:
> DISP_OVL address offset changed, color format definition changed.
> DISP_RDMA fifo size changed.
> DISP_COLOR offset changed.
> MIPI_TX pll setting changed.
> And add
Hi YT,
I don't see a reason to handle device_data in such a generic way at
the generic mtk_ddp_comp layer.
The device data is very component specific, so just define different
structs for different comp types, ie:
struct mtk_disp_ovl_driver_data {
unsigned int reg_ovl_addr;
unsigned int
Hi YT,
I don't see a reason to handle device_data in such a generic way at
the generic mtk_ddp_comp layer.
The device data is very component specific, so just define different
structs for different comp types, ie:
struct mtk_disp_ovl_driver_data {
unsigned int reg_ovl_addr;
unsigned int
Hi CK,
On Thu, Nov 17, 2016 at 1:36 PM, CK Hu wrote:
> Hi, Jitao:
>
>
> On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote:
>> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
>> Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
>>
Hi CK,
On Thu, Nov 17, 2016 at 1:36 PM, CK Hu wrote:
> Hi, Jitao:
>
>
> On Wed, 2016-11-16 at 11:20 +0800, Jitao Shi wrote:
>> Tune dsi frame rate by pixel clock, dsi add some extra signal (i.e.
>> Tlpx, Ths-prepare, Ths-zero, Ths-trail,Ths-exit) when enter and exit LP
>> mode, those signals
Hi YT,
Sorry for the very late review.
My biggest problem with this patch is it describes itself as adding
support for a new use case "DSI -> panel", but makes many changes to
the existing working flow "DSI -> bridge -> panel".
If these changes are really needed, or improve the existing flow,
Hi YT,
Sorry for the very late review.
My biggest problem with this patch is it describes itself as adding
support for a new use case "DSI -> panel", but makes many changes to
the existing working flow "DSI -> bridge -> panel".
If these changes are really needed, or improve the existing flow,
iatek.com>
For this patch,
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
But, one more clean up suggestion for another patch, below...
> ---
> Change since v4:
> - tune the calc comment more clear.
> - define the phy timings as constants.
>
> Chnage since v3:
> -
S.
> So need to multiply a coefficient to offset the extra signal's effect.
> coefficient = ((htotal*bpp/lane_number)+Tlpx+Ths_prep+Ths_zero+
> Ths_trail+Ths_exit)/(htotal*bpp/lane_number)
>
> Signed-off-by: Jitao Shi
For this patch,
Reviewed-by: Daniel Kurtz
But, o
On Tue, Oct 25, 2016 at 6:23 AM, Matthias Brugger
wrote:
>
> On 10/18/2016 04:37 PM, Enric Balletbo Serra wrote:
> [...]
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> [...]
>>>
>>> +
>>> +/* Firmware */
>>> +#define PS_FW_NAME
On Tue, Oct 25, 2016 at 6:23 AM, Matthias Brugger
wrote:
>
> On 10/18/2016 04:37 PM, Enric Balletbo Serra wrote:
> [...]
>>> --- /dev/null
>>> +++ b/drivers/gpu/drm/bridge/parade-ps8640.c
> [...]
>>>
>>> +
>>> +/* Firmware */
>>> +#define PS_FW_NAME "ps864x_fw.bin"
>>> +
>>
>> From
On Wed, Oct 19, 2016 at 4:29 AM, Doug Anderson <diand...@chromium.org> wrote:
>
> Dan,
>
> On Tue, Oct 18, 2016 at 6:44 AM, Daniel Kurtz <djku...@chromium.org> wrote:
> > Hi Doug,
> >
> > On Tue, Oct 11, 2016 at 5:04 AM, Douglas Anderson <
On Wed, Oct 19, 2016 at 4:29 AM, Doug Anderson wrote:
>
> Dan,
>
> On Tue, Oct 18, 2016 at 6:44 AM, Daniel Kurtz wrote:
> > Hi Doug,
> >
> > On Tue, Oct 11, 2016 at 5:04 AM, Douglas Anderson
> > wrote:
> >> Users of usleep_range() expect that
Hi Doug,
On Tue, Oct 11, 2016 at 5:04 AM, Douglas Anderson wrote:
> Users of usleep_range() expect that it will _never_ return in less time
> than the minimum passed parameter. However, nothing in any of the code
> ensures this. Specifically:
>
> usleep_range() =>
Hi Doug,
On Tue, Oct 11, 2016 at 5:04 AM, Douglas Anderson wrote:
> Users of usleep_range() expect that it will _never_ return in less time
> than the minimum passed parameter. However, nothing in any of the code
> ensures this. Specifically:
>
> usleep_range() => do_usleep_range() =>
sleep.
Two caveats:
1) To avoid penalizing short delays, still use udelay for delays < 10us.
2) usleep_range() very often picks the upper bound, an upper bounds 10%
should be plenty.
Signed-off-by: Daniel Kurtz <djku...@chromium.org>
---
drivers/spi/spi.c | 10 --
1
sleep.
Two caveats:
1) To avoid penalizing short delays, still use udelay for delays < 10us.
2) usleep_range() very often picks the upper bound, an upper bounds 10%
should be plenty.
Signed-off-by: Daniel Kurtz
---
drivers/spi/spi.c | 10 --
1 file changed, 8 insertions(+), 2
On Thu, Sep 29, 2016 at 11:29 AM, Bibby Hsieh <bibby.hs...@mediatek.com> wrote:
>
> Clean the interrupt status before enable interrupt
> and set the vblank_disable_allowed to fix the issue.
For the series:
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
>
> Bibby
On Thu, Sep 29, 2016 at 11:29 AM, Bibby Hsieh wrote:
>
> Clean the interrupt status before enable interrupt
> and set the vblank_disable_allowed to fix the issue.
For the series:
Reviewed-by: Daniel Kurtz
>
> Bibby Hsieh (2):
> drm/mediatek: set vblank_disable_allow
Hi Emil,
One answer inline below. The rest I leave to Jitao...
[snip...]
On Fri, Jun 17, 2016 at 3:14 AM, Emil Velikov wrote:
>> +static ssize_t ps8640_update_fw_store(struct device *dev,
>> + struct device_attribute *attr,
>> +
Hi Emil,
One answer inline below. The rest I leave to Jitao...
[snip...]
On Fri, Jun 17, 2016 at 3:14 AM, Emil Velikov wrote:
>> +static ssize_t ps8640_update_fw_store(struct device *dev,
>> + struct device_attribute *attr,
>> +
Hi Jitao,
On Thu, Jun 2, 2016 at 5:57 PM, Jitao Shi <jitao@mediatek.com> wrote:
>
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi <jitao@mediatek.com>
> Reviewed-by: Daniel Kurtz <djku...@chromium.
Hi Jitao,
On Thu, Jun 2, 2016 at 5:57 PM, Jitao Shi wrote:
>
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> Reviewed-by: Daniel Kurtz
> ---
> Changes since v15:
> - Drop drm_connector_(un)register calls from para
Hi Henry,
On Wed, May 11, 2016 at 5:12 PM, Henry Chen wrote:
>
> Some regulators support their operating mode to be changed by
> consumers for module specific purpose.
>
> This patch adds support to parse those properties and fill the
> regulator constraints so the
Hi Henry,
On Wed, May 11, 2016 at 5:12 PM, Henry Chen wrote:
>
> Some regulators support their operating mode to be changed by
> consumers for module specific purpose.
>
> This patch adds support to parse those properties and fill the
> regulator constraints so the regulator core can call the
>
ULL_DISCHARGED is set,
> it is wrong to set as POWER_SUPPLY_STATUS_NOT_CHARGING.
> Just use BATTERY_DISCHARGING to decide the power supply status is
> discharging or charging.
>
> Signed-off-by: YH Huang <yh.hu...@mediatek.com>
Reviewed-by: Daniel Kurtz <djku...@chromi
it is wrong to set as POWER_SUPPLY_STATUS_NOT_CHARGING.
> Just use BATTERY_DISCHARGING to decide the power supply status is
> discharging or charging.
>
> Signed-off-by: YH Huang
Reviewed-by: Daniel Kurtz
> ---
> drivers/power/sbs-battery.c |4
> 1 file changed,
ing. Debounce time for first debounce setting is 500us,
> correct this as well.
>
> While I'm at it, also change the debounce time array name to
> "debounce_time" for readability.
>
> Signed-off-by: Yingjoe Chen <yingjoe.c...@mediatek.com>
Reviewed-by: Daniel Kurtz <dj
unce setting is 500us,
> correct this as well.
>
> While I'm at it, also change the debounce time array name to
> "debounce_time" for readability.
>
> Signed-off-by: Yingjoe Chen
Reviewed-by: Daniel Kurtz
> ---
> This was based on v4.6-rc1
> Change since v1:
>
Hi Yingjoe,
On Fri, Apr 1, 2016 at 9:51 PM, Yingjoe Chen wrote:
> The debounce time unit for gpio_chip.set_debounce is us but
> mtk_gpio_set_debounce regard it as ms.
> Fix this by correct debounce time array dbnc_arr so it can find correct
> debounce setting.
This
Hi Yingjoe,
On Fri, Apr 1, 2016 at 9:51 PM, Yingjoe Chen wrote:
> The debounce time unit for gpio_chip.set_debounce is us but
> mtk_gpio_set_debounce regard it as ms.
> Fix this by correct debounce time array dbnc_arr so it can find correct
> debounce setting.
This patch also changes the first
+Rhyland Klein who original wrote this code...
On Mon, Mar 28, 2016 at 10:32 AM, YH Huang <yh.hu...@mediatek.com> wrote:
>
> On Fri, 2016-03-25 at 11:06 +0800, Daniel Kurtz wrote:
> > On Thu, Mar 24, 2016 at 2:43 PM, YH Huang <yh.hu...@mediatek.com> wrot
+Rhyland Klein who original wrote this code...
On Mon, Mar 28, 2016 at 10:32 AM, YH Huang wrote:
>
> On Fri, 2016-03-25 at 11:06 +0800, Daniel Kurtz wrote:
> > On Thu, Mar 24, 2016 at 2:43 PM, YH Huang wrote:
> > >
> > > Hi Daniel,
> > >
> > >
On Thu, Mar 24, 2016 at 2:43 PM, YH Huang <yh.hu...@mediatek.com> wrote:
>
> Hi Daniel,
>
> On Thu, 2016-03-24 at 12:01 +0800, Daniel Kurtz wrote:
> > Hi YH,
> >
> > On Wed, Mar 23, 2016 at 5:53 PM, YH Huang <yh.hu...@mediatek.com> wrote:
> > >
On Thu, Mar 24, 2016 at 2:43 PM, YH Huang wrote:
>
> Hi Daniel,
>
> On Thu, 2016-03-24 at 12:01 +0800, Daniel Kurtz wrote:
> > Hi YH,
> >
> > On Wed, Mar 23, 2016 at 5:53 PM, YH Huang wrote:
> > > When the battery is dry and BATTERY_FULL_D
Hi YH,
On Wed, Mar 23, 2016 at 5:53 PM, YH Huang wrote:
> When the battery is dry and BATTERY_FULL_DISCHARGED is set,
> we should check BATTERY_DISCHARGING to decide the power status.
> If BATTERY_DISCHARGING is set, the power status is not charging.
> Or the power status
Hi YH,
On Wed, Mar 23, 2016 at 5:53 PM, YH Huang wrote:
> When the battery is dry and BATTERY_FULL_DISCHARGED is set,
> we should check BATTERY_DISCHARGING to decide the power status.
> If BATTERY_DISCHARGING is set, the power status is not charging.
> Or the power status should be charging.
>
>
Hi Jitao,
This patch looks really good now.
Just saw small nits below.
Other than these small items, for the series:
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
On Thu, Mar 17, 2016 at 9:15 AM, Jitao Shi <jitao@mediatek.com> wrote:
> This patch adds drm_bridge driver
Hi Jitao,
This patch looks really good now.
Just saw small nits below.
Other than these small items, for the series:
Reviewed-by: Daniel Kurtz
On Thu, Mar 17, 2016 at 9:15 AM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by:
Hi Jitao,
Getting very close now...
Comments inline...
On Tue, Feb 23, 2016 at 3:35 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> ---
> Changes since v10:
> - Tuning
Hi Jitao,
Getting very close now...
Comments inline...
On Tue, Feb 23, 2016 at 3:35 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> ---
> Changes since v10:
> - Tuning PS8640 reset sleep pins squence
>
> The
On Fri, Feb 26, 2016 at 5:00 PM, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
>
> On Wed, 2016-02-03 at 14:40 +0800, Daniel Kurtz wrote:
> > > Hi Dan,
> > >
> > > Thanks for your comment.
> > > This solution looks good to me.
> > > I w
On Fri, Feb 26, 2016 at 5:00 PM, Horng-Shyang Liao wrote:
>
> On Wed, 2016-02-03 at 14:40 +0800, Daniel Kurtz wrote:
> > > Hi Dan,
> > >
> > > Thanks for your comment.
> > > This solution looks good to me.
> > > I will change it as your suggest
On Tue, Feb 9, 2016 at 7:29 PM, Daniel Kurtz <djku...@chromium.org> wrote:
> Hi Tiffany,
>
> On Thu, Feb 4, 2016 at 7:34 PM, Tiffany Lin <tiffany@mediatek.com> wrote:
>> Add a DT binding documentation of Video Encoder for the
>> MT8173 SoC from Mediatek.
On Tue, Feb 9, 2016 at 7:29 PM, Daniel Kurtz wrote:
> Hi Tiffany,
>
> On Thu, Feb 4, 2016 at 7:34 PM, Tiffany Lin wrote:
>> Add a DT binding documentation of Video Encoder for the
>> MT8173 SoC from Mediatek.
>>
>> Signed-off-by: Tiffany Lin
>> ---
>
On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz <djku...@chromium.org> wrote:
> Hi Eduardo, Sascha,
>
> On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang <eddie.hu...@mediatek.com> wrote:
>>
>> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote:
>> > Eduard
On Mon, Feb 15, 2016 at 10:11 AM, Daniel Kurtz wrote:
> Hi Eduardo, Sascha,
>
> On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang wrote:
>>
>> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote:
>> > Eduardo,
>> >
>> > On Mon, Jan 04, 2016 at 03:19:4
Hi Eduardo, Sascha,
On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang wrote:
>
> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote:
> > Eduardo,
> >
> > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote:
> > > Hi Eduardo,
> > >
> > > >
> > > > That should
Hi Eduardo, Sascha,
On Mon, Feb 1, 2016 at 10:54 AM, Eddie Huang wrote:
>
> On Tue, 2016-01-19 at 15:29 +0800, Sascha Hauer wrote:
> > Eduardo,
> >
> > On Mon, Jan 04, 2016 at 03:19:40PM +0100, Sascha Hauer wrote:
> > > Hi Eduardo,
> > >
> > > >
> > > > That should remove the policy of computing
Hi Tiffany,
On Thu, Feb 4, 2016 at 7:34 PM, Tiffany Lin wrote:
> Add a DT binding documentation of Video Encoder for the
> MT8173 SoC from Mediatek.
>
> Signed-off-by: Tiffany Lin
> ---
> .../devicetree/bindings/media/mediatek-vcodec.txt | 59
>
> 1 file changed, 59
Hi Tiffany,
On Thu, Feb 4, 2016 at 7:34 PM, Tiffany Lin wrote:
> Add a DT binding documentation of Video Encoder for the
> MT8173 SoC from Mediatek.
>
> Signed-off-by: Tiffany Lin
> ---
> .../devicetree/bindings/media/mediatek-vcodec.txt |
Hi Jitao,
Looks really good.
Just a couple of tiny things...
On Wed, Feb 3, 2016 at 4:48 PM, Jitao Shi wrote:
>
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> ---
[snip]
> +static int ps8640_get_modes(struct drm_connector *connector)
Hi Jitao,
Looks really good.
Just a couple of tiny things...
On Wed, Feb 3, 2016 at 4:48 PM, Jitao Shi wrote:
>
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> ---
[snip]
> +static int
> Hi Dan,
>
> Thanks for your comment.
> This solution looks good to me.
> I will change it as your suggestion.
>
> But, I have a question about 'mask out the provided *device virtual*
> address'.
> Are lower 16-bits (or 24-bits for JUMP op) of device virtual address the
> same as device physical
Hi Jitao,
One more comment, inline...
On Mon, Feb 1, 2016 at 12:13 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
[snip]
> +static int ps8640_probe(struct i2c_client *client,
> + const struct
On Tue, Feb 2, 2016 at 2:48 PM, Horng-Shyang Liao wrote:
> On Mon, 2016-02-01 at 18:22 +0800, Daniel Kurtz wrote:
>> On Mon, Feb 1, 2016 at 2:20 PM, Horng-Shyang Liao
>> wrote:
>> > On Mon, 2016-02-01 at 12:15 +0800, Daniel Kurtz wrote:
>> >> On Mon, Feb 1,
On Tue, Feb 2, 2016 at 2:48 PM, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> On Mon, 2016-02-01 at 18:22 +0800, Daniel Kurtz wrote:
>> On Mon, Feb 1, 2016 at 2:20 PM, Horng-Shyang Liao <hs.l...@mediatek.com>
>> wrote:
>> > On Mon, 2016-02-01 at 12:15 +08
> Hi Dan,
>
> Thanks for your comment.
> This solution looks good to me.
> I will change it as your suggestion.
>
> But, I have a question about 'mask out the provided *device virtual*
> address'.
> Are lower 16-bits (or 24-bits for JUMP op) of device virtual address the
> same as device physical
Hi Jitao,
One more comment, inline...
On Mon, Feb 1, 2016 at 12:13 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
[snip]
> +static int ps8640_probe(struct i2c_client
On Tue, Feb 2, 2016 at 1:19 AM, Liguo Zhang wrote:
>
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang
Reviewed-by: Daniel Kurtz
>
> ---
> change in v6:
> Remove unnec
On Mon, Feb 1, 2016 at 12:13 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> ---
> Changes since v7:
> - Change ps8640_regw to ps8640_regw_bytes and remove devm_kzalloc
> - Fine tune ps8640 power squence
> - Add
c, struct i2c_msg *msgs,
>int num, int left_num)
> {
> @@ -373,6 +385,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c,
> struct i2c_msg *msgs,
> u16 start_reg;
> u16 control_reg;
> u16 restart_flag = 0;
> + u32 reg_4g_mode = 0;
nit: unnecessary init (as Yingjoe mentioned earlier).
Otherwise, this one is:
Reviewed-by: Daniel Kurtz
On Mon, Feb 1, 2016 at 2:20 PM, Horng-Shyang Liao wrote:
> On Mon, 2016-02-01 at 12:15 +0800, Daniel Kurtz wrote:
>> On Mon, Feb 1, 2016 at 10:04 AM, Horng-Shyang Liao
>> wrote:
>> >
>> > On Fri, 2016-01-29 at 21:15 +0800, Daniel Kurtz wrote:
>> > >
On Tue, Feb 2, 2016 at 1:19 AM, Liguo Zhang <liguo.zh...@mediatek.com> wrote:
>
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang <liguo.zh...@mediatek.com>
Revi
On Mon, Feb 1, 2016 at 2:20 PM, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> On Mon, 2016-02-01 at 12:15 +0800, Daniel Kurtz wrote:
>> On Mon, Feb 1, 2016 at 10:04 AM, Horng-Shyang Liao <hs.l...@mediatek.com>
>> wrote:
>> >
>> > On Fri,
On Mon, Feb 1, 2016 at 12:13 PM, Jitao Shi wrote:
> This patch adds drm_bridge driver for parade DSI to eDP bridge chip.
>
> Signed-off-by: Jitao Shi
> ---
> Changes since v7:
> - Change ps8640_regw to ps8640_regw_bytes and remove devm_kzalloc
>
}
> +
> static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
>int num, int left_num)
> {
> @@ -373,6 +385,7 @@ static int mtk_i2c_do_transfer(struct mtk_i2c *i2c,
> struct i2c_msg *msgs,
> u16 start_reg;
> u16 control_reg;
> u16 restart_flag = 0;
> + u32 reg_4g_mode = 0;
nit: unnecessary init (as Yingjoe mentioned earlier).
Otherwise, this one is:
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
On Mon, Feb 1, 2016 at 10:04 AM, Horng-Shyang Liao wrote:
>
> On Fri, 2016-01-29 at 21:15 +0800, Daniel Kurtz wrote:
> > On Fri, Jan 29, 2016 at 8:24 PM, Horng-Shyang Liao
> > wrote:
> > > On Fri, 2016-01-29 at 16:42 +0800, Daniel Kurtz wrote:
> > >>
On Mon, Feb 1, 2016 at 10:04 AM, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
>
> On Fri, 2016-01-29 at 21:15 +0800, Daniel Kurtz wrote:
> > On Fri, Jan 29, 2016 at 8:24 PM, Horng-Shyang Liao <hs.l...@mediatek.com>
> > wrote:
> > > On Fri, 2016-0
From: James Chao
The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices
that use the Chrome OS EC keyboard matrix.
Signed-off-by: James Chao
Signed-off-by: Daniel Kurtz
Signed-off-by: YH Huang
---
arch/arm/boot/dts/cros-ec-keyboard.dtsi | 1 +
1 file changed, 1 insertion
On Fri, Jan 29, 2016 at 8:24 PM, Horng-Shyang Liao wrote:
> On Fri, 2016-01-29 at 16:42 +0800, Daniel Kurtz wrote:
>> On Fri, Jan 29, 2016 at 3:39 PM, Horng-Shyang Liao
>> wrote:
>> > Hi Dan,
>> >
>> > Many thanks for your comments and time.
>>
On Fri, Jan 29, 2016 at 9:35 AM, Liguo Zhang wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang
Reviewed-by: Daniel Kurtz
On Fri, Jan 29, 2016 at 3:39 PM, Horng-Shyang Liao wrote:
> Hi Dan,
>
> Many thanks for your comments and time.
> I reply my plan inline.
>
>
> On Thu, 2016-01-28 at 12:49 +0800, Daniel Kurtz wrote:
>> Hi HS,
>>
>> Sorry for the delay. It is hard to find ti
On Fri, Jan 29, 2016 at 8:24 PM, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> On Fri, 2016-01-29 at 16:42 +0800, Daniel Kurtz wrote:
>> On Fri, Jan 29, 2016 at 3:39 PM, Horng-Shyang Liao <hs.l...@mediatek.com>
>> wrote:
>> > Hi Dan,
>> >
>&g
On Fri, Jan 29, 2016 at 3:39 PM, Horng-Shyang Liao <hs.l...@mediatek.com> wrote:
> Hi Dan,
>
> Many thanks for your comments and time.
> I reply my plan inline.
>
>
> On Thu, 2016-01-28 at 12:49 +0800, Daniel Kurtz wrote:
>> Hi HS,
>>
>> Sorry for
On Fri, Jan 29, 2016 at 9:35 AM, Liguo Zhang <liguo.zh...@mediatek.com> wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang <liguo.zh...@mediatek.com>
Reviewe
From: James Chao <james_c...@asus.com>
The LOCK key is at KSO9/KSI3 for Chromebook Flip and other devices
that use the Chrome OS EC keyboard matrix.
Signed-off-by: James Chao <james_c...@asus.com>
Signed-off-by: Daniel Kurtz <djku...@chromium.org>
Signed-off-by: YH Huang <
On Fri, Jan 29, 2016 at 7:06 AM, Liguo Zhang wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang
> ---
> change in v2:
> Define a static inline funtion mtk_i2c_set_4g_mode() for support 4g mode.
On Tue, Jan 26, 2016 at 12:12 PM, Yong Wu wrote:
> This patch add the iommu/larbs nodes for mt8173
>
> Signed-off-by: Yong Wu
Reviewed-by: Daniel Kurtz
p Zabel
Reviewed-by: Daniel Kurtz
Tested-by: Daniel Kurtz
Thanks!
On Fri, Jan 29, 2016 at 7:06 AM, Liguo Zhang wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang
> ---
> change in v2:
> Define a static
On Tue, Jan 26, 2016 at 12:12 PM, Yong Wu <yong...@mediatek.com> wrote:
> This patch add the iommu/larbs nodes for mt8173
>
> Signed-off-by: Yong Wu <yong...@mediatek.com>
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
<yong...@mediatek.com>
> Tested-by: Philipp Zabel <p.za...@pengutronix.de>
Reviewed-by: Daniel Kurtz <djku...@chromium.org>
Tested-by: Daniel Kurtz <djku...@chromium.org>
Thanks!
Hi HS,
Sorry for the delay. It is hard to find time to review a >3700 line
driver :-o in detail
Some review comments inline, although I still do not completely
understand how all that this driver does and how it works.
I'll try to find time to go through this driver in detail again next
Hi HS,
Sorry for the delay. It is hard to find time to review a >3700 line
driver :-o in detail
Some review comments inline, although I still do not completely
understand how all that this driver does and how it works.
I'll try to find time to go through this driver in detail again next
Hi Liguo,
Thanks for the patch.
On Fri, Jan 22, 2016 at 1:38 AM, Liguo Zhang wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang
> ---
> drivers/i2c/busses/i2c-mt65xx.c | 41
>
Hi Liguo,
Thanks for the patch.
On Fri, Jan 22, 2016 at 1:38 AM, Liguo Zhang wrote:
> If 4GB mode is enable, we should add 4gb mode support in i2c driver.
> Set 4GB mode register to support 4GB mode.
>
> Signed-off-by: Liguo Zhang
> ---
>
On Mon, Jan 4, 2016 at 11:05 AM, Henry Chen wrote:
> On Thu, 2015-12-31 at 22:19 +0800, Daniel Kurtz wrote:
>> On Wed, Dec 30, 2015 at 8:36 PM, Henry Chen wrote:
>> >
>> > The STAUPD_TRIG will be enable when WDT_INT enable on probe function, if
>> > doesn't e
On Mon, Jan 4, 2016 at 11:05 AM, Henry Chen <henryc.c...@mediatek.com> wrote:
> On Thu, 2015-12-31 at 22:19 +0800, Daniel Kurtz wrote:
>> On Wed, Dec 30, 2015 at 8:36 PM, Henry Chen <henryc.c...@mediatek.com> wrote:
>> >
>> > The STAUPD_TRIG will be enabl
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