On Mon, Jul 20, 2015 at 4:17 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM node in mt8173-evb.dts and mt8173.dtsi.
Signed-off-by: YH Huang yh.hu...@mediatek.com
For the series:
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15
On Mon, Jul 20, 2015 at 10:51 PM, Yingjoe Chen
yingjoe.c...@mediatek.com wrote:
Hi Daniel, Chunfeng,
On Mon, 2015-07-20 at 22:39 +0800, chunfeng yun wrote:
Hi,
On Tue, 2015-07-14 at 18:12 +0800, Daniel Kurtz wrote:
...
+
+ usb_p1_vbus: fixedregulator@0 {
Why @0
On Fri, Jul 17, 2015 at 2:35 PM, YH Huang wrote:
>
> On Fri, 2015-07-17 at 01:18 +0800, Daniel Kurtz wrote:
> > On Fri, Jul 17, 2015 at 12:44 AM, YH Huang wrote:
> > > On Thu, 2015-07-16 at 23:21 +0800, Daniel Kurtz wrote:
> > >> On Thu, Jul 16, 2015 at 3:17 PM,
On Fri, Jul 17, 2015 at 2:35 PM, YH Huang yh.hu...@mediatek.com wrote:
On Fri, 2015-07-17 at 01:18 +0800, Daniel Kurtz wrote:
On Fri, Jul 17, 2015 at 12:44 AM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 23:21 +0800, Daniel Kurtz wrote:
On Thu, Jul 16, 2015 at 3:17 PM, YH
On Fri, Jul 17, 2015 at 12:44 AM, YH Huang wrote:
> On Thu, 2015-07-16 at 23:21 +0800, Daniel Kurtz wrote:
>> On Thu, Jul 16, 2015 at 3:17 PM, YH Huang wrote:
>> > On Thu, 2015-07-16 at 14:54 +0800, Daniel Kurtz wrote:
>> >> On Thu, Jul 16, 2015 at 1:38 PM, YH Huan
On Thu, Jul 16, 2015 at 3:17 PM, YH Huang wrote:
> On Thu, 2015-07-16 at 14:54 +0800, Daniel Kurtz wrote:
>> On Thu, Jul 16, 2015 at 1:38 PM, YH Huang wrote:
>> > On Wed, 2015-07-15 at 23:59 +0800, YH Huang wrote:
>> >> On Mon, 2015-07-13 at 18:19 +0800, Daniel Ku
> + pinmux = ;
> + bias-pull-down;
> + drive-strength = ;
> + };
>
On Thu, Jul 16, 2015 at 1:38 PM, YH Huang wrote:
> On Wed, 2015-07-15 at 23:59 +0800, YH Huang wrote:
>> On Mon, 2015-07-13 at 18:19 +0800, Daniel Kurtz wrote:
>> > On Mon, Jul 13, 2015 at 5:04 PM, YH Huang wrote:
>> > > Add display PWM driver support to modify b
On Thu, Jul 16, 2015 at 1:38 PM, YH Huang yh.hu...@mediatek.com wrote:
On Wed, 2015-07-15 at 23:59 +0800, YH Huang wrote:
On Mon, 2015-07-13 at 18:19 +0800, Daniel Kurtz wrote:
On Mon, Jul 13, 2015 at 5:04 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM driver support to modify
;
+ bias-pull-up;
+ };
+ };
+
+ mmc0_pins_uhs: mmc0@0{
(1) I don't think these @0 are needed (here and for mmc1_pins_uhs)
(2) A space before the '{' would be nice.
Other than these tiny nits, this one is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
On Thu, Jul 16, 2015 at 3:17 PM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 14:54 +0800, Daniel Kurtz wrote:
On Thu, Jul 16, 2015 at 1:38 PM, YH Huang yh.hu...@mediatek.com wrote:
On Wed, 2015-07-15 at 23:59 +0800, YH Huang wrote:
On Mon, 2015-07-13 at 18:19 +0800, Daniel
On Fri, Jul 17, 2015 at 12:44 AM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 23:21 +0800, Daniel Kurtz wrote:
On Thu, Jul 16, 2015 at 3:17 PM, YH Huang yh.hu...@mediatek.com wrote:
On Thu, 2015-07-16 at 14:54 +0800, Daniel Kurtz wrote:
On Thu, Jul 16, 2015 at 1:38 PM, YH
On Mon, Jul 13, 2015 at 6:34 PM, Sascha Hauer wrote:
> Signed-off-by: Sascha Hauer
> ---
> .../bindings/thermal/mediatek-thermal.txt | 38
> ++
> 1 file changed, 38 insertions(+)
> create mode 100644
>
On Mon, Jul 13, 2015 at 6:34 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
.../bindings/thermal/mediatek-thermal.txt | 38
++
1 file changed, 38 insertions(+)
create mode 100644
On Tue, Jul 14, 2015 at 5:34 PM, Pi-Cheng Chen wrote:
> From: "pi-cheng.chen"
>
> This patch adds CPU mux clocks which are used by Mediatek cpufreq driver
> for intermediate clock source switching.
>
> Signed-off-by: Pi-Cheng Chen
> Reviewed-by: Daniel Kurtz
>
On Tue, Jul 14, 2015 at 5:46 PM, James Liao wrote:
> Hi Daniel,
>
> On Tue, 2015-07-14 at 11:23 +0800, Daniel Kurtz wrote:
>> On Tue, Jul 14, 2015 at 10:45 AM, James Liao
>> wrote:
>> > On Mon, 2015-07-13 at 22:46 +0800, Daniel Kurtz wrote:
>&g
Hi Chunfeng,
On Wed, Jul 8, 2015 at 5:41 PM, Chunfeng Yun wrote:
> Signed-off-by: Chunfeng Yun
> ---
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +++
> arch/arm64/boot/dts/mediatek/mt8173.dtsi| 27 +++
> 2 files changed, 42 insertions(+)
>
> diff
3.c
> +++ b/drivers/clk/mediatek/clk-mt8173.c
> @@ -19,6 +19,7 @@
>
> #include "clk-mtk.h"
> #include "clk-gate.h"
> +#include "clk-cpumux.h"
>
> #include
>
> @@ -517,6 +518,25 @@ static const char * const i2s3_b_ck_parents[]
>
than this tiny nit, and the small potential conflict in patch 4,
this whole series is:
Reviewed-by: Daniel Kurtz
(I do think it is a bit strange that the mediatek,mt6577-timer binding
does not use "clock-names", but that is independent of this patch
set).
Thanks!
> {
> +
On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen wrote:
> Add 13mhz clock used by GPT timer in infracfg.
>
> Signed-off-by: Yingjoe Chen
> ---
> drivers/clk/mediatek/clk-mt8173.c | 5 +
> include/dt-bindings/clock/mt8173-clk.h | 3 ++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
>
in patch 4,
this whole series is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
(I do think it is a bit strange that the mediatek,mt6577-timer binding
does not use clock-names, but that is independent of this patch
set).
Thanks!
{
+ u32 val;
+
writel(TIMER_CTRL_CLEAR
,
+ mainpll,
+ univpll
+};
+
+static struct mtk_composite cpu_muxes[] __initdata = {
static const struct mtk_composite cpu_muxes[] __initconst = {
With the above small fixes, this one is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
+ MUX(CLK_INFRA_CA53SEL
On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen yingjoe.c...@mediatek.com wrote:
Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: Yingjoe Chen yingjoe.c...@mediatek.com
---
drivers/clk/mediatek/clk-mt8173.c | 5 +
include/dt-bindings/clock/mt8173-clk.h | 3 ++-
2 files
On Tue, Jul 14, 2015 at 5:46 PM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
On Tue, 2015-07-14 at 11:23 +0800, Daniel Kurtz wrote:
On Tue, Jul 14, 2015 at 10:45 AM, James Liao jamesjj.l...@mediatek.com
wrote:
On Mon, 2015-07-13 at 22:46 +0800, Daniel Kurtz wrote:
+static
Hi Chunfeng,
On Wed, Jul 8, 2015 at 5:41 PM, Chunfeng Yun chunfeng@mediatek.com wrote:
Signed-off-by: Chunfeng Yun chunfeng@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 15 +++
arch/arm64/boot/dts/mediatek/mt8173.dtsi| 27 +++
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
Changes in v4:
- Address comments for v3
- Rebase to the patch that adds 13mhz clock for MT8173[1]
Changes in v3:
- Rebase to 4.2-rc1
- Fix some issues of v2
Changes in v2:
- Remove use of .determine_rate callback
[1] http
On Tue, Jul 14, 2015 at 12:26 PM, Daniel Kurtz wrote:
> On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen
> wrote:
>> From: Daniel Kurtz
>>
>> Add device node to enable GPT timer. This timer will be
>> used as sched clock source.
>>
>> Signed-off-by: D
On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen wrote:
> From: Daniel Kurtz
>
> Add device node to enable GPT timer. This timer will be
> used as sched clock source.
>
> Signed-off-by: Daniel Kurtz
> Signed-off-by: Eddie Huang
> Signed-off-by: Yingjoe Chen
This bin
On Tue, Jul 14, 2015 at 10:45 AM, James Liao wrote:
> Hi Daniel,
>
> On Mon, 2015-07-13 at 22:46 +0800, Daniel Kurtz wrote:
>
>> > +static const struct clk_ops mtk_ref2usb_tx_ops = {
>> > + .is_prepared= mtk_ref2usb_tx_is_prepared,
>> > + .
Hi James,
On Fri, Jul 10, 2015 at 6:00 PM, James Liao wrote:
> Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
> is needed by USB 3.0.
>
> Signed-off-by: James Liao
> ---
> drivers/clk/mediatek/clk-mt8173.c | 143
> +
>
On Mon, Jul 13, 2015 at 5:04 PM, YH Huang wrote:
> Add display PWM driver support to modify backlight for MT8173 and MT6595.
> The PWM has one channel to control the brightness of the display.
> When the (high_width / period) is closer to 1, the screen is brighter;
> otherwise, it is darker.
>
>
On Mon, Jul 13, 2015 at 5:04 PM, YH Huang wrote:
> Document the device-tree binding of MediatTek display PWM.
> The PWM has one channel to control the backlight brightness for display.
> It supports MT8173 and MT6595.
>
> Signed-off-by: YH Huang
> ---
>
On Mon, Jul 13, 2015 at 5:04 PM, YH Huang yh.hu...@mediatek.com wrote:
Document the device-tree binding of MediatTek display PWM.
The PWM has one channel to control the backlight brightness for display.
It supports MT8173 and MT6595.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
On Mon, Jul 13, 2015 at 5:04 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM driver support to modify backlight for MT8173 and MT6595.
The PWM has one channel to control the brightness of the display.
When the (high_width / period) is closer to 1, the screen is brighter;
otherwise,
On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen yingjoe.c...@mediatek.com wrote:
From: Daniel Kurtz djku...@chromium.org
Add device node to enable GPT timer. This timer will be
used as sched clock source.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Signed-off-by: Eddie Huang eddie.hu
On Tue, Jul 14, 2015 at 12:26 PM, Daniel Kurtz djku...@chromium.org wrote:
On Mon, Jul 13, 2015 at 5:32 PM, Yingjoe Chen yingjoe.c...@mediatek.com
wrote:
From: Daniel Kurtz djku...@chromium.org
Add device node to enable GPT timer. This timer will be
used as sched clock source.
Signed-off
On Tue, Jul 14, 2015 at 10:45 AM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
On Mon, 2015-07-13 at 22:46 +0800, Daniel Kurtz wrote:
+static const struct clk_ops mtk_ref2usb_tx_ops = {
+ .is_prepared= mtk_ref2usb_tx_is_prepared,
+ .prepare
Hi James,
On Fri, Jul 10, 2015 at 6:00 PM, James Liao jamesjj.l...@mediatek.com wrote:
Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
drivers/clk/mediatek/clk-mt8173.c | 143
On Wed, Jun 24, 2015 at 2:17 PM, Sascha Hauer wrote:
> This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs.
>
> Signed-off-by: Sascha Hauer
> ---
> .../devicetree/bindings/soc/mediatek/scpsys.txt| 41
> ++
> 1 file changed, 41 insertions(+)
>
On Wed, Jun 24, 2015 at 2:17 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds documentation for the MediaTek SCPSYS unit found in MT8173 SoCs.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
.../devicetree/bindings/soc/mediatek/scpsys.txt| 41
++
1
On Fri, Jul 10, 2015 at 5:16 PM, James Liao wrote:
> This patchset is based on 4.2-rc1 and adds a dummy clock "clk_null"
> to be the root clock of clocks whose parents are not contained in
> CCF clock tree.
>
> In previous patch [1], it seems not suitable to declare clk_null in
> device tree
On Fri, Jul 10, 2015 at 3:27 PM, Eddie Huang wrote:
> Hi all,
>
> On Wed, 2015-07-08 at 13:44 +0800, Sascha Hauer wrote:
>> On Wed, Jul 08, 2015 at 10:37:21AM +0800, Eddie Huang wrote:
>> > On Tue, 2015-07-07 at 23:10 +0800, Daniel Kurtz wrote:
>> > > On Tue, J
On Fri, Jul 10, 2015 at 3:27 PM, Eddie Huang eddie.hu...@mediatek.com wrote:
Hi all,
On Wed, 2015-07-08 at 13:44 +0800, Sascha Hauer wrote:
On Wed, Jul 08, 2015 at 10:37:21AM +0800, Eddie Huang wrote:
On Tue, 2015-07-07 at 23:10 +0800, Daniel Kurtz wrote:
On Tue, Jul 7, 2015 at 10:36 PM
On Fri, Jul 10, 2015 at 5:16 PM, James Liao jamesjj.l...@mediatek.com wrote:
This patchset is based on 4.2-rc1 and adds a dummy clock clk_null
to be the root clock of clocks whose parents are not contained in
CCF clock tree.
In previous patch [1], it seems not suitable to declare clk_null in
On Thu, Jul 9, 2015 at 11:32 AM, Koro Chen wrote:
> This adds afe (audio front end) device node to the MT8173 dtsi file.
>
> Signed-off-by: Koro Chen
Reviewed-by: Daniel Kurtz
I believe this patch depends on the fix in:
https://patchwork.kernel.org/patch/6752521/
If so, I think it w
On Thu, Jul 9, 2015 at 11:32 AM, Koro Chen koro.c...@mediatek.com wrote:
This adds afe (audio front end) device node to the MT8173 dtsi file.
Signed-off-by: Koro Chen koro.c...@mediatek.com
Reviewed-by: Daniel Kurtz djku...@chromium.org
I believe this patch depends on the fix in:
https
On Thu, Jul 9, 2015 at 10:45 AM, YH Huang wrote:
>
> On Wed, 2015-07-08 at 20:11 +0800, Daniel Kurtz wrote:
> > On Mon, Jul 6, 2015 at 9:29 PM, YH Huang wrote:
> > > Document the device-tree binding of MediatTek display PWM.
> > > The PWM has one channel to co
On Mon, Jul 6, 2015 at 9:29 PM, YH Huang wrote:
> Document the device-tree binding of MediatTek display PWM.
> The PWM has one channel to control the backlight brightness for display.
> It supports MT8173 and MT6595.
>
> Signed-off-by: YH Huang
> ---
>
On Mon, Jul 6, 2015 at 9:29 PM, YH Huang yh.hu...@mediatek.com wrote:
Document the device-tree binding of MediatTek display PWM.
The PWM has one channel to control the backlight brightness for display.
It supports MT8173 and MT6595.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
On Thu, Jul 9, 2015 at 10:45 AM, YH Huang yh.hu...@mediatek.com wrote:
On Wed, 2015-07-08 at 20:11 +0800, Daniel Kurtz wrote:
On Mon, Jul 6, 2015 at 9:29 PM, YH Huang yh.hu...@mediatek.com wrote:
Document the device-tree binding of MediatTek display PWM.
The PWM has one channel
On Tue, Jul 7, 2015 at 10:36 PM, Sascha Hauer wrote:
> On Tue, Jul 07, 2015 at 10:15:29PM +0800, Daniel Kurtz wrote:
>> On Tue, Jul 7, 2015 at 9:07 PM, Sascha Hauer wrote:
>> > On Thu, Jun 18, 2015 at 01:29:11PM +0800, Eddie Huang wrote:
>> >> Add clk_null, wh
On Tue, Jul 7, 2015 at 9:07 PM, Sascha Hauer wrote:
> On Thu, Jun 18, 2015 at 01:29:11PM +0800, Eddie Huang wrote:
>> Add clk_null, which represents clocks that can not / need not
>> controlled by software.
>> There are many clocks' parent set to clk_null.
>>
>> Signed-off-by: James Liao
>>
] Previously, we were performing the mmap() without first taking a
reference on the underlying gem buffer. This could leak ptes if the gem
object is destroyed while userspace is still holding the mapping.
Signed-off-by: Daniel Kurtz
Reviewed-by: Daniel Vetter
Cc: sta...@vger.kernel.org
---
drivers/gpu
On Sun, Apr 19, 2015 at 12:55 AM, Heiko Stübner wrote:
>
> Am Donnerstag, 16. April 2015, 16:41:51 schrieb Ørjan Eide:
> > Set vm_pgoff to 0 after using it to look up the GEM node, before passing
> > it on rockchip_gem_mmap_buf() where the offset must be from the start of
> > the buffer.
> >
> >
On Sun, Apr 19, 2015 at 12:55 AM, Heiko Stübner he...@sntech.de wrote:
Am Donnerstag, 16. April 2015, 16:41:51 schrieb Ørjan Eide:
Set vm_pgoff to 0 after using it to look up the GEM node, before passing
it on rockchip_gem_mmap_buf() where the offset must be from the start of
the buffer.
] Previously, we were performing the mmap() without first taking a
reference on the underlying gem buffer. This could leak ptes if the gem
object is destroyed while userspace is still holding the mapping.
Signed-off-by: Daniel Kurtz djku...@chromium.org
Reviewed-by: Daniel Vetter daniel.vet...@ffwll.ch
Cc
On Tue, Jul 7, 2015 at 10:36 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Jul 07, 2015 at 10:15:29PM +0800, Daniel Kurtz wrote:
On Tue, Jul 7, 2015 at 9:07 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Thu, Jun 18, 2015 at 01:29:11PM +0800, Eddie Huang wrote:
Add clk_null
On Tue, Jul 7, 2015 at 9:07 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Thu, Jun 18, 2015 at 01:29:11PM +0800, Eddie Huang wrote:
Add clk_null, which represents clocks that can not / need not
controlled by software.
There are many clocks' parent set to clk_null.
Signed-off-by: James
On Mon, Jul 6, 2015 at 9:29 PM, YH Huang wrote:
> Add display PWM node in mt8173.dtsi.
>
> Signed-off-by: YH Huang
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 ++
> 1 file changed, 22 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
>
On Mon, Jul 6, 2015 at 2:52 PM, Koro Chen wrote:
> This adds afe (audio front end) device node to the MT8173 dtsi file.
>
> This patch is based on Matthias's tree:
> https://github.com/mbgg/linux-mediatek
> branch: v4.2-next/arm64
>
> Signed-off-by: Koro Chen
> ---
>
On Mon, Jul 6, 2015 at 2:52 PM, Koro Chen koro.c...@mediatek.com wrote:
This adds afe (audio front end) device node to the MT8173 dtsi file.
This patch is based on Matthias's tree:
https://github.com/mbgg/linux-mediatek
branch: v4.2-next/arm64
Signed-off-by: Koro Chen koro.c...@mediatek.com
On Mon, Jul 6, 2015 at 9:29 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM node in mt8173.dtsi.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git
clean up the code and provide
> mtk_clock_event_device globally.
> Please add the patch below, which does exactly this.
I don't think this is so hacky.
In light of Stephen's comment about the benefit of using
container_of() to extract gpt_base from the passed in struct
clock_event_device
On Fri, Jul 3, 2015 at 7:40 AM, Stephen Boyd wrote:
> On 07/01/2015 09:26 PM, Daniel Kurtz wrote:
>> On Thu, Jul 2, 2015 at 10:52 AM, James Liao
>> wrote:
>>> Hi Daniel,
>>>
>>>>> +Required Properties:
>>>>> +
>>>>&g
Hi Stephen,
On Fri, Jul 3, 2015 at 7:03 AM, Stephen Boyd wrote:
> On 06/30, James Liao wrote:
>> From: Sascha Hauer
>>
>> On the MT8173 the clocks are provided by different units. To enable
>> the critical clocks we must be sure that all parent clocks are already
>> registered, otherwise the
On Fri, Jul 3, 2015 at 1:38 PM, James Liao wrote:
> Hi Daniel,
>
> On Wed, 2015-07-01 at 23:22 +0800, Daniel Kurtz wrote:
>> This looks like 3 separate gate clocks in a chain, with a timing
>> constraint: USB_LPF must be enabled 100 us after USB_TX.
>>
>>
On Fri, Jul 3, 2015 at 1:15 PM, James Liao wrote:
> On Wed, 2015-07-01 at 22:54 +0800, Daniel Kurtz wrote:
>> On Tue, Jun 30, 2015 at 10:58 AM, James Liao
>> wrote:
>> >
>> > +static struct mtk_gate_regs cg_regs_4_8_0 = {
>>
>> These should al
container_of() to extract gpt_base from the passed in struct
clock_event_device in the other routines, what is the benefit of
making more of mtk_clock_event_device global?
I think what Yingjoe has implemented is short and sweet.
Reviewed-by: Daniel Kurtz djku...@chromium.org
--
To unsubscribe from this list
On Fri, Jul 3, 2015 at 1:15 PM, James Liao jamesjj.l...@mediatek.com wrote:
On Wed, 2015-07-01 at 22:54 +0800, Daniel Kurtz wrote:
On Tue, Jun 30, 2015 at 10:58 AM, James Liao jamesjj.l...@mediatek.com
wrote:
+static struct mtk_gate_regs cg_regs_4_8_0 = {
These should all be:
static
On Fri, Jul 3, 2015 at 1:38 PM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
On Wed, 2015-07-01 at 23:22 +0800, Daniel Kurtz wrote:
This looks like 3 separate gate clocks in a chain, with a timing
constraint: USB_LPF must be enabled 100 us after USB_TX.
26MHz-- [GATE] --USB_TX
Hi Stephen,
On Fri, Jul 3, 2015 at 7:03 AM, Stephen Boyd sb...@codeaurora.org wrote:
On 06/30, James Liao wrote:
From: Sascha Hauer s.ha...@pengutronix.de
On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are
On Fri, Jul 3, 2015 at 7:40 AM, Stephen Boyd sb...@codeaurora.org wrote:
On 07/01/2015 09:26 PM, Daniel Kurtz wrote:
On Thu, Jul 2, 2015 at 10:52 AM, James Liao jamesjj.l...@mediatek.com
wrote:
Hi Daniel,
+Required Properties:
+
+- compatible: Should be:
+ - mediatek,mt8173-imgsys
On Mon, Jun 29, 2015 at 11:24 PM, YH Huang wrote:
> I am sorry for forgetting to remove Change-Id in [PATCH v3 1/2] and
> [PATCH v3 1/2].
>
> Regards,
> YH Huang
>
> On Mon, 2015-06-29 at 23:03 +0800, YH Huang wrote:
>> Document the device-tree binding of MediatTek display PWM.
>> The clock
On Mon, Jun 29, 2015 at 11:03 PM, YH Huang wrote:
> Add display PWM driver support to modify backlight for MT8173 and MT6595.
> The PWM has one channel to control the brightness of the display.
> When the (high_width / period) is closer to 1, the screen is brighter;
> otherwise, it is darker.
>
On Mon, Jun 29, 2015 at 11:03 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM driver support to modify backlight for MT8173 and MT6595.
The PWM has one channel to control the brightness of the display.
When the (high_width / period) is closer to 1, the screen is brighter;
otherwise,
On Mon, Jun 29, 2015 at 11:24 PM, YH Huang yh.hu...@mediatek.com wrote:
I am sorry for forgetting to remove Change-Id in [PATCH v3 1/2] and
[PATCH v3 1/2].
Regards,
YH Huang
On Mon, 2015-06-29 at 23:03 +0800, YH Huang wrote:
Document the device-tree binding of MediatTek display PWM.
The
On Thu, Jul 2, 2015 at 10:52 AM, James Liao wrote:
> Hi Daniel,
>
>> > +Required Properties:
>> > +
>> > +- compatible: Should be:
>> > + - "mediatek,mt8173-imgsys", "syscon"
>> > +- #clock-cells: Must be 1
>> > +
>> > +The imgsys controller uses the common clk binding from
>> >
On Thu, Jul 2, 2015 at 11:06 AM, James Liao wrote:
> Hi Daniel,
>
> On Wed, 2015-07-01 at 19:54 +0800, Daniel Kurtz wrote:
>> On Wed, Jul 1, 2015 at 2:49 PM, Sascha Hauer wrote:
>> > The problem is not that you use fixed clocks for non software
>> > cont
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu wrote:
> Signed-off-by: Leilk Liu
> ---
> .../devicetree/bindings/spi/spi-mt65xx.txt | 32
> ++
> 1 file changed, 32 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/spi/spi-mt65xx.txt
>
> diff --git
On Wed, Jul 1, 2015 at 10:21 PM, Daniel Kurtz wrote:
> Hi James,
>
> To be precise, it is the CLK_TOP clocks that have CLK_APMIXED PLLs as
> their parents, so we cannot enable the CLK_TOP critical clocks until
> the CLK_APMIXED clocks have all been registered.
>
> Plea
the best way to model the delay; but in theory that could
be handled by the clock user (USB driver).
-Dan
On Wed, Jul 1, 2015 at 11:22 PM, Daniel Kurtz wrote:
> Hi James,
>
> This looks like 3 separate gate clocks in a chain, with a timing constraint:
> USB_LPF must be enabled 100 us a
On Tue, Jun 30, 2015 at 10:58 AM, James Liao wrote:
> Most multimedia subsystem clocks will be accessed by multiple
> drivers, so it's a better way to manage these clocks in CCF.
> This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
> subsystems.
>
> Signed-off-by: James Liao
> ---
clk_onecell_data *mt8173_top_clk_data;
> +static struct clk_onecell_data *mt8173_pll_clk_data;
These globals can be:
__initdata
> +
> +static void mtk_clk_enable_critical(void)
And this function is:
static void __init
Other than the above, this one is:
Reviewed-by: Daniel
On Tue, Jun 30, 2015 at 10:58 AM, James Liao wrote:
>
> This adds the binding documentation for the mmsys, imgsys, vdecsys,
> vencsys and vencltsys controllers found on Mediatek SoCs.
>
> Signed-off-by: James Liao
> ---
> .../bindings/arm/mediatek/mediatek,imgsys.txt | 22
>
On Wed, Jul 1, 2015 at 2:49 PM, Sascha Hauer wrote:
>
> On Tue, Jun 30, 2015 at 05:07:09PM +0800, James Liao wrote:
> > Hi Heiko,
> >
> > There are 4 clocks which are derived from clk_null directly in current
> > topckgen implementation:
> >
> > clkph_mck_o, dpi_ck, usb_syspll_125m,
On Tue, Jun 30, 2015 at 10:58 AM, James Liao jamesjj.l...@mediatek.com wrote:
This adds the binding documentation for the mmsys, imgsys, vdecsys,
vencsys and vencltsys controllers found on Mediatek SoCs.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
---
;
+static struct clk_onecell_data *mt8173_pll_clk_data;
These globals can be:
__initdata
+
+static void mtk_clk_enable_critical(void)
And this function is:
static void __init
Other than the above, this one is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
-Dan
On Wed, Jul 1, 2015 at 2:49 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, Jun 30, 2015 at 05:07:09PM +0800, James Liao wrote:
Hi Heiko,
There are 4 clocks which are derived from clk_null directly in current
topckgen implementation:
clkph_mck_o, dpi_ck, usb_syspll_125m,
On Tue, Jun 30, 2015 at 10:58 AM, James Liao jamesjj.l...@mediatek.com wrote:
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
to model the delay; but in theory that could
be handled by the clock user (USB driver).
-Dan
On Wed, Jul 1, 2015 at 11:22 PM, Daniel Kurtz djku...@chromium.org wrote:
Hi James,
This looks like 3 separate gate clocks in a chain, with a timing constraint:
USB_LPF must be enabled 100 us after USB_TX
On Thu, Jul 2, 2015 at 11:06 AM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
On Wed, 2015-07-01 at 19:54 +0800, Daniel Kurtz wrote:
On Wed, Jul 1, 2015 at 2:49 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
The problem is not that you use fixed clocks for non software
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu leilk@mediatek.com wrote:
Signed-off-by: Leilk Liu leilk@mediatek.com
---
.../devicetree/bindings/spi/spi-mt65xx.txt | 32
++
1 file changed, 32 insertions(+)
create mode 100644
On Thu, Jul 2, 2015 at 10:52 AM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
+Required Properties:
+
+- compatible: Should be:
+ - mediatek,mt8173-imgsys, syscon
+- #clock-cells: Must be 1
+
+The imgsys controller uses the common clk binding from
On Wed, Jul 1, 2015 at 10:21 PM, Daniel Kurtz djku...@chromium.org wrote:
Hi James,
To be precise, it is the CLK_TOP clocks that have CLK_APMIXED PLLs as
their parents, so we cannot enable the CLK_TOP critical clocks until
the CLK_APMIXED clocks have all been registered.
Please add
Hi Leilk,
Please see comments inline...
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu wrote:
> This patch adds basic spi bus for MT8173.
>
> Signed-off-by: Leilk Liu
> Signed-off-by: Eddie Huang
> ---
> drivers/spi/Kconfig | 9 +
> drivers/spi/Makefile | 1 +
>
Hi Leilk,
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu wrote:
> This patch adds MT8173 spi bus controllers into device tree.
>
> Signed-off-by: Leilk Liu
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git
Hi YH,
Please also include a patch that adds PWM bindings to mt8173.dtsi.
The clock definitions (CLK_MM_DISP_PWM*) are added by James LIao's patch:
clk: mediatek: Add subsystem clocks of MT8173
I think it is ok to mention in the cover-letter that the PWM .dtsi
change depends on that other
Hi Leilk,
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu leilk@mediatek.com wrote:
This patch adds MT8173 spi bus controllers into device tree.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
Hi Leilk,
Please see comments inline...
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu leilk@mediatek.com wrote:
This patch adds basic spi bus for MT8173.
Signed-off-by: Leilk Liu leilk@mediatek.com
Signed-off-by: Eddie Huang eddie.hu...@mediatek.com
---
drivers/spi/Kconfig | 9
Hi YH,
Please also include a patch that adds PWM bindings to mt8173.dtsi.
The clock definitions (CLK_MM_DISP_PWM*) are added by James LIao's patch:
clk: mediatek: Add subsystem clocks of MT8173
I think it is ok to mention in the cover-letter that the PWM .dtsi
change depends on that other
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