Hi Leilk,
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu wrote:
> This patch adds MT8173 spi bus controllers into device tree.
>
> Signed-off-by: Leilk Liu
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
> 1 file changed, 9 insertions(+)
>
> diff --git
On Thu, Jun 18, 2015 at 10:28 AM, Eddie Huang wrote:
>
> Hi Dan,
>
> On Thu, 2015-06-18 at 10:04 +0800, Eddie Huang wrote:
> > Hi Dan,
> >
> > On Tue, 2015-06-16 at 20:20 +0800, Daniel Kurtz wrote:
> > > On Tue, Jun 16, 2015 at 7:39 PM, Daniel Kurtz
&g
On Thu, Jun 18, 2015 at 10:28 AM, Eddie Huang eddie.hu...@mediatek.com wrote:
Hi Dan,
On Thu, 2015-06-18 at 10:04 +0800, Eddie Huang wrote:
Hi Dan,
On Tue, 2015-06-16 at 20:20 +0800, Daniel Kurtz wrote:
On Tue, Jun 16, 2015 at 7:39 PM, Daniel Kurtz djku...@chromium.org
wrote
Hi Leilk,
On Mon, Jun 29, 2015 at 9:04 PM, Leilk Liu leilk@mediatek.com wrote:
This patch adds MT8173 spi bus controllers into device tree.
Signed-off-by: Leilk Liu leilk@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
e I have put it to drivers/soc/mediatek. As the SCPSYS unit has
> several other tasks that also do not fit into some specific subsystem
> this probably is a good place for this driver.
>
> Please review, any input welcome.
For the series:
Reviewed-by: Daniel Kurtz
>
> Sascha
Hi Matthias,
On Wed, Jun 24, 2015 at 4:04 AM, Matthias Brugger
wrote:
> On Monday, June 01, 2015 09:08:27 PM Eddie Huang wrote:
>> Add MT8173 I2C device nodes, include I2C controllers and pins.
>> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
>> The 6th I2C controller register
/mediatek. As the SCPSYS unit has
several other tasks that also do not fit into some specific subsystem
this probably is a good place for this driver.
Please review, any input welcome.
For the series:
Reviewed-by: Daniel Kurtz djku...@chromium.org
Sascha
changes since v5:
- Fix array out
Hi Matthias,
On Wed, Jun 24, 2015 at 4:04 AM, Matthias Brugger
matthias@gmail.com wrote:
On Monday, June 01, 2015 09:08:27 PM Eddie Huang wrote:
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C
ion
> + * @regmap: The infracfg regmap
> + * @mask: The mask containing the protection bits to be enabled.
> + *
> + * This function enables the bus protection bits for disabled power
> + * domains so that the system does not hanf when some unit accesses the
typo: hanf -&g
On Mon, Jun 22, 2015 at 2:35 PM, Sascha Hauer wrote:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency
On Mon, Jun 22, 2015 at 11:36 AM, Eddie Huang wrote:
> Hi Dan,
>
> On Thu, 2015-06-18 at 23:16 +0800, Daniel Kurtz wrote:
>> On Wed, Jun 17, 2015 at 11:08 PM, Eddie Huang
>> wrote:
>> > Add MT8173 I2C device nodes, include I2C controllers and pins.
>> > MT
On Mon, Jun 22, 2015 at 11:36 AM, Eddie Huang eddie.hu...@mediatek.com wrote:
Hi Dan,
On Thu, 2015-06-18 at 23:16 +0800, Daniel Kurtz wrote:
On Wed, Jun 17, 2015 at 11:08 PM, Eddie Huang eddie.hu...@mediatek.com
wrote:
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173
On Mon, Jun 22, 2015 at 2:35 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic
power
+ * domains so that the system does not hanf when some unit accesses the
typo: hanf - hang
Other than that tiny nit, this one is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
+ * bus while in power down.
+ */
+int mtk_infracfg_set_bus_protection(struct regmap *infracfg, u32 mask
On Wed, Jun 17, 2015 at 11:08 PM, Eddie Huang wrote:
> Add MT8173 I2C device nodes, include I2C controllers and pins.
> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> The 6th I2C controller register base doesn't next to 5th I2C,
> and there is a hardware between 5th and 6th
On Wed, Jun 17, 2015 at 11:08 PM, Eddie Huang eddie.hu...@mediatek.com wrote:
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a hardware
On Tue, Jun 16, 2015 at 10:55 PM, Will Deacon wrote:
> On Tue, Jun 16, 2015 at 03:35:41PM +0100, Daniel Kurtz wrote:
>> The cros-ec-keyboard.dtsi snippet is useful for both arm and arm64 boards.
>> Create a link between the two.
>>
>> This may not be the most sca
The cros-ec-keyboard.dtsi snippet is useful for both arm and arm64 boards.
Create a link between the two.
This may not be the most scalable solution, so consider it temporary until
we find a more central repository for such shared .dtsi snippets.
Signed-off-by: Daniel Kurtz
---
arch/arm64/boot
On Tue, Jun 16, 2015 at 7:39 PM, Daniel Kurtz wrote:
> Hi Chaotian,
>
> On Mon, Jun 15, 2015 at 7:20 PM, Chaotian Jing
> wrote:
>> From: Eddie Huang
>>
>> Add node mmc0 ~ mmc3 for mt8173.dtsi
>> Add node mmc0, mmc1 for mt8173-evb.dts
>>
>> Signe
On Fri, Jun 12, 2015 at 5:27 PM, Eddie Huang wrote:
> Add MT8173 watchdog device node.
>
> Signed-off-by: Eddie Huang
This one is:
Reviewed-by: Daniel Kurtz
It is also independent of the i2c nodes, and as far as I can tell can
go in already.
Thanks!
-Dan
> ---
> arch
Hi Chaotian,
On Mon, Jun 15, 2015 at 7:20 PM, Chaotian Jing
wrote:
> From: Eddie Huang
>
> Add node mmc0 ~ mmc3 for mt8173.dtsi
> Add node mmc0, mmc1 for mt8173-evb.dts
>
> Signed-off-by: Chaotian Jing
> Signed-off-by: Eddie Huang
> ---
> arch/arm64/boot/dts/mediatek/mt8173-evb.dts | 126
>
On Tue, Jun 16, 2015 at 7:39 PM, Daniel Kurtz djku...@chromium.org wrote:
Hi Chaotian,
On Mon, Jun 15, 2015 at 7:20 PM, Chaotian Jing
chaotian.j...@mediatek.com wrote:
From: Eddie Huang eddie.hu...@mediatek.com
Add node mmc0 ~ mmc3 for mt8173.dtsi
Add node mmc0, mmc1 for mt8173-evb.dts
The cros-ec-keyboard.dtsi snippet is useful for both arm and arm64 boards.
Create a link between the two.
This may not be the most scalable solution, so consider it temporary until
we find a more central repository for such shared .dtsi snippets.
Signed-off-by: Daniel Kurtz djku...@chromium.org
On Tue, Jun 16, 2015 at 10:55 PM, Will Deacon will.dea...@arm.com wrote:
On Tue, Jun 16, 2015 at 03:35:41PM +0100, Daniel Kurtz wrote:
The cros-ec-keyboard.dtsi snippet is useful for both arm and arm64 boards.
Create a link between the two.
This may not be the most scalable solution, so
Hi Chaotian,
On Mon, Jun 15, 2015 at 7:20 PM, Chaotian Jing
chaotian.j...@mediatek.com wrote:
From: Eddie Huang eddie.hu...@mediatek.com
Add node mmc0 ~ mmc3 for mt8173.dtsi
Add node mmc0, mmc1 for mt8173-evb.dts
Signed-off-by: Chaotian Jing chaotian.j...@mediatek.com
Signed-off-by: Eddie
On Fri, Jun 12, 2015 at 5:27 PM, Eddie Huang eddie.hu...@mediatek.com wrote:
Add MT8173 watchdog device node.
Signed-off-by: Eddie Huang eddie.hu...@mediatek.com
This one is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
It is also independent of the i2c nodes, and as far as I can tell can
Hi Eddie,
On Fri, Jun 12, 2015 at 5:27 PM, Eddie Huang wrote:
>
> Add MT8173 I2C device nodes, include I2C controllers and pins.
> MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
> The 6th I2C controller register base doesn't next to 5th I2C,
> and there is a hardware between
Hi Eddie,
On Fri, Jun 12, 2015 at 5:27 PM, Eddie Huang eddie.hu...@mediatek.com wrote:
Add MT8173 I2C device nodes, include I2C controllers and pins.
MT8173 has six I2C controllers, from i2c0 to i2c6, exclude i2c5.
The 6th I2C controller register base doesn't next to 5th I2C,
and there is a
Hi James,
On Fri, May 22, 2015 at 1:40 PM, James Liao wrote:
> Hi Daniel,
>
> On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
>> On Fri, May 22, 2015 at 10:41 AM, James Liao
>> wrote:
>> >
>> > Sascha is right. I had confirmed with our desig
Hi James,
On Fri, May 22, 2015 at 1:40 PM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
On Fri, 2015-05-22 at 12:19 +0800, Daniel Kurtz wrote:
On Fri, May 22, 2015 at 10:41 AM, James Liao jamesjj.l...@mediatek.com
wrote:
Sascha is right. I had confirmed with our designer
Hi James,
On Thu, May 21, 2015 at 3:12 PM, James Liao wrote:
> Most multimedia subsystem clocks will be accessed by multiple
> drivers, so it's a better way to manage these clocks in CCF.
> This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
> subsystems.
Is there a reason why
On Fri, May 22, 2015 at 10:41 AM, James Liao wrote:
> Hi Daniel,
>
> On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
>> On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
>> > > + scpsys: scpsys@10006000 {
>> > > +
eems to be never used. Please delete it.
>>>
>>> > + struct clk *clk[MTK_CLK_MAX];
>>> > +};
>>> > +
>>> > +struct mtk_smi_larb {
>>> > + void __iomem*base;
>>> > + spinlock_t portlock; /*
On Thu, May 21, 2015 at 4:53 PM, Eddie Huang wrote:
> This series is for Mediatek SoCs I2C controller common bus driver.
>
> Earlier MTK SoC (for example, MT6589, MT8135) I2C HW has some limitations.
> New generation SoC like MT8173 fix following limitations:
>
> 1. Only support one i2c_msg
On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer wrote:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git
On Wed, May 20, 2015 at 10:19 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds the SCPSYS device node to the MT8173 dtsi file.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff
On Thu, May 21, 2015 at 4:53 PM, Eddie Huang eddie.hu...@mediatek.com wrote:
This series is for Mediatek SoCs I2C controller common bus driver.
Earlier MTK SoC (for example, MT6589, MT8135) I2C HW has some limitations.
New generation SoC like MT8173 fix following limitations:
1. Only support
; /* lock for config port */
+ struct clk *clk[MTK_CLK_MAX];
+ struct device *smi;
+};
+
Thanks,
Matthias
--
motzblog.wordpress.com
--
Daniel Kurtz | Software Engineer | djku...@google.com | 650.204.0722
--
To unsubscribe from this list: send
On Fri, May 22, 2015 at 10:41 AM, James Liao jamesjj.l...@mediatek.com wrote:
Hi Daniel,
On Thu, 2015-05-21 at 19:49 +0200, Sascha Hauer wrote:
On Thu, May 21, 2015 at 10:32:40PM +0800, Daniel Kurtz wrote:
+ scpsys: scpsys@10006000 {
+ compatible
Hi James,
On Thu, May 21, 2015 at 3:12 PM, James Liao jamesjj.l...@mediatek.com wrote:
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.
Is
Fix indentation nits to make mt8173.dtsi more consistent.
Signed-off-by: Eddie Huang
Signed-off-by: Daniel Kurtz
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b
Fix indentation nits to make mt8173.dtsi more consistent.
Signed-off-by: Eddie Huang eddie.hu...@mediatek.com
Signed-off-by: Daniel Kurtz djku...@chromium.org
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 19 +--
1 file changed, 9 insertions(+), 10 deletions(-)
diff --git
On Tue, May 19, 2015 at 3:45 PM, Sascha Hauer wrote:
> On Tue, May 19, 2015 at 02:54:41PM +0800, Daniel Kurtz wrote:
>> >> > + while (1) {
>> >> > + ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1,
>>
On Mon, May 18, 2015 at 4:16 PM, Sascha Hauer wrote:
> Hi Daniel,
>
> On Fri, May 15, 2015 at 10:17:33PM +0800, Daniel Kurtz wrote:
>> Hi Sascha,
>>
>> On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer wrote:
>> > This adds support for some miscellan
On Mon, May 18, 2015 at 4:16 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
Hi Daniel,
On Fri, May 15, 2015 at 10:17:33PM +0800, Daniel Kurtz wrote:
Hi Sascha,
On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds support for some miscellaneous bits
On Tue, May 19, 2015 at 3:45 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
On Tue, May 19, 2015 at 02:54:41PM +0800, Daniel Kurtz wrote:
+ while (1) {
+ ret = regmap_read(infracfg, INFRA_TOPAXI_PROTECTSTA1,
val);
+ if (ret
On Mon, May 11, 2015 at 5:26 PM, YH Huang wrote:
> Add display PWM driver support to modify backlight for MT8173/MT6595.
>
> Signed-off-by: YH Huang
> ---
> drivers/pwm/Kconfig | 9 ++
> drivers/pwm/Makefile| 1 +
> drivers/pwm/pwm-disp-mediatek.c | 225
>
On Mon, May 11, 2015 at 5:26 PM, YH Huang yh.hu...@mediatek.com wrote:
Add display PWM driver support to modify backlight for MT8173/MT6595.
Signed-off-by: YH Huang yh.hu...@mediatek.com
---
drivers/pwm/Kconfig | 9 ++
drivers/pwm/Makefile| 1 +
create mode 100644 drivers/iommu/io-pgtable-arm-short.c
> create mode 100644 drivers/iommu/mtk_iommu.c
> create mode 100644 drivers/soc/mediatek/mt8173-smi.c
> create mode 100644 include/dt-bindings/iommu/mt8173-iommu-port.h
> create mode 100644 include/linux/mtk-smi.h
>
>
/iommu/io-pgtable-arm-short.c
create mode 100644 drivers/iommu/mtk_iommu.c
create mode 100644 drivers/soc/mediatek/mt8173-smi.c
create mode 100644 include/dt-bindings/iommu/mt8173-iommu-port.h
create mode 100644 include/linux/mtk-smi.h
--
1.8.1.1.dirty
--
Daniel Kurtz | Software Engineer
On Mon, May 11, 2015 at 9:11 PM, Sascha Hauer wrote:
> This adds the SCPSYS device node to the MT8173 dtsi file.
>
> Signed-off-by: Sascha Hauer
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12
> 1 file changed, 12 insertions(+)
>
> diff --git
Hi Sascha,
On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer wrote:
> This adds support for some miscellaneous bits of the infracfg controller.
> The mtk_infracfg_set/clear_bus_protection functions are necessary for
> the scpsys power domain driver to handle the bus protection bits which
> are
On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer wrote:
> This adds a power domain driver for the Mediatek SCPSYS unit.
>
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. The tasks include thermal
> measurement, dynamic voltage frequency
On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds a power domain driver for the Mediatek SCPSYS unit.
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. The tasks include thermal
measurement, dynamic
On Mon, May 11, 2015 at 9:11 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds the SCPSYS device node to the MT8173 dtsi file.
Signed-off-by: Sascha Hauer s.ha...@pengutronix.de
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12
1 file changed, 12 insertions(+)
diff
Hi Sascha,
On Tue, May 12, 2015 at 3:23 AM, Sascha Hauer s.ha...@pengutronix.de wrote:
This adds support for some miscellaneous bits of the infracfg controller.
The mtk_infracfg_set/clear_bus_protection functions are necessary for
the scpsys power domain driver to handle the bus protection
Hi Alexandre,
On Sat, May 9, 2015 at 9:08 PM, Alexandre Belloni
wrote:
> On 06/05/2015 at 15:23:39 +0800, Eddie Huang wrote :
>> RTC is one submodule of Mediatek MT6397 PMIC chip[1]. This series
>> support RTC driver that work with Mediatek SoC like MT8135, MT8173.
>> It implements second
Hi Alexandre,
On Sat, May 9, 2015 at 9:08 PM, Alexandre Belloni
alexandre.bell...@free-electrons.com wrote:
On 06/05/2015 at 15:23:39 +0800, Eddie Huang wrote :
RTC is one submodule of Mediatek MT6397 PMIC chip[1]. This series
support RTC driver that work with Mediatek SoC like MT8135, MT8173.
On Tue, Apr 28, 2015 at 5:23 PM, Yingjoe Chen wrote:
>
> The 8173 pinctrl node doesn't follow dts convention. Fix them.
> Also add a comment to explain pinctrl register usage to make it
> more clear.
>
> Signed-off-by: Yingjoe Chen
Thanks for the fix.
Reviewe
.
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 8346c0f..e4a30cd 100644
mments start are
supposed to start with a single "/*"
[0] https://www.kernel.org/doc/Documentation/CodingStyle
Other than that, this patch is
Reviewed-by: Daniel Kurtz
Thanks for sending this up!
>
> + vma->vm_pgoff = 0;
> +
> obj = contain
ith the cookie value still in vma->vm_pgoff.
>
> rockchip_gem_mmap_buf() in drivers/gpu/drm/rockchip/rockchip_drm_gem.c
> still does this. It should be fixed before fixing
> arm_iommu_mmap_attrs().
>
> Signed-off-by: Ørjan Eide
Reviewed-by: Daniel Kurtz
I tested this patch on my
-vm_pgoff.
rockchip_gem_mmap_buf() in drivers/gpu/drm/rockchip/rockchip_drm_gem.c
still does this. It should be fixed before fixing
arm_iommu_mmap_attrs().
Signed-off-by: Ørjan Eide orjan.e...@arm.com
Reviewed-by: Daniel Kurtz djku...@chromium.org
I tested this patch on my RK3288 board
://www.kernel.org/doc/Documentation/CodingStyle
Other than that, this patch is
Reviewed-by: Daniel Kurtz djku...@chromium.org
Thanks for sending this up!
+ vma-vm_pgoff = 0;
+
obj = container_of(node, struct drm_gem_object, vma_node);
ret = rockchip_gem_mmap_buf(obj, vma
Hi Sascha,
Drive-by review...
On Sun, Feb 22, 2015 at 7:49 PM, Sascha Hauer wrote:
> From: James Liao
>
> This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs,
> INFRA and PERI clocks.
>
> Signed-off-by: James Liao
> Signed-off-by: Henry Chen
> Signed-off-by: Sascha Hauer
> ---
Hi Sascha,
Drive-by review...
On Sun, Feb 22, 2015 at 7:49 PM, Sascha Hauer s.ha...@pengutronix.de wrote:
From: James Liao jamesjj.l...@mediatek.com
This patch adds basic clocks for MT8135, including TOPCKGEN, PLLs,
INFRA and PERI clocks.
Signed-off-by: James Liao jamesjj.l...@mediatek.com
Hi Yong Wu,
On Fri, Mar 6, 2015 at 6:48 PM, wrote:
> From: Yong Wu
>
> This patch adds support for mediatek m4u (MultiMedia Memory Management Unit).
> Currently this only supports m4u gen 2 with 2 levels of page table on mt8173.
>
> Signed-off-by: Yong Wu
> ---
> drivers/iommu/Kconfig
Hi Yong,
On Fri, Mar 6, 2015 at 6:37 PM, wrote:
> From: Yong Wu
>
> This patch add SMI(Smart Multimedia Interface) driver. This driver
> is responsible to enable/disable iommu and control the clocks of each
> local arbiter.
High-level:
Is there more to the smi (or smi-larb) driver, or is
educe one level of indirection
makes the code slightly more readable."
, but otherwise this is:
Reviewed-by: Daniel Kurtz
> ---
>
> Changes in v2: None
>
> drivers/gpu/drm/bridge/dw_hdmi.c | 8
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git
Hi Yong,
On Fri, Mar 6, 2015 at 6:37 PM, yong...@mediatek.com wrote:
From: Yong Wu yong...@mediatek.com
This patch add SMI(Smart Multimedia Interface) driver. This driver
is responsible to enable/disable iommu and control the clocks of each
local arbiter.
High-level:
Is there more to
Hi Yong Wu,
On Fri, Mar 6, 2015 at 6:48 PM, yong...@mediatek.com wrote:
From: Yong Wu yong...@mediatek.com
This patch adds support for mediatek m4u (MultiMedia Memory Management Unit).
Currently this only supports m4u gen 2 with 2 levels of page table on mt8173.
Signed-off-by: Yong Wu
more readable.
, but otherwise this is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
Changes in v2: None
drivers/gpu/drm/bridge/dw_hdmi.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/bridge/dw_hdmi.c
b/drivers/gpu/drm/bridge/dw_hdmi.c
Hi Yong,
On Fri, Mar 6, 2015 at 6:48 PM, wrote:
> From: Yong Wu
>
> This patch add the iommu/larbs nodes for mt8173
>
> Signed-off-by: Yong Wu
> ---
> arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60
> include/dt-bindings/iommu/mt8173-iommu-port.h | 127
>
Hi Yong,
On Fri, Mar 6, 2015 at 6:48 PM, yong...@mediatek.com wrote:
From: Yong Wu yong...@mediatek.com
This patch add the iommu/larbs nodes for mt8173
Signed-off-by: Yong Wu yong...@mediatek.com
---
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 60
On Tue, Feb 3, 2015 at 11:12 PM, Yakir Yang wrote:
> Signed-off-by: Yakir Yang
Reviewed-by: Daniel Kurtz
> ---
> Changes in v3:
> - Combine hdmi_set_clock_regenerator_n() and hdmi_regenerate_cts()
>
> Changes in v2: None
>
> drivers/gpu/drm/bridge/dw_hdmi.c | 16 ++
On Tue, Feb 3, 2015 at 11:11 PM, Yakir Yang wrote:
> By parsing the indentification registers we can know what functions
> are present on the hdmi ip.
>
> Signed-off-by: Yakir Yang
> ---
> Changes in v3:
> - Add ID registers parse and record
>
> Changes in v2: None
>
>
On Tue, Feb 3, 2015 at 11:12 PM, Yakir Yang y...@rock-chips.com wrote:
Signed-off-by: Yakir Yang y...@rock-chips.com
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
Changes in v3:
- Combine hdmi_set_clock_regenerator_n() and hdmi_regenerate_cts()
Changes in v2: None
drivers/gpu/drm
On Tue, Feb 3, 2015 at 11:11 PM, Yakir Yang y...@rock-chips.com wrote:
By parsing the indentification registers we can know what functions
are present on the hdmi ip.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Add ID registers parse and record
Changes in v2: None
On Feb 4, 2015 11:38 AM, "Mark yao" wrote:
>
> On 2015年02月02日 15:53, Daniel Vetter wrote:
>>
>> On Mon, Feb 02, 2015 at 10:30:09AM +0800, Mark yao wrote:
>>>
>>> On 2015年02月02日 10:07, Daniel Kurtz wrote:
>>>>
>>>> Hi M
On Feb 4, 2015 11:38 AM, Mark yao mark@rock-chips.com wrote:
On 2015年02月02日 15:53, Daniel Vetter wrote:
On Mon, Feb 02, 2015 at 10:30:09AM +0800, Mark yao wrote:
On 2015年02月02日 10:07, Daniel Kurtz wrote:
Hi Mark, Heiko,
On Sat, Jan 31, 2015 at 4:41 PM, Mark Yao mark@rock
Hi ykk,
On Fri, Jan 30, 2015 at 7:29 PM, Yakir Yang wrote:
> RK3288's VOP do not support INTERLACE display mode, so we should
> remove those modes out of mode_ok list.
>
> Signed-off-by: Yakir Yang
Reviewed-by: Daniel Kurtz
Can you move this patch out of your hdmi audio patch s
Hi ykk,
On Fri, Jan 30, 2015 at 7:29 PM, Yakir Yang y...@rock-chips.com wrote:
RK3288's VOP do not support INTERLACE display mode, so we should
remove those modes out of mode_ok list.
Signed-off-by: Yakir Yang y...@rock-chips.com
Reviewed-by: Daniel Kurtz djku...@chromium.org
Can you move
Hi ykk,
On Sat, Jan 31, 2015 at 10:34 PM, Yang Kuankuan wrote:
>
> On 01/31/2015 06:48 AM, Russell King - ARM Linux wrote:
>>
>>> +void hdmi_audio_clk_enable(struct dw_hdmi *hdmi)
>>> +{
>>> + if (hdmi->audio_enable)
>>> + return;
>>> +
>>> + mutex_lock(>audio_mutex);
& FS_INTR)) {
> - DRM_ERROR("Unknown VOP IRQs: %#02x\n", active_irqs);
> - return IRQ_NONE;
> + if (active_irqs & DSP_HOLD_VALID_INTR) {
> + if (!completion_done(>dsp_hold_completion))
Why i
Hi ykk,
On Sat, Jan 31, 2015 at 10:34 PM, Yang Kuankuan y...@rock-chips.com wrote:
On 01/31/2015 06:48 AM, Russell King - ARM Linux wrote:
+void hdmi_audio_clk_enable(struct dw_hdmi *hdmi)
+{
+ if (hdmi-audio_enable)
+ return;
+
+ mutex_lock(hdmi-audio_mutex);
(vop-dsp_hold_completion))
Why is this completion_done check needed?
I guess it doesn't help, but isn't strictly needed, since the
dsp_hold_completion is a one shot, right?
In any case, this should work as it is, so:
Reviewed-by: Daniel Kurtz djku...@chromium.org
On Mon, Jan 26, 2015 at 9:47 AM, huang lin wrote:
> The AUO b101ean01 panel is a 10.1" 1280x800 panel,
> which can be supported by the simple panel driver.
>
> Signed-off-by: huang lin
Reviewed-by: Daniel Kurtz
>
> ---
>
> Changes in v4:
> - Add auo,b101ea
On Mon, Jan 26, 2015 at 9:47 AM, huang lin h...@rock-chips.com wrote:
The AUO b101ean01 panel is a 10.1 1280x800 panel,
which can be supported by the simple panel driver.
Signed-off-by: huang lin h...@rock-chips.com
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
Changes in v4:
- Add
9540
> /sys/class/thermal/thermal_zone2/temp:39994
>
> Signed-off-by: Caesar Wang
> Reviewed-by: Dmitry Torokhov
>
> ---
>
> Changes in v5:
> Fixed some style.
>
> Changes in v4:
> "return -EAGAIN" instead of "return rk_tsadcv2_co
-by: Caesar Wang w...@rock-chips.com
Reviewed-by: Dmitry Torokhov dmitry.torok...@gmail.com
---
Changes in v5:
Fixed some style.
Changes in v4:
return -EAGAIN instead of return rk_tsadcv2_code_to_temp(code)
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject code == 0xfff
9540
> /sys/class/thermal/thermal_zone2/temp:39994
>
> Signed-off-by: Caesar Wang
> Reviewed-by: Dmitry Torokhov
>
> ---
>
> Changes in v4:
> "return -EAGAIN" instead of "return rk_tsadcv2_code_to_temp(code)"
>
> Changes in v3:
> Sugge
ady power off at SUSPEND, crash
> so use a bool val is more suitable.
>
> Signed-off-by: Mark Yao
This version looks good. Moving to atomic is definitely important,
and part of the plan.
For now, though, this series is:
Reviewed-by: Daniel Kurtz
> ---
> Changes in v2:
&g
off at SUSPEND, crash
so use a bool val is more suitable.
Signed-off-by: Mark Yao mark@rock-chips.com
This version looks good. Moving to atomic is definitely important,
and part of the plan.
For now, though, this series is:
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
Changes in v2
-by: Caesar Wang w...@rock-chips.com
Reviewed-by: Dmitry Torokhov dmitry.torok...@gmail.com
---
Changes in v4:
return -EAGAIN instead of return rk_tsadcv2_code_to_temp(code)
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject code == 0xfff
Fixed in rk_tsadcv2_code_to_temp
On Thu, Jan 22, 2015 at 12:21 PM, Caesar Wang
wrote:
>
> 在 2015年01月22日 12:01, Daniel Kurtz 写道:
>
>> On Thu, Jan 22, 2015 at 1:29 AM, Caesar Wang wrote:
>>>
>>> In general, the kernel should report temperature readings exactly as
>>> reported by the ha
9540
> /sys/class/thermal/thermal_zone2/temp:39994
>
> Signed-off-by: Caesar Wang
> Reviewed-by: Dmitry Torokhov
>
> ---
>
> Changes in v3:
> Suggested-by Daniel Kurtz,
> the check doesn't reject "code == 0xfff"
> Fixed in rk_tsadcv2_code_to_te
dsp_vsync_pol
> VSYNC polarity
> 1'b0 : negative
> 1'b1 : positive
> dsp_hsync_pol
> HSYNC polarity
> 1'b0 : negative
> 1'b1 : positive
>
> Signed-off-by: Mark Yao
Looks good!
Reviewed-by: Daniel Kurtz
> ---
> drivers/gpu/drm/r
On Thu, Jan 22, 2015 at 12:21 PM, Caesar Wang
caesar.w...@rock-chips.com wrote:
在 2015年01月22日 12:01, Daniel Kurtz 写道:
On Thu, Jan 22, 2015 at 1:29 AM, Caesar Wang w...@rock-chips.com wrote:
In general, the kernel should report temperature readings exactly as
reported by the hardware
:
dsp_vsync_pol
VSYNC polarity
1'b0 : negative
1'b1 : positive
dsp_hsync_pol
HSYNC polarity
1'b0 : negative
1'b1 : positive
Signed-off-by: Mark Yao mark@rock-chips.com
Looks good!
Reviewed-by: Daniel Kurtz djku...@chromium.org
---
drivers/gpu/drm
-by: Caesar Wang w...@rock-chips.com
Reviewed-by: Dmitry Torokhov dmitry.torok...@gmail.com
---
Changes in v3:
Suggested-by Daniel Kurtz,
the check doesn't reject code == 0xfff
Fixed in rk_tsadcv2_code_to_temp(u32 code)
Changes in v2:
Reviewed-by: Dmitry Torokhov dmitry.torok...@gmail.com
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