Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 18.08.2017 19:15, Mikko Perttunen wrote: > Since Tegra186 the Host1x hardware allows syncpoints to be assigned to > specific channels, preventing any other channels from incrementing > them. > > Enable this feature where available and assign syncpoints to channels > when submitting a job.

Re: [PATCH 4/4] drm/tegra: Use u64_to_user_ptr helper

On 18.08.2017 19:15, Mikko Perttunen wrote: > Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values > to user pointers instead of writing out the cast manually. > > Signed-off-by: Mikko Perttunen > --- > drivers/gpu/drm/tegra/drm.c | 9 - > 1 file

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 19.08.2017 11:10, Mikko Perttunen wrote: [snip] >>> +host1x_hw_syncpt_set_protection(host, true); >> >> Is it really okay to force the protection? Maybe protection should be enabled >> with a respect to CONFIG_TEGRA_HOST1X_FIREWALL? In that case we would have to >> avoid software jobs

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 19.08.2017 13:35, Mikko Perttunen wrote: > On 08/19/2017 01:09 PM, Dmitry Osipenko wrote: >> On 19.08.2017 11:10, Mikko Perttunen wrote: >> [snip] >>>>> +host1x_hw_syncpt_set_protection(host, true); >>>> >>>> Is it really

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 19.08.2017 14:32, Mikko Perttunen wrote: > > > On 08/19/2017 02:11 PM, Dmitry Osipenko wrote: >> On 19.08.2017 13:35, Mikko Perttunen wrote: >>> On 08/19/2017 01:09 PM, Dmitry Osipenko wrote: >>>> On 19.08.2017 11:1

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 18.08.2017 19:15, Mikko Perttunen wrote: > Since Tegra186 the Host1x hardware allows syncpoints to be assigned to > specific channels, preventing any other channels from incrementing > them. > > Enable this feature where available and assign syncpoints to channels > when submitting a job.

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 19.08.2017 13:46, Mikko Perttunen wrote: > On 08/19/2017 01:42 PM, Dmitry Osipenko wrote: >> On 18.08.2017 19:15, Mikko Perttunen wrote: >>> The gather filter is a feature present on Tegra124 and newer where the >>> hardware prevents GATHERed command buffers from exec

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 18.08.2017 19:15, Mikko Perttunen wrote: > The gather filter is a feature present on Tegra124 and newer where the > hardware prevents GATHERed command buffers from executing commands > normally reserved for the CDMA pushbuffer which is maintained by the > kernel driver. > > This commit enables

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 18.08.2017 19:15, Mikko Perttunen wrote: > Since Tegra186 the Host1x hardware allows syncpoints to be assigned to > specific channels, preventing any other channels from incrementing > them. > > Enable this feature where available and assign syncpoints to channels > when submitting a job.

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 18.08.2017 19:15, Mikko Perttunen wrote: > The gather filter is a feature present on Tegra124 and newer where the > hardware prevents GATHERed command buffers from executing commands > normally reserved for the CDMA pushbuffer which is maintained by the > kernel driver. > > This commit enables

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 18.08.2017 19:15, Mikko Perttunen wrote: > Since Tegra186 the Host1x hardware allows syncpoints to be assigned to > specific channels, preventing any other channels from incrementing > them. > > Enable this feature where available and assign syncpoints to channels > when submitting a job.

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 20.08.2017 19:44, Dmitry Osipenko wrote: > On 20.08.2017 19:24, Dmitry Osipenko wrote: >> On 18.08.2017 19:15, Mikko Perttunen wrote: >>> The gather filter is a feature present on Tegra124 and newer where the >>> hardware prevents GATHERed command buffers from exec

Re: [PATCH 1/4] gpu: host1x: Enable Tegra186 syncpoint protection

On 18.08.2017 19:15, Mikko Perttunen wrote: > Since Tegra186 the Host1x hardware allows syncpoints to be assigned to > specific channels, preventing any other channels from incrementing > them. > > Enable this feature where available and assign syncpoints to channels > when submitting a job.

Re: [PATCH 2/4] gpu: host1x: Enable gather filter

On 20.08.2017 19:24, Dmitry Osipenko wrote: > On 18.08.2017 19:15, Mikko Perttunen wrote: >> The gather filter is a feature present on Tegra124 and newer where the >> hardware prevents GATHERed command buffers from executing commands >> normally reserved for the CDMA pushbuffe

Re: [PATCH 2/2] iommu/tegra-gart: Add support for struct iommu_device

On 17.08.2017 16:52, Thierry Reding wrote: > On Thu, Aug 17, 2017 at 01:21:52AM +0300, Dmitry Osipenko wrote: >> Hello Joerg, >> >> On 10.08.2017 01:29, Joerg Roedel wrote: >>> From: Joerg Roedel <jroe...@suse.de> >>> >>> Add

Re: [PATCH v2 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

On 22.09.2017 17:02, Mikko Perttunen wrote: > On 09/05/2017 04:33 PM, Dmitry Osipenko wrote: >> On 05.09.2017 11:10, Mikko Perttunen wrote: >>> ... >> diff --git a/drivers/gpu/host1x/hw/channel_hw.c > b/drivers/gpu/host1x/hw/channel_hw.c >>> ind

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 02.10.2017 20:05, Stephen Warren wrote: > On 09/29/2017 09:11 PM, Dmitry Osipenko wrote: >> On 29.09.2017 22:30, Stephen Warren wrote: >>> On 09/27/2017 02:34 AM, Jon Hunter wrote: >>>> >>>> On 27/09/17 02:57, Dmitry Osipenko wrote: &

[PATCH v2 0/2] NVIDIA Tegra20 video decoder driver

- Miscellaneous code cleanups - Changed 'TODO' - CC'd media maintainers for the review as per Greg K-H request, v1 can be viewed at https://lkml.org/lkml/2017/9/25/606 Dmitry Osipenko (2): staging: Introduce NVIDIA Tegra20 video decoder driver ARM: dts: tegra20: Add video

[PATCH v2 2/2] ARM: dts: tegra20: Add video decoder node

Add a device node for the video decoder engine found on Tegra20. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi

[PATCH v2 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports decoding of CAVLC H.264 only. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../bindings/arm/tegra/nvidia,tegra20-vde.txt | 43 + d

[PATCH v2 3/4] clk: tegra20: Use common definition of APBDMA clock gate

The APBDMA clock is defined in the common clock gates table that is used by Tegra30+. Tegra20 can use it too, let's remove the custom definition and use the common one. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk-tegra20.c | 6 +- 1 file changed, 1 ins

[PATCH v2 2/4] clk: tegra: Correct parent of the APBDMA clock

APBDMA represents a clock gate to the APB DMA controller, the actual clock source for the controller is PCLK. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk-tegra-periph.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/tegra/clk

[PATCH v2 4/4] clk: tegra20: Bump SCLK clock rate to 216MHz

AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Acked-By: Peter De Schrijver <pdeschrij...@nvidia.com> --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 fil

[PATCH v2 0/4] Tegra DMA clocks addition / correction

Tegra20 to utilize the 'common' APB DMA clock gate definition. Dmitry Osipenko (4): clk: tegra: Add AHB DMA clock entry clk: tegra: Correct parent of the APBDMA clock clk: tegra20: Use common definition of APBDMA clock gate clk: tegra20: Bump SCLK clock rate to 216MHz drivers/clk

[PATCH v2 1/4] clk: tegra: Add AHB DMA clock entry

AHB DMA engine presents on Tegra20/30. Add missing clock entries, so that driver for the AHB DMA controller could be implemented. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 1 + drivers/clk/teg

Re: [PATCH v2 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

to > help improve the system] > > url: > https://github.com/0day-ci/linux/commits/Dmitry-Osipenko/staging-Introduce-NVIDIA-Tegra20-video-decoder-driver/20171006-101015 > config: ia64-allmodconfig (attached as .config) > compiler: ia64-linux-gcc (GCC) 6.2.0

Re: [PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node

On 12.10.2017 13:57, Jon Hunter wrote: > > On 12/10/17 11:51, Dmitry Osipenko wrote: >> On 12.10.2017 11:49, Jon Hunter wrote: >>> >>> On 11/10/17 21:08, Dmitry Osipenko wrote: >>>> Add a device node for the video decoder engine found on Tegra20. >

Re: [PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node

On 12.10.2017 11:49, Jon Hunter wrote: > > On 11/10/17 21:08, Dmitry Osipenko wrote: >> Add a device node for the video decoder engine found on Tegra20. >> >> Signed-off-by: Dmitry Osipenko <dig...@gmail.com> >> --- >> arch/arm/boot/dts/tegra20.dtsi | 1

Re: [PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node

Hello Vladimir, On 12.10.2017 10:43, Vladimir Zapolskiy wrote: > Hello Dmitry, > > On 10/11/2017 11:08 PM, Dmitry Osipenko wrote: >> Add a device node for the video decoder engine found on Tegra20. >> >> Signed-off-by: Dmitry Osipenko <dig...@gmail.com> >>

Re: [PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node

On 12.10.2017 16:45, Jon Hunter wrote: > > On 12/10/17 14:25, Thierry Reding wrote: >> * PGP Signed by an unknown key >> >> On Thu, Oct 12, 2017 at 03:06:17PM +0300, Dmitry Osipenko wrote: >>> Hello Vladimir, >>> >>> On 12.10.2017

Re: [PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

On 26.09.2017 02:01, Stephen Warren wrote: > On 09/25/2017 04:15 PM, Dmitry Osipenko wrote: >> Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of >> video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports >> decoding of CAVLC H.264 only. &g

[PATCH v1 0/2] NVIDIA Tegra20 video decoder driver

interface, so any video player that supports VDPAU can provide accelerated video decoding on Tegra20 on Linux. [0] https://github.com/grate-driver/libvdpau-tegra Dmitry Osipenko (2): staging: Introduce NVIDIA Tegra20 video decoder driver ARM: dts: tegra20: Add video decoder node .../bindings

[PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry

AHB DMA presents on Tegra20/30. Add missing entries, so that driver for AHB DMA could be implemented. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk-id.h | 1 + drivers/clk/tegra/clk-tegra-periph.c | 1 + drivers/clk/tegra/clk-tegra20.c

[PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

igned-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/dma/Kconfig | 9 + drivers/dma/Makefile | 1 + drivers/dma/tegra20-ahb-dma.c | 679 ++ 3 files changed, 689 insertions(+) create mode 100644 drivers/dma/tegra20-ahb-dm

[PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

Document DT bindings for NVIDIA Tegra AHB DMA controller that presents on Tegra20/30 SoC's. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../bindings/dma/nvidia,tegra20-ahbdma.txt | 23 ++ 1 file changed, 23 insertions(+) create mode 100644 Documen

[PATCH v1 5/5] ARM: dts: tegra: Add AHB DMA controller nodes

Add AHB DMA controller nodes to Tegra20/30 DT's. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 9 + arch/arm/boot/dts/tegra30.dtsi | 9 + 2 files changed, 18 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/bo

[PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver

NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels, supports AHB <-> Memory and Memory <-> Memory transfers, slave / master modes. This driver is primarily supposed to be used by gpu/host1x in a master mode, performing 3D HW context stores. Dmitry Osipenko (5):

[PATCH v1 2/5] clk: tegra: Bump SCLK clock rate to 216MHz on Tegra20

AHB DMA is a running on 1/2 of SCLK rate, APB on 1/4. Increasing SCLK rate results in an increased DMA transfer rate. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/clk/tegra/clk-tegra20.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/teg

[PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports decoding of CAVLC H.264 only. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../bindings/arm/tegra/nvidia,tegra20-vde.txt | 38 + d

[PATCH v1 2/2] ARM: dts: tegra20: Add video decoder node

Add a device node for the video decoder engine found on Tegra20. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 16 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi

Re: [PATCH v1 0/2] NVIDIA Tegra20 video decoder driver

On 27.09.2017 00:35, Greg Kroah-Hartman wrote: > On Tue, Sep 26, 2017 at 03:32:23PM +0300, Dmitry Osipenko wrote: >> On 26.09.2017 09:54, Greg Kroah-Hartman wrote: >>> On Tue, Sep 26, 2017 at 01:15:41AM +0300, Dmitry Osipenko wrote: >>>> This driver provides accele

Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

On 27.09.2017 00:37, Jon Hunter wrote: > Hi Dmitry, > > On 26/09/17 17:06, Dmitry Osipenko wrote: >> Hi Jon, >> >> On 26.09.2017 17:45, Jon Hunter wrote: >>> Hi Dmitry, >>> >>> On 26/09/17 00:22, Dmitry Osipenko wrote: >>>> AHB

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 26.09.2017 17:50, Jon Hunter wrote: > > On 26/09/17 00:22, Dmitry Osipenko wrote: >> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents >> on Tegra20/30 SoC's. >> >> Signed-off-by: Dmitry Osipenko <dig...@gmail.com> >> --- >

Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

Hi Jon, On 26.09.2017 17:45, Jon Hunter wrote: > Hi Dmitry, > > On 26/09/17 00:22, Dmitry Osipenko wrote: >> AHB DMA controller presents on Tegra20/30 SoC's, it supports transfers >> memory <-> AHB bus peripherals as well as mem-to-mem transfers. Driver >> doesn

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 26.09.2017 17:50, Jon Hunter wrote: > > On 26/09/17 00:22, Dmitry Osipenko wrote: >> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents >> on Tegra20/30 SoC's. >> >> Signed-off-by: Dmitry Osipenko <dig...@gmail.com> >> --- >

Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

On 28.09.2017 19:22, Vinod Koul wrote: > On Thu, Sep 28, 2017 at 05:35:59PM +0300, Dmitry Osipenko wrote: >> On 28.09.2017 17:06, Dmitry Osipenko wrote: >>> On 28.09.2017 12:29, Vinod Koul wrote: >>>>> + default: >>>>> + return -EI

Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry

On 26.09.2017 12:56, Peter De Schrijver wrote: > On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote: >> AHB DMA presents on Tegra20/30. Add missing entries, so that driver >> for AHB DMA could be implemented. >> >> Signed-off-by: Dmitry Osipenko <dig...

Re: [PATCH v1 0/2] NVIDIA Tegra20 video decoder driver

On 26.09.2017 09:54, Greg Kroah-Hartman wrote: > On Tue, Sep 26, 2017 at 01:15:41AM +0300, Dmitry Osipenko wrote: >> This driver provides accelerated video decoding to NVIDIA Tegra20 SoC's, >> it is a result of reverse-engineering efforts. Driver has been tested on >> Toshib

Re: [PATCH v3 4/6] gpu: host1x: Disassemble more instructions

On 28.09.2017 15:50, Mikko Perttunen wrote: > The disassembler for debug dumps was missing some newer host1x opcodes. > Add disassembly support for these. > > Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> > --- Reviewed-by: Dmitry Osipenko <dig...@gmail.com

Re: [PATCH v3 6/6] drm/tegra: Use u64_to_user_ptr helper

; > Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> > --- Reviewed-by: Dmitry Osipenko <dig...@gmail.com> Tested-by: Dmitry Osipenko <dig...@gmail.com> > drivers/gpu/drm/tegra/drm.c | 29 +++-- > 1 file changed, 15 insertions(+), 14 deletio

Re: [PATCH v3 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

n submitting a job. Syncpoints are currently never unassigned from > channels since that would require extra work and is unnecessary with > the current channel allocation model. > > Signed-off-by: Mikko Perttunen <mperttu...@nvidia.com> > --- Reviewed-by: Dmitry Osipenko <dig..

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 29.09.2017 22:30, Stephen Warren wrote: > On 09/27/2017 02:34 AM, Jon Hunter wrote: >> >> On 27/09/17 02:57, Dmitry Osipenko wrote: >>> On 26.09.2017 17:50, Jon Hunter wrote: >>>> >>>> On 26/09/17 00:22, Dmitry Osipenko wrote: >>>&g

Re: [PATCH v1 1/5] clk: tegra: Add AHB DMA clock entry

On 27.09.2017 11:36, Peter De Schrijver wrote: > On Tue, Sep 26, 2017 at 05:46:01PM +0300, Dmitry Osipenko wrote: >> On 26.09.2017 12:56, Peter De Schrijver wrote: >>> On Tue, Sep 26, 2017 at 02:22:02AM +0300, Dmitry Osipenko wrote: >>>> AHB DMA presents on Tegra

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 27.09.2017 11:34, Jon Hunter wrote: > > On 27/09/17 02:57, Dmitry Osipenko wrote: >> On 26.09.2017 17:50, Jon Hunter wrote: >>> >>> On 26/09/17 00:22, Dmitry Osipenko wrote: >>>> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 27.09.2017 16:46, Jon Hunter wrote: > > On 27/09/17 14:44, Jon Hunter wrote: >> >> On 27/09/17 13:12, Dmitry Osipenko wrote: >>> On 27.09.2017 11:34, Jon Hunter wrote: >>>> >>>> On 27/09/17 02:57, Dmitry Osipenko wrote: >>>>> O

Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

On 28.09.2017 12:29, Vinod Koul wrote: > On Tue, Sep 26, 2017 at 02:22:05AM +0300, Dmitry Osipenko wrote: > >> +config TEGRA20_AHB_DMA >> +tristate "NVIDIA Tegra20 AHB DMA support" >> +depends on ARCH_TEGRA > > Can we add COMPILE_TEST,

Re: [PATCH v1 0/5] NVIDIA Tegra AHB DMA controller driver

On 28.09.2017 12:31, Vinod Koul wrote: > On Tue, Sep 26, 2017 at 02:22:01AM +0300, Dmitry Osipenko wrote: >> NVIDIA Tegra20/30 SoC's have AHB DMA controller. It has 4 DMA channels, >> supports AHB <-> Memory and Memory <-> Memory transfers, slave / master >>

Re: [PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

On 28.09.2017 10:23, Dan Carpenter wrote: > On Thu, Sep 28, 2017 at 02:28:04AM +0300, Dmitry Osipenko wrote: >>>> + if (is_baseline_profile) >>>> + frame->aux_paddr = 0xF4DEAD00; >>> >>> The handling of is_baseline_profile is strange

Re: [PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

much for the awesome review. I agree with the most of the comments. > On Tue, Sep 26, 2017 at 01:15:42AM +0300, Dmitry Osipenko wrote: >> diff --git a/drivers/staging/tegra-vde/Kconfig >> b/drivers/staging/tegra-vde/Kconfig >> new file mode 100644 >> index 00

Re: [PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

On 27.09.2017 12:45, Dan Carpenter wrote: >> --- /dev/null >> +++ b/drivers/staging/tegra-vde/Kconfig >> @@ -0,0 +1,6 @@ >> +config TEGRA_VDE >> +tristate "NVIDIA Tegra20 video decoder driver" >> +depends on ARCH_TEGRA_2x_SOC > > Could we get a || COMPILE_TEST here as well? > Good

Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

On 28.09.2017 12:29, Vinod Koul wrote: >> +default: >> +return -EINVAL; >> +} >> + >> +ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT; >> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_ADDR_WRAP; >> +ahb_seq |= TEGRA_AHBDMA_CHANNEL_INTR_ENB; >> + >> +

Re: [PATCH v1 4/5] dmaengine: Add driver for NVIDIA Tegra AHB DMA controller

On 28.09.2017 17:06, Dmitry Osipenko wrote: > On 28.09.2017 12:29, Vinod Koul wrote: >>> + default: >>> + return -EINVAL; >>> + } >>> + >>> + ahb_seq = burst << TEGRA_AHBDMA_CHANNEL_AHB_BURST_SHIFT; >>>

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 03.10.2017 13:32, Jon Hunter wrote: > > > On 03/10/17 00:02, Dmitry Osipenko wrote: >> On 02.10.2017 20:05, Stephen Warren wrote: >>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote: >>>> On 29.09.2017 22:30, Stephen Warren wrote: >>&g

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 03.10.2017 18:38, Stephen Warren wrote: > On 10/03/2017 04:32 AM, Jon Hunter wrote: >> >> >> On 03/10/17 00:02, Dmitry Osipenko wrote: >>> On 02.10.2017 20:05, Stephen Warren wrote: >>>> On 09/29/2017 09:11 PM, Dmitry Osipenko wrote: >>>>>

Re: [PATCH v1 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

On 26.09.2017 08:11, Stephen Warren wrote: > On 09/25/2017 05:45 PM, Dmitry Osipenko wrote: >> On 26.09.2017 02:01, Stephen Warren wrote: >>> On 09/25/2017 04:15 PM, Dmitry Osipenko wrote: >>>> Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of

Re: [PATCH v2 1/6] gpu: host1x: Enable Tegra186 syncpoint protection

On 05.09.2017 11:10, Mikko Perttunen wrote: > Since Tegra186 the Host1x hardware allows syncpoints to be assigned to > specific channels, preventing any other channels from incrementing > them. > > Enable this feature where available and assign syncpoints to channels > when submitting a job.

Re: [PATCH v2 6/6] drm/tegra: Use u64_to_user_ptr helper

On 05.09.2017 11:10, Mikko Perttunen wrote: > Use the u64_to_user_ptr helper macro to cast IOCTL argument u64 values > to user pointers instead of writing out the cast manually. > > Signed-off-by: Mikko Perttunen > --- This patch doesn't apply to linux-next, you should

Re: [PATCH v2 4/6] gpu: host1x: Disassemble more instructions

On 05.09.2017 11:10, Mikko Perttunen wrote: > The disassembler for debug dumps was missing some newer host1x opcodes. > Add disassembly support for these. > > Signed-off-by: Mikko Perttunen > --- > drivers/gpu/host1x/hw/debug_hw.c | 57 >

Re: [PATCH v2 5/6] gpu: host1x: Fix incorrect comment for channel_request

May return NULL if CDMA > + * Allocates a new host1x channel for @device. May return NULL if CDMA > * initialization fails. > */ > struct host1x_channel *host1x_channel_request(struct device *dev) > Reviewed-by: Dmitry Osipenko <dig...@gmail.com> -- Dmitry

Re: [PATCH v1 3/5] dt-bindings: Add DT bindings for NVIDIA Tegra AHB DMA controller

On 05.10.2017 23:33, Rob Herring wrote: > On Tue, Sep 26, 2017 at 02:22:04AM +0300, Dmitry Osipenko wrote: >> Document DT bindings for NVIDIA Tegra AHB DMA controller that presents >> on Tegra20/30 SoC's. >> >> Signed-off-by: Dmitry Osipenko <dig...@gmail.com> &

Re: [PATCH 01/11] Initialize the mapping of KASan shadow memory

On 11.10.2017 11:22, Abbott Liu wrote: > From: Andrey Ryabinin > > This patch initializes KASan shadow region's page table and memory. > There are two stage for KASan initializing: > 1. At early boot stage the whole shadow region is mapped to just >one physical page

Re: [PATCH v3 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

On 11.10.2017 23:47, Nicolas Dufresne wrote: > Le mercredi 11 octobre 2017 à 23:08 +0300, Dmitry Osipenko a écrit : >> diff --git a/drivers/staging/tegra-vde/TODO b/drivers/staging/tegra- >> vde/TODO >> new file mode 100644 >> index ..e98bbc7b3c19 >&g

[PATCH v3 2/2] ARM: dts: tegra20: Add video decoder node

Add a device node for the video decoder engine found on Tegra20. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- arch/arm/boot/dts/tegra20.dtsi | 17 + 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi

[PATCH v3 0/2] NVIDIA Tegra20 video decoder driver

Stephen Warren and Dan Carpenter - Implemented runtime PM - Miscellaneous code cleanups - Changed 'TODO' - CC'd media maintainers for the review as per Greg K-H request, v1 can be viewed at https://lkml.org/lkml/2017/9/25/606 Dmitry Osipenko (2): staging

[PATCH v3 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

Video decoder, found on NVIDIA Tegra20 SoC, supports a standard set of video formats like H.264 / MPEG-4 / WMV / VC1. Currently driver supports decoding of CAVLC H.264 only. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- .../bindings/arm/tegra/nvidia,tegra20-vde.txt | 44 + d

Re: [PATCH v3 1/2] staging: Introduce NVIDIA Tegra20 video decoder driver

On 18.10.2017 00:13, Rob Herring wrote: > On Tue, Oct 17, 2017 at 3:24 PM, Thierry Reding > wrote: >> On Tue, Oct 17, 2017 at 03:13:54PM -0500, Rob Herring wrote: >> [...] diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra20-vde.txt

[PATCH v4 0/5] NVIDIA Tegra20 video decoder driver

CC'd media maintainers for the review as per Greg's K-H request, v1 can be viewed at https://lkml.org/lkml/2017/9/25/606 Dmitry Osipenko (4): media: dt: bindings: Add binding for NVIDIA Tegra Video Decoder Engine staging: Introduce NVIDIA Tegra video decoder driver ARM: dts: tegra20:

[PATCH v4 3/5] staging: Introduce NVIDIA Tegra video decoder driver

NVIDIA Tegra20/30/114/124/132 SoC's have video decoder engine that supports standard set of video formats like H.264 / MPEG-4 / WMV / VC1. Currently implemented decoding of CAVLC H.264 on Tegra20 only. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/staging/K

Re: [PATCH 08/10] drm/tegra: Implement dynamic channel allocation model

On 07.11.2017 15:29, Mikko Perttunen wrote: > On 05.11.2017 19:43, Dmitry Osipenko wrote: >> On 05.11.2017 14:01, Mikko Perttunen wrote: >>> In the traditional channel allocation model, a single hardware channel >>> was allocated for each client. This is si

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 29.11.2017 12:10, Mikko Perttunen wrote: > On 12.11.2017 13:23, Dmitry Osipenko wrote: >> On 11.11.2017 00:15, Dmitry Osipenko wrote: >>> On 07.11.2017 18:29, Dmitry Osipenko wrote: >>>> On 07.11.2017 16:11, Mikko Perttunen wrote: >>>>&g

Re: [PATCH 10/10] gpu: host1x: Optionally block when acquiring channel

On 29.11.2017 15:25, Mikko Perttunen wrote: > On 29.11.2017 14:18, Dmitry Osipenko wrote: >> On 29.11.2017 12:10, Mikko Perttunen wrote: >>> On 12.11.2017 13:23, Dmitry Osipenko wrote: >>>> On 11.11.2017 00:15, Dmitry Osipenko wrote: >>>>&g

[PATCH v2] usb: phy: tegra: Increase PHY clock stabilization timeout

This fixes "utmi_phy_clk_enable: timeout waiting for phy to stabilize" error message. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- Change log: v2: Increased delay for the poll retry from 1us to 2000ms, thanks to Thierry Reding for the suggestion. drivers/u

[PATCH v2 1/4] usb: phy: tegra: Cleanup error messages

Tegra's PHY driver has a mix of pr_err() and dev_err(), let's switch to dev_err() and use common errors message formatting across the driver for consistency. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- Change log: v2: Removed function names as per Thierry's suggestion. d

[PATCH v2 3/4] usb: phy: Add Kconfig entry for Tegra PHY driver

Currently tegra-phy driver is built only when ehci-tegra is. Add own Kconfig entry for tegra-phy so that drivers other than ehci-tegra (like ChipIdea) could work without ehci-tegra. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- Change log: v2: Added missed USB_ULPI depe

[PATCH v2 4/4] usb: host: ehci-tegra: Remove USB_PHY dependencies from Kconfig

Previously tegra-phy driver was built only when ehci-tegra was, now tegra-phy has its own Kconfig entry. Remove the USB_PHY dependencies from ehci-tegra's Kconfig since they aren't useful anymore. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/usb/host/Kconfig | 3 ---

[PATCH v2 2/4] usb: tegra: Move utmi-pads reset from ehci-tegra to tegra-phy

to resolve the problem. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- Change log: v2: Corrected UTMI pads reset by moving reset assert/deassert to the PHY's probe. drivers/usb/host/ehci-tegra.c | 87 ++- drivers/usb/phy/phy-tegra

[PATCH v2] drm/tegra: dc: Link DC1 to DC0 on Tegra20

HW reset isn't actually broken on Tegra20, but there is a dependency on first display controller to be taken out of reset for the second to be enabled successfully. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- Change log: v2: Got rid of global variable and now use driver_find_

[PATCH v1] drm/tegra: Restore opaque formats on Tegra20/30

non-alpha. Fixes: 7772fdaef939 ("drm/tegra: Support ARGB and ABGR formats") Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/dc.c| 19 ++- drivers/gpu/drm/tegra/dc.h| 1 + drivers/gpu/drm/tegra/fb.c| 13 - drivers/

[PATCH v1] drm/tegra: Correct timeout in tegra_syncpt_wait

host1x_syncpt_wait() takes timeout value in jiffies, but DRM passes it in milliseconds. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/drm.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/tegra/drm.c b/drivers/gpu/drm

[PATCH v1] drm/tegra: gem: Correct iommu_map_sg() error checking

iommu_map_sg() doesn't return a error value, but a size of the requested IOMMU mapping or zero in case of error. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/gem.c | 13 ++--- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/drivers/g

[PATCH v1] drm/tegra: Trade overlay plane for cursor on older Tegra's

-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/gpu/drm/tegra/dc.c | 52 +- 1 file changed, 37 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c index 7e58143f4145..3282aa911351 100644 --- a/drive

Re: [PATCH v5 0/4] NVIDIA Tegra video decoder driver

On 12.12.2017 03:26, Dmitry Osipenko wrote: > VDE driver provides accelerated video decoding to NVIDIA Tegra SoC's, > it is a result of reverse-engineering efforts. Driver has been tested on > Toshiba AC100 and Acer A500, it should work on any Tegra20 device. > > In usersp

Re: [PATCH v1] clk: tegra20: Add 216 MHz entry for PLL_X

On 12.12.2017 18:17, Peter De Schrijver wrote: > On Tue, Dec 12, 2017 at 03:08:08PM +0300, Dmitry Osipenko wrote: >> On 12.12.2017 13:02, Peter De Schrijver wrote: >>> On Mon, Dec 11, 2017 at 09:50:09PM +0300, Dmitry Osipenko wrote: >>>> The cpufreq driver uses 2

[PATCH v1 1/2] memory: tegra: Squash tegra20-mc into common tegra-mc driver

Tegra30+ has some minor differences in registers / bits layout compared to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver to reduce code a tad, this also will be useful for the upcoming Tegra's MC reset API. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- d

[PATCH v1 2/2] memory: tegra: Introduce memory client hot reset API

/encoder/camera) and graphics (2d/3d). Signed-off-by: Dmitry Osipenko <dig...@gmail.com> --- drivers/memory/tegra/mc.c | 172 drivers/memory/tegra/tegra114.c | 25 ++ drivers/memory/tegra/tegra124.c | 32 drivers/memory/tegra/teg

Re: [PATCH v1 2/2] drm/tegra: Support disabled CONFIG_PM

On 15.12.2017 00:41, Lucas Stach wrote: > Am Montag, den 11.12.2017, 18:26 +0300 schrieb Dmitry Osipenko: >> On 11.12.2017 17:27, Thierry Reding wrote: >>> On Mon, Dec 11, 2017 at 04:53:56PM +0300, Dmitry Osipenko wrote: >>>> On 11.12.2017 13:13, Thierry Reding wro

Re: [PATCH v1 2/2] drm/tegra: Support disabled CONFIG_PM

On 15.12.2017 00:41, Lucas Stach wrote: > Am Montag, den 11.12.2017, 18:26 +0300 schrieb Dmitry Osipenko: >> On 11.12.2017 17:27, Thierry Reding wrote: >>> On Mon, Dec 11, 2017 at 04:53:56PM +0300, Dmitry Osipenko wrote: >>>> On 11.12.2017 13:13, Thierry Reding wro

Re: [PATCH v1 2/2] memory: tegra: Introduce memory client hot reset API

On 13.12.2017 06:12, Dmitry Osipenko wrote: > In order to reset busy HW properly, memory controller needs to be > involved, otherwise it possible to get corrupted memory if HW was reset > during DMA. Introduce memory client 'hot reset' API that will be used > for resetting busy HW.

[PATCH v2 1/2] clk: tegra: Mark HCLK, SCLK, EMC, MC and PLL_P outputs as critical

once drivers would be corrected. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Acked-By: Peter De Schrijver <pdeschrij...@nvidia.com> --- Change log: v2: Fixed accidentally missed marking EMC as critical on Tegra30 and Tegra124. Switched to a use of common EMC gat

[PATCH v2 2/2] clk: tegra20: Correct PLL_C_OUT1 setup

PLL_C_OUT_1 can't produce 216 MHz defined in the init_table. Let's set it to 240 MHz and explicitly specify HCLK rate for consistency. Signed-off-by: Dmitry Osipenko <dig...@gmail.com> Acked-By: Peter De Schrijver <pdeschrij...@nvidia.com> --- Change log: v2: No change. drive

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