-by: Douglas Anderson diand...@chromium.org
---
drivers/usb/core/hub.c | 7 ---
include/linux/usb/hcd.h | 5 +
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 43cb2f2..fdc59db 100644
--- a/drivers/usb/core/hub.c
+++ b
Some SoCs with a dwc2 USB controller may need to keep the PHY on to
support remote wakeup. Allow specifying this as a device tree
property.
Signed-off-by: Douglas Anderson diand...@chromium.org
---
Documentation/devicetree/bindings/usb/dwc2.txt | 4
1 file changed, 4 insertions(+)
diff
of dwc2 backports
from upstream, so this is expected to function upstream once we get
everything setup there.
Douglas Anderson (3):
USB: Export usb_wakeup_enabled_descendants()
Documentation: dt-bindings: Add snps,need-phy-for-wake for dwc2 USB
USB: dwc2: Don't turn off the usbphy in suspend
a way to call
device_set_wakeup_capable() without keeping the PHY on at suspend
time.
Signed-off-by: Chris Zhong z...@rock-chips.com
Signed-off-by: Douglas Anderson diand...@chromium.org
---
drivers/usb/dwc2/core.h | 2 ++
drivers/usb/dwc2/platform.c | 45
-by: Douglas Anderson diand...@chromium.org
---
drivers/usb/core/hub.c | 7 ---
include/linux/usb/hcd.h | 5 +
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 43cb2f2..fdc59db 100644
--- a/drivers/usb/core/hub.c
+++ b
a way to call
device_set_wakeup_capable() without keeping the PHY on at suspend
time.
Signed-off-by: Chris Zhong z...@rock-chips.com
Signed-off-by: Douglas Anderson diand...@chromium.org
---
drivers/usb/dwc2/core.h | 2 ++
drivers/usb/dwc2/platform.c | 45
Some SoCs with a dwc2 USB controller may need to keep the PHY on to
support remote wakeup. Allow specifying this as a device tree
property.
Signed-off-by: Douglas Anderson diand...@chromium.org
---
Documentation/devicetree/bindings/usb/dwc2.txt | 4
1 file changed, 4 insertions(+)
diff
of dwc2 backports
from upstream, so this is expected to function upstream once we get
everything setup there.
Douglas Anderson (3):
USB: Export usb_wakeup_enabled_descendants()
Documentation: dt-bindings: Add snps,need-phy-for-wake for dwc2 USB
USB: dwc2: Don't turn off the usbphy in suspend
in a small way (hopefully for the better).
Signed-off-by: Douglas Anderson diand...@chromium.org
---
drivers/clk/rockchip/clk-pll.c| 18 +-
drivers/clk/rockchip/clk-rk3188.c | 2 +-
drivers/clk/rockchip/clk-rk3288.c | 2 +-
drivers/clk/rockchip/clk.h| 8
4
...@chromium.org
Signed-off-by: Douglas Anderson diand...@chromium.org
---
arch/arm/kernel/patch.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm/kernel/patch.c b/arch/arm/kernel/patch.c
index 69bda1a..abf30ec 100644
--- a/arch/arm/kernel/patch.c
+++ b/arch/arm/kernel
As per the change to the rk3288 USB phy driver, we can now enable the
PHYs as reset providers. Do so.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm/boot/dts/rk3288.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/ar
ed in.
These patches currently conflict with patches that I posted previously
to enable USB wakeup from S3, specifically:
* https://patchwork.kernel.org/patch/6727081/
* https://patchwork.kernel.org/patch/6727121/
...those patches no longer apply anyway, so presumably they need to be
reposted and I can d
rent hardware errata. Only the host port
gets the quirk property, though.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm/boot/dts/rk3288.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
ind
er sets this), so we'll update the
former "else" case based on this test.
Fixes: 734643dfbdde ("usb: dwc2: host: add flag to reflect bus state")
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/hcd.c | 9 +
1 file changed, 5 insertions(+
for
some details on the reset that we plan to use.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
---
Documentation/devicetree/bindings/usb/dwc2.txt | 7 +++
drivers/usb/dwc2/core.h| 5 +
drivers/us
e the ability to unwedge
the dwc2 "host" port when a remote wakeup happens. It may have other
redeeming qualities as well.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
.../devicetree/bindings/phy/rockchip-usb-phy.txt | 6 ++
drivers/phy/phy-rockchip-usb.c
or this up on pastebin:
http://pastebin.com/PjxktNYA
Note that the frames picked by the microframe scheduler functions aren't
properly used yet elsewhere, so this patch won't really have much of an
effect. See future patches in the series.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
-
and ftrace is more
appropriate for performance-critical traces.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v3:
- scheduler tracing new for v3.
Changes in v2: None
drivers/usb/dwc2/core.h | 9 +
drivers/usb/dwc2/hcd.h | 5 +
drivers/us
experience) to be much more common and any schedule that
would work on a single_tt hub will also work on a multi_tt hub. This
will prevent more than 8 total low/full speed devices to be on the bus
at one time, but that's a reasonable restriction until we've made things
smarter.
Signed-off-by: Douglas
dwc2: host: Add a delay before
releasing periodic bandwidth") to come first.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
Changes in v2:
- Commit message now says that URB giveback change needs delay chan
The microframe scheduler did a lot of work to pick the proper
microframe. Then dwc2_sched_periodic_split() went ahead and ignored
which microframe we picked if it ever needed to re-assign things.
Let's keep track of the uframe and then we'll always use it.
Signed-off-by: Douglas Anderson <di
params.
- If we can remove the 65535 limit, we can transfer more!
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v3: None
Changes in v2: None
drivers/usb/dwc2/platform.c | 2 +-
1 file changed, 1 insertion(+), 1 delet
of removing the 65535 max transfer size
limit.
NOTE: The actual code to allocate the aligned buffers is ripped almost
completely from the tegra EHCI driver. At some point in the future we
may want to add this functionality to the USB core to share more code
everywhere.
Signed-off-by: Douglas Anderson
rrupt qh unlink") and add a 5ms delay. Since we don't have a whole
timer infrastructure in dwc2, we'll just add a timer per QH. The
overhead for this is very small.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v3:
- Moved periodic bandwidth release delay
scheduler again after writing test code.
- uframe scheduler atop delayed bandwidth release patches.
- Periodic bandwidth release delay new for V2
- Commit message now says that URB giveback change needs delay change.
Douglas Anderson (8):
usb: dwc2: rockchip: Make the max_transfer_size automati
nge, we no longer get dropped characters from the
above mentioned keyboard. Other devices on the same bus as the keyboard
also behave more properly.
Thanks for Julius Werner for the expert analysis and suggestions.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Repost without t
nge, we no longer get dropped characters from the
above mentioned keyboard. Other devices on the same bus as the keyboard
also behave more properly.
Thanks for Julius Werner for the expert analysis and suggestions.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/
tle impact of the microframe scheduler overall.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Since no known bugs are fixed by this code and my current setup hardly
stress the microframe scheduler at all, please give extra eyes and extra
testing to this patch. Thanks!
Changes in v2:
-
bad state.
Note that we add the reset to both dwc2 controllers even though only one
has the errata in case we find some other use for this reset that's
unrelated to the current hardware errata. Only the host port gets the
quirk property, though.
Signed-off-by: Douglas Anderson <diand...@chromi
On the rk3288 USB host-only port (the one that's not the OTG-enabled
port) the PHY can get into a bad state when a wakeup is asserted (not
just a wakeup from full system suspend but also a wakeup from
autosuspend).
We can get the PHY out of its bad state by asserting its "port reset",
but
the changes that have happened to dwc2 in the meantime, it's
possible that the Altera SOCFPGA will just magically work with this
change now. ...and it would be good to get bus suspend/resume
implemented.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
I've posted up a bunch of pat
than alternative of letting the bus get
wedged.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
---
Changes in v2:
- Use a full PHY reset for safety; no PHY changes needed for that.
Documentation/devicetree/bindings/usb/dwc2.txt |
y, it merely adds another set of changes that upstream could
benefit from.
Douglas Anderson (3):
usb: dwc2: rockchip: Make the max_transfer_size automatic
usb: dwc2: host: Giveback URB in tasklet context
usb: dwc2: host: Get aligned DMA in a more supported way
driv
In commit 94dfd7edfd5c ("USB: HCD: support giveback of URB in tasklet
context") support was added to give back the URB in tasklet context.
Let's take advantage of this in dwc2.
This speeds up the dwc2 interrupt handler considerably.
Signed-off-by: Douglas Anderson <diand...
of removing the 65535 max transfer size
limit.
NOTE: The actual code to allocate the aligned buffers is ripped almost
completely from the tegra EHCI driver. At some point in the future we
may want to add this functionality to the USB core to share more code
everywhere.
Signed-off-by: Douglas Anderson
params.
- If we can remove the 65535 limit, we can transfer more!
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/dwc2/platform.c b/drivers/usb/dwc2/platform.c
index 5859b0f
dwc2: host: Add a delay before
releasing periodic bandwidth") to come first.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v2:
- Commit message now says that URB giveback change needs delay change.
drivers/usb/dwc2/h
of the microframe scheduler overall.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/hcd_queue.c | 72
1 file changed, 32 insertions(+), 40 deletions(-)
diff --git a/drivers/usb/dwc2/hcd_queue.c b/drivers/usb/dwc2/hcd_queue.c
if setup_dma is not aligned (Julius Werner).
- Periodic bandwidth release delay new for V2
- Commit message now says that URB giveback change needs delay change.
Douglas Anderson (4):
usb: dwc2: rockchip: Make the max_transfer_size automatic
usb: dwc2: host: Get aligned DMA in a more supported way
of removing the 65535 max transfer size
limit.
NOTE: The actual code to allocate the aligned buffers is ripped almost
completely from the tegra EHCI driver. At some point in the future we
may want to add this functionality to the USB core to share more code
everywhere.
Signed-off-by: Douglas Anderson
rrupt qh unlink") and add a 5ms delay. Since we don't have a whole
timer infrastructure in dwc2, we'll just add a timer per QH. The
overhead for this is very small.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Periodic bandwidth release delay new for V
params.
- If we can remove the 65535 limit, we can transfer more!
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Tested-by: Heiko Stuebner <he...@sntech.de>
---
Changes in v2: None
drivers/usb/dwc2/platform.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
drivers/usb/dwc2/core_intr.c | 55 ++--
drivers/usb/dwc2/hcd_intr.c | 16 ++---
2 files changed, 35 insertions(+), 36 deletions(-)
diff --git a/drivers/usb/dwc2/core_intr.c b/drive
-connecting after the disconnect is posted. We don't skip the
disconnect because if there is a transitory disconnect we really want to
de-enumerate and re-enumerate.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Don't reconnect when called from _dwc2_hcd_stop()
e this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v3:
- Don't pass NULL if qtd freed, just return (John Youn)
- Don't keep track of interrupts left: list_first_entry()
Though we could add specific code to handle this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/hcd_intr.c | 80 +++--
1 fi
>From code inspection, it appears to be unsafe to do a read-modify-write
of PCGCTL in dwc2_port_resume(). Let's make sure the spinlock is held
around this operation.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/hcd.c | 5 -
1 file changed, 4 inserti
Though we could add specific code to handle this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Add static as correctly pointed by kbuild test robot
drivers/usb/dw
e ?
I have tried this patch in my RK3288-evb board. It works well.
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers
.
Since we're now looking at GUSBCFG, it's obvious that we shouldn't need
all the extra delays if FORCEHOSTMODE was already set. This will avoid
some delays for any ports that have forced host mode.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/core.
oid the reset, we remove "irq" and rename "select_phy" to
"initial_setup" and adjust the callers accordingly.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/core.c | 29 ++---
drivers/usb/dwc2/core.h | 2
linuxnext dwc2
patches pulled in to avoid conflicts.
These patches have either landed or are planned to land on the
chromeos-3.14 branch for use in several Chromebooks that use rk3288.
Douglas Anderson (3):
usb: dwc2: Restore GUSBCFG in dwc2_get_hwparams()
CHROMIUM: usb: dwc2: Avoid double-
RXFSIZ/GNPTXFSIZ/HPTXFSIZ registers.
This patch could avoid warnning massage like in rk3288 platform:
[2.074764] dwc2 ff58.usb: 256 invalid for
host_perio_tx_fifo_size. Check HW configuration.
Signed-off-by: Yunzhi Li <l...@rock-chips.com>
Signed-off-by: Douglas Anderson <diand.
() is always called before
dwc2_get_hwparams() and we know dwc2_core_reset() should have set
GUSBCFG_FORCEHOSTMODE whenever hsotg->dr_mode == USB_DR_MODE_HOST, we
can just check hsotg->dr_mode to decide that we can skip the delays in
dwc2_get_hwparams().
Signed-off-by: Douglas Anderson
$(seq 10); do
dd if=/dev/zero of=/dev/sdb bs=1M count=750
done
With the above tests I found that speeds went from ~15MB/s to ~18MB/s.
Note that most other tests I did (including reading from the same USB
reader) didn't show any difference in performance.
Signed-off-by: Douglas Anderson
tes are only present (and
only transitioned in to and out of) when (optional) power management
is enabled.
Signed-off-by: Doug Anderson <diand...@chromium.org>
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: Greg Kroah-Hartman <gre...@linuxfoundation.org
of) when (optional) power management
is enabled.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: Greg Kroah-Hartman <gre...@linuxfoundation.org>
Tested-by: Caesar Wang <w...@rock-chips.com>
---
Changes in v3:
- Moved declarations to pinctrl/devinfo.h
- Fixed au
-connecting after the disconnect is posted. We don't skip the
disconnect because if there is a transitory disconnect we really want to
de-enumerate and re-enumerate.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/usb/dwc2/core.h | 2 ++
drivers/usb/dwc2/hcd.c
e this case, adding the
general purpose code to check for all cases where qtd might be freed
seemed safer.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v4:
- Fix NULL qh case
Changes in v3:
- Don't pass NULL if qtd freed, just return (John Youn)
- Don't keep track of
. dwc2_handle_common_intr() - calls dwc2_hcd_disconnect()
...but with different timing then sometimes we'd still miss cable
insertions.
In any case, though this patch doesn't fix any (known) problems, it
still seems wise as a general policy to clear interrupt before handling
them.
Signed-off-by: Douglas
a PHY
SELECT. That means that if we see that we can avoid the PHY SELECT then
we can avoid the reset.
This patch appears to successfully bypass two resets (one per USB
device) on rk3288-based ARM Chromebooks.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
This patch should
-off-by: Douglas Anderson diand...@chromium.org
---
Changes in v2:
- Don't use task_pt_regs(task) at all.
arch/arm/kernel/kgdb.c | 31 ---
1 file changed, 12 insertions(+), 19 deletions(-)
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index a6ad93c
)
Reported-by: Aapo Vienamo avien...@nvidia.com
Signed-off-by: Douglas Anderson diand...@chromium.org
---
arch/arm/kernel/kgdb.c | 8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/arch/arm/kernel/kgdb.c b/arch/arm/kernel/kgdb.c
index a6ad93c..fd9eefc 100644
--- a/arch/arm
nown
to work.
Once driver support in dw_hdmi lands, boards would use this by selecting
this pinctrl for the HDMI block and then _not_ specifying a ddc-i2c-bus
and _not_ setting the status to "okay" for i2c5 (which uses the same
pins).
Signed-off-by: Douglas Anderson <diand...@chromium.org&
The ddc-i2c-bus property was missing from the veyron dtsi file since
downstream the ddc-i2c-bus was still being specified in rk3288.dtsi and
nobody noticed when the veyron dtsi was sent upstream. Add it.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Note: I n
and implement whatever feature / fix was needed then we can drop this
patch. The 'cable_plugin' member has been unused since the code was
first added in (9aaf880 imx-drm: Add mx6 hdmi transmitter support).
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/gpu/drm/bridge/dw_
11]
call phy0+ returned 0 after 12 usecs
calling rfkill1+ @ 15793, parent: phy0, cb: rfkill_resume
call rfkill1+ returned 0 after 1 usecs
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/base/power/main.c | 10 +-
1 file changed, 5 insertions(+), 5 deletion
t's simplify by just allocating one page at a time. We may make more
total allocate calls but it works way better. In real world tests that
used to sometimes see a 24 second allocation call I can now see at most
250 ms.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm/mm/dma-
ide that TLB optimization isn't
important and that we should use smaller chunks. Presumably this would
be a sane strategy for some callers.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v3: None
Changes in v2:
- No longer just 1 page at a time, but gives up higher orde
DMA_ATTR_RANDOM to indicate that random access is
expected.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v3:
- add DMA_ATTR_SEQUENTIAL attribute new for v3
Changes in v2: None
Documentation/DMA-attributes.txt | 11 +++
include/linux/dma-attrs.h| 1 +
2
to ensure alignment.
Changes in v3:
- add DMA_ATTR_SEQUENTIAL attribute new for v3
- Use DMA_ATTR_SEQUENTIAL hint patch new for v3.
Changes in v2:
- No longer just 1 page at a time, but gives up higher order quickly.
- Only tries important higher order allocations that might help us.
Douglas Anderson (3
with dwc2 USB trying to allocate
buffers for Ethernet data and with WiFi trying to allocate buffers for
WiFi data), it is yet another big performance hit.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v3:
- Use DMA_ATTR_SEQUENTIAL hint patch new for v3.
Changes in v2
0us for a 4MB allocation.
That's much faster than the actual allocation which was more than a
millisecond even in the fastest case (and was often several hundred ms).
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Sort patch new for v2 (and optional if people hate it
ide that TLB optimization isn't
important and that we should use smaller chunks. Presumably this would
be a sane strategy for some callers.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- No longer just 1 page at a time, but gives up higher order quickly.
- O
it's still probably wise to fix the function.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v5:
- New for v5 of the series
drivers/usb/dwc2/hcd.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/usb/dwc2/hcd.c b/drivers/usb/dwc2/hcd.c
index 42b6c51276
that for dwc2_handle_usb_port_intr(), instead of moving the clear
of PRTINT to the beginning of the function we remove it completely. The
only way to clear PRTINT is to clear the sources that set it in the
first place.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v5:
- Rebase
).
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: John Youn <johny...@synopsys.com>
---
Changes in v3:
- Add notes to device insertions commit message (Felipe Balbi)
Changes in v2:
- Don't reconnect when called from
-by: Douglas Anderson <diand...@chromium.org>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: John Youn <johny...@synopsys.com>
---
Changes in v3:
- Don't (uselessly) clear the PRTINT anymore (Felipe Balbi).
Changes in v2: None
drivers/usb/dwc
).
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: John Youn <johny...@synopsys.com>
Tested-by: John Youn <johny...@synopsys.com>
---
Changes in v4: None
Changes in v3:
- Add notes to device insertions commit message (Felipe Balbi)
Changes in v2:
- Don'
that for dwc2_handle_usb_port_intr(), instead of moving the clear
of PRTINT to the beginning of the function we remove it completely. The
only way to clear PRTINT is to clear the sources that set it in the
first place.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
Acked-by: John Youn
ms if picked without that change.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/host/sdhci-of-arasan.c | 23 ---
1 file changed, 8 insertions(+), 15 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mmc/host/sdhci-of-a
to at least
50 MHz before, though this reliance wasn't documented anywhere.
This change will be even more useful in future changes where we actually
need to be able to wait for a DLL lock at slower clock speeds.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/phy/phy-ro
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 27 --
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/D
On rk3399 we'd like to be able to properly set corecfg registers in the
Arasan SDHCI component. Specify the syscon to enable that.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch
with the outstanding code patches
or I could try folding those patches into mine. Since those patches
aren't in 4.7-rc1 presumably they would also make sense to take through
the MMC tree if others agree.
Douglas Anderson (11):
phy: rockchip-emmc: Increase lock time allowance
mmc: sdhci
r
SoCs. Note that a specific compatible string for rk3399 is already in
use and so we add that to the table to match rk3399.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/host/sdhc
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/mmc/host/sdhci-of-arasan.c | 125 -
1 file changed, 122 insertions(+), 3 deletions(-)
diff --git a/drivers/mmc/host/sdhci-of-arasan.c
b/drivers/mm
series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/phy/phy-rockchip-emmc.c | 74 +++
om/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt | 7 +++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/rockchip-emmc-phy.txt
Previous changes in this series allowed exposing the card clock from the
rk3399 SDHCI device and allowed consuming the card clock in the rk3399
eMMC PHY. Hook things up in the main rk3399 dtsi file.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/rockchip/
Some SD/eMMC PHYs (like the PHY from Arasan that is designed to work
with arasan,sdhci-5.1) need to know the card clock in order to function
properly. Let's expose this clock using a standard device tree
mechanism so that the PHY can get access to and query the card clock.
Signed-off-by: Douglas
There's no reason to store the return value of rockchip_emmc_phy_power()
in a variable nor to check it. Just return it.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/phy/phy-rockchip-emmc.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/d
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
.../devicetree/bindings/display/panel/starry,kr122ea0sra.txt | 7 +++
1 file changed, 7 insertions(+)
create
The Starry KR122EA0SRA is a 12.2", 1920x1200 TFT-LCD panel connected
using eDP interfaces.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Proper title (sorry!)
.../devicetree/bindings/display/panel/starry,kr122ea0sra.txt | 7 +++
1 file
turer-specified data, tag 15
ASCII string: STARRY
ASCII string: KR122EA0SRA
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2: None
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/
>From their website:
http://www.b001.com.cn/
Starry appears to be a company involved in LCD panels and related
components.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Documentation/devicetree/bindings/vendor-prefixes.txt | 1 +
1 file changed, 1 insertion(+)
d
turer-specified data, tag 15
ASCII string: STARRY
ASCII string: KR122EA0SRA
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
drivers/gpu/drm/panel/panel-simple.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/panel/panel-simple.c
ute from rk3288 back to rk3288. Presumably
on rk3399 this is simply not needed since the pins don't appear to exist
there.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
arch/arm64/boot/dts/rockchip/rk3399.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/b
the PHY a good chance to query our clock.
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Note: just sending the one quick fix as v2.1. If further spins are
needed I'll send out a full v3.
Changes in v2.1:
- Add dependency on COMMON_CLK (Guenter Roeck)
Changes in v2: None
drive
series, since
performance is still good but signal integrity problems are less
prevelant at 150 MHz.
[1]: https://arasan.com/wp-content/media/eMMC-5-1-Total-Solution_Rev-1-3.pdf
Signed-off-by: Douglas Anderson <diand...@chromium.org>
---
Changes in v2:
- Warn if we're more than 15 MHz from ide
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