From: "Edward A. James"
Add structures to define all sensor types and versions. Add sysfs show
and store functions for each sensor type. Add a method to construct the
"set user power cap" command and send it to the OCC. Add rate limit to
polling the OCC (in case user-space reads our hwmon
null
+++ b/Documentation/hwmon/occ
@@ -0,0 +1,84 @@
+Kernel driver occ-hwmon
+===
+
+Supported chips:
+ * POWER8
+ * POWER9
+
+Author: Eddie James
+
+Description
+---
+
+This driver supports hardware monitoring for the On-Chip Controller (OCC)
+embedded on POWER processor
From: "Edward A. James"
Add logic to detect a number of error scenarios on the OCC. Export any
error through an additional non-hwmon device attribute.
Signed-off-by: Edward A. James
---
Documentation/ABI/testing/sysfs-driver-occ-hwmon | 12 ++
drivers/hwmon/occ/common.c
From: "Edward A. James"
This series adds a hwmon driver to support the OCC on POWER8 and POWER9
processors. The OCC is an embedded processor that provides realtime power and
thermal monitoring and management.
This driver has two different platform drivers as a "base" for the
hwmon stuff, as the
On 06/22/2017 11:52 PM, Guenter Roeck wrote:
On 06/22/2017 03:48 PM, Eddie James wrote:
From: "Edward A. James"
This series adds a hwmon driver to support the OCC on POWER8 and POWER9
processors. The OCC is an embedded processor that provides realtime
power and
thermal
: Eddie James
+L: linux-hw...@vger.kernel.org
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the openbmc list?
+S: Maintained
+F: Documentation/hwmon/occ
+F: drivers/hwmon/occ/
+
ONENAND FLASH DRIVER
M: Kyungmin Park
L: linux
From: "Edward A. James"
This patchset adds a hwmon driver to support the OCC (On-Chip Controller)
on the IBM POWER8 and POWER9 processors, from a BMC (Baseboard Management
Controller). The OCC is an embedded processor that provides real time
power and thermal monitoring.
The driver provides an
the driver does not run on these processors. Instead, the
+driver runs on a connected service processor, such as an AST2400. (see the
+BMC - Host Communications section).
+
+Author: Eddie James
+
+Description
+---
+
+This driver implements support for the OCC (On-Chip Controller) on the I
= _ops,
+};
+
+const u32 *p8_get_sensor_hwmon_configs()
+{
+ return p8_sensor_hwmon_configs;
+}
+
+struct occ *p8_occ_init(struct device *dev, void *bus,
+ const struct occ_bus_ops *bus_ops)
+{
+ return occ_init(dev, bus, bus_ops, _init);
+}
+
+MODULE_AUTHOR("
_NAME,
+ .of_match_table = occ_of_match,
+ },
+ .probe = p8_occ_probe,
+ .id_table = occ_ids,
+};
+
+module_i2c_driver(p8_occ_driver);
+
+MODULE_AUTHOR("Eddie James ");
+MODULE_DESCRIPTION("BMC P8 OCC hwmon driver");
+MODULE_LICENSE("GPL");
--
1.8.3.1
of(u32) * 3);
+ if (rc < 0)
+ return rc;
+ else if (rc != sizeof(u32) * 3)
+ return -EIO;
+
+ return 0;
+}
+
+MODULE_AUTHOR("Eddie James ");
+MODULE_DESCRIPTION("I2C OCC SCOM transport");
+MODULE_LICENSE("GPL");
diff
tic const struct occ_init_data p9_init = {
+ .command_addr = 0xFFFBE000,
+ .response_addr = 0xFFFBF000,
+ .ops = _ops,
+};
+
+const u32 *p9_get_sensor_hwmon_configs()
+{
+ return p9_sensor_hwmon_configs;
+}
+
+struct occ *p9_occ_init(struct device *dev, void *bus,
+
gt;dev = devm_hwmon_device_register_with_info(dev,
+ hwmon->hwmon_name,
+ hwmon,
+ >occ_info,
+ NULL);
+ if (IS_
: Eddie James
+L: linux-hw...@vger.kernel.org
Have you subscribed to this list? Would you prefer the mail to come to
the openbmc list?
+S: Maintained
+F: Documentation/hwmon/occ
+F: drivers/hwmon/occ/
+
ONENAND FLASH DRIVER
M: Kyungmin Park
L: linux
On 02/09/2017 11:31 PM, Joel Stanley wrote:
On Wed, Feb 8, 2017 at 9:40 AM, wrote:
From: "Edward A. James"
Add functions to send SCOM operations over I2C bus. The BMC can
communicate with the Power8 host processor over I2C, but needs to use SCOM
operations in order to access the OCC
On 04/02/2017 06:19 AM, Guenter Roeck wrote:
On 03/14/2017 01:55 PM, Eddie James wrote:
From: "Edward A. James"
Add a generic mechanism to expose the sensors provided by the OCC in
sysfs.
Signed-off-by: Edward A. James
Signed-off-by: Andrew Jeffery
---
Documentation
Log an error if the response checksum doesn't match the
calculated checksum.
Signed-off-by: Eddie James
---
drivers/fsi/fsi-occ.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c
index cb05b6dacc9d..524460995465 100644
Initialize the sequence number at one, rather than zero, in order
to prevent false matches with the zero-initialized OCC SRAM
buffer before the OCC is fully initialized.
Signed-off-by: Eddie James
---
drivers/hwmon/occ/common.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/hwmon
In order to better debug problems starting up the driver, print
the response status from the OCC in the error logged when the first
poll command fails.
Signed-off-by: Eddie James
---
drivers/hwmon/occ/common.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers
state before returning the response in order to detect this condition and
continue waiting if necessary.
Eddie James (4):
fsi: occ: Don't accept response from un-initialized OCC
fsi: occ: Log error for checksum failure
hwmon: (occ) Start sequence number at one
hwmon: (occ) Print response
If the OCC is not initialized and responds as such, the driver
should continue waiting for a valid response until the timeout
expires.
Signed-off-by: Eddie James
---
drivers/fsi/fsi-occ.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/fsi/fsi-occ.c b/drivers/fsi/fsi-occ.c
index
On Thu, 2021-03-25 at 13:50 +, Mark Brown wrote:
> On Wed, Mar 24, 2021 at 05:05:16PM -0500, Eddie James wrote:
>
> > Updated restricted chips have trouble processing multiple sequenced
> > operations. So remove the capability to sequence multiple
> > operations an
On Tue, 2021-02-09 at 11:12 -0600, Eddie James wrote:
> In the event that the OCC is not initialized when the driver sends a
> poll
> command, the driver may receive an invalid response. This isn't an
> error
> condition unless there is no valid response before the timeout
> ex
restart, as the locking is broken somehow.
Fixes: 0795fb2021f0 ("net/ncsi: Stop monitor if channel times out or is
inactive")
Signed-off-by: Milton Miller
Signed-off-by: Eddie James
---
net/ncsi/ncsi-manage.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
The error bits in the FSI2PIB status are only cleared by a reset. So
the driver needs to perform a reset after seeing any of the FSI2PIB
errors, otherwise subsequent operations will also look like failures.
Fixes: 6b293258cded ("fsi: scom: Major overhaul")
Signed-off-by: Eddie James
--
Updated restricted chips have trouble processing multiple sequenced
operations. So remove the capability to sequence multiple operations and
reduce the maximum transfer size to 8 bytes.
Signed-off-by: Eddie James
---
drivers/spi/spi-fsi.c | 27 +++
1 file changed, 7
1:27:25 rain27bmc kernel: [<80734cdc>] (aspeed_master_read) from
[<807320f0>] (fsi_master_read+0x6c/0x1bc)
...
Signed-off-by: Eddie James
---
drivers/fsi/fsi-master-aspeed.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fsi/fsi-master-aspeed.c b/dr
801 - 827 of 827 matches
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