[PATCH v3 12/12] arm64: defconfig: enable Armada 3700 related config

[Gregory CLEMENT]

This patch enables the configuration for the Armada 3700 family and for
the related driver it uses.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/configs/defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 18ca9fb9e65f..7ca2f0247ec5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_BCM_IPROC=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_EXYNOS7=y
@@ -93,6 +94,7 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
 CONFIG_AHCI_XGENE=y
 CONFIG_SATA_RCAR=y
 CONFIG_PATA_PLATFORM=y
@@ -132,6 +134,7 @@ CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
 CONFIG_VIRTIO_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
@@ -162,6 +165,8 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_RCAR=y
 CONFIG_SND_SOC_AK4613=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.5.0

[PATCH v3 04/12] ata: ahci_mvebu: add support for Armada 3700 variant

[Gregory CLEMENT]

From: Lior Amsalem <al...@marvell.com>

The main difference in the new Armada 3700 is that no address
decoding needs to take place in the driver probe.

[gregory.clem...@free-electrons.com: reformulate the commit log]

Signed-off-by: Lior Amsalem <al...@marvell.com>
Reviewed-by: Nadav Haklai <nad...@marvell.com>
Tested-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/ata/ahci_mvebu.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index f7a7fa81740e..de7128d81e9c 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -112,12 +112,15 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
if (rc)
return rc;
 
-   dram = mv_mbus_dram_info();
-   if (!dram)
-   return -ENODEV;
+   if (of_device_is_compatible(pdev->dev.of_node,
+   "marvell,armada-380-ahci")) {
+   dram = mv_mbus_dram_info();
+   if (!dram)
+   return -ENODEV;
 
-   ahci_mvebu_mbus_config(hpriv, dram);
-   ahci_mvebu_regret_option(hpriv);
+   ahci_mvebu_mbus_config(hpriv, dram);
+   ahci_mvebu_regret_option(hpriv);
+   }
 
rc = ahci_platform_init_host(pdev, hpriv, _mvebu_port_info,
 _platform_sht);
@@ -133,6 +136,7 @@ disable_resources:
 
 static const struct of_device_id ahci_mvebu_of_match[] = {
{ .compatible = "marvell,armada-380-ahci", },
+   { .compatible = "marvell,armada-3700-ahci", },
{ },
 };
 MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
-- 
2.5.0

[PATCH v3 06/12] Documentation: dt-bindings: Add a new compatible for the Armada 3700

[Gregory CLEMENT]

The AHCI interfaces used in the Armada 3700 has a few differences with
the one used in the Armada 38x, so it deserves its own compatible string.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt 
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c2340eeeb97f..796e2c23e5df 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -13,6 +13,7 @@ Required properties:
   - "hisilicon,hisi-ahci"
   - "ibm,476gtr-ahci"
   - "marvell,armada-380-ahci"
+  - "marvell,armada-3700-ahci"
   - "snps,dwc-ahci"
   - "snps,exynos5440-ahci"
   - "snps,spear-ahci"
-- 
2.5.0

[PATCH v3 09/12] arm64: dts: add the Marvell Armada 3700 family and a development board

[Gregory CLEMENT]

Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).

It also adds a dts file for the Marvell Armada 3720 DB board.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/Makefile   |   4 +
 arch/arm64/boot/dts/marvell/armada-371x.dtsi   |  53 ++
 arch/arm64/boot/dts/marvell/armada-3720-db.dts |  86 
 arch/arm64/boot/dts/marvell/armada-372x.dtsi   |  63 
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 131 +
 5 files changed, 337 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-371x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-db.dts
 create mode 100644 arch/arm64/boot/dts/marvell/armada-372x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-37xx.dtsi

diff --git a/arch/arm64/boot/dts/marvell/Makefile 
b/arch/arm64/boot/dts/marvell/Makefile
index 348f4db4f313..2114af8d312d 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -1,6 +1,10 @@
+# Berlin SoC Family
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
 
+# Mvebu SoC Family
+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
+
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
 clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi 
b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
new file mode 100644
index ..c9e5325b8ac3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Device Tree Include file for Marvell Armada 371x family of SoCs
+ * (also named 88F3710)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+   model = "Marvell Armada 3710 SoC";
+   compatible = "marvell,armada3710", "marvell,armada3700";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts 
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
new file mode 100644
index ..359050154511
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -0,0 +1,86 @@
+/*
+ * Device Tree file for Marvell Armada 3720 development board
+ * (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option)

[PATCH v3 07/12] Documentation: dt: Tidy up the Marvell related files

[Gregory CLEMENT]

Over the last releases we have added more and more Marvell related binding
directly in the arm directory. It's time to have our proper directory
inside it, and move all the files in it.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/arm/{ => marvell}/armada-370-xp-pmsu.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt| 0
 .../devicetree/bindings/arm/{ => marvell}/armada-380-mpcore-soc-ctrl.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-cpu-reset.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/coherency-fabric.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/mvebu-cpu-config.txt  | 0
 .../devicetree/bindings/arm/{ => marvell}/mvebu-system-controller.txt | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-370-xp-pmsu.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-380-mpcore-soc-ctrl.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-cpu-reset.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/coherency-fabric.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/marvell,kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-cpu-config.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-system-controller.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-375.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-375.txt
diff --git 
a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
rename to 
Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-38x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-39x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-cpu-reset.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-

Re: [PATCH net-next 03/10] net: mvneta: bm: add support for hardware buffer management

[Gregory CLEMENT]

Hi Marcin,
 
 On mar., janv. 12 2016, Marcin Wojtas <m...@semihalf.com> wrote:

> Hi Gregory,
>
> I have two remarks to my own code. Please let me know before patch v2,
> I will provide you with corrected version (I already did it locally).

I resumled my work on the subject yestaerdy, and I just remebered this
email now.

Could you provide the correct version of your patches?

Thanks!

>
>> @@ -1556,17 +1777,20 @@ static void mvneta_rxq_drop_pkts(struct mvneta_port 
>> *pp,
>> int rx_done, i;
>>
>> rx_done = mvneta_rxq_busy_desc_num_get(pp, rxq);
>> +   if (rx_done)
>> +   mvneta_rxq_desc_num_update(pp, rxq, rx_done, rx_done);
>> +
>> +   if (pp->bm_priv)
>> +   return;
>> +
>
> This is wrong - buffers that are supposed to be dropped should return
> to bm_pool.
>
>> @@ -1587,23 +1812,35 @@ static int mvneta_rx(struct mvneta_port *pp, int 
>> rx_todo,
>>
>> rx_done = 0;
>>
>> +   bm_in_use = pp->bm_priv ? true : false;
>> +
>> /* Fairness NAPI loop */
>> while (rx_done < rx_todo) {
>> struct mvneta_rx_desc *rx_desc = 
>> mvneta_rxq_next_desc_get(rxq);
>> +   struct mvneta_bm_pool *bm_pool = NULL;
>> struct sk_buff *skb;
>> unsigned char *data;
>> dma_addr_t phys_addr;
>> -   u32 rx_status;
>> +   u32 rx_status, frag_size;
>> int rx_bytes, err;
>> +   u8 pool_id;
>>
>> rx_done++;
>> rx_status = rx_desc->status;
>> rx_bytes = rx_desc->data_size - (ETH_FCS_LEN + 
>> MVNETA_MH_SIZE);
>> data = (unsigned char *)rx_desc->buf_cookie;
>> phys_addr = rx_desc->buf_phys_addr;
>> +   if (bm_in_use) {
>> +   pool_id = MVNETA_RX_GET_BM_POOL_ID(rx_desc);
>> +   bm_pool = >bm_priv->bm_pools[pool_id];
>> +   }
>>
>> if (!mvneta_rxq_desc_is_first_last(rx_status) ||
>> (rx_status & MVNETA_RXD_ERR_SUMMARY)) {
>> +   /* Return the buffer to the pool */
>> +   if (bm_in_use)
>> +   mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
>> + 
>> rx_desc->buf_phys_addr);
>> err_drop_frame:
>> dev->stats.rx_errors++;
>> mvneta_rx_error(pp, rx_desc);
>> @@ -1633,25 +1870,38 @@ static int mvneta_rx(struct mvneta_port *pp, int 
>> rx_todo,
>> rcvd_pkts++;
>> rcvd_bytes += rx_bytes;
>>
>> +   /* Return the buffer to the pool */
>> +   if (bm_in_use)
>> +   mvneta_bm_pool_put_bp(pp->bm_priv, bm_pool,
>> + 
>> rx_desc->buf_phys_addr);
>> +
>> /* leave the descriptor and buffer untouched */
>> continue;
>> }
>>
>> /* Refill processing */
>> -   err = mvneta_rx_refill(pp, rx_desc);
>> +   err = bm_in_use ? mvneta_bm_pool_refill(pp->bm_priv, 
>> bm_pool) :
>> + mvneta_rx_refill(pp, rx_desc);
>> if (err) {
>> netdev_err(dev, "Linux processing - Can't refill\n");
>> rxq->missed++;
>> goto err_drop_frame;
>
> Wrong - on refill fail, original buffer should be returned to bm_pool.
> Same case is, when netdev_alloc_skb_ip_align fail inside copybreak
> (this should also be fixed).
>
> Best regards,
> Marcin

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH net 3/6] net: mvneta: Remove unused code

[Gregory CLEMENT]

Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
each CPU") all the percpu irq are used and unmask at initialization, so
there is no point to unmask them first.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 3d6e3137f305..861b7e0d7d5f 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3009,14 +3009,6 @@ static int mvneta_open(struct net_device *dev)
goto err_cleanup_txqs;
}
 
-   /* Even though the documentation says that request_percpu_irq
-* doesn't enable the interrupts automatically, it actually
-* does so on the local CPU.
-*
-* Make sure it's disabled.
-*/
-   mvneta_percpu_disable(pp);
-
/* Enable per-CPU interrupt on all the CPU to handle our RX
 * queue interrupts
 */
-- 
2.5.0

[PATCH net 5/6] net: mvneta: The mvneta_percpu_elect function should be atomic

[Gregory CLEMENT]

Electing a CPU must be done in an atomic way: it should be done after or
before the removal/insertion of a CPU and this function is not reentrant.

During the loop of mvneta_percpu_elect we associates the queues to the
CPUs, if there is a topology change during this loop, then the mapping
between the CPUs and the queues could be wrong. During this loop the
interrupt mask is also updating for each CPUs, It should not be changed
in the same time by other part of the driver.

This patch adds spinlock to create the needed critical sections.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 13 +
 1 file changed, 13 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 1ed813d478e8..3358c9a70467 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -370,6 +370,8 @@ struct mvneta_port {
struct net_device *dev;
struct notifier_block cpu_notifier;
int rxq_def;
+   /* protect  */
+   spinlock_t lock;
 
/* Core clock */
struct clk *clk;
@@ -2855,6 +2857,11 @@ static void mvneta_percpu_elect(struct mvneta_port *pp)
 {
int online_cpu_idx, max_cpu, cpu, i = 0;
 
+   /* Electing a CPU must done in an atomic way: it should be
+* done after or before the removal/insertion of a CPU and
+* this function is not reentrant.
+*/
+   spin_lock(>lock);
online_cpu_idx = pp->rxq_def % num_online_cpus();
max_cpu = num_present_cpus();
 
@@ -2893,6 +2900,7 @@ static void mvneta_percpu_elect(struct mvneta_port *pp)
i++;
 
}
+   spin_unlock(>lock);
 };
 
 static int mvneta_percpu_notifier(struct notifier_block *nfb,
@@ -2947,8 +2955,13 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
case CPU_DOWN_PREPARE:
case CPU_DOWN_PREPARE_FROZEN:
netif_tx_stop_all_queues(pp->dev);
+   /* Thanks to this lock we are sure that any pending
+* cpu election is done
+*/
+   spin_lock(>lock);
/* Mask all ethernet port interrupts */
on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
+   spin_unlock(>lock);
 
napi_synchronize(>napi);
napi_disable(>napi);
-- 
2.5.0

[PATCH net 4/6] net: mvneta: Modify the queue related fields from each cpu

[Gregory CLEMENT]

In the MVNETA_INTR_* registers, the queues related fields are per cpu,
according to the datasheet (comment in [] are added by me):
"In a multi-CPU system, bits of RX[or TX] queues for which the access by
the reading[or writing] CPU is disabled are read as 0, and cannot be
cleared[or written]."

That means that each time we want to manipulate these bits we had to do
it on each cpu and not only on the current cpu.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 100 --
 1 file changed, 46 insertions(+), 54 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 861b7e0d7d5f..1ed813d478e8 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1038,6 +1038,43 @@ static void mvneta_set_autoneg(struct mvneta_port *pp, 
int enable)
}
 }
 
+static void mvneta_percpu_unmask_interrupt(void *arg)
+{
+   struct mvneta_port *pp = arg;
+
+   /* All the queue are unmasked, but actually only the ones
+* mapped to this CPU will be unmasked
+*/
+   mvreg_write(pp, MVNETA_INTR_NEW_MASK,
+   MVNETA_RX_INTR_MASK_ALL |
+   MVNETA_TX_INTR_MASK_ALL |
+   MVNETA_MISCINTR_INTR_MASK);
+}
+
+static void mvneta_percpu_mask_interrupt(void *arg)
+{
+   struct mvneta_port *pp = arg;
+
+   /* All the queue are masked, but actually only the ones
+* mapped to this CPU will be masked
+*/
+   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
+   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
+   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+}
+
+static void mvneta_percpu_clear_intr_cause(void *arg)
+{
+   struct mvneta_port *pp = arg;
+
+   /* All the queue are cleared, but actually only the ones
+* mapped to this CPU will be cleared
+*/
+   mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
+   mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
+   mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
+}
+
 /* This method sets defaults to the NETA port:
  * Clears interrupt Cause and Mask registers.
  * Clears all MAC tables.
@@ -1055,14 +1092,10 @@ static void mvneta_defaults_set(struct mvneta_port *pp)
int max_cpu = num_present_cpus();
 
/* Clear all Cause registers */
-   mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
+   on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
 
/* Mask all interrupts */
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+   on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
 
/* Enable MBUS Retry bit16 */
@@ -2528,31 +2561,6 @@ static int mvneta_setup_txqs(struct mvneta_port *pp)
return 0;
 }
 
-static void mvneta_percpu_unmask_interrupt(void *arg)
-{
-   struct mvneta_port *pp = arg;
-
-   /* All the queue are unmasked, but actually only the ones
-* maped to this CPU will be unmasked
-*/
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK,
-   MVNETA_RX_INTR_MASK_ALL |
-   MVNETA_TX_INTR_MASK_ALL |
-   MVNETA_MISCINTR_INTR_MASK);
-}
-
-static void mvneta_percpu_mask_interrupt(void *arg)
-{
-   struct mvneta_port *pp = arg;
-
-   /* All the queue are masked, but actually only the ones
-* maped to this CPU will be masked
-*/
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-}
-
 static void mvneta_start_dev(struct mvneta_port *pp)
 {
int cpu;
@@ -2603,13 +2611,10 @@ static void mvneta_stop_dev(struct mvneta_port *pp)
mvneta_port_disable(pp);
 
/* Clear all ethernet port interrupts */
-   mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
+   on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
 
/* Mask all ethernet port interrupts */
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+   on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
 
mvneta_tx_reset(pp);
mvneta_rx_reset(pp);
@@ -2916,9 +2921,7 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
}
 
/* Mask all ethernet port interrupts */
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+   on_each_cpu(mvneta_percpu_mask_int

[PATCH net 6/6] net: mvneta: Fix race condition during stopping

[Gregory CLEMENT]

When stopping the port, the CPU notifier are still there whereas the
mvneta_stop_dev function calls mvneta_percpu_disable() on each CPUs.
It was possible to have a new CPU coming at this point which could be
racy.

This patch adds a flag preventing executing the code notifier for a new CPU
when the port is stopping.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 3358c9a70467..22962fac47c2 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -372,6 +372,7 @@ struct mvneta_port {
int rxq_def;
/* protect  */
spinlock_t lock;
+   bool is_stopping;
 
/* Core clock */
struct clk *clk;
@@ -2914,6 +2915,11 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
switch (action) {
case CPU_ONLINE:
case CPU_ONLINE_FROZEN:
+   /* Configuring the driver for a new CPU while the
+* driver is stopping is racy, so just avoid it.
+*/
+   if (pp->is_stopping)
+   break;
netif_tx_stop_all_queues(pp->dev);
 
/* We have to synchronise on tha napi of each CPU
@@ -3052,9 +3058,17 @@ static int mvneta_stop(struct net_device *dev)
 {
struct mvneta_port *pp = netdev_priv(dev);
 
+   /* Inform that we are stopping so we don't want to setup the
+* driver for new CPUs in the notifiers
+*/
+   pp->is_stopping = true;
mvneta_stop_dev(pp);
mvneta_mdio_remove(pp);
unregister_cpu_notifier(>cpu_notifier);
+   /* Now that the notifier are unregistered, we can clear the
+* flag
+*/
+   pp->is_stopping = false;
on_each_cpu(mvneta_percpu_disable, pp, true);
free_percpu_irq(dev->irq, pp->ports);
mvneta_cleanup_rxqs(pp);
-- 
2.5.0

[PATCH net 0/6] mvneta fixes for SMP

[Gregory CLEMENT]

Hi,

Following this bug report:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/468173 and the
suggestions from Russell King, I reviewed all the code involving
multi-CPU. It ended with this series of patches which should improve
the stability of the driver.

The first patch fix a real bug, the other fix potential issues in the
driver.

Thanks,

Gregory

Gregory CLEMENT (6):
  net: mvneta: Fix for_each_present_cpu usage
  net: mvneta: Use on_each_cpu when possible
  net: mvneta: Remove unused code
  net: mvneta: Modify the queue related fields from each cpu
  net: mvneta: The mvneta_percpu_elect function should be atomic
  net: mvneta: Fix race condition during stopping

 drivers/net/ethernet/marvell/mvneta.c | 160 +-
 1 file changed, 82 insertions(+), 78 deletions(-)

-- 
2.5.0

[PATCH net 1/6] net: mvneta: Fix for_each_present_cpu usage

[Gregory CLEMENT]

This patch convert the for_each_present in on_each_cpu, instead of
applying on the present cpus it will be applied only on the online cpus.
This fix a bug reported on
http://thread.gmane.org/gmane.linux.ports.arm.kernel/468173.

Using the macro on_each_cpu (instead of a for_each_* loop) also ensures
that all the calls will be done all at once.

Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
Reported-by: Stefan Roese <stefan.ro...@gmail.com>
Suggested-by: Jisheng Zhang <jszh...@marvell.com>
Suggested-by: Russell King <rmk+ker...@arm.linux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 662c2ee268c7..90ff5c7e19ea 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2564,7 +2564,7 @@ static void mvneta_start_dev(struct mvneta_port *pp)
mvneta_port_enable(pp);
 
/* Enable polling on the port */
-   for_each_present_cpu(cpu) {
+   for_each_online_cpu(cpu) {
struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
 
napi_enable(>napi);
@@ -2589,7 +2589,7 @@ static void mvneta_stop_dev(struct mvneta_port *pp)
 
phy_stop(pp->phy_dev);
 
-   for_each_present_cpu(cpu) {
+   for_each_online_cpu(cpu) {
struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
 
napi_disable(>napi);
@@ -3057,13 +3057,11 @@ err_cleanup_rxqs:
 static int mvneta_stop(struct net_device *dev)
 {
struct mvneta_port *pp = netdev_priv(dev);
-   int cpu;
 
mvneta_stop_dev(pp);
mvneta_mdio_remove(pp);
unregister_cpu_notifier(>cpu_notifier);
-   for_each_present_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_disable, pp, true);
+   on_each_cpu(mvneta_percpu_disable, pp, true);
free_percpu_irq(dev->irq, pp->ports);
mvneta_cleanup_rxqs(pp);
mvneta_cleanup_txqs(pp);
-- 
2.5.0

[PATCH net 2/6] net: mvneta: Use on_each_cpu when possible

[Gregory CLEMENT]

Instead of using a for_each_* loop in which we just call the
smp_call_function_single macro, it is more simple to directly use the
on_each_cpu macro. Moreover, this macro ensures that the calls will be
done all at once.

Suggested-by: Russell King <rmk+ker...@arm.linux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 17 ++---
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 90ff5c7e19ea..3d6e3137f305 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2555,7 +2555,7 @@ static void mvneta_percpu_mask_interrupt(void *arg)
 
 static void mvneta_start_dev(struct mvneta_port *pp)
 {
-   unsigned int cpu;
+   int cpu;
 
mvneta_max_rx_size_set(pp, pp->pkt_size);
mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
@@ -2571,9 +2571,8 @@ static void mvneta_start_dev(struct mvneta_port *pp)
}
 
/* Unmask interrupts. It has to be done from each CPU */
-   for_each_online_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
-pp, true);
+   on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
+
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
MVNETA_CAUSE_PHY_STATUS_CHANGE |
MVNETA_CAUSE_LINK_CHANGE |
@@ -2988,7 +2987,7 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
 static int mvneta_open(struct net_device *dev)
 {
struct mvneta_port *pp = netdev_priv(dev);
-   int ret, cpu;
+   int ret;
 
pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
@@ -3021,9 +3020,7 @@ static int mvneta_open(struct net_device *dev)
/* Enable per-CPU interrupt on all the CPU to handle our RX
 * queue interrupts
 */
-   for_each_online_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_enable,
-pp, true);
+   on_each_cpu(mvneta_percpu_enable, pp, true);
 
 
/* Register a CPU notifier to handle the case where our CPU
@@ -3310,9 +3307,7 @@ static int  mvneta_config_rss(struct mvneta_port *pp)
 
netif_tx_stop_all_queues(pp->dev);
 
-   for_each_online_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_mask_interrupt,
-pp, true);
+   on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
 
/* We have to synchronise on the napi of each CPU */
for_each_online_cpu(cpu) {
-- 
2.5.0

[PATCH 04/10] Documentation: dt-bindings: Add a new compatible for the Armada 3700

[Gregory CLEMENT]

The AHCI interfaces used in the Armada 3700 has a few differences with
the one used in the Armada 38x, so it deserves its own compatible string.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt 
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c2340eeeb97f..796e2c23e5df 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -13,6 +13,7 @@ Required properties:
   - "hisilicon,hisi-ahci"
   - "ibm,476gtr-ahci"
   - "marvell,armada-380-ahci"
+  - "marvell,armada-3700-ahci"
   - "snps,dwc-ahci"
   - "snps,exynos5440-ahci"
   - "snps,spear-ahci"
-- 
2.5.0

[PATCH 07/10] arm64: dts: add the Marvell Armada 3700 family and a development board

[Gregory CLEMENT]

Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).

It also adds a dts file for the Marvell Armada 3720 DB board.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/Makefile   |   4 +
 arch/arm64/boot/dts/marvell/armada-371x.dtsi   |  53 ++
 arch/arm64/boot/dts/marvell/armada-3720-db.dts |  87 
 arch/arm64/boot/dts/marvell/armada-372x.dtsi   |  63 
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 131 +
 5 files changed, 338 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-371x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-db.dts
 create mode 100644 arch/arm64/boot/dts/marvell/armada-372x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-37xx.dtsi

diff --git a/arch/arm64/boot/dts/marvell/Makefile 
b/arch/arm64/boot/dts/marvell/Makefile
index 348f4db4f313..bc2eabe1cab1 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -1,6 +1,10 @@
+# Berlin SoC Family
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
 
+# Mvebu SoC Family
+dtb-$(CONFIG_ARCH_ARMADA_3700) += armada-3720-db.dtb
+
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
 clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi 
b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
new file mode 100644
index ..c9e5325b8ac3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Device Tree Include file for Marvell Armada 371x family of SoCs
+ * (also named 88F3710)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+   model = "Marvell Armada 3710 SoC";
+   compatible = "marvell,armada3710", "marvell,armada3700";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts 
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
new file mode 100644
index ..76cae6ba2bd6
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -0,0 +1,87 @@
+/*
+ * Device Tree file for Marvell Armada 3720 development board
+ * (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option)

[PATCH 09/10] Documentation: arm: update supported Marvell EBU processors

[Gregory CLEMENT]

Now that we support Armada 37xx, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details about
those processors. As for Armda 39x, no datasheet is publicly
available at this time.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 Documentation/arm/Marvell/README | 13 +
 1 file changed, 13 insertions(+)

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index ae89b67d8e23..ddbc048bb467 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -118,6 +118,19 @@ EBU Armada family
   Linux kernel mach directory: arch/arm/mach-mvebu
   Linux kernel plat directory: none
 
+EBU Armada family ARMv8
+---
+
+  Armada 3710/3720 Flavors:
+   88F3710
+   88F3720
+
+  Core: ARM Cortex A53 (ARMv8)
+
+  Homepage : http://www.marvell.com/embedded-processors/armada-3700/
+
+  Device tree descritpion located in arch/arm64/boot/dts/marvell/armada-37*
+
 Avanta family
 -
 
-- 
2.5.0

[PATCH 03/10] arm64: add Armada 3700 architecture entry

[Gregory CLEMENT]

The Armada 3700 is an mvebu ARM64 SoC using one or two Cortex-A53 cores
depending of the variant.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/Kconfig.platforms | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 21074f674bde..7da341f7b90d 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -1,5 +1,11 @@
 menu "Platform selection"
 
+config ARCH_ARMADA_3700
+   bool "Armada 3700 SoC Family"
+   help
+ This enables support for Armada 3700 SoC Family. It is is an
+ ARMv8 based chipset belonging to the mvebu family.
+
 config ARCH_BCM_IPROC
bool "Broadcom iProc SoC Family"
help
-- 
2.5.0

[PATCH 06/10] devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family

[Gregory CLEMENT]

The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit
introduces the Device Tree binding that documents the top-level
compatible strings for Armada 3700 based platforms.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 .../devicetree/bindings/arm/marvell/armada-37xx.txt | 17 +
 1 file changed, 17 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
new file mode 100644
index ..5db9f1a90da2
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
@@ -0,0 +1,17 @@
+Marvell Armada 37xx Platforms Device Tree Bindings
+--
+
+Boards using a SoC of the Marvell Armada 37xx family must carry the
+following root node property:
+
+ - compatible: must contain "marvell,armada3700"
+
+In addition, depending on whether the Armada 3710 or Armada 3720 SoCs
+are being used, the following root node property must be added:
+
+ - compatible: must contain either "marvell,armada3710" or
+   "marvell,armada3720"
+
+Example:
+
+compatible = "marvell,armada-3720-db", "marvell,armada3720", 
"marvell,armada3700";
-- 
2.5.0

[PATCH 00/10] Add support for the Armada 3700 SoC an mvebu ARM64 based

[Gregory CLEMENT]

Hi,

This series introduce the support of the Armada 3700 family: it is the
first ARM64 SoC of the mvebu family submitted to the mainline!

Currently there are two members of the Armada 3700 family, the only
difference is the number of core: the Armada 3710 comes with one
Cortex-A53 whereas the Armada 3720 comes with 2 Cortex-A53. In this
series we enabled only the minimum to boot, pinctrl and clock tree
will come soon.

Besides this the patches are pretty usual:

The first patch introduces a new serial driver for the uart used on
this SoC. The driver remains simple even if the hardware is capable of
doing more.

The second one adapts the ahci driver to support the Armada 3700 SoC.
The forth patch updates the binding documentation with the new
compatible string.

The third patch adds a new entry Kconfig entry for this SoC family.

I took the opportunity of this series to tidy up the Marvell related
files in the binding documentation with the fifth patch.

The sixth patch introduces the compatible string for the SoCs of the
Armada 3700 family.

The seventh patch could be considered as the bulk of this series: it
adds the device tree files for the Armada 3700 SoCs and for the
reference board.

With the introduction of this new family the MAINTAINERS file, the
Marvell README and the ARM64 defconfig files have to be updated: it is
the purpose of the last 3 patches.

The first two patches could be taken directly by the maintainer of
their respective subsystem as there is no dependency at all with the
rest of the series. I think that the rest of the series should go
through the arm-soc maintainer but in doubt I also added the ARM64
maintainer as suggested by get_maintainer.pl. Actually all the patches
are independents.

Thanks,

Gregory

Gregory CLEMENT (8):
  arm64: add Armada 3700 architecture entry
  Documentation: dt-bindings: Add a new compatible for the Armada 3700
  Documentation: dt: Tidy up the Marvell related files
  devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC
family
  arm64: dts: add the Marvell Armada 3700 family and a development board
  MAINTAINERS: Extend dts entry for ARM64 mvebu files
  Documentation: arm: update supported Marvell EBU processors
  arm64: defconfig: enable Armada 3700 related config

Lior Amsalem (1):
  ata: ahci_mvebu: add support for Armada 3700 variant

Wilson Ding (1):
  serial: mvebu-uart: initial support for Armada-3700 serial port

 Documentation/arm/Marvell/README   |  13 +
 .../arm/{ => marvell}/armada-370-xp-pmsu.txt   |   0
 .../bindings/arm/{ => marvell}/armada-370-xp.txt   |   0
 .../bindings/arm/{ => marvell}/armada-375.txt  |   0
 .../bindings/arm/marvell/armada-37xx.txt   |  17 +
 .../{ => marvell}/armada-380-mpcore-soc-ctrl.txt   |   0
 .../bindings/arm/{ => marvell}/armada-38x.txt  |   0
 .../bindings/arm/{ => marvell}/armada-39x.txt  |   0
 .../arm/{ => marvell}/armada-cpu-reset.txt |   0
 .../arm/{ => marvell}/coherency-fabric.txt |   0
 .../bindings/arm/{ => marvell}/kirkwood.txt|   0
 .../bindings/arm/{ => marvell}/marvell,berlin.txt  |   0
 .../bindings/arm/{ => marvell}/marvell,dove.txt|   0
 .../arm/{ => marvell}/marvell,kirkwood.txt |   0
 .../arm/{ => marvell}/mvebu-cpu-config.txt |   0
 .../arm/{ => marvell}/mvebu-system-controller.txt  |   0
 .../devicetree/bindings/ata/ahci-platform.txt  |   1 +
 .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
 Documentation/kernel-parameters.txt|   6 +
 MAINTAINERS|   1 +
 arch/arm64/Kconfig.platforms   |   6 +
 arch/arm64/boot/dts/marvell/Makefile   |   4 +
 arch/arm64/boot/dts/marvell/armada-371x.dtsi   |  53 ++
 arch/arm64/boot/dts/marvell/armada-3720-db.dts |  87 +++
 arch/arm64/boot/dts/marvell/armada-372x.dtsi   |  63 ++
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 131 +
 arch/arm64/configs/defconfig   |   5 +
 drivers/ata/Kconfig|   2 +-
 drivers/ata/ahci_mvebu.c   |  14 +-
 drivers/tty/serial/Kconfig |  22 +
 drivers/tty/serial/Makefile|   1 +
 drivers/tty/serial/mvebu-uart.c| 649 +
 include/uapi/linux/serial_core.h   |   3 +
 33 files changed, 1085 insertions(+), 6 deletions(-)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-370-xp-pmsu.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt 
(100%)
 create mode 100644 
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-380-mpcore-soc-ctrl.txt (100%)
 rename Documentation/devi

[PATCH 08/10] MAINTAINERS: Extend dts entry for ARM64 mvebu files

[Gregory CLEMENT]

Extend the mvebu entry to ARM64 device tree sources.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 30aca4aa5467..ad49b62c5abc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1279,6 +1279,7 @@ F:arch/arm/mach-mvebu/
 F: drivers/rtc/rtc-armada38x.c
 F: arch/arm/boot/dts/armada*
 F: arch/arm/boot/dts/kirkwood*
+F: arch/arm64/boot/dts/marvell/armada*
 
 
 ARM/Marvell Berlin SoC support
-- 
2.5.0

[PATCH 01/10] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

From: Wilson Ding <ding...@marvell.com>

Armada-3700's uart is a simple serial port, which doesn't
support. Configuring the modem control lines. The uart port has a 32
bytes Tx FIFO and a 64 bytes Rx FIFO

The uart driver implements the uart core operations. It also support the
system (early) console based on Armada-3700's serial port.

Known Issue:

The uart driver currently doesn't support clock programming, which means
the baud-rate stays with the default value configured by the bootloader
at boot time

[gregory.clem...@free-electrons.com: Rewrite many part which are too long
to enumerate]

Signed-off-by: Wilson Ding <ding...@marvell.com>
Signed-off-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
 Documentation/kernel-parameters.txt|   6 +
 drivers/tty/serial/Kconfig |  22 +
 drivers/tty/serial/Makefile|   1 +
 drivers/tty/serial/mvebu-uart.c| 649 +
 include/uapi/linux/serial_core.h   |   3 +
 6 files changed, 694 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
 create mode 100644 drivers/tty/serial/mvebu-uart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt 
b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
new file mode 100644
index ..6087defd9f93
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
@@ -0,0 +1,13 @@
+* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., 
Armada-3700)
+
+Required properties:
+- compatible: "marvell,armada-3700-uart"
+- reg: offset and length of the register set for the device.
+- interrupts: device interrupt
+
+Example:
+   serial@12000 {
+   compatible = "marvell,armada-3700-uart";
+   reg = <0x12000 0x400>;
+   interrupts = <43>;
+   };
diff --git a/Documentation/kernel-parameters.txt 
b/Documentation/kernel-parameters.txt
index 87d40a72f6a1..198f6bd56e84 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1058,6 +1058,12 @@ bytes respectively. Such letter suffixes can also be 
entirely omitted.
A valid base address must be provided, and the serial
port must already be setup and configured.
 
+   mvebu_uart,
+   Start an early, polled-mode console on an some mvebu
+   SoC (as the Armada-3700) serial port at the specified
+   address. The serial port must already be setup and
+   configured. Options are not yet supported.
+
earlyprintk=[X86,SH,BLACKFIN,ARM,M68k]
earlyprintk=vga
earlyprintk=efi
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 39721ec4f415..b291f934d51b 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1606,6 +1606,28 @@ config SERIAL_STM32_CONSOLE
depends on SERIAL_STM32=y
select SERIAL_CORE_CONSOLE
 
+config SERIAL_MVEBU_UART
+   bool "Marvell EBU serial port support"
+   select SERIAL_CORE
+   help
+ This driver is for Marvell EBU SoC's UART. If you have a machine
+ based on the Armada-3700 SoC and wish to use the on-board serial
+ port,
+ say 'Y' here.
+ Otherwise, say 'N'.
+
+config SERIAL_MVEBU_CONSOLE
+   bool "Console on Marvell EBU serial port"
+   depends on SERIAL_MVEBU_UART
+   select SERIAL_CORE_CONSOLE
+   select SERIAL_EARLYCON
+   default y
+   help
+ Say 'Y' here if you wish to use Armada-3700 UART as the system 
console.
+ (the system console is the device which receives all kernel messages
+ and warnings and which allows logins in single user mode)
+ Otherwise, say 'N'.
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index b391c9b31960..988167595330 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR)   += 
digicolor-usart.o
 obj-$(CONFIG_SERIAL_MEN_Z135)  += men_z135_uart.o
 obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
 obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
+obj-$(CONFIG_SERIAL_MVEBU_UART)+= mvebu-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
new file mode 100644
index ..9624070d6058
--- /dev/null
+++ b/drivers/tty/serial/mvebu-uart.c
@@ -0,0 +1,649 @@
+/*
+* ***

[PATCH 10/10] arm64: defconfig: enable Armada 3700 related config

[Gregory CLEMENT]

This patch enables the configuration for the Armada 3700 family and for
the related driver it uses.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/configs/defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 18ca9fb9e65f..f7f3ce09ead0 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_ARMADA_3700=y
 CONFIG_ARCH_BCM_IPROC=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_EXYNOS7=y
@@ -93,6 +94,7 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
 CONFIG_AHCI_XGENE=y
 CONFIG_SATA_RCAR=y
 CONFIG_PATA_PLATFORM=y
@@ -132,6 +134,7 @@ CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
 CONFIG_VIRTIO_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
@@ -162,6 +165,8 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_RCAR=y
 CONFIG_SND_SOC_AK4613=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.5.0

[PATCH 05/10] Documentation: dt: Tidy up the Marvell related files

[Gregory CLEMENT]

Over the last releases we have added more and more Marvell related binding
directly in the arm directory. It's time to have our proper directory
inside it, and move all the files in it.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 .../devicetree/bindings/arm/{ => marvell}/armada-370-xp-pmsu.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt| 0
 .../devicetree/bindings/arm/{ => marvell}/armada-380-mpcore-soc-ctrl.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-cpu-reset.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/coherency-fabric.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/mvebu-cpu-config.txt  | 0
 .../devicetree/bindings/arm/{ => marvell}/mvebu-system-controller.txt | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-370-xp-pmsu.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-380-mpcore-soc-ctrl.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-cpu-reset.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/coherency-fabric.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/marvell,kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-cpu-config.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-system-controller.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-375.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-375.txt
diff --git 
a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
rename to 
Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-38x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-39x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-cpu-reset.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt
diff --git a/Documentation/devicet

[PATCH 02/10] ata: ahci_mvebu: add support for Armada 3700 variant

[Gregory CLEMENT]

From: Lior Amsalem <al...@marvell.com>

The main difference in the new Armada 3700 is that no address
decoding needs to take place in the driver probe.

[gregory.clem...@free-electrons.com: reformulate the commit log]

Signed-off-by: Lior Amsalem <al...@marvell.com>
Reviewed-by: Nadav Haklai <nad...@marvell.com>
Tested-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/ata/Kconfig  |  2 +-
 drivers/ata/ahci_mvebu.c | 14 +-
 2 files changed, 10 insertions(+), 6 deletions(-)

diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index 861643ea91b5..1cc0c966ff88 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -144,7 +144,7 @@ config AHCI_CEVA
 
 config AHCI_MVEBU
tristate "Marvell EBU AHCI SATA support"
-   depends on ARCH_MVEBU
+   depends on ARCH_MVEBU || ARCH_ARMADA_3700
help
  This option enables support for the Marvebu EBU SoC's
  onboard AHCI SATA.
diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index f7a7fa81740e..de7128d81e9c 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -112,12 +112,15 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
if (rc)
return rc;
 
-   dram = mv_mbus_dram_info();
-   if (!dram)
-   return -ENODEV;
+   if (of_device_is_compatible(pdev->dev.of_node,
+   "marvell,armada-380-ahci")) {
+   dram = mv_mbus_dram_info();
+   if (!dram)
+   return -ENODEV;
 
-   ahci_mvebu_mbus_config(hpriv, dram);
-   ahci_mvebu_regret_option(hpriv);
+   ahci_mvebu_mbus_config(hpriv, dram);
+   ahci_mvebu_regret_option(hpriv);
+   }
 
rc = ahci_platform_init_host(pdev, hpriv, _mvebu_port_info,
 _platform_sht);
@@ -133,6 +136,7 @@ disable_resources:
 
 static const struct of_device_id ahci_mvebu_of_match[] = {
{ .compatible = "marvell,armada-380-ahci", },
+   { .compatible = "marvell,armada-3700-ahci", },
{ },
 };
 MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
-- 
2.5.0

Re: [PATCH net 5/6] net: mvneta: The mvneta_percpu_elect function should be atomic

[Gregory CLEMENT]

Hi David,
 
 On sam., janv. 30 2016, David Miller <da...@davemloft.net> wrote:

> From: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Date: Fri, 29 Jan 2016 17:26:06 +0100
>
>> @@ -370,6 +370,8 @@ struct mvneta_port {
>>  struct net_device *dev;
>>  struct notifier_block cpu_notifier;
>>  int rxq_def;
>> +/* protect  */
>> +spinlock_t lock;
>>  
>>  /* Core clock */
>>  struct clk *clk;
>
> Protect what?  This comment needs a lot of improvement.

Sorry about it, this was a left-over.

>
> Everyone knows a spinlock "protects" things, so if you aren't going
> to actually describe what this lock protects, and in what contexts
> the lock is used, you might as well not say anything at all.

I can only agree with you, I will fix it for next version.

Thanks,

Gregory


-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 net 3/6] net: mvneta: Remove unused code

[Gregory CLEMENT]

Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
each CPU") all the percpu irq are used and unmask at initialization, so
there is no point to unmask them first.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 8 
 1 file changed, 8 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 3d6e3137f305..861b7e0d7d5f 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -3009,14 +3009,6 @@ static int mvneta_open(struct net_device *dev)
goto err_cleanup_txqs;
}
 
-   /* Even though the documentation says that request_percpu_irq
-* doesn't enable the interrupts automatically, it actually
-* does so on the local CPU.
-*
-* Make sure it's disabled.
-*/
-   mvneta_percpu_disable(pp);
-
/* Enable per-CPU interrupt on all the CPU to handle our RX
 * queue interrupts
 */
-- 
2.5.0

[PATCH v2 net 0/6] mvneta fixes for SMP

[Gregory CLEMENT]

Hi,

Following this bug report:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/468173 and the
suggestions from Russell King, I reviewed all the code involving
multi-CPU. It ended with this series of patches which should improve
the stability of the driver.

The first patch fix a real bug, the other fix potential issues in the
driver.

Thanks,

Gregory

Changelog:

v1 -> v2
Fix spinlock comment. Pointed by David Miller


Gregory CLEMENT (6):
  net: mvneta: Fix for_each_present_cpu usage
  net: mvneta: Use on_each_cpu when possible
  net: mvneta: Remove unused code
  net: mvneta: Modify the queue related fields from each cpu
  net: mvneta: The mvneta_percpu_elect function should be atomic
  net: mvneta: Fix race condition during stopping

 drivers/net/ethernet/marvell/mvneta.c | 162 ++
 1 file changed, 84 insertions(+), 78 deletions(-)

-- 
2.5.0

[PATCH v2 net 2/6] net: mvneta: Use on_each_cpu when possible

[Gregory CLEMENT]

Instead of using a for_each_* loop in which we just call the
smp_call_function_single macro, it is more simple to directly use the
on_each_cpu macro. Moreover, this macro ensures that the calls will be
done all at once.

Suggested-by: Russell King <rmk+ker...@arm.linux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 17 ++---
 1 file changed, 6 insertions(+), 11 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 90ff5c7e19ea..3d6e3137f305 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2555,7 +2555,7 @@ static void mvneta_percpu_mask_interrupt(void *arg)
 
 static void mvneta_start_dev(struct mvneta_port *pp)
 {
-   unsigned int cpu;
+   int cpu;
 
mvneta_max_rx_size_set(pp, pp->pkt_size);
mvneta_txq_max_tx_size_set(pp, pp->pkt_size);
@@ -2571,9 +2571,8 @@ static void mvneta_start_dev(struct mvneta_port *pp)
}
 
/* Unmask interrupts. It has to be done from each CPU */
-   for_each_online_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_unmask_interrupt,
-pp, true);
+   on_each_cpu(mvneta_percpu_unmask_interrupt, pp, true);
+
mvreg_write(pp, MVNETA_INTR_MISC_MASK,
MVNETA_CAUSE_PHY_STATUS_CHANGE |
MVNETA_CAUSE_LINK_CHANGE |
@@ -2988,7 +2987,7 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
 static int mvneta_open(struct net_device *dev)
 {
struct mvneta_port *pp = netdev_priv(dev);
-   int ret, cpu;
+   int ret;
 
pp->pkt_size = MVNETA_RX_PKT_SIZE(pp->dev->mtu);
pp->frag_size = SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(pp->pkt_size)) +
@@ -3021,9 +3020,7 @@ static int mvneta_open(struct net_device *dev)
/* Enable per-CPU interrupt on all the CPU to handle our RX
 * queue interrupts
 */
-   for_each_online_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_enable,
-pp, true);
+   on_each_cpu(mvneta_percpu_enable, pp, true);
 
 
/* Register a CPU notifier to handle the case where our CPU
@@ -3310,9 +3307,7 @@ static int  mvneta_config_rss(struct mvneta_port *pp)
 
netif_tx_stop_all_queues(pp->dev);
 
-   for_each_online_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_mask_interrupt,
-pp, true);
+   on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
 
/* We have to synchronise on the napi of each CPU */
for_each_online_cpu(cpu) {
-- 
2.5.0

[PATCH v2 net 1/6] net: mvneta: Fix for_each_present_cpu usage

[Gregory CLEMENT]

This patch convert the for_each_present in on_each_cpu, instead of
applying on the present cpus it will be applied only on the online cpus.
This fix a bug reported on
http://thread.gmane.org/gmane.linux.ports.arm.kernel/468173.

Using the macro on_each_cpu (instead of a for_each_* loop) also ensures
that all the calls will be done all at once.

Fixes: f86428854480 ("net: mvneta: Statically assign queues to CPUs")
Reported-by: Stefan Roese <stefan.ro...@gmail.com>
Suggested-by: Jisheng Zhang <jszh...@marvell.com>
Suggested-by: Russell King <rmk+ker...@arm.linux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 8 +++-
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 662c2ee268c7..90ff5c7e19ea 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -2564,7 +2564,7 @@ static void mvneta_start_dev(struct mvneta_port *pp)
mvneta_port_enable(pp);
 
/* Enable polling on the port */
-   for_each_present_cpu(cpu) {
+   for_each_online_cpu(cpu) {
struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
 
napi_enable(>napi);
@@ -2589,7 +2589,7 @@ static void mvneta_stop_dev(struct mvneta_port *pp)
 
phy_stop(pp->phy_dev);
 
-   for_each_present_cpu(cpu) {
+   for_each_online_cpu(cpu) {
struct mvneta_pcpu_port *port = per_cpu_ptr(pp->ports, cpu);
 
napi_disable(>napi);
@@ -3057,13 +3057,11 @@ err_cleanup_rxqs:
 static int mvneta_stop(struct net_device *dev)
 {
struct mvneta_port *pp = netdev_priv(dev);
-   int cpu;
 
mvneta_stop_dev(pp);
mvneta_mdio_remove(pp);
unregister_cpu_notifier(>cpu_notifier);
-   for_each_present_cpu(cpu)
-   smp_call_function_single(cpu, mvneta_percpu_disable, pp, true);
+   on_each_cpu(mvneta_percpu_disable, pp, true);
free_percpu_irq(dev->irq, pp->ports);
mvneta_cleanup_rxqs(pp);
mvneta_cleanup_txqs(pp);
-- 
2.5.0

[PATCH v2 net 5/6] net: mvneta: The mvneta_percpu_elect function should be atomic

[Gregory CLEMENT]

Electing a CPU must be done in an atomic way: it should be done after or
before the removal/insertion of a CPU and this function is not reentrant.

During the loop of mvneta_percpu_elect we associates the queues to the
CPUs, if there is a topology change during this loop, then the mapping
between the CPUs and the queues could be wrong. During this loop the
interrupt mask is also updating for each CPUs, It should not be changed
in the same time by other part of the driver.

This patch adds spinlock to create the needed critical sections.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 15 +++
 1 file changed, 15 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 1ed813d478e8..4d40d2fde7ca 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -370,6 +370,10 @@ struct mvneta_port {
struct net_device *dev;
struct notifier_block cpu_notifier;
int rxq_def;
+   /* Protect the access to the percpu interrupt registers,
+* ensuring that the configuration remains coherent.
+*/
+   spinlock_t lock;
 
/* Core clock */
struct clk *clk;
@@ -2855,6 +2859,11 @@ static void mvneta_percpu_elect(struct mvneta_port *pp)
 {
int online_cpu_idx, max_cpu, cpu, i = 0;
 
+   /* Electing a CPU must done in an atomic way: it should be
+* done after or before the removal/insertion of a CPU and
+* this function is not reentrant.
+*/
+   spin_lock(>lock);
online_cpu_idx = pp->rxq_def % num_online_cpus();
max_cpu = num_present_cpus();
 
@@ -2893,6 +2902,7 @@ static void mvneta_percpu_elect(struct mvneta_port *pp)
i++;
 
}
+   spin_unlock(>lock);
 };
 
 static int mvneta_percpu_notifier(struct notifier_block *nfb,
@@ -2947,8 +2957,13 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
case CPU_DOWN_PREPARE:
case CPU_DOWN_PREPARE_FROZEN:
netif_tx_stop_all_queues(pp->dev);
+   /* Thanks to this lock we are sure that any pending
+* cpu election is done
+*/
+   spin_lock(>lock);
/* Mask all ethernet port interrupts */
on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
+   spin_unlock(>lock);
 
napi_synchronize(>napi);
napi_disable(>napi);
-- 
2.5.0

Re: [PATCH v2 net 3/6] net: mvneta: Remove unused code

[Gregory CLEMENT]

Hi Sergei,
 
 On lun., févr. 01 2016, Sergei Shtylyov <sergei.shtyl...@cogentembedded.com> 
wrote:

> Hello.
>
> On 2/1/2016 4:07 PM, Gregory CLEMENT wrote:
>
>> Since the commit 2dcf75e2793c ("net: mvneta: Associate RX queues with
>> each CPU") all the percpu irq are used and unmask at initialization, so
>
>Unmasked, you mean?

yes and disabled would be more appropriate actually.

>
>> there is no point to unmask them first.
>
>Mask, maybe (looking at the patch)?

not mask, but here again disable would be more appropriate. The code
removed disables the interrupt.


Thanks,

Gregory

>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>>   drivers/net/ethernet/marvell/mvneta.c | 8 
>>   1 file changed, 8 deletions(-)
>>
>> diff --git a/drivers/net/ethernet/marvell/mvneta.c 
>> b/drivers/net/ethernet/marvell/mvneta.c
>> index 3d6e3137f305..861b7e0d7d5f 100644
>> --- a/drivers/net/ethernet/marvell/mvneta.c
>> +++ b/drivers/net/ethernet/marvell/mvneta.c
>> @@ -3009,14 +3009,6 @@ static int mvneta_open(struct net_device *dev)
>>  goto err_cleanup_txqs;
>>  }
>>
>> -/* Even though the documentation says that request_percpu_irq
>> - * doesn't enable the interrupts automatically, it actually
>> - * does so on the local CPU.
>> - *
>> - * Make sure it's disabled.
>> - */
>> -mvneta_percpu_disable(pp);
>> -
>>  /* Enable per-CPU interrupt on all the CPU to handle our RX
>>   * queue interrupts
>>   */
>
> MBR, Sergei
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 net 4/6] net: mvneta: Modify the queue related fields from each cpu

[Gregory CLEMENT]

In the MVNETA_INTR_* registers, the queues related fields are per cpu,
according to the datasheet (comment in [] are added by me):
"In a multi-CPU system, bits of RX[or TX] queues for which the access by
the reading[or writing] CPU is disabled are read as 0, and cannot be
cleared[or written]."

That means that each time we want to manipulate these bits we had to do
it on each cpu and not only on the current cpu.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 100 --
 1 file changed, 46 insertions(+), 54 deletions(-)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 861b7e0d7d5f..1ed813d478e8 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -1038,6 +1038,43 @@ static void mvneta_set_autoneg(struct mvneta_port *pp, 
int enable)
}
 }
 
+static void mvneta_percpu_unmask_interrupt(void *arg)
+{
+   struct mvneta_port *pp = arg;
+
+   /* All the queue are unmasked, but actually only the ones
+* mapped to this CPU will be unmasked
+*/
+   mvreg_write(pp, MVNETA_INTR_NEW_MASK,
+   MVNETA_RX_INTR_MASK_ALL |
+   MVNETA_TX_INTR_MASK_ALL |
+   MVNETA_MISCINTR_INTR_MASK);
+}
+
+static void mvneta_percpu_mask_interrupt(void *arg)
+{
+   struct mvneta_port *pp = arg;
+
+   /* All the queue are masked, but actually only the ones
+* mapped to this CPU will be masked
+*/
+   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
+   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
+   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+}
+
+static void mvneta_percpu_clear_intr_cause(void *arg)
+{
+   struct mvneta_port *pp = arg;
+
+   /* All the queue are cleared, but actually only the ones
+* mapped to this CPU will be cleared
+*/
+   mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
+   mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
+   mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
+}
+
 /* This method sets defaults to the NETA port:
  * Clears interrupt Cause and Mask registers.
  * Clears all MAC tables.
@@ -1055,14 +1092,10 @@ static void mvneta_defaults_set(struct mvneta_port *pp)
int max_cpu = num_present_cpus();
 
/* Clear all Cause registers */
-   mvreg_write(pp, MVNETA_INTR_NEW_CAUSE, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
+   on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
 
/* Mask all interrupts */
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+   on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
mvreg_write(pp, MVNETA_INTR_ENABLE, 0);
 
/* Enable MBUS Retry bit16 */
@@ -2528,31 +2561,6 @@ static int mvneta_setup_txqs(struct mvneta_port *pp)
return 0;
 }
 
-static void mvneta_percpu_unmask_interrupt(void *arg)
-{
-   struct mvneta_port *pp = arg;
-
-   /* All the queue are unmasked, but actually only the ones
-* maped to this CPU will be unmasked
-*/
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK,
-   MVNETA_RX_INTR_MASK_ALL |
-   MVNETA_TX_INTR_MASK_ALL |
-   MVNETA_MISCINTR_INTR_MASK);
-}
-
-static void mvneta_percpu_mask_interrupt(void *arg)
-{
-   struct mvneta_port *pp = arg;
-
-   /* All the queue are masked, but actually only the ones
-* maped to this CPU will be masked
-*/
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
-}
-
 static void mvneta_start_dev(struct mvneta_port *pp)
 {
int cpu;
@@ -2603,13 +2611,10 @@ static void mvneta_stop_dev(struct mvneta_port *pp)
mvneta_port_disable(pp);
 
/* Clear all ethernet port interrupts */
-   mvreg_write(pp, MVNETA_INTR_MISC_CAUSE, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_CAUSE, 0);
+   on_each_cpu(mvneta_percpu_clear_intr_cause, pp, true);
 
/* Mask all ethernet port interrupts */
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+   on_each_cpu(mvneta_percpu_mask_interrupt, pp, true);
 
mvneta_tx_reset(pp);
mvneta_rx_reset(pp);
@@ -2916,9 +2921,7 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
}
 
/* Mask all ethernet port interrupts */
-   mvreg_write(pp, MVNETA_INTR_NEW_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_OLD_MASK, 0);
-   mvreg_write(pp, MVNETA_INTR_MISC_MASK, 0);
+   on_each_cpu(mvneta_percpu_mask_int

[PATCH v2 net 6/6] net: mvneta: Fix race condition during stopping

[Gregory CLEMENT]

When stopping the port, the CPU notifier are still there whereas the
mvneta_stop_dev function calls mvneta_percpu_disable() on each CPUs.
It was possible to have a new CPU coming at this point which could be
racy.

This patch adds a flag preventing executing the code notifier for a new CPU
when the port is stopping.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/mvneta.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 4d40d2fde7ca..2f53975aa6ec 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -374,6 +374,7 @@ struct mvneta_port {
 * ensuring that the configuration remains coherent.
 */
spinlock_t lock;
+   bool is_stopping;
 
/* Core clock */
struct clk *clk;
@@ -2916,6 +2917,11 @@ static int mvneta_percpu_notifier(struct notifier_block 
*nfb,
switch (action) {
case CPU_ONLINE:
case CPU_ONLINE_FROZEN:
+   /* Configuring the driver for a new CPU while the
+* driver is stopping is racy, so just avoid it.
+*/
+   if (pp->is_stopping)
+   break;
netif_tx_stop_all_queues(pp->dev);
 
/* We have to synchronise on tha napi of each CPU
@@ -3054,9 +3060,17 @@ static int mvneta_stop(struct net_device *dev)
 {
struct mvneta_port *pp = netdev_priv(dev);
 
+   /* Inform that we are stopping so we don't want to setup the
+* driver for new CPUs in the notifiers
+*/
+   pp->is_stopping = true;
mvneta_stop_dev(pp);
mvneta_mdio_remove(pp);
unregister_cpu_notifier(>cpu_notifier);
+   /* Now that the notifier are unregistered, we can clear the
+* flag
+*/
+   pp->is_stopping = false;
on_each_cpu(mvneta_percpu_disable, pp, true);
free_percpu_irq(dev->irq, pp->ports);
mvneta_cleanup_rxqs(pp);
-- 
2.5.0

Re: [PATCH 03/10] arm64: add Armada 3700 architecture entry

[Gregory CLEMENT]

Hi Jisheng,
 
 On mer., févr. 03 2016, Jisheng Zhang <jszh...@marvell.com> wrote:

> On Tue, 2 Feb 2016 19:07:41 +0100 Gregory CLEMENT wrote:
>
>> The Armada 3700 is an mvebu ARM64 SoC using one or two Cortex-A53 cores
>> depending of the variant.
>> 
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
>> ---
>>  arch/arm64/Kconfig.platforms | 6 ++
>>  1 file changed, 6 insertions(+)
>> 
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 21074f674bde..7da341f7b90d 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -1,5 +1,11 @@
>>  menu "Platform selection"
>>  
>> +config ARCH_ARMADA_3700
>
> Would it be better to use ARCH_MVEBU? IMHO, there will be more ARMv8 SoCs
> from our EBU, do we plan to add one CONFIG_ARMADA_yyzz for each SoC?

Not for each SoC but for each family, yes. As we did for the other mvebu
SoC families.

Gregory

>
>> +bool "Armada 3700 SoC Family"
>> +help
>> +  This enables support for Armada 3700 SoC Family. It is is an
>> +  ARMv8 based chipset belonging to the mvebu family.
>> +
>>  config ARCH_BCM_IPROC
>>  bool "Broadcom iProc SoC Family"
>>  help
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 07/10] arm64: dts: add the Marvell Armada 3700 family and a development board

[Gregory CLEMENT]

Hi Mark,
 
 On mar., févr. 02 2016, Mark Rutland <mark.rutl...@arm.com> wrote:

>> +memory {
>> +device_type = "memory";
>> +/* use only 256 MB on the 512 MB available */
>> +reg = <0x 0x 0x 0x1000>;
>> +};
>
> It would be good to comment as to why we can't use 256M of the memory.

Actually the comment is wrong and the size too, we do use the 512MB.

I will fix it

Thanks,

Gregory

>
> Otherwise this looks fine.
>
> Mark.

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 06/10] devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family

[Gregory CLEMENT]

Hi Rob,
 
 On mar., févr. 02 2016, Rob Herring <r...@kernel.org> wrote:

> On Tue, Feb 02, 2016 at 07:07:44PM +0100, Gregory CLEMENT wrote:
>> The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit
>> introduces the Device Tree binding that documents the top-level
>> compatible strings for Armada 3700 based platforms.
>> 
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>>  .../devicetree/bindings/arm/marvell/armada-37xx.txt | 17 
>> +
>>  1 file changed, 17 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
>> 
>> diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt 
>> b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
>> new file mode 100644
>> index ..5db9f1a90da2
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
>> @@ -0,0 +1,17 @@
>> +Marvell Armada 37xx Platforms Device Tree Bindings
>> +--
>> +
>> +Boards using a SoC of the Marvell Armada 37xx family must carry the
>> +following root node property:
>> +
>> + - compatible: must contain "marvell,armada3700"
>
> Is 3700 an actual chip? If not, please drop this.

As for I know, it is not an actual chip, so I will remove it.

Thanks,

Gregory

>
>> +
>> +In addition, depending on whether the Armada 3710 or Armada 3720 SoCs
>> +are being used, the following root node property must be added:
>> +
>> + - compatible: must contain either "marvell,armada3710" or
>> +   "marvell,armada3720"
>> +
>> +Example:
>> +
>> +compatible = "marvell,armada-3720-db", "marvell,armada3720", 
>> "marvell,armada3700";
>> -- 
>> 2.5.0
>> 
>> --
>> To unsubscribe from this list: send the line "unsubscribe devicetree" in
>> the body of a message to majord...@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 03/10] arm64: add Armada 3700 architecture entry

[Gregory CLEMENT]

Hi Arnd,
 
 On mer., févr. 03 2016, Arnd Bergmann <a...@arndb.de> wrote:

> On Wednesday 03 February 2016 08:55:22 Gregory CLEMENT wrote:
>> >> 
>> >> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> >> index 21074f674bde..7da341f7b90d 100644
>> >> --- a/arch/arm64/Kconfig.platforms
>> >> +++ b/arch/arm64/Kconfig.platforms
>> >> @@ -1,5 +1,11 @@
>> >>  menu "Platform selection"
>> >>  
>> >> +config ARCH_ARMADA_3700
>> >
>> > Would it be better to use ARCH_MVEBU? IMHO, there will be more ARMv8 SoCs
>> > from our EBU, do we plan to add one CONFIG_ARMADA_yyzz for each SoC?
>> 
>> Not for each SoC but for each family, yes. As we did for the other mvebu
>> SoC families.
>> 
>
> We tend to use a little more general config strings for arm64 than we have
> for arm32. I think just using ARCH_MVEBU is fine here, no need to list
> the 3700 series separately.

OK, for the arm32 mvebu SoC, the CONFIG_ARMADA_ were barely used, and
CONFIG_ARCH_MVEBU is mostly use as a "depends on" and do not force
anything.

The only annoying point was with the irqchip, but thanks to the last
series sent by Thomas irq-armada-370-xp.c won't be inconditionnaly built
if CONFIG_ARCH_MVEBU is selected.

So OK I will use CONFIG_ARCH_MVEBU.

Thanks,

Gregory



>   Arnd

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 01/10] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

Hi Marcin,
 
 On mer., févr. 03 2016, Marcin Wojtas <m...@semihalf.com> wrote:

> Hi Gregory
>
>> +
>> +static int mvebu_uart_startup(struct uart_port *port)
>> +{
>> +   int ret;
>> +
>> +   writel(CTRL_TXFIFO_RST | CTRL_RXFIFO_RST,
>> +  port->membase + UART_CTRL);
>> +   udelay(1);
>> +   writel(CTRL_RX_INT, port->membase + UART_CTRL);
>> +
>> +   ret = request_irq(port->irq, mvebu_uart_isr, port->irqflags, 
>> "serial",
>> + port);
>> +   if (ret) {
>> +   dev_err(port->dev, "failed to request irq\n");
>> +   return ret;
>> +   }
>> +
>> +   return 0;
>> +}
>> +
>
>> +static int mvebu_uart_probe(struct platform_device *pdev)
>> +{
>> +   struct resource *reg = platform_get_resource(pdev, IORESOURCE_MEM, 
>> 0);
>> +   struct resource *irq = platform_get_resource(pdev, IORESOURCE_IRQ, 
>> 0);
>> +   struct uart_port *port;
>> +   struct mvebu_uart_data *data;
>> +   int ret;
>> +
>> +   if (!reg || !irq) {
>> +   dev_err(>dev, "no registers/irq defined\n");
>> +   return -EINVAL;
>> +   }
>> +
>> +   port = _uart_ports[0];
>> +
>> +   spin_lock_init(>lock);
>> +
>> +   port->dev= >dev;
>> +   port->type   = PORT_MVEBU;
>> +   port->ops= _uart_ops;
>> +   port->regshift   = 0;
>> +
>> +   port->fifosize   = 32;
>> +   port->iotype = UPIO_MEM32;
>> +   port->flags  = UPF_FIXED_PORT;
>> +   port->line   = 0; /* single port: force line number to  0 */
>> +
>> +   port->irq= irq->start;
>> +   port->irqflags   = 0;
>
> Please use port->irqflags = IRQF_SHARED;
> As ubuntu opens multiple consoles A3700 can't boot to it (only to
> buildroot with single console).

But this irq is not shared, this looks like a hack hidding the real
issue.

Gregory

>
> Best regards,
> Marcin

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 01/10] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

Hi,
 
 On mar., févr. 02 2016, One Thousand Gnomes <gno...@lxorguk.ukuu.org.uk> wrote:

>> +static void mvebu_uart_set_termios(struct uart_port *port,
>> +   struct ktermios *termios,
>> +   struct ktermios *old)
>> +{
>> +unsigned long flags;
>> +unsigned int baud;
>> +
>> +spin_lock_irqsave(>lock, flags);
>> +
>> +port->read_status_mask = STAT_RX_RDY | STAT_OVR_ERR |
>> +STAT_TX_RDY | STAT_TX_FIFO_FUL;
>> +
>> +if (termios->c_iflag & INPCK)
>> +port->read_status_mask |= STAT_FRM_ERR | STAT_PAR_ERR;
>> +
>> +port->ignore_status_mask = 0;
>> +if (termios->c_iflag & IGNPAR)
>> +port->ignore_status_mask |=
>> +STAT_FRM_ERR | STAT_PAR_ERR | STAT_OVR_ERR;
>> +
>> +if ((termios->c_cflag & CREAD) == 0)
>> +port->ignore_status_mask |= STAT_RX_RDY | STAT_BRK_ERR;
>
> If you don't support parity or charactive size then you should be forcing
> those bits in the tty->termios so that the caller sees what settings they
> get. tty_termios_copy_hw is close to what you need except that you can
> support IGNPAR.

OK thanks for the pointer.

>
> You also want to provide the actual baud rate chosen (see how 8250.c does
> it using tty_termios_encode_baud_rate().
>
>
>> +static struct uart_driver mvebu_uart_driver = {
>> +.owner  = THIS_MODULE,
>> +.driver_name= "serial",
>> +.dev_name   = "ttyS",
>> +.major  = TTY_MAJOR,
>> +.minor  = 64,
>
> NAK
>
> TTY_MAJOR 64+ is the 8250 driver and ttyS is the 8250 driver name. You
> should be using a dynamic major (0) for all new drivers and you need to
> pick a different and unused ttyXXX format name.

I missed this one, I will remove .major and .minor and use our own
ttyXX.

Thanks,

Gregory

>
> Alan

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 01/10] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

Hi Mark,
 
 On mar., févr. 02 2016, Mark Rutland <mark.rutl...@arm.com> wrote:

> On Tue, Feb 02, 2016 at 07:07:39PM +0100, Gregory CLEMENT wrote:
>> From: Wilson Ding <ding...@marvell.com>
>> 
>> Armada-3700's uart is a simple serial port, which doesn't
>> support. Configuring the modem control lines. The uart port has a 32
>> bytes Tx FIFO and a 64 bytes Rx FIFO
>> 
>> The uart driver implements the uart core operations. It also support the
>> system (early) console based on Armada-3700's serial port.
>> 
>> Known Issue:
>> 
>> The uart driver currently doesn't support clock programming, which means
>> the baud-rate stays with the default value configured by the bootloader
>> at boot time
>
> To ensure that the bootloader and kernel match, it's best to place the
> rate in the stdout-path property (as in
> Documentation/devicetree/bindings/chosen.txt).
>
> Presumably that is what you want?

It is done in patch 7.

>
> Is it difficutl to add clock programming?

Currently there is no clock tree support before adding it I would like
to be able to test it.

Thanks,

Gregory

>
>> 
>> [gregory.clem...@free-electrons.com: Rewrite many part which are too long
>> to enumerate]
>> 
>> Signed-off-by: Wilson Ding <ding...@marvell.com>
>> Signed-off-by: Nadav Haklai <nad...@marvell.com>
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>>  .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
>>  Documentation/kernel-parameters.txt|   6 +
>>  drivers/tty/serial/Kconfig |  22 +
>>  drivers/tty/serial/Makefile|   1 +
>>  drivers/tty/serial/mvebu-uart.c| 649 
>> +
>>  include/uapi/linux/serial_core.h   |   3 +
>>  6 files changed, 694 insertions(+)
>>  create mode 100644 
>> Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
>>  create mode 100644 drivers/tty/serial/mvebu-uart.c
>> 
>> diff --git a/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt 
>> b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
>> new file mode 100644
>> index ..6087defd9f93
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
>> @@ -0,0 +1,13 @@
>> +* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., 
>> Armada-3700)
>> +
>> +Required properties:
>> +- compatible: "marvell,armada-3700-uart"
>> +- reg: offset and length of the register set for the device.
>> +- interrupts: device interrupt
>> +
>> +Example:
>> +serial@12000 {
>> +compatible = "marvell,armada-3700-uart";
>> +reg = <0x12000 0x400>;
>> +interrupts = <43>;
>> +};
>
> There are no external clock inputs?
>
>> diff --git a/Documentation/kernel-parameters.txt 
>> b/Documentation/kernel-parameters.txt
>> index 87d40a72f6a1..198f6bd56e84 100644
>> --- a/Documentation/kernel-parameters.txt
>> +++ b/Documentation/kernel-parameters.txt
>> @@ -1058,6 +1058,12 @@ bytes respectively. Such letter suffixes can also be 
>> entirely omitted.
>>  A valid base address must be provided, and the serial
>>      port must already be setup and configured.
>>  
>> +mvebu_uart,
>> +Start an early, polled-mode console on an some mvebu
>> +SoC (as the Armada-3700) serial port at the specified
>> +address. The serial port must already be setup and
>> +configured. Options are not yet supported.
>> +
>
> Does the the mvebu UART vary between platforms at all?
>
> Thanks,
> Mark.

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 01/10] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

Hi Mark,
 
 On mar., févr. 02 2016, Mark Rutland <mark.rutl...@arm.com> wrote:

>> diff --git a/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt 
>> b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
>> new file mode 100644
>> index ..6087defd9f93
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
>> @@ -0,0 +1,13 @@
>> +* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., 
>> Armada-3700)
>> +
>> +Required properties:
>> +- compatible: "marvell,armada-3700-uart"
>> +- reg: offset and length of the register set for the device.
>> +- interrupts: device interrupt
>> +
>> +Example:
>> +serial@12000 {
>> +compatible = "marvell,armada-3700-uart";
>> +reg = <0x12000 0x400>;
>> +interrupts = <43>;
>> +};
>
> There are no external clock inputs?

Right, even if we don't use it in the driver we should ad it in the
binding because there is an external clock input.

>
>> diff --git a/Documentation/kernel-parameters.txt 
>> b/Documentation/kernel-parameters.txt
>> index 87d40a72f6a1..198f6bd56e84 100644
>> --- a/Documentation/kernel-parameters.txt
>> +++ b/Documentation/kernel-parameters.txt
>> @@ -1058,6 +1058,12 @@ bytes respectively. Such letter suffixes can also be 
>> entirely omitted.
>>  A valid base address must be provided, and the serial
>>  port must already be setup and configured.
>>  
>> +mvebu_uart,
>> +Start an early, polled-mode console on an some mvebu
>> +SoC (as the Armada-3700) serial port at the specified
>> +address. The serial port must already be setup and
>> +configured. Options are not yet supported.
>> +
>
> Does the the mvebu UART vary between platforms at all?

I am not sure to undersatnd your question.

If you asked about the UART used on the other mvebu SoCs then my answer
is: on all the other mvebu SoC until now third party IPs were used. This
one is the first one dedicated to an mevbu SoC and currently only used
on Armada 3700 but I don't know what are the plan for the future mvebu
SoCs.

Gregory

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH net-next 09/10] net: Add a hardware buffer management helper API

[Gregory CLEMENT]

Hi Florian,

thanks for your review!
 
 On mer., janv. 27 2016, Florian Fainelli <f.faine...@gmail.com> wrote:

> On 12/01/16 11:10, Gregory CLEMENT wrote:
>> This basic implementation allows to share code between driver using
>> hardware buffer management. As the code is hardware agnostic, there is
>> few helpers, most of the optimization brought by the an HW BM has to be
>> done at driver level.
>> 
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>>  include/net/hwbm.h | 19 +
>>  net/core/Makefile  |  2 +-
>>  net/core/hwbm.c| 78 
>> ++
>>  3 files changed, 98 insertions(+), 1 deletion(-)
>>  create mode 100644 include/net/hwbm.h
>>  create mode 100644 net/core/hwbm.c
>> 
>> diff --git a/include/net/hwbm.h b/include/net/hwbm.h
>> new file mode 100644
>> index ..898ccd2fb58d
>> --- /dev/null
>> +++ b/include/net/hwbm.h
>> @@ -0,0 +1,19 @@
>> +#ifndef _HWBM_H
>> +#define _HWBM_H
>> +
>> +struct hwbm_pool {
>> +/* Size of the buffers managed */
>> +int size;
>> +/* Number of buffers currently used by this pool */
>> +int buf_num;
>> +/* constructor called during alocation */
>> +int (*construct)(struct hwbm_pool *bm_pool, void *buf);
>
> Having the buffer size might be handy too.
>
>> +/* private data */
>> +void *priv;
>> +};
>> +
>> +void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf);
>> +int hwbm_pool_refill(struct hwbm_pool *bm_pool);
>> +int hwbm_pool_add(struct hwbm_pool *bm_pool, int buf_num);
>> +
>> +#endif /* _HWBM_H */
>> diff --git a/net/core/Makefile b/net/core/Makefile
>> index 0b835de04de3..df81bf11f072 100644
>> --- a/net/core/Makefile
>> +++ b/net/core/Makefile
>> @@ -9,7 +9,7 @@ obj-$(CONFIG_SYSCTL) += sysctl_net_core.o
>>  
>>  obj-y+= dev.o ethtool.o dev_addr_lists.o dst.o 
>> netevent.o \
>>  neighbour.o rtnetlink.o utils.o link_watch.o filter.o \
>> -sock_diag.o dev_ioctl.o tso.o sock_reuseport.o
>> +sock_diag.o dev_ioctl.o tso.o sock_reuseport.o hwbm.o
>
> Not everybody will want this built in by default, we probably need a
> hidden config symbol here.

I copied what was done for TSO, but I agree to not build it by default.

>
>>  
>>  obj-$(CONFIG_XFRM) += flow.o
>>  obj-y += net-sysfs.o
>> diff --git a/net/core/hwbm.c b/net/core/hwbm.c
>> new file mode 100644
>> index ..d5d40d63cb34
>> --- /dev/null
>> +++ b/net/core/hwbm.c
>> @@ -0,0 +1,78 @@
>> +/* Support for hardware buffer manager.
>> + *
>> + * Copyright (C) 2016 Marvell
>> + *
>> + * Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> + *
>> + *  This program is free software; you can redistribute it and/or modify
>> + *  it under the terms of the GNU General Public License as published by
>> + *  the Free Software Foundation; either version 2 of the License, or
>> + *  (at your option) any later version.
>> + */
>> +#include 
>> +#include 
>> +#include 
>> +#include 
>> +
>> +void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf)
>> +{
>> +if (likely(bm_pool->size <= PAGE_SIZE))
>> +skb_free_frag(buf);
>> +else
>> +kfree(buf);
>> +}
>> +EXPORT_SYMBOL_GPL(hwbm_buf_free);
>> +
>> +/* Refill processing for HW buffer management */
>> +int hwbm_pool_refill(struct hwbm_pool *bm_pool)
>> +{
>> +void *buf;
>> +int frag_size = bm_pool->size;
>
> Reverse christmas tree declaration looks a bit nicer.

First time I heard about it :) I though it was something related to the
tree algorithms until I visualized it!

My logical here was first uninitialized variable then the initialized
ones. But I don't have a strong opinion about it so I can change it.

>
>> +
>> +if (likely(frag_size <= PAGE_SIZE))
>> +buf = netdev_alloc_frag(frag_size);
>> +else
>> +buf = kmalloc(frag_size, GFP_ATOMIC);
>
> Maybe we should allow the caller to specify a gfp_t, just in case
> GFP_ATOMIC is not good enough.

Good idea.

>
>> +
>> +if (!buf)
>> +return -ENOMEM;
>> +
>> +if (bm_pool->construct)
>> +if (bm_pool->construct(bm_pool, buf)) {
>> +hwbm_buf_free(bm_pool, buf);
>> +return -ENOM

Re: [PATCH 01/10] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

Hi Arnd,
 
 On mar., févr. 02 2016, Arnd Bergmann <a...@arndb.de> wrote:

> On Tuesday 02 February 2016 19:07:39 Gregory CLEMENT wrote:
>
>> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
>> index 39721ec4f415..b291f934d51b 100644
>> --- a/drivers/tty/serial/Kconfig
>> +++ b/drivers/tty/serial/Kconfig
>> @@ -1606,6 +1606,28 @@ config SERIAL_STM32_CONSOLE
>>  depends on SERIAL_STM32=y
>>  select SERIAL_CORE_CONSOLE
>>  
>> +config SERIAL_MVEBU_UART
>> +bool "Marvell EBU serial port support"
>
> Could this be a loadable module?

I don't see any reason to not being able to use it as a module. But I
didn't test it because currently te serial port is the only way ro
cimmunicate with the board.

>
>> +config SERIAL_MVEBU_CONSOLE
>> +bool "Console on Marvell EBU serial port"
>> +depends on SERIAL_MVEBU_UART
>
> If yes, this would become 
>
>   depends on SERIAL_MVEBU_UART=y

OK, let's try to enable it.

Thanks,

Gregory

>
>   Arnd
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 01/12] irqchip: armada-370-xp: add Kconfig option for the driver

[Gregory CLEMENT]

From: Thomas Petazzoni 

Instead of building the irq-armada-370-xp driver directly when
CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate
CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option.

This allows this option to select other interrupt-related Kconfig
options (which will be needed in follow-up commits) rather than having
such selects done from arch/arm/mach-/.

Signed-off-by: Thomas Petazzoni 
---
 drivers/irqchip/Kconfig  | 5 +
 drivers/irqchip/Makefile | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 715923d5236c..e2cab879d641 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -60,6 +60,11 @@ config ARM_VIC_NR
  The maximum number of VICs available in the system, for
  power management.
 
+config ARMADA_370_XP_IRQ
+   bool
+   default y if ARCH_MVEBU
+   select GENERIC_IRQ_CHIP
+
 config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 18caacb60d58..30dba044d0b8 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -5,7 +5,6 @@ obj-$(CONFIG_ARCH_BCM2835)  += irq-bcm2836.o
 obj-$(CONFIG_ARCH_EXYNOS)  += exynos-combiner.o
 obj-$(CONFIG_ARCH_HIP04)   += irq-hip04.o
 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
-obj-$(CONFIG_ARCH_MVEBU)   += irq-armada-370-xp.o
 obj-$(CONFIG_IRQ_MXS)  += irq-mxs.o
 obj-$(CONFIG_ARCH_TEGRA)   += irq-tegra.o
 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
@@ -28,6 +27,7 @@ obj-$(CONFIG_ARM_GIC_V3_ITS)  += irq-gic-v3-its.o 
irq-gic-v3-its-pci-msi.o irq-g
 obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
 obj-$(CONFIG_ARM_VIC)  += irq-vic.o
+obj-$(CONFIG_ARMADA_370_XP_IRQ)+= irq-armada-370-xp.o
 obj-$(CONFIG_ATMEL_AIC_IRQ)+= irq-atmel-aic-common.o 
irq-atmel-aic.o
 obj-$(CONFIG_ATMEL_AIC5_IRQ)   += irq-atmel-aic-common.o irq-atmel-aic5.o
 obj-$(CONFIG_I8259)+= irq-i8259.o
-- 
2.5.0

[PATCH v2 00/12] Add support for the Armada 3700 SoC an mvebu ARM64 based

[Gregory CLEMENT]

Hi,

This series introduce the support of the Armada 3700 family: it is the
first ARM64 SoC of the mvebu family submitted to the mainline!

Currently there are two members of the Armada 3700 family, the only
difference is the number of core: the Armada 3710 comes with one
Cortex-A53 whereas the Armada 3720 comes with 2 Cortex-A53. In this
series we enabled only the minimum to boot, pinctrl and clock tree
will come soon.

This is the second version of the series, see the changelog for the
detail. The bigger change was the addition of two itqchip patches to
be able to use the the ARCH_MVEBU for the Armada 3700 SoCs. The first
ones is only here to have standalone series but it comes from Thomas
Petazzoni's series:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/472625

Then on top of it I added a small patch allowing building the kernel
without this driver for ARM64. So now there is a dependency :/

Besides this the patches are pretty usual:

The third patch introduces a new serial driver for the uart used on
this SoC. The driver remains simple even if the hardware is capable of
doing more.

The forth one adapts the ahci driver to support the Armada 3700 SoC.
The forth patch updates the binding documentation with the new
compatible string.

The fifth patch adds a new entry Kconfig entry for this SoC family.

I took the opportunity of this series to tidy up the Marvell related
files in the binding documentation with the seventh patch.

The eighth patch introduces the compatible string for the SoCs of the
Armada 3700 family.

The ninth patch could be considered as the bulk of this series: it
adds the device tree files for the Armada 3700 SoCs and for the
reference board.

With the introduction of this new family the MAINTAINERS file, the
Marvell README and the ARM64 defconfig files have to be updated: it is
the purpose of the last 3 patches.

The patches 3 and 4 could be taken directly by the maintainer of their
respective subsystem as there is no dependency at all with the rest of
the series. I think that the rest of the series should go through the
arm-soc maintainer but in doubt I also added the ARM64 maintainer as
suggested by get_maintainer.pl. 

Thanks,

Gregory

Changelog:
v1 -> v2
- Added Rob acked-by on patches 3, 6 and 7
- Used armada3700_uart instead of mvebu_uart for the uart driver:
  suggested by Mark
- In mvebu-uart, do not use anymore TTY_MAJOR, or ttyS, but dynamic
  major and ttyMV: pointed by Alan
- Use tty_termios_copy_hw in mvebu_uart_set_termios: suggested by Alan
- Use ARCH_MVEBU instead of creating ARCH_ARMADA_3700: suggested by
  Jisheng
- Added a new irqchip pacthes to fix build on ARM64 when ARCH_MVEBU is
  selected
- Removed marvell,armada3700 from the device tree binding and directly
  used marvell,armada3710 for common feature: pointed by Rob
- Fix memory node with coorect size in armada-3720-db.dts: suggested
  by Mark

Gregory CLEMENT (9):
  irqchip: armada-370-xp: do not enable it by default when ARCH_MVEBU is
selected
  arm64: add mvebu architecture entry
  Documentation: dt-bindings: Add a new compatible for the Armada 3700
  Documentation: dt: Tidy up the Marvell related files
  devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC
family
  arm64: dts: add the Marvell Armada 3700 family and a development board
  MAINTAINERS: Extend dts entry for ARM64 mvebu files
  Documentation: arm: update supported Marvell EBU processors
  arm64: defconfig: enable Armada 3700 related config

Lior Amsalem (1):
  ata: ahci_mvebu: add support for Armada 3700 variant

Thomas Petazzoni (1):
  irqchip: armada-370-xp: add Kconfig option for the driver

Wilson Ding (1):
  serial: mvebu-uart: initial support for Armada-3700 serial port

 Documentation/arm/Marvell/README   |  13 +
 .../arm/{ => marvell}/armada-370-xp-pmsu.txt   |   0
 .../bindings/arm/{ => marvell}/armada-370-xp.txt   |   0
 .../bindings/arm/{ => marvell}/armada-375.txt  |   0
 .../bindings/arm/marvell/armada-37xx.txt   |  16 +
 .../{ => marvell}/armada-380-mpcore-soc-ctrl.txt   |   0
 .../bindings/arm/{ => marvell}/armada-38x.txt  |   0
 .../bindings/arm/{ => marvell}/armada-39x.txt  |   0
 .../arm/{ => marvell}/armada-cpu-reset.txt |   0
 .../arm/{ => marvell}/coherency-fabric.txt |   0
 .../bindings/arm/{ => marvell}/kirkwood.txt|   0
 .../bindings/arm/{ => marvell}/marvell,berlin.txt  |   0
 .../bindings/arm/{ => marvell}/marvell,dove.txt|   0
 .../arm/{ => marvell}/marvell,kirkwood.txt |   0
 .../arm/{ => marvell}/mvebu-cpu-config.txt |   0
 .../arm/{ => marvell}/mvebu-system-controller.txt  |   0
 .../devicetree/bindings/ata/ahci-platform.txt  |   1 +
 .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
 Documentation/kernel-parameters.txt|   6 +
 MAINTAINERS|   1 +
 arch/arm64/Kconfig.platforms  

[PATCH v2 06/12] Documentation: dt-bindings: Add a new compatible for the Armada 3700

[Gregory CLEMENT]

The AHCI interfaces used in the Armada 3700 has a few differences with
the one used in the Armada 38x, so it deserves its own compatible string.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt 
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c2340eeeb97f..796e2c23e5df 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -13,6 +13,7 @@ Required properties:
   - "hisilicon,hisi-ahci"
   - "ibm,476gtr-ahci"
   - "marvell,armada-380-ahci"
+  - "marvell,armada-3700-ahci"
   - "snps,dwc-ahci"
   - "snps,exynos5440-ahci"
   - "snps,spear-ahci"
-- 
2.5.0

[PATCH v2 02/12] irqchip: armada-370-xp: do not enable it by default when ARCH_MVEBU is selected

[Gregory CLEMENT]

The irq-armada-370-xp driver can only be built for ARM 32 bits. The mvebu
family had grown with a new ARM64 SoC which will also select the
ARCH_MEVBU configuration. Since "ARM: mvebu: use the ARMADA_370_XP_IRQ
option", the ARM32 mvebu SoC directly select this new option. Selecting
it by default when ARCH_MEVBU is selected is no more needed.

This patch removes this dependency, thanks to this, a kernel for ARM64
mvebu SoC can be built without error due this driver.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/irqchip/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e2cab879d641..b6e7e86a57e1 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -62,7 +62,6 @@ config ARM_VIC_NR
 
 config ARMADA_370_XP_IRQ
bool
-   default y if ARCH_MVEBU
select GENERIC_IRQ_CHIP
 
 config ATMEL_AIC_IRQ
-- 
2.5.0

[PATCH v2 03/12] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

From: Wilson Ding <ding...@marvell.com>

Armada-3700's uart is a simple serial port, which doesn't
support. Configuring the modem control lines. The uart port has a 32
bytes Tx FIFO and a 64 bytes Rx FIFO

The uart driver implements the uart core operations. It also support the
system (early) console based on Armada-3700's serial port.

Known Issue:

The uart driver currently doesn't support clock programming, which means
the baud-rate stays with the default value configured by the bootloader
at boot time

[gregory.clem...@free-electrons.com: Rewrite many part which are too long
to enumerate]

Signed-off-by: Wilson Ding <ding...@marvell.com>
Signed-off-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
 Documentation/kernel-parameters.txt|   6 +
 drivers/tty/serial/Kconfig |  22 +
 drivers/tty/serial/Makefile|   1 +
 drivers/tty/serial/mvebu-uart.c| 650 +
 include/uapi/linux/serial_core.h   |   3 +
 6 files changed, 695 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
 create mode 100644 drivers/tty/serial/mvebu-uart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt 
b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
new file mode 100644
index ..6087defd9f93
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
@@ -0,0 +1,13 @@
+* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., 
Armada-3700)
+
+Required properties:
+- compatible: "marvell,armada-3700-uart"
+- reg: offset and length of the register set for the device.
+- interrupts: device interrupt
+
+Example:
+   serial@12000 {
+   compatible = "marvell,armada-3700-uart";
+   reg = <0x12000 0x400>;
+   interrupts = <43>;
+   };
diff --git a/Documentation/kernel-parameters.txt 
b/Documentation/kernel-parameters.txt
index 87d40a72f6a1..ea0aba48d616 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1058,6 +1058,12 @@ bytes respectively. Such letter suffixes can also be 
entirely omitted.
A valid base address must be provided, and the serial
port must already be setup and configured.
 
+   armada3700_uart,
+   Start an early, polled-mode console on the
+   Armada 3700 serial port at the specified
+   address. The serial port must already be setup
+   and configured. Options are not yet supported.
+
earlyprintk=[X86,SH,BLACKFIN,ARM,M68k]
earlyprintk=vga
earlyprintk=efi
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 39721ec4f415..b291f934d51b 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1606,6 +1606,28 @@ config SERIAL_STM32_CONSOLE
depends on SERIAL_STM32=y
select SERIAL_CORE_CONSOLE
 
+config SERIAL_MVEBU_UART
+   bool "Marvell EBU serial port support"
+   select SERIAL_CORE
+   help
+ This driver is for Marvell EBU SoC's UART. If you have a machine
+ based on the Armada-3700 SoC and wish to use the on-board serial
+ port,
+ say 'Y' here.
+ Otherwise, say 'N'.
+
+config SERIAL_MVEBU_CONSOLE
+   bool "Console on Marvell EBU serial port"
+   depends on SERIAL_MVEBU_UART
+   select SERIAL_CORE_CONSOLE
+   select SERIAL_EARLYCON
+   default y
+   help
+ Say 'Y' here if you wish to use Armada-3700 UART as the system 
console.
+ (the system console is the device which receives all kernel messages
+ and warnings and which allows logins in single user mode)
+ Otherwise, say 'N'.
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index b391c9b31960..988167595330 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR)   += 
digicolor-usart.o
 obj-$(CONFIG_SERIAL_MEN_Z135)  += men_z135_uart.o
 obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
 obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
+obj-$(CONFIG_SERIAL_MVEBU_UART)+= mvebu-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
new file mode 100644
index ..f8e3ba21a7b7
--- /dev/null
+++ b/drivers/tty/serial/mvebu-uart.c
@@ -0,0 +1,650 @@
+/*
+* ***

[PATCH v2 07/12] Documentation: dt: Tidy up the Marvell related files

[Gregory CLEMENT]

Over the last releases we have added more and more Marvell related binding
directly in the arm directory. It's time to have our proper directory
inside it, and move all the files in it.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/arm/{ => marvell}/armada-370-xp-pmsu.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt| 0
 .../devicetree/bindings/arm/{ => marvell}/armada-380-mpcore-soc-ctrl.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-cpu-reset.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/coherency-fabric.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/mvebu-cpu-config.txt  | 0
 .../devicetree/bindings/arm/{ => marvell}/mvebu-system-controller.txt | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-370-xp-pmsu.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-380-mpcore-soc-ctrl.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-cpu-reset.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/coherency-fabric.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/marvell,kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-cpu-config.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-system-controller.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-375.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-375.txt
diff --git 
a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
rename to 
Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-38x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-39x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-cpu-reset.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-

[PATCH v2 04/12] ata: ahci_mvebu: add support for Armada 3700 variant

[Gregory CLEMENT]

From: Lior Amsalem <al...@marvell.com>

The main difference in the new Armada 3700 is that no address
decoding needs to take place in the driver probe.

[gregory.clem...@free-electrons.com: reformulate the commit log]

Signed-off-by: Lior Amsalem <al...@marvell.com>
Reviewed-by: Nadav Haklai <nad...@marvell.com>
Tested-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/ata/ahci_mvebu.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index f7a7fa81740e..de7128d81e9c 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -112,12 +112,15 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
if (rc)
return rc;
 
-   dram = mv_mbus_dram_info();
-   if (!dram)
-   return -ENODEV;
+   if (of_device_is_compatible(pdev->dev.of_node,
+   "marvell,armada-380-ahci")) {
+   dram = mv_mbus_dram_info();
+   if (!dram)
+   return -ENODEV;
 
-   ahci_mvebu_mbus_config(hpriv, dram);
-   ahci_mvebu_regret_option(hpriv);
+   ahci_mvebu_mbus_config(hpriv, dram);
+   ahci_mvebu_regret_option(hpriv);
+   }
 
rc = ahci_platform_init_host(pdev, hpriv, _mvebu_port_info,
 _platform_sht);
@@ -133,6 +136,7 @@ disable_resources:
 
 static const struct of_device_id ahci_mvebu_of_match[] = {
{ .compatible = "marvell,armada-380-ahci", },
+   { .compatible = "marvell,armada-3700-ahci", },
{ },
 };
 MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
-- 
2.5.0

[PATCH v2 12/12] arm64: defconfig: enable Armada 3700 related config

[Gregory CLEMENT]

This patch enables the configuration for the Armada 3700 family and for
the related driver it uses.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/configs/defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 18ca9fb9e65f..7ca2f0247ec5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_BCM_IPROC=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_EXYNOS7=y
@@ -93,6 +94,7 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
 CONFIG_AHCI_XGENE=y
 CONFIG_SATA_RCAR=y
 CONFIG_PATA_PLATFORM=y
@@ -132,6 +134,7 @@ CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
 CONFIG_VIRTIO_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
@@ -162,6 +165,8 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_RCAR=y
 CONFIG_SND_SOC_AK4613=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.5.0

[PATCH v2 10/12] MAINTAINERS: Extend dts entry for ARM64 mvebu files

[Gregory CLEMENT]

Extend the mvebu entry to ARM64 device tree sources.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 30aca4aa5467..ad49b62c5abc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1279,6 +1279,7 @@ F:arch/arm/mach-mvebu/
 F: drivers/rtc/rtc-armada38x.c
 F: arch/arm/boot/dts/armada*
 F: arch/arm/boot/dts/kirkwood*
+F: arch/arm64/boot/dts/marvell/armada*
 
 
 ARM/Marvell Berlin SoC support
-- 
2.5.0

[PATCH v2 11/12] Documentation: arm: update supported Marvell EBU processors

[Gregory CLEMENT]

Now that we support Armada 37xx, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details about
those processors. As for Armda 39x, no datasheet is publicly
available at this time.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 Documentation/arm/Marvell/README | 13 +
 1 file changed, 13 insertions(+)

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index ae89b67d8e23..ddbc048bb467 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -118,6 +118,19 @@ EBU Armada family
   Linux kernel mach directory: arch/arm/mach-mvebu
   Linux kernel plat directory: none
 
+EBU Armada family ARMv8
+---
+
+  Armada 3710/3720 Flavors:
+   88F3710
+   88F3720
+
+  Core: ARM Cortex A53 (ARMv8)
+
+  Homepage : http://www.marvell.com/embedded-processors/armada-3700/
+
+  Device tree descritpion located in arch/arm64/boot/dts/marvell/armada-37*
+
 Avanta family
 -
 
-- 
2.5.0

[PATCH v2 09/12] arm64: dts: add the Marvell Armada 3700 family and a development board

[Gregory CLEMENT]

Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).

It also adds a dts file for the Marvell Armada 3720 DB board.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/Makefile   |   4 +
 arch/arm64/boot/dts/marvell/armada-371x.dtsi   |  53 ++
 arch/arm64/boot/dts/marvell/armada-3720-db.dts |  86 
 arch/arm64/boot/dts/marvell/armada-372x.dtsi   |  63 
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 131 +
 5 files changed, 337 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-371x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-db.dts
 create mode 100644 arch/arm64/boot/dts/marvell/armada-372x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-37xx.dtsi

diff --git a/arch/arm64/boot/dts/marvell/Makefile 
b/arch/arm64/boot/dts/marvell/Makefile
index 348f4db4f313..2114af8d312d 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -1,6 +1,10 @@
+# Berlin SoC Family
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
 
+# Mvebu SoC Family
+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
+
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
 clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi 
b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
new file mode 100644
index ..c9e5325b8ac3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Device Tree Include file for Marvell Armada 371x family of SoCs
+ * (also named 88F3710)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+   model = "Marvell Armada 3710 SoC";
+   compatible = "marvell,armada3710", "marvell,armada3700";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts 
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
new file mode 100644
index ..359050154511
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -0,0 +1,86 @@
+/*
+ * Device Tree file for Marvell Armada 3720 development board
+ * (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option)

[PATCH v2 05/12] arm64: add mvebu architecture entry

[Gregory CLEMENT]

The Armada 3700 is an mvebu ARM64 SoC using one or two Cortex-A53 cores
depending of the variant.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/Kconfig.platforms | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 21074f674bde..d6fee5cafcae 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -1,5 +1,11 @@
 menu "Platform selection"
 
+config ARCH_MVEBU
+   bool "Marvell EBU SoC Family"
+   help
+ This enables support for Marvell EBU familly such as the
+ Armada 3700 SoC Family.
+
 config ARCH_BCM_IPROC
bool "Broadcom iProc SoC Family"
help
-- 
2.5.0

[PATCH v2 08/12] devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family

[Gregory CLEMENT]

The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit
introduces the Device Tree binding that documents the top-level
compatible strings for Armada 3700 based platforms.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 .../devicetree/bindings/arm/marvell/armada-37xx.txt  | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
new file mode 100644
index ..17e90e8b5f76
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
@@ -0,0 +1,16 @@
+Marvell Armada 37xx Platforms Device Tree Bindings
+--
+
+Boards using a SoC of the Marvell Armada 37xx family must carry the
+following root node property:
+
+ - compatible: must contain "marvell,armada3710"
+
+In addition, boards using the Marvell Armada 3720 SoC shall have the
+following property before the previous one:
+
+ - compatible: must contain "marvell,armada3720"
+
+Example:
+
+compatible = "marvell,armada-3720-db", "marvell,armada3710", 
"marvell,armada3720";
-- 
2.5.0

[PATCH] usb: host: xhci-plat: fix NULL pointer in probe for device tree case

[Gregory CLEMENT]

During probe, in the device tree case, the data pointer associated to a
compatible is dereferenced. However, not all the compatibles are
associated to a private data pointer.

The generic-xhci and the xhci-platform don't need them, this patch adds a
test on the data pointer before accessing it, avoiding a kernel crash.

Fixes: 4efb2f694114 ("usb: host: xhci-plat: add struct xhci_plat_priv")
Cc: sta...@vger.kernel.org
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/usb/host/xhci-plat.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/usb/host/xhci-plat.c b/drivers/usb/host/xhci-plat.c
index 770b6b088797..d39d6bf1d090 100644
--- a/drivers/usb/host/xhci-plat.c
+++ b/drivers/usb/host/xhci-plat.c
@@ -184,7 +184,8 @@ static int xhci_plat_probe(struct platform_device *pdev)
struct xhci_plat_priv *priv = hcd_to_xhci_priv(hcd);
 
/* Just copy data for now */
-   *priv = *priv_match;
+   if (priv_match)
+   *priv = *priv_match;
}
 
if (xhci_plat_type_is(hcd, XHCI_PLAT_TYPE_MARVELL_ARMADA)) {
-- 
2.5.0

Re: [PATCH] ARM: mv78xx0: use "depends on" instead of "if" after prompt

[Gregory CLEMENT]

Hi Masahiro,
 
 On lun., janv. 25 2016, Masahiro Yamada <yamada.masah...@socionext.com> wrote:

> This platform recently moved to multi-platform, so missed the global
> fixup by commit e32465429490 ("ARM: use "depends on" for SoC configs
> instead of "if" after prompt").  Fix it now.
>
> Signed-off-by: Masahiro Yamada <yamada.masah...@socionext.com>

Applied on mvebu/cleanup

Thanks,

Gregory
> ---
>
>  arch/arm/mach-mv78xx0/Kconfig | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-mv78xx0/Kconfig b/arch/arm/mach-mv78xx0/Kconfig
> index a32575f..c32f855 100644
> --- a/arch/arm/mach-mv78xx0/Kconfig
> +++ b/arch/arm/mach-mv78xx0/Kconfig
> @@ -1,5 +1,6 @@
>  menuconfig ARCH_MV78XX0
> - bool "Marvell MV78xx0" if ARCH_MULTI_V5
> + bool "Marvell MV78xx0"
> + depends on ARCH_MULTI_V5
>   select ARCH_REQUIRE_GPIOLIB
>   select CPU_FEROCEON
>   select MVEBU_MBUS
> -- 
> 1.9.1
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v4 00/12] Add support for the Armada 3700 SoC an mvebu ARM64 based

[Gregory CLEMENT]

This series introduce the support of the Armada 3700 family: it is the
first ARM64 SoC of the mvebu family submitted to the mainline!

Currently there are two members of the Armada 3700 family, the only
difference is the number of core: the Armada 3710 comes with one
Cortex-A53 whereas the Armada 3720 comes with 2 Cortex-A53. In this
series we enabled only the minimum to boot, pinctrl and clock tree
will come soon.

The changes in this forth version are even smaller than the former one
(see the changelog).

The first two patches patches are here to be able to use the the
ARCH_MVEBU for the Armada 3700 SoCs. The first ones is only here to
have standalone series but it comes from Thomas Petazzoni's series:
http://thread.gmane.org/gmane.linux.ports.arm.kernel/472625

The third patch introduces a new serial driver for the uart used on
this SoC. The driver remains simple even if the hardware is capable of
doing more.

The forth one adapts the ahci driver to support the Armada 3700 SoC.
The forth patch updates the binding documentation with the new
compatible string.

The fifth patch adds a new entry Kconfig entry for this SoC family.

I took the opportunity of this series to tidy up the Marvell related
files in the binding documentation with the seventh patch.

The eighth patch introduces the compatible string for the SoCs of the
Armada 3700 family.

The ninth patch could be considered as the bulk of this series: it
adds the device tree files for the Armada 3700 SoCs and for the
reference board.

With the introduction of this new family the MAINTAINERS file, the
Marvell README and the ARM64 defconfig files have to be updated: it is
the purpose of the last 3 patches.

The patches 3 and 4 could be taken directly by the maintainer of their
respective subsystem as there is no dependency at all with the rest of
the series. I think that the rest of the series should go through the
arm-soc maintainer but in doubt I also added the ARM64 maintainer as
suggested by get_maintainer.pl.

Thanks,

Gregory

Changelog:
v3 -> v4
- Preserved alphabetical order in arch/arm64/Kconfig.platforms file,
  suggested by Jisheng
- Added Rob acked-by on patch 8
- Fix driver_name field in the uart_driver struct: use "mvebu_serial"
  instead of "serial"

v2 -> v3
- Renamed the remaining ttyS into ttyMV: reported by Greg KH
- Fixed the order of the compatible in the example of the binding
  documentation: pointed by Rob
- Fix a typo in Kconfig entry: pointed by Thomas Petazzoni

v1 -> v2
- Added Rob acked-by on patches 3, 6 and 7
- Used armada3700_uart instead of mvebu_uart for the uart driver:
  suggested by Mark
- In mvebu-uart, do not use anymore TTY_MAJOR, or ttyS, but dynamic
  major and ttyMV: pointed by Alan
- Use tty_termios_copy_hw in mvebu_uart_set_termios: suggested by Alan
- Use ARCH_MVEBU instead of creating ARCH_ARMADA_3700: suggested by
  Jisheng
- Added a new irqchip pacthes to fix build on ARM64 when ARCH_MVEBU is
  selected
- Removed marvell,armada3700 from the device tree binding and directly
  used marvell,armada3710 for common feature: pointed by Rob
- Fix memory node with coorect size in armada-3720-db.dts: suggested
  by Mark

Gregory CLEMENT (9):
  irqchip: armada-370-xp: do not enable it by default when ARCH_MVEBU is
selected
  arm64: add mvebu architecture entry
  Documentation: dt-bindings: Add a new compatible for the Armada 3700
  Documentation: dt: Tidy up the Marvell related files
  devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC
family
  arm64: dts: add the Marvell Armada 3700 family and a development board
  MAINTAINERS: Extend dts entry for ARM64 mvebu files
  Documentation: arm: update supported Marvell EBU processors
  arm64: defconfig: enable Armada 3700 related config

Lior Amsalem (1):
  ata: ahci_mvebu: add support for Armada 3700 variant

Thomas Petazzoni (1):
  irqchip: armada-370-xp: add Kconfig option for the driver

Wilson Ding (1):
  serial: mvebu-uart: initial support for Armada-3700 serial port

 Documentation/arm/Marvell/README   |  13 +
 .../arm/{ => marvell}/armada-370-xp-pmsu.txt   |   0
 .../bindings/arm/{ => marvell}/armada-370-xp.txt   |   0
 .../bindings/arm/{ => marvell}/armada-375.txt  |   0
 .../bindings/arm/marvell/armada-37xx.txt   |  16 +
 .../{ => marvell}/armada-380-mpcore-soc-ctrl.txt   |   0
 .../bindings/arm/{ => marvell}/armada-38x.txt  |   0
 .../bindings/arm/{ => marvell}/armada-39x.txt  |   0
 .../arm/{ => marvell}/armada-cpu-reset.txt |   0
 .../arm/{ => marvell}/coherency-fabric.txt |   0
 .../bindings/arm/{ => marvell}/kirkwood.txt|   0
 .../bindings/arm/{ => marvell}/marvell,berlin.txt  |   0
 .../bindings/arm/{ => marvell}/marvell,dove.txt|   0
 .../arm/{ => marvell}/marvell,kirkwood.txt |   0
 .../arm/{ => marvell}/mvebu-cpu-config.txt |   0
 .../arm/{ => marvell}/mvebu-syst

[PATCH v4 11/12] Documentation: arm: update supported Marvell EBU processors

[Gregory CLEMENT]

Now that we support Armada 37xx, let's add this family of SoC to the
Marvell documentation, and a reference to a link with more details about
those processors. As for Armda 39x, no datasheet is publicly
available at this time.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 Documentation/arm/Marvell/README | 13 +
 1 file changed, 13 insertions(+)

diff --git a/Documentation/arm/Marvell/README b/Documentation/arm/Marvell/README
index ae89b67d8e23..ddbc048bb467 100644
--- a/Documentation/arm/Marvell/README
+++ b/Documentation/arm/Marvell/README
@@ -118,6 +118,19 @@ EBU Armada family
   Linux kernel mach directory: arch/arm/mach-mvebu
   Linux kernel plat directory: none
 
+EBU Armada family ARMv8
+---
+
+  Armada 3710/3720 Flavors:
+   88F3710
+   88F3720
+
+  Core: ARM Cortex A53 (ARMv8)
+
+  Homepage : http://www.marvell.com/embedded-processors/armada-3700/
+
+  Device tree descritpion located in arch/arm64/boot/dts/marvell/armada-37*
+
 Avanta family
 -
 
-- 
2.5.0

[PATCH v4 07/12] Documentation: dt: Tidy up the Marvell related files

[Gregory CLEMENT]

Over the last releases we have added more and more Marvell related binding
directly in the arm directory. It's time to have our proper directory
inside it, and move all the files in it.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/arm/{ => marvell}/armada-370-xp-pmsu.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt| 0
 .../devicetree/bindings/arm/{ => marvell}/armada-380-mpcore-soc-ctrl.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/armada-cpu-reset.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/coherency-fabric.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt| 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/marvell,kirkwood.txt  | 0
 Documentation/devicetree/bindings/arm/{ => marvell}/mvebu-cpu-config.txt  | 0
 .../devicetree/bindings/arm/{ => marvell}/mvebu-system-controller.txt | 0
 14 files changed, 0 insertions(+), 0 deletions(-)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-370-xp-pmsu.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-370-xp.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-375.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-380-mpcore-soc-ctrl.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-38x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/armada-39x.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/armada-cpu-reset.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/coherency-fabric.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,berlin.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => marvell}/marvell,dove.txt 
(100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/marvell,kirkwood.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-cpu-config.txt (100%)
 rename Documentation/devicetree/bindings/arm/{ => 
marvell}/mvebu-system-controller.txt (100%)

diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp-pmsu.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp-pmsu.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-370-xp.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-370-xp.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-375.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-375.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-375.txt
diff --git 
a/Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-380-mpcore-soc-ctrl.txt
rename to 
Documentation/devicetree/bindings/arm/marvell/armada-380-mpcore-soc-ctrl.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-38x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-38x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-38x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-39x.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-39x.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-39x.txt
diff --git a/Documentation/devicetree/bindings/arm/armada-cpu-reset.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-cpu-reset.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/armada-cpu-reset.txt
rename to Documentation/devicetree/bindings/arm/marvell/armada-

[PATCH v4 09/12] arm64: dts: add the Marvell Armada 3700 family and a development board

[Gregory CLEMENT]

Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
CPUs. There are two members in this family: the Armada 3710 (Single CPU)
and the Armada 3720 (Dual CPUs).

It also adds a dts file for the Marvell Armada 3720 DB board.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm64/boot/dts/marvell/Makefile   |   4 +
 arch/arm64/boot/dts/marvell/armada-371x.dtsi   |  53 ++
 arch/arm64/boot/dts/marvell/armada-3720-db.dts |  86 
 arch/arm64/boot/dts/marvell/armada-372x.dtsi   |  63 
 arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 131 +
 5 files changed, 337 insertions(+)
 create mode 100644 arch/arm64/boot/dts/marvell/armada-371x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-db.dts
 create mode 100644 arch/arm64/boot/dts/marvell/armada-372x.dtsi
 create mode 100644 arch/arm64/boot/dts/marvell/armada-37xx.dtsi

diff --git a/arch/arm64/boot/dts/marvell/Makefile 
b/arch/arm64/boot/dts/marvell/Makefile
index 348f4db4f313..2114af8d312d 100644
--- a/arch/arm64/boot/dts/marvell/Makefile
+++ b/arch/arm64/boot/dts/marvell/Makefile
@@ -1,6 +1,10 @@
+# Berlin SoC Family
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
 dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
 
+# Mvebu SoC Family
+dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
+
 always := $(dtb-y)
 subdir-y   := $(dts-dirs)
 clean-files:= *.dtb
diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi 
b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
new file mode 100644
index ..c9e5325b8ac3
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
@@ -0,0 +1,53 @@
+/*
+ * Device Tree Include file for Marvell Armada 371x family of SoCs
+ * (also named 88F3710)
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "armada-37xx.dtsi"
+
+/ {
+   model = "Marvell Armada 3710 SoC";
+   compatible = "marvell,armada3710", "marvell,armada3700";
+};
diff --git a/arch/arm64/boot/dts/marvell/armada-3720-db.dts 
b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
new file mode 100644
index ..359050154511
--- /dev/null
+++ b/arch/arm64/boot/dts/marvell/armada-3720-db.dts
@@ -0,0 +1,86 @@
+/*
+ * Device Tree file for Marvell Armada 3720 development board
+ * (DB-88F3720-DDR3)
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option)

[PATCH v4 12/12] arm64: defconfig: enable Armada 3700 related config

[Gregory CLEMENT]

This patch enables the configuration for the Armada 3700 family and for
the related driver it uses.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/configs/defconfig | 5 +
 1 file changed, 5 insertions(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index 18ca9fb9e65f..7ca2f0247ec5 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -31,6 +31,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_MVEBU=y
 CONFIG_ARCH_BCM_IPROC=y
 CONFIG_ARCH_BERLIN=y
 CONFIG_ARCH_EXYNOS7=y
@@ -93,6 +94,7 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_AHCI_PLATFORM=y
 CONFIG_AHCI_CEVA=y
+CONFIG_AHCI_MVEBU=y
 CONFIG_AHCI_XGENE=y
 CONFIG_SATA_RCAR=y
 CONFIG_PATA_PLATFORM=y
@@ -132,6 +134,7 @@ CONFIG_SERIAL_MSM_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
 CONFIG_SERIAL_XILINX_PS_UART=y
 CONFIG_SERIAL_XILINX_PS_UART_CONSOLE=y
+CONFIG_SERIAL_MVEBU_UART=y
 CONFIG_VIRTIO_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
@@ -162,6 +165,8 @@ CONFIG_SND_SOC=y
 CONFIG_SND_SOC_RCAR=y
 CONFIG_SND_SOC_AK4613=y
 CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_PLATFORM=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_HCD_PLATFORM=y
 CONFIG_USB_OHCI_HCD=y
-- 
2.5.0

[PATCH v4 10/12] MAINTAINERS: Extend dts entry for ARM64 mvebu files

[Gregory CLEMENT]

Extend the mvebu entry to ARM64 device tree sources.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 MAINTAINERS | 1 +
 1 file changed, 1 insertion(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 30aca4aa5467..ad49b62c5abc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1279,6 +1279,7 @@ F:arch/arm/mach-mvebu/
 F: drivers/rtc/rtc-armada38x.c
 F: arch/arm/boot/dts/armada*
 F: arch/arm/boot/dts/kirkwood*
+F: arch/arm64/boot/dts/marvell/armada*
 
 
 ARM/Marvell Berlin SoC support
-- 
2.5.0

[PATCH v4 01/12] irqchip: armada-370-xp: add Kconfig option for the driver

[Gregory CLEMENT]

From: Thomas Petazzoni 

Instead of building the irq-armada-370-xp driver directly when
CONFIG_ARCH_MVEBU is enabled, this commit introduces an intermediate
CONFIG_ARMADA_370_XP_IRQ hidden Kconfig option.

This allows this option to select other interrupt-related Kconfig
options (which will be needed in follow-up commits) rather than having
such selects done from arch/arm/mach-/.

Signed-off-by: Thomas Petazzoni 
---
 drivers/irqchip/Kconfig  | 5 +
 drivers/irqchip/Makefile | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 715923d5236c..e2cab879d641 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -60,6 +60,11 @@ config ARM_VIC_NR
  The maximum number of VICs available in the system, for
  power management.
 
+config ARMADA_370_XP_IRQ
+   bool
+   default y if ARCH_MVEBU
+   select GENERIC_IRQ_CHIP
+
 config ATMEL_AIC_IRQ
bool
select GENERIC_IRQ_CHIP
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 18caacb60d58..30dba044d0b8 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -5,7 +5,6 @@ obj-$(CONFIG_ARCH_BCM2835)  += irq-bcm2836.o
 obj-$(CONFIG_ARCH_EXYNOS)  += exynos-combiner.o
 obj-$(CONFIG_ARCH_HIP04)   += irq-hip04.o
 obj-$(CONFIG_ARCH_MMP) += irq-mmp.o
-obj-$(CONFIG_ARCH_MVEBU)   += irq-armada-370-xp.o
 obj-$(CONFIG_IRQ_MXS)  += irq-mxs.o
 obj-$(CONFIG_ARCH_TEGRA)   += irq-tegra.o
 obj-$(CONFIG_ARCH_S3C24XX) += irq-s3c24xx.o
@@ -28,6 +27,7 @@ obj-$(CONFIG_ARM_GIC_V3_ITS)  += irq-gic-v3-its.o 
irq-gic-v3-its-pci-msi.o irq-g
 obj-$(CONFIG_HISILICON_IRQ_MBIGEN) += irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC) += irq-nvic.o
 obj-$(CONFIG_ARM_VIC)  += irq-vic.o
+obj-$(CONFIG_ARMADA_370_XP_IRQ)+= irq-armada-370-xp.o
 obj-$(CONFIG_ATMEL_AIC_IRQ)+= irq-atmel-aic-common.o 
irq-atmel-aic.o
 obj-$(CONFIG_ATMEL_AIC5_IRQ)   += irq-atmel-aic-common.o irq-atmel-aic5.o
 obj-$(CONFIG_I8259)+= irq-i8259.o
-- 
2.5.0

[PATCH v4 08/12] devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family

[Gregory CLEMENT]

The Marvell Armada 3700 is a family of ARMv8 CA53 SoCs. This commit
introduces the Device Tree binding that documents the top-level
compatible strings for Armada 3700 based platforms.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/arm/marvell/armada-37xx.txt  | 16 
 1 file changed, 16 insertions(+)
 create mode 100644 
Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt

diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt 
b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
new file mode 100644
index ..51336e5fc761
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.txt
@@ -0,0 +1,16 @@
+Marvell Armada 37xx Platforms Device Tree Bindings
+--
+
+Boards using a SoC of the Marvell Armada 37xx family must carry the
+following root node property:
+
+ - compatible: must contain "marvell,armada3710"
+
+In addition, boards using the Marvell Armada 3720 SoC shall have the
+following property before the previous one:
+
+ - compatible: must contain "marvell,armada3720"
+
+Example:
+
+compatible = "marvell,armada-3720-db", "marvell,armada3720", 
"marvell,armada3710";
-- 
2.5.0

[PATCH v4 05/12] arm64: add mvebu architecture entry

[Gregory CLEMENT]

The Armada 3700 is an mvebu ARM64 SoC using one or two Cortex-A53 cores
depending of the variant.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
---
 arch/arm64/Kconfig.platforms | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
index 21074f674bde..85bec422d508 100644
--- a/arch/arm64/Kconfig.platforms
+++ b/arch/arm64/Kconfig.platforms
@@ -48,6 +48,12 @@ config ARCH_MEDIATEK
help
  Support for Mediatek MT65xx & MT81xx ARMv8 SoCs
 
+config ARCH_MVEBU
+   bool "Marvell EBU SoC Family"
+   help
+ This enables support for Marvell EBU family such as the
+ Armada 3700 SoC family.
+
 config ARCH_QCOM
bool "Qualcomm Platforms"
select PINCTRL
-- 
2.5.0

[PATCH v4 06/12] Documentation: dt-bindings: Add a new compatible for the Armada 3700

[Gregory CLEMENT]

The AHCI interfaces used in the Armada 3700 has a few differences with
the one used in the Armada 38x, so it deserves its own compatible string.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 Documentation/devicetree/bindings/ata/ahci-platform.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ata/ahci-platform.txt 
b/Documentation/devicetree/bindings/ata/ahci-platform.txt
index c2340eeeb97f..796e2c23e5df 100644
--- a/Documentation/devicetree/bindings/ata/ahci-platform.txt
+++ b/Documentation/devicetree/bindings/ata/ahci-platform.txt
@@ -13,6 +13,7 @@ Required properties:
   - "hisilicon,hisi-ahci"
   - "ibm,476gtr-ahci"
   - "marvell,armada-380-ahci"
+  - "marvell,armada-3700-ahci"
   - "snps,dwc-ahci"
   - "snps,exynos5440-ahci"
   - "snps,spear-ahci"
-- 
2.5.0

[PATCH v4 04/12] ata: ahci_mvebu: add support for Armada 3700 variant

[Gregory CLEMENT]

From: Lior Amsalem <al...@marvell.com>

The main difference in the new Armada 3700 is that no address
decoding needs to take place in the driver probe.

[gregory.clem...@free-electrons.com: reformulate the commit log]

Signed-off-by: Lior Amsalem <al...@marvell.com>
Reviewed-by: Nadav Haklai <nad...@marvell.com>
Tested-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/ata/ahci_mvebu.c | 14 +-
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
index f7a7fa81740e..de7128d81e9c 100644
--- a/drivers/ata/ahci_mvebu.c
+++ b/drivers/ata/ahci_mvebu.c
@@ -112,12 +112,15 @@ static int ahci_mvebu_probe(struct platform_device *pdev)
if (rc)
return rc;
 
-   dram = mv_mbus_dram_info();
-   if (!dram)
-   return -ENODEV;
+   if (of_device_is_compatible(pdev->dev.of_node,
+   "marvell,armada-380-ahci")) {
+   dram = mv_mbus_dram_info();
+   if (!dram)
+   return -ENODEV;
 
-   ahci_mvebu_mbus_config(hpriv, dram);
-   ahci_mvebu_regret_option(hpriv);
+   ahci_mvebu_mbus_config(hpriv, dram);
+   ahci_mvebu_regret_option(hpriv);
+   }
 
rc = ahci_platform_init_host(pdev, hpriv, _mvebu_port_info,
 _platform_sht);
@@ -133,6 +136,7 @@ disable_resources:
 
 static const struct of_device_id ahci_mvebu_of_match[] = {
{ .compatible = "marvell,armada-380-ahci", },
+   { .compatible = "marvell,armada-3700-ahci", },
{ },
 };
 MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
-- 
2.5.0

[PATCH v4 03/12] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

From: Wilson Ding <ding...@marvell.com>

Armada-3700's uart is a simple serial port, which doesn't
support. Configuring the modem control lines. The uart port has a 32
bytes Tx FIFO and a 64 bytes Rx FIFO

The uart driver implements the uart core operations. It also support the
system (early) console based on Armada-3700's serial port.

Known Issue:

The uart driver currently doesn't support clock programming, which means
the baud-rate stays with the default value configured by the bootloader
at boot time

[gregory.clem...@free-electrons.com: Rewrite many part which are too long
to enumerate]

Signed-off-by: Wilson Ding <ding...@marvell.com>
Signed-off-by: Nadav Haklai <nad...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Acked-by: Rob Herring <r...@kernel.org>
---
 .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
 Documentation/kernel-parameters.txt|   6 +
 drivers/tty/serial/Kconfig |  22 +
 drivers/tty/serial/Makefile|   1 +
 drivers/tty/serial/mvebu-uart.c| 650 +
 include/uapi/linux/serial_core.h   |   3 +
 6 files changed, 695 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
 create mode 100644 drivers/tty/serial/mvebu-uart.c

diff --git a/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt 
b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
new file mode 100644
index ..6087defd9f93
--- /dev/null
+++ b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
@@ -0,0 +1,13 @@
+* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., 
Armada-3700)
+
+Required properties:
+- compatible: "marvell,armada-3700-uart"
+- reg: offset and length of the register set for the device.
+- interrupts: device interrupt
+
+Example:
+   serial@12000 {
+   compatible = "marvell,armada-3700-uart";
+   reg = <0x12000 0x400>;
+   interrupts = <43>;
+   };
diff --git a/Documentation/kernel-parameters.txt 
b/Documentation/kernel-parameters.txt
index 87d40a72f6a1..ea0aba48d616 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1058,6 +1058,12 @@ bytes respectively. Such letter suffixes can also be 
entirely omitted.
A valid base address must be provided, and the serial
port must already be setup and configured.
 
+   armada3700_uart,
+   Start an early, polled-mode console on the
+   Armada 3700 serial port at the specified
+   address. The serial port must already be setup
+   and configured. Options are not yet supported.
+
earlyprintk=[X86,SH,BLACKFIN,ARM,M68k]
earlyprintk=vga
earlyprintk=efi
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index 39721ec4f415..b291f934d51b 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -1606,6 +1606,28 @@ config SERIAL_STM32_CONSOLE
depends on SERIAL_STM32=y
select SERIAL_CORE_CONSOLE
 
+config SERIAL_MVEBU_UART
+   bool "Marvell EBU serial port support"
+   select SERIAL_CORE
+   help
+ This driver is for Marvell EBU SoC's UART. If you have a machine
+ based on the Armada-3700 SoC and wish to use the on-board serial
+ port,
+ say 'Y' here.
+ Otherwise, say 'N'.
+
+config SERIAL_MVEBU_CONSOLE
+   bool "Console on Marvell EBU serial port"
+   depends on SERIAL_MVEBU_UART
+   select SERIAL_CORE_CONSOLE
+   select SERIAL_EARLYCON
+   default y
+   help
+ Say 'Y' here if you wish to use Armada-3700 UART as the system 
console.
+ (the system console is the device which receives all kernel messages
+ and warnings and which allows logins in single user mode)
+ Otherwise, say 'N'.
+
 endmenu
 
 config SERIAL_MCTRL_GPIO
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index b391c9b31960..988167595330 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -91,6 +91,7 @@ obj-$(CONFIG_SERIAL_CONEXANT_DIGICOLOR)   += 
digicolor-usart.o
 obj-$(CONFIG_SERIAL_MEN_Z135)  += men_z135_uart.o
 obj-$(CONFIG_SERIAL_SPRD) += sprd_serial.o
 obj-$(CONFIG_SERIAL_STM32) += stm32-usart.o
+obj-$(CONFIG_SERIAL_MVEBU_UART)+= mvebu-uart.o
 
 # GPIOLIB helpers for modem control lines
 obj-$(CONFIG_SERIAL_MCTRL_GPIO)+= serial_mctrl_gpio.o
diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
new file mode 100644
index ..0ff27818bb87
--- /dev/null
+++ b/drivers/tty/serial/mvebu-uart.c
@@ -0,0 +1,650 @@
+/*
+* ***

[PATCH v4 02/12] irqchip: armada-370-xp: do not enable it by default when ARCH_MVEBU is selected

[Gregory CLEMENT]

The irq-armada-370-xp driver can only be built for ARM 32 bits. The mvebu
family had grown with a new ARM64 SoC which will also select the
ARCH_MEVBU configuration. Since "ARM: mvebu: use the ARMADA_370_XP_IRQ
option", the ARM32 mvebu SoC directly select this new option. Selecting
it by default when ARCH_MEVBU is selected is no more needed.

This patch removes this dependency, thanks to this, a kernel for ARM64
mvebu SoC can be built without error due this driver.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/irqchip/Kconfig | 1 -
 1 file changed, 1 deletion(-)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e2cab879d641..b6e7e86a57e1 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -62,7 +62,6 @@ config ARM_VIC_NR
 
 config ARMADA_370_XP_IRQ
bool
-   default y if ARCH_MVEBU
select GENERIC_IRQ_CHIP
 
 config ATMEL_AIC_IRQ
-- 
2.5.0

Re: [PATCH v4 00/12] Add support for the Armada 3700 SoC an mvebu ARM64 based

[Gregory CLEMENT]

Hi Arnd,
 
 On mar., févr. 16 2016, Arnd Bergmann <a...@arndb.de> wrote:

> On Tuesday 16 February 2016 19:14:50 Gregory CLEMENT wrote:
>> This series introduce the support of the Armada 3700 family: it is the
>> first ARM64 SoC of the mvebu family submitted to the mainline!
>> 
>> Currently there are two members of the Armada 3700 family, the only
>> difference is the number of core: the Armada 3710 comes with one
>> Cortex-A53 whereas the Armada 3720 comes with 2 Cortex-A53. In this
>> series we enabled only the minimum to boot, pinctrl and clock tree
>> will come soon.
>> 
>
> Whole series
>
> Acked-by: Arnd Bergmann <a...@arndb.de>

Great!

I am going to do a first pull requests for the mvebu arm64. Let me know
if I do it correctly.

Thanks,

Gregory

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH] PCI: mvebu: Restrict build to 32-bit ARM

[Gregory CLEMENT]

Hi Arnd,
 
 On jeu., févr. 18 2016, Arnd Bergmann <a...@arndb.de> wrote:

> On Thursday 18 February 2016 14:32:10 Thierry Reding wrote:
>> From: Thierry Reding <tred...@nvidia.com>
>> 
>> This driver uses PCI glue that is only available on 32-bit ARM. This
>> used to work fine as long as ARCH_MVEBU and ARCH_DOVE were exclusively
>> 32-bit, but that's changed now, with ARCH_MVEBU also being available
>> on 64-bit ARM.
>> 
>> Signed-off-by: Thierry Reding <tred...@nvidia.com>
>
> Looks fine as a temporary workaround, but I think what we really want to
> do here is to remove the dependency, as the new ARM64 platforms are going
> to need this driver anyway.

Actually the mvebu ARM64 platform we know about (Armada 3700, 7K and
8K), won't use the same controller. A7K/A8K will use a synopsis IP and
Armada 3700 a new Marvell IP.

So for me depending on ARM32 is enough.

Gregory

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v2 net-next 0/8] API set for HW Buffer management

[Gregory CLEMENT]

Hi Willy,
 
 On mer., févr. 17 2016, Willy Tarreau <w...@1wt.eu> wrote:

> Hi Gregory,
>
> On Tue, Feb 16, 2016 at 04:33:35PM +0100, Gregory CLEMENT wrote:
>> Hello,
>> 
>> A few weeks ago I sent a proposal for a API set for HW Buffer
>> management, to have a better view of the motivation for this API see
>> the cover letter of this proposal:
>> http://thread.gmane.org/gmane.linux.kernel/2125152
>> 
>> Since this version I took into account the review from Florian:
>> - The hardware buffer management helpers are no more built by default
>>   and now depend on a hidden config symbol which has to be selected
>>   by the driver if needed
>> - The hwbm_pool_refill() and hwbm_pool_add() now receive a gfp_t as
>>   argument allowing the caller to specify the flag it needs.
>> - buf_num is now tested to ensure there is no wrapping
>> - A spinlock has been added to protect the hwbm_pool_add() function in
>>   SMP or irq context.
>> 
>> I also used pr_warn instead of pr_debug in case of errors.
>> 
>> I fixed the mvneta implementation by returning the buffer to the pool
>> at various place instead of ignoring it.
>> 
>> About the series itself I tried to make this series easier to merge:
>> - Squashed "bus: mvenus-mbus: Fix size test for
>>mvebu_mbus_get_dram_win_info" into bus: mvebu-mbus: provide api for
>>obtaining IO and DRAM window information.
>> - Added my signed-otf-by on all the patches as submitter of the series.
>> - Renamed the dts patches with the pattern "ARM: dts: platform:"
>> - Removed the patch "ARM: mvebu: enable SRAM support in
>>   mvebu_v7_defconfig" of this series and already applied it
>> - Rodified the order of the patches.
>> 
>> In order to ease the test the branch mvneta-BM-framework-v2 is
>> available at g...@github.com:MISL-EBU-System-SW/mainline-public.git.
>
> Well, I tested this patch series on top of latest master (from today)
> on my fresh new clearfog board. I compared carefully with and without
> the patchset. My workload was haproxy receiving connections and forwarding
> them to my PC via the same port. I tested both with short connections
> (HTTP GET of an empty file) and long ones (1 MB or more). No trouble
> was detected at all, which is pretty good. I noticed a very tiny
> performance drop which is more noticeable on short connections (high
> packet rates), my forwarded connection rate went down from 17500/s to
> 17300/s. But I have not checked yet what can be tuned when using the
> BM, nor did I compare CPU usage. I remember having run some tests in
> the past, I guess it was on the XP-GP board, and noticed that the BM
> could save a significant amount of CPU and improve cache efficiency,
> so if this is the case here, we don't really care about a possible 1%
> performance drop.
>
> I'll try to provide more results as time permits.
>
> In the mean time if you want (or plan to submit a next batch), feel
> free to add a Tested-by: Willy Tarreau <w...@1wt.eu>.

Great!  thanks for testing.

Gregory

>
> cheers,
> Willy
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v4 03/12] serial: mvebu-uart: initial support for Armada-3700 serial port

[Gregory CLEMENT]

Hi Greg and Jiri
 
 On mar., févr. 16 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com> 
wrote:

> From: Wilson Ding <ding...@marvell.com>
>
> Armada-3700's uart is a simple serial port, which doesn't
> support. Configuring the modem control lines. The uart port has a 32
> bytes Tx FIFO and a 64 bytes Rx FIFO
>
> The uart driver implements the uart core operations. It also support the
> system (early) console based on Armada-3700's serial port.
>
> Known Issue:
>
> The uart driver currently doesn't support clock programming, which means
> the baud-rate stays with the default value configured by the bootloader
> at boot time
>
> [gregory.clem...@free-electrons.com: Rewrite many part which are too long
> to enumerate]
>
> Signed-off-by: Wilson Ding <ding...@marvell.com>
> Signed-off-by: Nadav Haklai <nad...@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
> Acked-by: Rob Herring <r...@kernel.org>

I took care of the arm related part of the series, but I will let you
apply this patch in the serial subsystem once you have reviewed it. But
if for any reason you preferred that I took it through mvebu just tell
me.

Thanks,

Gregory

> ---
>  .../devicetree/bindings/tty/serial/mvebu-uart.txt  |  13 +
>  Documentation/kernel-parameters.txt|   6 +
>  drivers/tty/serial/Kconfig |  22 +
>  drivers/tty/serial/Makefile|   1 +
>  drivers/tty/serial/mvebu-uart.c| 650 
> +
>  include/uapi/linux/serial_core.h   |   3 +
>  6 files changed, 695 insertions(+)
>  create mode 100644 
> Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
>  create mode 100644 drivers/tty/serial/mvebu-uart.c
>
> diff --git a/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt 
> b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
> new file mode 100644
> index ..6087defd9f93
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/tty/serial/mvebu-uart.txt
> @@ -0,0 +1,13 @@
> +* Marvell UART : Non standard UART used in some of Marvell EBU SoCs (e.g., 
> Armada-3700)
> +
> +Required properties:
> +- compatible: "marvell,armada-3700-uart"
> +- reg: offset and length of the register set for the device.
> +- interrupts: device interrupt
> +
> +Example:
> + serial@12000 {
> + compatible = "marvell,armada-3700-uart";
> + reg = <0x12000 0x400>;
> + interrupts = <43>;
> + };
> diff --git a/Documentation/kernel-parameters.txt 
> b/Documentation/kernel-parameters.txt
> index 87d40a72f6a1..ea0aba48d616 100644
> --- a/Documentation/kernel-parameters.txt
> +++ b/Documentation/kernel-parameters.txt
> @@ -1058,6 +1058,12 @@ bytes respectively. Such letter suffixes can also be 
> entirely omitted.
>   A valid base address must be provided, and the serial
>   port must already be setup and configured.
>  
> + armada3700_uart,
> + Start an early, polled-mode console on the
> + Armada 3700 serial port at the specified
> + address. The serial port must already be setup
> + and configured. Options are not yet supported.
> +
>   earlyprintk=[X86,SH,BLACKFIN,ARM,M68k]
>   earlyprintk=vga
>   earlyprintk=efi
> diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
> index 39721ec4f415..b291f934d51b 100644
> --- a/drivers/tty/serial/Kconfig
> +++ b/drivers/tty/serial/Kconfig
> @@ -1606,6 +1606,28 @@ config SERIAL_STM32_CONSOLE
>   depends on SERIAL_STM32=y
>   select SERIAL_CORE_CONSOLE
>  
> +config SERIAL_MVEBU_UART
> + bool "Marvell EBU serial port support"
> + select SERIAL_CORE
> + help
> +   This driver is for Marvell EBU SoC's UART. If you have a machine
> +   based on the Armada-3700 SoC and wish to use the on-board serial
> +   port,
> +   say 'Y' here.
> +   Otherwise, say 'N'.
> +
> +config SERIAL_MVEBU_CONSOLE
> + bool "Console on Marvell EBU serial port"
> + depends on SERIAL_MVEBU_UART
> + select SERIAL_CORE_CONSOLE
> + select SERIAL_EARLYCON
> + default y
> + help
> +   Say 'Y' here if you wish to use Armada-3700 UART as the system 
> console.
> +   (the system console is the device which receives all kernel messages
> +   and warnings and which allows logins in single user mode)
> +   Otherwise, say 'N'.
> +
>  endmenu
>  
&g

Re: [PATCH v4 04/12] ata: ahci_mvebu: add support for Armada 3700 variant

[Gregory CLEMENT]

Hi Tejun and Hans,
 
 On mar., févr. 16 2016, Gregory CLEMENT <gregory.clem...@free-electrons.com> 
wrote:

> From: Lior Amsalem <al...@marvell.com>
>
> The main difference in the new Armada 3700 is that no address
> decoding needs to take place in the driver probe.
>
> [gregory.clem...@free-electrons.com: reformulate the commit log]
>
> Signed-off-by: Lior Amsalem <al...@marvell.com>
> Reviewed-by: Nadav Haklai <nad...@marvell.com>
> Tested-by: Nadav Haklai <nad...@marvell.com>
> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>

I took care of the arm related part of the series, but I will let you
apply this patch in the sata subsystem once you have reviewed it. But
if for any reason you preferred that I took it through mvebu just tell
me.

Thanks,

Gregory


> ---
>  drivers/ata/ahci_mvebu.c | 14 +-
>  1 file changed, 9 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/ata/ahci_mvebu.c b/drivers/ata/ahci_mvebu.c
> index f7a7fa81740e..de7128d81e9c 100644
> --- a/drivers/ata/ahci_mvebu.c
> +++ b/drivers/ata/ahci_mvebu.c
> @@ -112,12 +112,15 @@ static int ahci_mvebu_probe(struct platform_device 
> *pdev)
>   if (rc)
>   return rc;
>  
> - dram = mv_mbus_dram_info();
> - if (!dram)
> - return -ENODEV;
> + if (of_device_is_compatible(pdev->dev.of_node,
> + "marvell,armada-380-ahci")) {
> + dram = mv_mbus_dram_info();
> + if (!dram)
> + return -ENODEV;
>  
> - ahci_mvebu_mbus_config(hpriv, dram);
> - ahci_mvebu_regret_option(hpriv);
> + ahci_mvebu_mbus_config(hpriv, dram);
> + ahci_mvebu_regret_option(hpriv);
> + }
>  
>   rc = ahci_platform_init_host(pdev, hpriv, _mvebu_port_info,
>_platform_sht);
> @@ -133,6 +136,7 @@ disable_resources:
>  
>  static const struct of_device_id ahci_mvebu_of_match[] = {
>   { .compatible = "marvell,armada-380-ahci", },
> + { .compatible = "marvell,armada-3700-ahci", },
>   { },
>  };
>  MODULE_DEVICE_TABLE(of, ahci_mvebu_of_match);
> -- 
> 2.5.0
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH 08/13] ARM: mvebu: enable SRAM support in mvebu_v7_defconfig

[Gregory CLEMENT]

Hi Marcin,
 
 On dim., nov. 22 2015, Marcin Wojtas <m...@semihalf.com> wrote:

As this config will be needed in any case, I have applied on
mvebu/defconfig. I also added a commit log.

Thanks,

Gregory

> Signed-off-by: Marcin Wojtas <m...@semihalf.com>
> ---
>  arch/arm/configs/mvebu_v7_defconfig | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/arch/arm/configs/mvebu_v7_defconfig 
> b/arch/arm/configs/mvebu_v7_defconfig
> index c6729bf..fe57e20 100644
> --- a/arch/arm/configs/mvebu_v7_defconfig
> +++ b/arch/arm/configs/mvebu_v7_defconfig
> @@ -58,6 +58,7 @@ CONFIG_MTD_M25P80=y
>  CONFIG_MTD_NAND=y
>  CONFIG_MTD_NAND_PXA3xx=y
>  CONFIG_MTD_SPI_NOR=y
> +CONFIG_SRAM=y
>  CONFIG_EEPROM_AT24=y
>  CONFIG_BLK_DEV_SD=y
>  CONFIG_ATA=y
> -- 
> 1.8.3.1
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v2 1/8] ARM: dts: armada-38x: add buffer manager nodes

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada 38x network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-38x.dtsi - for the actual common BM unit (bm@c8000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi 
b/arch/arm/boot/dts/armada-38x.dtsi
index e8b7f6726772..1b7d690d8e10 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -540,6 +540,14 @@
status = "disabled";
};
 
+   bm: bm@c8000 {
+   compatible = "marvell,armada-380-neta-bm";
+   reg = <0xc8000 0xac>;
+   clocks = < 13>;
+   internal-mem = <_bppi>;
+   status = "disabled";
+   };
+
sata@e {
compatible = "marvell,armada-380-ahci";
reg = <0xe 0x2000>;
@@ -618,6 +626,16 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
+
+   bm_bppi: bm-bppi {
+   compatible = "mmio-sram";
+   reg = <MBUS_ID(0x0c, 0x04) 0 0x10>;
+   ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < 13>;
+   status = "disabled";
+   };
};
 
clocks {
-- 
2.5.0

[PATCH v2 2/8] ARM: dts: armada-38x: enable buffer manager support on Armada 38x boards

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on:
* A385-DB-AP - each port has its own pool for long and common pool for
short packets,
* A388-ClearFog - same as above,
* A388-DB - to each port unique 'short' and 'long' pools are mapped,
* A388-GP - same as above.

Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.

[gregory.clem...@free-electrons.com: add suppport for the ClearFog board]

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-385-db-ap.dts  | 20 +++-
 arch/arm/boot/dts/armada-388-clearfog.dts   |  6 ++
 arch/arm/boot/dts/armada-388-db.dts | 17 -
 arch/arm/boot/dts/armada-388-gp.dts | 17 -
 arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 15 ++-
 5 files changed, 71 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts 
b/arch/arm/boot/dts/armada-385-db-ap.dts
index acd5b1519edb..5f9451be21ff 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -61,7 +61,8 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf100 0x10
  MBUS_ID(0x01, 0x1d) 0 0xfff0 0x10
  MBUS_ID(0x09, 0x19) 0 0xf110 0x1
- MBUS_ID(0x09, 0x15) 0 0xf111 0x1>;
+ MBUS_ID(0x09, 0x15) 0 0xf111 0x1
+ MBUS_ID(0x0c, 0x04) 0 0xf120 0x10>;
 
internal-regs {
spi1: spi@10680 {
@@ -138,12 +139,18 @@
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
+   bm,pool-short = <3>;
};
 
ethernet@34000 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
+   bm,pool-short = <3>;
};
 
ethernet@7 {
@@ -157,6 +164,13 @@
status = "okay";
phy = <>;
phy-mode = "rgmii-id";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
+   bm,pool-short = <3>;
+   };
+
+   bm@c8000 {
+   status = "okay";
};
 
nfc: flash@d {
@@ -178,6 +192,10 @@
};
};
 
+   bm-bppi {
+   status = "okay";
+   };
+
pcie-controller {
status = "okay";
 
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts 
b/arch/arm/boot/dts/armada-388-clearfog.dts
index c6e180eb3b11..c60206efb583 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -78,6 +78,9 @@
internal-regs {
ethernet@3 {
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
+   bm,pool-short = <1>;
status = "okay";
 
fixed-link {
@@ -88,6 +91,9 @@
 
ethernet@34000 {
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <3>;
+   bm,pool-short = <1>;
status = "okay";
 
fixed-link {
diff --git a/arch/arm/boot/dts/armada-388-db.dts 
b/arch/arm/boot/dts/armada-388-db.dts
index ff47af57f091..ea93ed727030 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -66,7 +66,8 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf100 0

[PATCH v2 net-next 0/8] API set for HW Buffer management

[Gregory CLEMENT]

Hello,

A few weeks ago I sent a proposal for a API set for HW Buffer
management, to have a better view of the motivation for this API see
the cover letter of this proposal:
http://thread.gmane.org/gmane.linux.kernel/2125152

Since this version I took into account the review from Florian:
- The hardware buffer management helpers are no more built by default
  and now depend on a hidden config symbol which has to be selected
  by the driver if needed
- The hwbm_pool_refill() and hwbm_pool_add() now receive a gfp_t as
  argument allowing the caller to specify the flag it needs.
- buf_num is now tested to ensure there is no wrapping
- A spinlock has been added to protect the hwbm_pool_add() function in
  SMP or irq context.

I also used pr_warn instead of pr_debug in case of errors.

I fixed the mvneta implementation by returning the buffer to the pool
at various place instead of ignoring it.

About the series itself I tried to make this series easier to merge:
- Squashed "bus: mvenus-mbus: Fix size test for
   mvebu_mbus_get_dram_win_info" into bus: mvebu-mbus: provide api for
   obtaining IO and DRAM window information.
- Added my signed-otf-by on all the patches as submitter of the series.
- Renamed the dts patches with the pattern "ARM: dts: platform:"
- Removed the patch "ARM: mvebu: enable SRAM support in
  mvebu_v7_defconfig" of this series and already applied it
- Rodified the order of the patches.

In order to ease the test the branch mvneta-BM-framework-v2 is
available at g...@github.com:MISL-EBU-System-SW/mainline-public.git.

David,

I would like to merge the 4 first patches myself once you will have
take the 4 last patches of the series. Patch 5 do not modify files in
the net subsystem, but as there is a build dependency it is better if
you merge it in the same time as the 3 other ones.

Thanks,

Gregory

Gregory CLEMENT (2):
  net: add a hardware buffer management helper API
  net: mvneta: Use the new hwbm framework

Marcin Wojtas (6):
  ARM: dts: armada-38x: add buffer manager nodes
  ARM: dts: armada-38x: enable buffer manager support on Armada 38x
boards
  ARM: dts: armada-xp: add buffer manager nodes
  ARM: dts: armada-xp: enable buffer manager support on Armada XP boards
  bus: mvebu-mbus: provide api for obtaining IO and DRAM window
information
  net: mvneta: bm: add support for hardware buffer management

 .../bindings/net/marvell-armada-370-neta.txt   |  19 +-
 .../devicetree/bindings/net/marvell-neta-bm.txt|  49 +++
 arch/arm/boot/dts/armada-385-db-ap.dts |  20 +-
 arch/arm/boot/dts/armada-388-clearfog.dts  |   6 +
 arch/arm/boot/dts/armada-388-db.dts|  17 +-
 arch/arm/boot/dts/armada-388-gp.dts|  17 +-
 .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi |  15 +-
 arch/arm/boot/dts/armada-38x.dtsi  |  18 +
 arch/arm/boot/dts/armada-xp-db.dts |  19 +-
 arch/arm/boot/dts/armada-xp-gp.dts |  19 +-
 arch/arm/boot/dts/armada-xp.dtsi   |  18 +
 drivers/bus/mvebu-mbus.c   |  51 +++
 drivers/net/ethernet/marvell/Kconfig   |  15 +
 drivers/net/ethernet/marvell/Makefile  |   1 +
 drivers/net/ethernet/marvell/mvneta.c  | 430 +++---
 drivers/net/ethernet/marvell/mvneta_bm.c   | 486 +
 drivers/net/ethernet/marvell/mvneta_bm.h   | 162 +++
 include/linux/mbus.h   |   3 +
 include/net/hwbm.h |  21 +
 net/Kconfig|   3 +
 net/core/Makefile  |   1 +
 net/core/hwbm.c|  87 
 22 files changed, 1415 insertions(+), 62 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-neta-bm.txt
 create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.c
 create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.h
 create mode 100644 include/net/hwbm.h
 create mode 100644 net/core/hwbm.c

-- 
2.5.0

[PATCH v2 net-next 6/8] net: mvneta: bm: add support for hardware buffer management

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Buffer manager (BM) is a dedicated hardware unit that can be used by all
ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
path by sparing DRAM access on refilling buffer pool, hardware-based
filling of descriptor ring data and better memory utilization due to HW
arbitration for using 'short' pools for small packets.

Tests performed with A388 SoC working as a network bridge between two
packet generators showed increase of maximum processed 64B packets by
~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
when pushing 1500B-packets with a line rate achieved, CPU load decreased
from around 25% without BM to 20% with BM.

BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
are called external BP pools - BPPE. Allocating and releasing buffer
pointers (BP) to/from BPPE is performed indirectly by write/read access
to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
BM hardware controls status of BPPE automatically, as well as assigning
proper buffers to RX descriptors. For more details please refer to
Functional Specification of Armada XP or 38x SoC.

In order to enable support for a separate hardware block, common for all
ports, a new driver has to be implemented ('mvneta_bm'). It provides
initialization sequence of address space, clocks, registers, SRAM,
empty pools' structures and also obtaining optional configuration
from DT (please refer to device tree binding documentation). mvneta_bm
exposes also a necessary API to mvneta driver, as well as a dedicated
structure with BM information (bm_priv), whose presence is used as a
flag notifying of BM usage by port. It has to be ensured that mvneta_bm
probe is executed prior to the ones in ports' driver. In case BM is not
used or its probe fails, mvneta falls back to use software buffer
management.

A sequence executed in mvneta_probe function is modified in order to have
an access to needed resources before possible port's BM initialization is
done. According to port-pools mapping provided by DT appropriate registers
are configured and the buffer pools are filled. RX path is modified
accordingly. Becaues the hardware allows a wide variety of configuration
options, following assumptions are made:
* using BM mechanisms can be selectively disabled/enabled basing
  on DT configuration among the ports
* 'long' pool's single buffer size is tied to port's MTU
* using 'long' pool by port is obligatory and it cannot be shared
* using 'short' pool for smaller packets is optional
* one 'short' pool can be shared among all ports

This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.

[gregory.clem...@free-electrons.com: removed the suspend/resume part]

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 .../bindings/net/marvell-armada-370-neta.txt   |  19 +-
 .../devicetree/bindings/net/marvell-neta-bm.txt|  49 ++
 drivers/net/ethernet/marvell/Kconfig   |  14 +
 drivers/net/ethernet/marvell/Makefile  |   1 +
 drivers/net/ethernet/marvell/mvneta.c  | 417 ---
 drivers/net/ethernet/marvell/mvneta_bm.c   | 562 +
 drivers/net/ethernet/marvell/mvneta_bm.h   | 167 ++
 7 files changed, 1169 insertions(+), 60 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-neta-bm.txt
 create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.c
 create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.h

diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt 
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index d0cb8693963b..73be8970815e 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -18,15 +18,30 @@ Optional properties:
   "core" for core clock and "bus" for the optional bus clock.
 
 
+Optional properties (valid only for Armada XP/38x):
+
+- buffer-manager: a phandle to a buffer manager node. Please refer to
+  Documentation/devicetree/bindings/net/marvell-neta-bm.txt
+- bm,pool-long: ID of a pool, that will accept all packets of a size
+  higher than 'short' pool's threshold (if set) and up to MTU value.
+  Obligatory, when the port is supposed to use hardware
+  buffer management.
+- bm,pool-short: ID of a pool, that will be used for accepting
+  packets of a size lower than given threshold. If not set, the port
+  will use a single 'long' pool for all packets, as defined above.
+
 Example:
 
-ethernet@d007 {
+ethernet@7 {
compatible = "marvell,armada-370-neta";
-   reg = <0xd007 0x2500>;
+   reg = <0x7 0x

[PATCH v2 net-next 8/8] net: mvneta: Use the new hwbm framework

[Gregory CLEMENT]

Now that the hardware buffer management framework had been introduced,
let's use it.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/Kconfig |   1 +
 drivers/net/ethernet/marvell/mvneta.c|  45 +++---
 drivers/net/ethernet/marvell/mvneta_bm.c | 140 +++
 drivers/net/ethernet/marvell/mvneta_bm.h |  11 +--
 4 files changed, 69 insertions(+), 128 deletions(-)

diff --git a/drivers/net/ethernet/marvell/Kconfig 
b/drivers/net/ethernet/marvell/Kconfig
index 6c8dc6d62572..3ae9450c7f1c 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -43,6 +43,7 @@ config MVMDIO
 config MVNETA_BM
tristate "Marvell Armada 38x/XP network interface BM support"
depends on MVNETA
+   select HWBM
---help---
  This driver supports auxiliary block of the network
  interface units in the Marvell ARMADA XP and ARMADA 38x SoC
diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index 1db70565ce8b..981d786b270e 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "mvneta_bm.h"
 #include 
 #include 
@@ -1018,11 +1019,12 @@ static int mvneta_bm_port_init(struct platform_device 
*pdev,
 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
 {
struct mvneta_bm_pool *bm_pool = pp->pool_long;
+   struct hwbm_pool *hwbm_pool = _pool->hwbm_pool;
int num;
 
/* Release all buffers from long pool */
mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
-   if (bm_pool->buf_num) {
+   if (hwbm_pool->buf_num) {
WARN(1, "cannot free all buffers in pool %d\n",
 bm_pool->id);
goto bm_mtu_err;
@@ -1030,14 +1032,14 @@ static void mvneta_bm_update_mtu(struct mvneta_port 
*pp, int mtu)
 
bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
-   bm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
+   hwbm_pool->size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
  SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
 
/* Fill entire long pool */
-   num = mvneta_bm_bufs_add(pp->bm_priv, bm_pool, bm_pool->size);
-   if (num != bm_pool->size) {
+   num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
+   if (num != hwbm_pool->size) {
WARN(1, "pool %d: %d of %d allocated\n",
-bm_pool->id, num, bm_pool->size);
+bm_pool->id, num, hwbm_pool->size);
goto bm_mtu_err;
}
mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
@@ -1717,6 +1719,14 @@ static void mvneta_txq_done(struct mvneta_port *pp,
}
 }
 
+void *mvneta_frag_alloc(unsigned int frag_size)
+{
+   if (likely(frag_size <= PAGE_SIZE))
+   return netdev_alloc_frag(frag_size);
+   else
+   return kmalloc(frag_size, GFP_ATOMIC);
+}
+
 /* Refill processing for SW buffer management */
 static int mvneta_rx_refill(struct mvneta_port *pp,
struct mvneta_rx_desc *rx_desc)
@@ -1772,6 +1782,14 @@ static u32 mvneta_skb_tx_csum(struct mvneta_port *pp, 
struct sk_buff *skb)
return MVNETA_TX_L4_CSUM_NOT;
 }
 
+void mvneta_frag_free(unsigned int frag_size, void *data)
+{
+   if (likely(frag_size <= PAGE_SIZE))
+   skb_free_frag(data);
+   else
+   kfree(data);
+}
+
 /* Drop packets received by the RXQ and free buffers */
 static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
 struct mvneta_rx_queue *rxq)
@@ -1892,7 +1910,8 @@ err_drop_frame:
}
 
/* Refill processing */
-   err = bm_in_use ? mvneta_bm_pool_refill(pp->bm_priv, bm_pool) :
+   err = bm_in_use ? hwbm_pool_refill(_pool->hwbm_pool,
+  GFP_ATOMIC) :
  mvneta_rx_refill(pp, rx_desc);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
@@ -1900,7 +1919,8 @@ err_drop_frame:
goto err_drop_frame_ret_pool;
}
 
-   frag_size = bm_in_use ? bm_pool->frag_size : pp->frag_size;
+   frag_size = bm_in_use ? bm_pool->hwbm_pool.size :
+   pp->frag_size;
 
skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
 
@@ -3963,11 +3983,6 @@ static int mvneta_probe(struct platform_dev

[PATCH v2 net-next 7/8] net: add a hardware buffer management helper API

[Gregory CLEMENT]

This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 include/net/hwbm.h | 21 +
 net/Kconfig|  3 ++
 net/core/Makefile  |  1 +
 net/core/hwbm.c| 87 ++
 4 files changed, 112 insertions(+)
 create mode 100644 include/net/hwbm.h
 create mode 100644 net/core/hwbm.c

diff --git a/include/net/hwbm.h b/include/net/hwbm.h
new file mode 100644
index ..9ae9449a7eda
--- /dev/null
+++ b/include/net/hwbm.h
@@ -0,0 +1,21 @@
+#ifndef _HWBM_H
+#define _HWBM_H
+
+struct hwbm_pool {
+   /* Size of the buffers managed */
+   int size;
+   /* Number of buffers currently used by this pool */
+   int buf_num;
+   /* constructor called during alocation */
+   int (*construct)(struct hwbm_pool *bm_pool, void *buf);
+   /* protect acces to the buffer counter*/
+   spinlock_t lock;
+   /* private data */
+   void *priv;
+};
+
+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf);
+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp);
+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp);
+
+#endif /* _HWBM_H */
diff --git a/net/Kconfig b/net/Kconfig
index 174354618f8a..f50c8af4308b 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -253,6 +253,9 @@ config XPS
depends on SMP
default y
 
+config HWBM
+   bool
+
 config SOCK_CGROUP_DATA
bool
default n
diff --git a/net/core/Makefile b/net/core/Makefile
index 0b835de04de3..57e6dd81c6be 100644
--- a/net/core/Makefile
+++ b/net/core/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_NET_PTP_CLASSIFY) += ptp_classifier.o
 obj-$(CONFIG_CGROUP_NET_PRIO) += netprio_cgroup.o
 obj-$(CONFIG_CGROUP_NET_CLASSID) += netclassid_cgroup.o
 obj-$(CONFIG_LWTUNNEL) += lwtunnel.o
+obj-$(CONFIG_HWBM) += hwbm.o
diff --git a/net/core/hwbm.c b/net/core/hwbm.c
new file mode 100644
index ..a98d2a74ca02
--- /dev/null
+++ b/net/core/hwbm.c
@@ -0,0 +1,87 @@
+/* Support for hardware buffer manager.
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+#include 
+#include 
+#include 
+#include 
+
+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf)
+{
+   if (likely(bm_pool->size <= PAGE_SIZE))
+   skb_free_frag(buf);
+   else
+   kfree(buf);
+}
+EXPORT_SYMBOL_GPL(hwbm_buf_free);
+
+/* Refill processing for HW buffer management */
+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp)
+{
+   int frag_size = bm_pool->size;
+   void *buf;
+
+   if (likely(frag_size <= PAGE_SIZE))
+   buf = netdev_alloc_frag(frag_size);
+   else
+   buf = kmalloc(frag_size, gfp);
+
+   if (!buf)
+   return -ENOMEM;
+
+   if (bm_pool->construct)
+   if (bm_pool->construct(bm_pool, buf)) {
+   hwbm_buf_free(bm_pool, buf);
+   return -ENOMEM;
+   }
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(hwbm_pool_refill);
+
+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp)
+{
+   int err, i;
+   unsigned long flags;
+
+   spin_lock_irqsave(_pool->lock, flags);
+   if (bm_pool->buf_num == bm_pool->size) {
+   pr_warn("pool already filled\n");
+   return bm_pool->buf_num;
+   }
+
+   if (buf_num + bm_pool->buf_num > bm_pool->size) {
+   pr_warn("cannot allocate %d buffers for pool\n",
+   buf_num);
+   return 0;
+   }
+
+   if ((buf_num + bm_pool->buf_num) < bm_pool->buf_num) {
+   pr_warn("Adding %d buffers to the %d current buffers will 
overflow\n",
+   buf_num,  bm_pool->buf_num);
+   return 0;
+   }
+
+   for (i = 0; i < buf_num; i++) {
+   err = hwbm_pool_refill(bm_pool, gfp);
+   if (err < 0)
+   break;
+   }
+
+   /* Update BM driver with number of buffers added to pool */
+   bm_pool->buf_num += i;
+
+   pr_debug("hwpm pool: %d of %d buffers added\n", i, buf_num);
+   spin_unlock_irqrestore(_pool->lock, flags);
+
+   return i;
+}
+EXPORT_SYMBOL_GPL(hwbm_pool_add);
-- 
2.5.0

[PATCH v2 net-next 5/8] bus: mvebu-mbus: provide api for obtaining IO and DRAM window information

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

This commit enables finding appropriate mbus window and obtaining its
target id and attribute for given physical address in two separate
routines, both for IO and DRAM windows. This functionality
is needed for Armada XP/38x Network Controller's Buffer Manager and
PnC configuration.

[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang <xsw...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/bus/mvebu-mbus.c | 52 
 include/linux/mbus.h |  3 +++
 2 files changed, 55 insertions(+)

diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index c43c3d2baf73..c2e52864bb03 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -948,6 +948,58 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
*res = mbus_state.pcie_io_aperture;
 }
 
+int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
+{
+   const struct mbus_dram_target_info *dram;
+   int i;
+
+   /* Get dram info */
+   dram = mv_mbus_dram_info();
+   if (!dram) {
+   pr_err("missing DRAM information\n");
+   return -ENODEV;
+   }
+
+   /* Try to find matching DRAM window for phyaddr */
+   for (i = 0; i < dram->num_cs; i++) {
+   const struct mbus_dram_window *cs = dram->cs + i;
+
+   if (cs->base <= phyaddr &&
+   phyaddr <= (cs->base + cs->size - 1)) {
+   *target = dram->mbus_dram_target_id;
+   *attr = cs->mbus_attr;
+   return 0;
+   }
+   }
+
+   pr_err("invalid dram address 0x%x\n", phyaddr);
+   return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
+
+int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
+  u8 *attr)
+{
+   int win;
+
+   for (win = 0; win < mbus_state.soc->num_wins; win++) {
+   u64 wbase;
+   int enabled;
+
+   mvebu_mbus_read_window(_state, win, , ,
+  size, target, attr, NULL);
+
+   if (!enabled)
+   continue;
+
+   if (wbase <= phyaddr && phyaddr <= wbase + *size)
+   return win;
+   }
+
+   return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
+
 static __init int mvebu_mbus_debugfs_init(void)
 {
struct mvebu_mbus_state *s = _state;
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index 1f7bc630d225..ea34a867caa0 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -69,6 +69,9 @@ static inline const struct mbus_dram_target_info 
*mv_mbus_dram_info_nooverlap(vo
 int mvebu_mbus_save_cpu_target(u32 *store_addr);
 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
 void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
+int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
+  u8 *attr);
 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
  unsigned int attribute,
  phys_addr_t base, size_t size,
-- 
2.5.0

[PATCH v2 3/8] ARM: dts: armada-xp: add buffer manager nodes

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada XP network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-xp.dtsi - for the actual common BM unit (bm@c) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-xp.dtsi | 18 ++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index be23196829bb..bd459360d7a6 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -253,6 +253,14 @@
marvell,crypto-sram-size = <0x800>;
};
 
+   bm: bm@c {
+   compatible = "marvell,armada-380-neta-bm";
+   reg = <0xc 0xac>;
+   clocks = < 13>;
+   internal-mem = <_bppi>;
+   status = "disabled";
+   };
+
xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
@@ -291,6 +299,16 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
+
+   bm_bppi: bm-bppi {
+   compatible = "mmio-sram";
+   reg = <MBUS_ID(0x0c, 0x04) 0 0x10>;
+   ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < 13>;
+   status = "disabled";
+   };
};
 
clocks {
-- 
2.5.0

[PATCH v2 4/8] ARM: dts: armada-xp: enable buffer manager support on Armada XP boards

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on AXP-DB and AXP-GP in same manner - because number of ports
on those boards is the same as number of possible pools, each port is
supposed to use single pool for all kind of packets.

Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-xp-db.dts | 19 ++-
 arch/arm/boot/dts/armada-xp-gp.dts | 19 ++-
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-db.dts 
b/arch/arm/boot/dts/armada-xp-db.dts
index f774101416a5..30657302305d 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -77,7 +77,8 @@
  MBUS_ID(0x01, 0x1d) 0 0 0xfff0 0x10
  MBUS_ID(0x01, 0x2f) 0 0 0xf000 0x100
  MBUS_ID(0x09, 0x09) 0 0 0xf810 0x1
- MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1>;
+ MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1
+ MBUS_ID(0x0c, 0x04) 0 0 0xf120 0x10>;
 
devbus-bootcs {
status = "okay";
@@ -181,21 +182,33 @@
status = "okay";
phy = <>;
phy-mode = "rgmii-id";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <>;
phy-mode = "rgmii-id";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
};
ethernet@3 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
};
ethernet@34000 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <3>;
+   };
+
+   bm@c {
+   status = "okay";
};
 
mvsdio@d4000 {
@@ -230,5 +243,9 @@
};
};
};
+
+   bm-bppi {
+   status = "okay";
+   };
};
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts 
b/arch/arm/boot/dts/armada-xp-gp.dts
index 4878d7353069..a1ded01d0c07 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -96,7 +96,8 @@
  MBUS_ID(0x01, 0x1d) 0 0 0xfff0 0x10
  MBUS_ID(0x01, 0x2f) 0 0 0xf000 0x100
  MBUS_ID(0x09, 0x09) 0 0 0xf810 0x1
- MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1>;
+ MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1
+ MBUS_ID(0x0c, 0x04) 0 0 0xf120 0x10>;
 
devbus-bootcs {
status = "okay";
@@ -196,21 +197,29 @@
status = "okay";
phy = <>;
phy-mode = "qsgmii";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <>;
phy-mode = "qsgmii";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
};
ethernet@3 {
status = "okay";
phy = <>;
phy-mode = 

Re: [PATCH net-next 08/10] bus: mvenus-mbus: Fix size test for mvebu_mbus_get_dram_win_info

[Gregory CLEMENT]

Hi David,
 
 On jeu., janv. 14 2016, David Laight <david.lai...@aculab.com> wrote:

> From: Gregory CLEMENT
>> Sent: 12 January 2016 19:11
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>>  drivers/bus/mvebu-mbus.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>> 
>> diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
>> index 3d1c0c3880ec..214bb964165b 100644
>> --- a/drivers/bus/mvebu-mbus.c
>> +++ b/drivers/bus/mvebu-mbus.c
>> @@ -964,7 +964,7 @@ int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 
>> *target, u8 *attr)
>>  for (i = 0; i < dram->num_cs; i++) {
>>  const struct mbus_dram_window *cs = dram->cs + i;
>> 
>> -if (cs->base <= phyaddr && phyaddr <= (cs->base + cs->size)) {
>> +if (cs->base <= phyaddr && phyaddr <= (cs->base + cs->size - 
>> 1)) {
>
> Wouldn't it be better to change the line to:
>> +if (cs->base <= phyaddr && phyaddr < (cs->base +
>cs->size)) {

It doesn't work if there is 4GB of memory in this case we can have
cs->base + cs->size which wrap to 0 and the test fails. It was exactly
what happened on Armada XP GP board.

Gregory

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

Re: [PATCH v3 09/12] arm64: dts: add the Marvell Armada 3700 family and a development board

[Gregory CLEMENT]

Hi Jisheng,
 
 On mar., févr. 16 2016, Jisheng Zhang <jszh...@marvell.com> wrote:

> Dear Gregory,
> On Mon, 8 Feb 2016 18:14:17 +0100 Gregory CLEMENT wrote:
>
>> Add initial dtsi files to support Marvell Armada 3700 SoC with Cortex-A53
>> CPUs. There are two members in this family: the Armada 3710 (Single CPU)
>> and the Armada 3720 (Dual CPUs).
>> 
>> It also adds a dts file for the Marvell Armada 3720 DB board.
>> 
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> ---
>>  arch/arm64/boot/dts/marvell/Makefile   |   4 +
>>  arch/arm64/boot/dts/marvell/armada-371x.dtsi   |  53 ++
>>  arch/arm64/boot/dts/marvell/armada-3720-db.dts |  86 
>>  arch/arm64/boot/dts/marvell/armada-372x.dtsi   |  63 
>>  arch/arm64/boot/dts/marvell/armada-37xx.dtsi   | 131 
>> +
>>  5 files changed, 337 insertions(+)
>>  create mode 100644 arch/arm64/boot/dts/marvell/armada-371x.dtsi
>>  create mode 100644 arch/arm64/boot/dts/marvell/armada-3720-db.dts
>>  create mode 100644 arch/arm64/boot/dts/marvell/armada-372x.dtsi
>>  create mode 100644 arch/arm64/boot/dts/marvell/armada-37xx.dtsi
>> 
>> diff --git a/arch/arm64/boot/dts/marvell/Makefile 
>> b/arch/arm64/boot/dts/marvell/Makefile
>> index 348f4db4f313..2114af8d312d 100644
>> --- a/arch/arm64/boot/dts/marvell/Makefile
>> +++ b/arch/arm64/boot/dts/marvell/Makefile
>> @@ -1,6 +1,10 @@
>> +# Berlin SoC Family
>>  dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-dmp.dtb
>>  dtb-$(CONFIG_ARCH_BERLIN) += berlin4ct-stb.dtb
>>  
>> +# Mvebu SoC Family
>> +dtb-$(CONFIG_ARCH_MVEBU) += armada-3720-db.dtb
>> +
>>  always  := $(dtb-y)
>>  subdir-y:= $(dts-dirs)
>>  clean-files := *.dtb
>> diff --git a/arch/arm64/boot/dts/marvell/armada-371x.dtsi 
>> b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
>> new file mode 100644
>> index ..c9e5325b8ac3
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/marvell/armada-371x.dtsi
>> @@ -0,0 +1,53 @@
>> +/*
>> + * Device Tree Include file for Marvell Armada 371x family of SoCs
>> + * (also named 88F3710)
>> + *
>> + * Copyright (C) 2016 Marvell
>
> Is it better to Add full Marvell company name, eg. Marvell Technology Group 
> Ltd.
>

Well for mvebu I also saw "Marvell International Ltd." and "Marvell
Semiconductors". So at least Marvell is the common pattern.

>> + *
>> + * Gregory CLEMENT <gregory.clem...@free-electrons.com>
>
> What does this mean? in copyright holder list or just author? Is it better
> to add "Author:" prefix or something else?
>
>

I don't know the subtilitis between copyright holder list and author...

> [...]
>
>> diff --git a/arch/arm64/boot/dts/marvell/armada-37xx.dtsi 
>> b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
>> new file mode 100644
>> index ..ba9df7ff2a72
>> --- /dev/null
>> +++ b/arch/arm64/boot/dts/marvell/armada-37xx.dtsi
>> @@ -0,0 +1,131 @@
>> +/*
>> + * Device Tree Include file for Marvell Armada 37xx family of SoCs.
>> + *
>> + * Copyright (C) 2016 Marvell
>> + *
>> + * Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> + *
>> + * This file is dual-licensed: you can use it either under the terms
>> + * of the GPL or the X11 license, at your option. Note that this dual
>> + * licensing only applies to this file, and not this project as a
>> + * whole.
>> + *
>> + *  a) This file is free software; you can redistribute it and/or
>> + * modify it under the terms of the GNU General Public License as
>> + * published by the Free Software Foundation; either version 2 of the
>> + * License, or (at your option) any later version.
>> + *
>> + * This file is distributed in the hope that it will be useful
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + *
>> + * Or, alternatively
>> + *
>> + *  b) Permission is hereby granted, free of charge, to any person
>> + * obtaining a copy of this software and associated documentation
>> + * files (the "Software"), to deal in the Software without
>> + * restriction, including without limitation the rights to use
>> + * copy, modify, merge, publish, distribute, sublicense, and/or
>> + * sell copies of the Software, and to permit persons to whom 

Re: [PATCH v3 05/12] arm64: add mvebu architecture entry

[Gregory CLEMENT]

Hi Jisheng,
 
 On mar., févr. 16 2016, Jisheng Zhang <jszh...@marvell.com> wrote:

> Dear Gregory,
>
> On Mon, 8 Feb 2016 18:14:13 +0100 Gregory CLEMENT wrote:
>
>> The Armada 3700 is an mvebu ARM64 SoC using one or two Cortex-A53 cores
>> depending of the variant.
>> 
>> Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
>> Reviewed-by: Thomas Petazzoni <thomas.petazz...@free-electrons.com>
>> ---
>>  arch/arm64/Kconfig.platforms | 6 ++
>>  1 file changed, 6 insertions(+)
>> 
>> diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms
>> index 21074f674bde..c621e69ed170 100644
>> --- a/arch/arm64/Kconfig.platforms
>> +++ b/arch/arm64/Kconfig.platforms
>> @@ -1,5 +1,11 @@
>>  menu "Platform selection"
>>  
>> +config ARCH_MVEBU
>
> it's better to keep ARCH_YYZZ sorted in alphabetic order


Yes I should have move the entry when I renamed it.

I will sent a v4 soon for this point.

Gregory

>
> Thanks,
> Jisheng
>
>> +bool "Marvell EBU SoC Family"
>> +help
>> +  This enables support for Marvell EBU family such as the
>> +  Armada 3700 SoC family.
>> +
>>  config ARCH_BCM_IPROC
>>  bool "Broadcom iProc SoC Family"
>>  help
>

-- 
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com

[PATCH v5 net-next 09/10] net: add a hardware buffer management helper API

[Gregory CLEMENT]

This basic implementation allows to share code between driver using
hardware buffer management. As the code is hardware agnostic, there is
few helpers, most of the optimization brought by the an HW BM has to be
done at driver level.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 include/net/hwbm.h | 28 ++
 net/Kconfig|  3 ++
 net/core/Makefile  |  1 +
 net/core/hwbm.c| 87 ++
 4 files changed, 119 insertions(+)
 create mode 100644 include/net/hwbm.h
 create mode 100644 net/core/hwbm.c

diff --git a/include/net/hwbm.h b/include/net/hwbm.h
new file mode 100644
index ..47d08662501b
--- /dev/null
+++ b/include/net/hwbm.h
@@ -0,0 +1,28 @@
+#ifndef _HWBM_H
+#define _HWBM_H
+
+struct hwbm_pool {
+   /* Capacity of the pool */
+   int size;
+   /* Size of the buffers managed */
+   int frag_size;
+   /* Number of buffers currently used by this pool */
+   int buf_num;
+   /* constructor called during alocation */
+   int (*construct)(struct hwbm_pool *bm_pool, void *buf);
+   /* protect acces to the buffer counter*/
+   spinlock_t lock;
+   /* private data */
+   void *priv;
+};
+#ifdef CONFIG_HWBM
+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf);
+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp);
+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp);
+#else
+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf) {}
+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp) { return 0; }
+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp)
+{ return 0; }
+#endif /* CONFIG_HWBM */
+#endif /* _HWBM_H */
diff --git a/net/Kconfig b/net/Kconfig
index 174354618f8a..f50c8af4308b 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -253,6 +253,9 @@ config XPS
depends on SMP
default y
 
+config HWBM
+   bool
+
 config SOCK_CGROUP_DATA
bool
default n
diff --git a/net/core/Makefile b/net/core/Makefile
index 0b835de04de3..57e6dd81c6be 100644
--- a/net/core/Makefile
+++ b/net/core/Makefile
@@ -24,3 +24,4 @@ obj-$(CONFIG_NET_PTP_CLASSIFY) += ptp_classifier.o
 obj-$(CONFIG_CGROUP_NET_PRIO) += netprio_cgroup.o
 obj-$(CONFIG_CGROUP_NET_CLASSID) += netclassid_cgroup.o
 obj-$(CONFIG_LWTUNNEL) += lwtunnel.o
+obj-$(CONFIG_HWBM) += hwbm.o
diff --git a/net/core/hwbm.c b/net/core/hwbm.c
new file mode 100644
index ..941c28486896
--- /dev/null
+++ b/net/core/hwbm.c
@@ -0,0 +1,87 @@
+/* Support for hardware buffer manager.
+ *
+ * Copyright (C) 2016 Marvell
+ *
+ * Gregory CLEMENT <gregory.clem...@free-electrons.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+#include 
+#include 
+#include 
+#include 
+
+void hwbm_buf_free(struct hwbm_pool *bm_pool, void *buf)
+{
+   if (likely(bm_pool->frag_size <= PAGE_SIZE))
+   skb_free_frag(buf);
+   else
+   kfree(buf);
+}
+EXPORT_SYMBOL_GPL(hwbm_buf_free);
+
+/* Refill processing for HW buffer management */
+int hwbm_pool_refill(struct hwbm_pool *bm_pool, gfp_t gfp)
+{
+   int frag_size = bm_pool->frag_size;
+   void *buf;
+
+   if (likely(frag_size <= PAGE_SIZE))
+   buf = netdev_alloc_frag(frag_size);
+   else
+   buf = kmalloc(frag_size, gfp);
+
+   if (!buf)
+   return -ENOMEM;
+
+   if (bm_pool->construct)
+   if (bm_pool->construct(bm_pool, buf)) {
+   hwbm_buf_free(bm_pool, buf);
+   return -ENOMEM;
+   }
+
+   return 0;
+}
+EXPORT_SYMBOL_GPL(hwbm_pool_refill);
+
+int hwbm_pool_add(struct hwbm_pool *bm_pool, unsigned int buf_num, gfp_t gfp)
+{
+   int err, i;
+   unsigned long flags;
+
+   spin_lock_irqsave(_pool->lock, flags);
+   if (bm_pool->buf_num == bm_pool->size) {
+   pr_warn("pool already filled\n");
+   return bm_pool->buf_num;
+   }
+
+   if (buf_num + bm_pool->buf_num > bm_pool->size) {
+   pr_warn("cannot allocate %d buffers for pool\n",
+   buf_num);
+   return 0;
+   }
+
+   if ((buf_num + bm_pool->buf_num) < bm_pool->buf_num) {
+   pr_warn("Adding %d buffers to the %d current buffers will 
overflow\n",
+   buf_num,  bm_pool->buf_num);
+   return 0;
+   }
+
+   for (i = 0; i < buf_num; i++) {
+   err = hwbm_pool_refill(bm_pool, gfp);
+   if (err < 0)
+   break;
+   }
+
+   /* Update BM driver with number of buffers added to

[PATCH v5 net-next 10/10] net: mvneta: Use the new hwbm framework

[Gregory CLEMENT]

Now that the hardware buffer management framework had been introduced,
let's use it.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/net/ethernet/marvell/Kconfig |   1 +
 drivers/net/ethernet/marvell/mvneta.c|  18 +++--
 drivers/net/ethernet/marvell/mvneta_bm.c | 125 ---
 drivers/net/ethernet/marvell/mvneta_bm.h |  17 ++---
 4 files changed, 49 insertions(+), 112 deletions(-)

diff --git a/drivers/net/ethernet/marvell/Kconfig 
b/drivers/net/ethernet/marvell/Kconfig
index ac6605c62f46..62d80fddbe34 100644
--- a/drivers/net/ethernet/marvell/Kconfig
+++ b/drivers/net/ethernet/marvell/Kconfig
@@ -43,6 +43,7 @@ config MVMDIO
 config MVNETA_BM
tristate "Marvell Armada 38x/XP network interface BM support"
depends on MVNETA
+   select HWBM
---help---
  This driver supports auxiliary block of the network
  interface units in the Marvell ARMADA XP and ARMADA 38x SoC
diff --git a/drivers/net/ethernet/marvell/mvneta.c 
b/drivers/net/ethernet/marvell/mvneta.c
index ade5b0b961d3..daf94a82c9f5 100644
--- a/drivers/net/ethernet/marvell/mvneta.c
+++ b/drivers/net/ethernet/marvell/mvneta.c
@@ -30,6 +30,7 @@
 #include 
 #include 
 #include 
+#include 
 #include "mvneta_bm.h"
 #include 
 #include 
@@ -1021,11 +1022,12 @@ static int mvneta_bm_port_init(struct platform_device 
*pdev,
 static void mvneta_bm_update_mtu(struct mvneta_port *pp, int mtu)
 {
struct mvneta_bm_pool *bm_pool = pp->pool_long;
+   struct hwbm_pool *hwbm_pool = _pool->hwbm_pool;
int num;
 
/* Release all buffers from long pool */
mvneta_bm_bufs_free(pp->bm_priv, bm_pool, 1 << pp->id);
-   if (bm_pool->buf_num) {
+   if (hwbm_pool->buf_num) {
WARN(1, "cannot free all buffers in pool %d\n",
 bm_pool->id);
goto bm_mtu_err;
@@ -1033,14 +1035,14 @@ static void mvneta_bm_update_mtu(struct mvneta_port 
*pp, int mtu)
 
bm_pool->pkt_size = MVNETA_RX_PKT_SIZE(mtu);
bm_pool->buf_size = MVNETA_RX_BUF_SIZE(bm_pool->pkt_size);
-   bm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
- SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
+   hwbm_pool->frag_size = SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
+   SKB_DATA_ALIGN(MVNETA_RX_BUF_SIZE(bm_pool->pkt_size));
 
/* Fill entire long pool */
-   num = mvneta_bm_bufs_add(pp->bm_priv, bm_pool, bm_pool->size);
-   if (num != bm_pool->size) {
+   num = hwbm_pool_add(hwbm_pool, hwbm_pool->size, GFP_ATOMIC);
+   if (num != hwbm_pool->size) {
WARN(1, "pool %d: %d of %d allocated\n",
-bm_pool->id, num, bm_pool->size);
+bm_pool->id, num, hwbm_pool->size);
goto bm_mtu_err;
}
mvneta_bm_pool_bufsize_set(pp, bm_pool->buf_size, bm_pool->id);
@@ -2028,14 +2030,14 @@ err_drop_frame:
}
 
/* Refill processing */
-   err = mvneta_bm_pool_refill(pp->bm_priv, bm_pool);
+   err = hwbm_pool_refill(_pool->hwbm_pool, GFP_ATOMIC);
if (err) {
netdev_err(dev, "Linux processing - Can't refill\n");
rxq->missed++;
goto err_drop_frame_ret_pool;
}
 
-   frag_size = bm_pool->frag_size;
+   frag_size = bm_pool->hwbm_pool.frag_size;
 
skb = build_skb(data, frag_size > PAGE_SIZE ? 0 : frag_size);
 
diff --git a/drivers/net/ethernet/marvell/mvneta_bm.c 
b/drivers/net/ethernet/marvell/mvneta_bm.c
index 8c968e7d2d8f..01fccec632ec 100644
--- a/drivers/net/ethernet/marvell/mvneta_bm.c
+++ b/drivers/net/ethernet/marvell/mvneta_bm.c
@@ -10,16 +10,17 @@
  * warranty of any kind, whether express or implied.
  */
 
-#include 
+#include 
 #include 
-#include 
-#include 
-#include 
+#include 
+#include 
 #include 
 #include 
-#include 
+#include 
 #include 
-#include 
+#include 
+#include 
+#include 
 #include "mvneta_bm.h"
 
 #define MVNETA_BM_DRIVER_NAME "mvneta_bm"
@@ -88,17 +89,13 @@ static void mvneta_bm_pool_target_set(struct mvneta_bm 
*priv, int pool_id,
mvneta_bm_write(priv, MVNETA_BM_XBAR_POOL_REG(pool_id), val);
 }
 
-/* Allocate skb for BM pool */
-void *mvneta_buf_alloc(struct mvneta_bm *priv, struct mvneta_bm_pool *bm_pool,
-  dma_addr_t *buf_phys_addr)
+int mvneta_bm_construct(struct hwbm_pool *hwbm_pool, void *buf)
 {
-   void *buf;
+   struct mvneta_bm_pool *bm_pool =
+   (struct mvneta_bm_pool *)hwbm_pool->priv;
+   struct mvneta_bm *priv = bm_pool->priv;
dma_addr_t phys_addr;
 
-   buf = mvneta_frag_all

[PATCH v5 net-next 01/10] misc: sram: add optional ioremap without write combining

[Gregory CLEMENT]

From: Marcin Wojtas 

Some SRAM users may require non-bufferable access to the memory, which is
impossible, because devm_ioremap_wc() is used for setting sram->virt_base.

This commit adds optional flag 'no-memory-wc', which allow to choose remap
method, using DT property. Documentation is updated accordingly.

Signed-off-by: Marcin Wojtas 
---
 Documentation/devicetree/bindings/sram/sram.txt | 5 +
 drivers/misc/sram.c | 5 -
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/sram/sram.txt 
b/Documentation/devicetree/bindings/sram/sram.txt
index 42ee9438b771..227e3a341af1 100644
--- a/Documentation/devicetree/bindings/sram/sram.txt
+++ b/Documentation/devicetree/bindings/sram/sram.txt
@@ -25,6 +25,11 @@ Required properties in the sram node:
 - ranges : standard definition, should translate from local addresses
within the sram to bus addresses
 
+Optional properties in the sram node:
+
+- no-memory-wc : the flag indicating, that SRAM memory region has not to
+ be remapped as write combining. WC is used by default.
+
 Required properties in the area nodes:
 
 - reg : iomem address range, relative to the SRAM range
diff --git a/drivers/misc/sram.c b/drivers/misc/sram.c
index 736dae715dbf..69cdabea9c03 100644
--- a/drivers/misc/sram.c
+++ b/drivers/misc/sram.c
@@ -360,7 +360,10 @@ static int sram_probe(struct platform_device *pdev)
return -EBUSY;
}
 
-   sram->virt_base = devm_ioremap_wc(sram->dev, res->start, size);
+   if (of_property_read_bool(pdev->dev.of_node, "no-memory-wc"))
+   sram->virt_base = devm_ioremap(sram->dev, res->start, size);
+   else
+   sram->virt_base = devm_ioremap_wc(sram->dev, res->start, size);
if (IS_ERR(sram->virt_base))
return PTR_ERR(sram->virt_base);
 
-- 
2.5.0

[PATCH v5 net-next 00/10] API set for HW Buffer management

[Gregory CLEMENT]

Hi,

This is the fifth version of the API set for HW Buffer management (that was
initially submitted here:
http://thread.gmane.org/gmane.linux.kernel/2125152).

Since the forth I integrated fixes found by Dmitri Epshtein:
- as pointed by Marcin, a filed witth the size of the buffer of the
  pool was added. It then allow to fix some misused size in the
  mvneta_bm code when using the new framework.

I also added a new patch from Marcin for sram allowing to require
non-bufferable access to the memory. It was needed for the hardwre
buffer management of the mvneta.

Finally, I fixed the build issue notified by the 0-day builder when
building the drivers as module.

For the record in the previous versions I made the following changes:
v3 -> v4
- Fix build issue when HWBM is not selected

v2 -> v3
- Make a HWBM and a SWBM version of the mvneta_rx() function in order
  to reduce the the conditional code. Kept a condition inside the
  mvneta_poll because specializing this function would have means
  duplicating 95% of the code.

- Put back the register_netdev() call at the end of the mvneta_probe()
  function. In order to have a unique ID for each port, just used a
  global variable in the driver.

- Added a fix from Marcin in the "net: mvneta: bm: add support for
  hardware buffer management" patch: "when dropping packets, only
  buffer pointers passed from BM to descriptors have to be returned to
  the pool. In submitted version after closing the port and
  mvneta_rxq_deinit(), it was very likely that a lot of fake buffers
  are added to the pool, because all descriptors took part in
  iteration."

- Removed the select MVNETA_BM from the Kconfig, it will let the user
  the choice to use not use it if they want.

v1 -> v2
- The hardware buffer management helpers are no more built by default
  and now depend on a hidden config symbol which has to be selected
  by the driver if needed
- The hwbm_pool_refill() and hwbm_pool_add() now receive a gfp_t as
  argument allowing the caller to specify the flag it needs.
- buf_num is now tested to ensure there is no wrapping
- A spinlock has been added to protect the hwbm_pool_add() function in
  SMP or irq context.
- used pr_warn instead of pr_debug in case of errors.
- fixed the mvneta implementation by returning the buffer to the pool
  at various place instead of ignoring it.
- Squashed "bus: mvenus-mbus: Fix size test for
   mvebu_mbus_get_dram_win_info" into bus: mvebu-mbus: provide api for
   obtaining IO and DRAM window information.
- Added my signed-otf-by on all the patches as submitter of the series.
- Renamed the dts patches with the pattern "ARM: dts: platform:"
- Removed the patch "ARM: mvebu: enable SRAM support in
  mvebu_v7_defconfig" of this series and already applied it
- Modified the order of the patches.

In order to ease the test the branch mvneta-BM-framework-v5 is
available at g...@github.com:MISL-EBU-System-SW/mainline-public.git.

Thanks,

Gregory


Gregory CLEMENT (3):
  ARM: dts: armada-xp-openblocks-ax3-4: Add BM support
  net: add a hardware buffer management helper API
  net: mvneta: Use the new hwbm framework

Marcin Wojtas (7):
  misc: sram: add optional ioremap without write combining
  ARM: dts: armada-38x: add buffer manager nodes
  ARM: dts: armada-38x: enable buffer manager support on Armada 38x
boards
  ARM: dts: armada-xp: add buffer manager nodes
  ARM: dts: armada-xp: enable buffer manager support on Armada XP boards
  bus: mvebu-mbus: provide api for obtaining IO and DRAM window
information
  net: mvneta: bm: add support for hardware buffer management

 .../bindings/net/marvell-armada-370-neta.txt   |  19 +-
 .../devicetree/bindings/net/marvell-neta-bm.txt|  49 ++
 Documentation/devicetree/bindings/sram/sram.txt|   5 +
 arch/arm/boot/dts/armada-385-db-ap.dts |  20 +-
 arch/arm/boot/dts/armada-388-clearfog.dts  |   6 +
 arch/arm/boot/dts/armada-388-db.dts|  17 +-
 arch/arm/boot/dts/armada-388-gp.dts|  17 +-
 .../arm/boot/dts/armada-38x-solidrun-microsom.dtsi |  15 +-
 arch/arm/boot/dts/armada-38x.dtsi  |  19 +
 arch/arm/boot/dts/armada-xp-db.dts |  19 +-
 arch/arm/boot/dts/armada-xp-gp.dts |  19 +-
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts   |  19 +-
 arch/arm/boot/dts/armada-xp.dtsi   |  19 +
 drivers/bus/mvebu-mbus.c   |  52 +++
 drivers/misc/sram.c|   5 +-
 drivers/net/ethernet/marvell/Kconfig   |  14 +
 drivers/net/ethernet/marvell/Makefile  |   1 +
 drivers/net/ethernet/marvell/mvneta.c  | 509 +++--
 drivers/net/ethernet/marvell/mvneta_bm.c   | 487 
 drivers/net/ethernet/marvell/mvneta_bm.h   | 182 
 include/linux/mbus.h   |   3 +
 include/net/h

[PATCH v5 net-next 03/10] ARM: dts: armada-38x: enable buffer manager support on Armada 38x boards

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on:
* A385-DB-AP - each port has its own pool for long and common pool for
short packets,
* A388-ClearFog - same as above,
* A388-DB - to each port unique 'short' and 'long' pools are mapped,
* A388-GP - same as above.

Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.

[gregory.clem...@free-electrons.com: add suppport for the ClearFog board]

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
Acked-by: Russell King <rmk+ker...@arm.linux.org.uk>
---
 arch/arm/boot/dts/armada-385-db-ap.dts  | 20 +++-
 arch/arm/boot/dts/armada-388-clearfog.dts   |  6 ++
 arch/arm/boot/dts/armada-388-db.dts | 17 -
 arch/arm/boot/dts/armada-388-gp.dts | 17 -
 arch/arm/boot/dts/armada-38x-solidrun-microsom.dtsi | 15 ++-
 5 files changed, 71 insertions(+), 4 deletions(-)

diff --git a/arch/arm/boot/dts/armada-385-db-ap.dts 
b/arch/arm/boot/dts/armada-385-db-ap.dts
index acd5b1519edb..5f9451be21ff 100644
--- a/arch/arm/boot/dts/armada-385-db-ap.dts
+++ b/arch/arm/boot/dts/armada-385-db-ap.dts
@@ -61,7 +61,8 @@
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf100 0x10
  MBUS_ID(0x01, 0x1d) 0 0xfff0 0x10
  MBUS_ID(0x09, 0x19) 0 0xf110 0x1
- MBUS_ID(0x09, 0x15) 0 0xf111 0x1>;
+ MBUS_ID(0x09, 0x15) 0 0xf111 0x1
+ MBUS_ID(0x0c, 0x04) 0 0xf120 0x10>;
 
internal-regs {
spi1: spi@10680 {
@@ -138,12 +139,18 @@
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
+   bm,pool-short = <3>;
};
 
ethernet@34000 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
+   bm,pool-short = <3>;
};
 
ethernet@7 {
@@ -157,6 +164,13 @@
status = "okay";
phy = <>;
phy-mode = "rgmii-id";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
+   bm,pool-short = <3>;
+   };
+
+   bm@c8000 {
+   status = "okay";
};
 
nfc: flash@d {
@@ -178,6 +192,10 @@
};
};
 
+   bm-bppi {
+   status = "okay";
+   };
+
pcie-controller {
status = "okay";
 
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dts 
b/arch/arm/boot/dts/armada-388-clearfog.dts
index c6e180eb3b11..c60206efb583 100644
--- a/arch/arm/boot/dts/armada-388-clearfog.dts
+++ b/arch/arm/boot/dts/armada-388-clearfog.dts
@@ -78,6 +78,9 @@
internal-regs {
ethernet@3 {
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
+   bm,pool-short = <1>;
status = "okay";
 
fixed-link {
@@ -88,6 +91,9 @@
 
ethernet@34000 {
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <3>;
+   bm,pool-short = <1>;
status = "okay";
 
fixed-link {
diff --git a/arch/arm/boot/dts/armada-388-db.dts 
b/arch/arm/boot/dts/armada-388-db.dts
index ff47af57f091..ea93ed727030 100644
--- a/arch/arm/boot/dts/armada-388-db.dts
+++ b/arch/arm/boot/dts/armada-388-db.dts
@@ -66,7 +66,8 @@
ranges = <

[PATCH v5 net-next 08/10] net: mvneta: bm: add support for hardware buffer management

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Buffer manager (BM) is a dedicated hardware unit that can be used by all
ethernet ports of Armada XP and 38x SoC's. It allows to offload CPU on RX
path by sparing DRAM access on refilling buffer pool, hardware-based
filling of descriptor ring data and better memory utilization due to HW
arbitration for using 'short' pools for small packets.

Tests performed with A388 SoC working as a network bridge between two
packet generators showed increase of maximum processed 64B packets by
~20k (~555k packets with BM enabled vs ~535 packets without BM). Also
when pushing 1500B-packets with a line rate achieved, CPU load decreased
from around 25% without BM to 20% with BM.

BM comprise up to 4 buffer pointers' (BP) rings kept in DRAM, which
are called external BP pools - BPPE. Allocating and releasing buffer
pointers (BP) to/from BPPE is performed indirectly by write/read access
to a dedicated internal SRAM, where internal BP pools (BPPI) are placed.
BM hardware controls status of BPPE automatically, as well as assigning
proper buffers to RX descriptors. For more details please refer to
Functional Specification of Armada XP or 38x SoC.

In order to enable support for a separate hardware block, common for all
ports, a new driver has to be implemented ('mvneta_bm'). It provides
initialization sequence of address space, clocks, registers, SRAM,
empty pools' structures and also obtaining optional configuration
from DT (please refer to device tree binding documentation). mvneta_bm
exposes also a necessary API to mvneta driver, as well as a dedicated
structure with BM information (bm_priv), whose presence is used as a
flag notifying of BM usage by port. It has to be ensured that mvneta_bm
probe is executed prior to the ones in ports' driver. In case BM is not
used or its probe fails, mvneta falls back to use software buffer
management.

A sequence executed in mvneta_probe function is modified in order to have
an access to needed resources before possible port's BM initialization is
done. According to port-pools mapping provided by DT appropriate registers
are configured and the buffer pools are filled. RX path is modified
accordingly. Becaues the hardware allows a wide variety of configuration
options, following assumptions are made:
* using BM mechanisms can be selectively disabled/enabled basing
  on DT configuration among the ports
* 'long' pool's single buffer size is tied to port's MTU
* using 'long' pool by port is obligatory and it cannot be shared
* using 'short' pool for smaller packets is optional
* one 'short' pool can be shared among all ports

This commit enables hardware buffer management operation cooperating with
existing mvneta driver. New device tree binding documentation is added and
the one of mvneta is updated accordingly.

[gregory.clem...@free-electrons.com: removed the suspend/resume part]

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 .../bindings/net/marvell-armada-370-neta.txt   |  19 +-
 .../devicetree/bindings/net/marvell-neta-bm.txt|  49 ++
 drivers/net/ethernet/marvell/Kconfig   |  13 +
 drivers/net/ethernet/marvell/Makefile  |   1 +
 drivers/net/ethernet/marvell/mvneta.c  | 507 +--
 drivers/net/ethernet/marvell/mvneta_bm.c   | 546 +
 drivers/net/ethernet/marvell/mvneta_bm.h   | 189 +++
 7 files changed, 1285 insertions(+), 39 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/net/marvell-neta-bm.txt
 create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.c
 create mode 100644 drivers/net/ethernet/marvell/mvneta_bm.h

diff --git a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt 
b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
index d0cb8693963b..73be8970815e 100644
--- a/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
+++ b/Documentation/devicetree/bindings/net/marvell-armada-370-neta.txt
@@ -18,15 +18,30 @@ Optional properties:
   "core" for core clock and "bus" for the optional bus clock.
 
 
+Optional properties (valid only for Armada XP/38x):
+
+- buffer-manager: a phandle to a buffer manager node. Please refer to
+  Documentation/devicetree/bindings/net/marvell-neta-bm.txt
+- bm,pool-long: ID of a pool, that will accept all packets of a size
+  higher than 'short' pool's threshold (if set) and up to MTU value.
+  Obligatory, when the port is supposed to use hardware
+  buffer management.
+- bm,pool-short: ID of a pool, that will be used for accepting
+  packets of a size lower than given threshold. If not set, the port
+  will use a single 'long' pool for all packets, as defined above.
+
 Example:
 
-ethernet@d007 {
+ethernet@7 {
compatible = "marvell,armada-370-neta";
-   reg = <0xd007 0x2500>;
+   reg = <0x7 0x

[PATCH v5 net-next 05/10] ARM: dts: armada-xp: enable buffer manager support on Armada XP boards

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Since mvneta driver supports using hardware buffer management (BM), in
order to use it, board files have to be adjusted accordingly. This commit
enables BM on AXP-DB and AXP-GP in same manner - because number of ports
on those boards is the same as number of possible pools, each port is
supposed to use single pool for all kind of packets.

Moreover appropriate entry is added to 'soc' node ranges, as well as "okay"
status for 'bm' and 'bm-bppi' (internal SRAM) nodes.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-xp-db.dts | 19 ++-
 arch/arm/boot/dts/armada-xp-gp.dts | 19 ++-
 2 files changed, 36 insertions(+), 2 deletions(-)

diff --git a/arch/arm/boot/dts/armada-xp-db.dts 
b/arch/arm/boot/dts/armada-xp-db.dts
index f774101416a5..30657302305d 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -77,7 +77,8 @@
  MBUS_ID(0x01, 0x1d) 0 0 0xfff0 0x10
  MBUS_ID(0x01, 0x2f) 0 0 0xf000 0x100
  MBUS_ID(0x09, 0x09) 0 0 0xf810 0x1
- MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1>;
+ MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1
+ MBUS_ID(0x0c, 0x04) 0 0 0xf120 0x10>;
 
devbus-bootcs {
status = "okay";
@@ -181,21 +182,33 @@
status = "okay";
phy = <>;
phy-mode = "rgmii-id";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <>;
phy-mode = "rgmii-id";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
};
ethernet@3 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
};
ethernet@34000 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <3>;
+   };
+
+   bm@c {
+   status = "okay";
};
 
mvsdio@d4000 {
@@ -230,5 +243,9 @@
};
};
};
+
+   bm-bppi {
+   status = "okay";
+   };
};
 };
diff --git a/arch/arm/boot/dts/armada-xp-gp.dts 
b/arch/arm/boot/dts/armada-xp-gp.dts
index 4878d7353069..a1ded01d0c07 100644
--- a/arch/arm/boot/dts/armada-xp-gp.dts
+++ b/arch/arm/boot/dts/armada-xp-gp.dts
@@ -96,7 +96,8 @@
  MBUS_ID(0x01, 0x1d) 0 0 0xfff0 0x10
  MBUS_ID(0x01, 0x2f) 0 0 0xf000 0x100
  MBUS_ID(0x09, 0x09) 0 0 0xf810 0x1
- MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1>;
+ MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1
+ MBUS_ID(0x0c, 0x04) 0 0 0xf120 0x10>;
 
devbus-bootcs {
status = "okay";
@@ -196,21 +197,29 @@
status = "okay";
phy = <>;
phy-mode = "qsgmii";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <>;
phy-mode = "qsgmii";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
};
ethernet@3 {
status = "okay";
phy = <>;
phy-mode = 

[PATCH v5 net-next 06/10] ARM: dts: armada-xp-openblocks-ax3-4: Add BM support

[Gregory CLEMENT]

Allow Openblock AX3 using hardware buffer management with mvneta.

Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts 
b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
index a5db17782e08..3aa29a91c7b8 100644
--- a/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
+++ b/arch/arm/boot/dts/armada-xp-openblocks-ax3-4.dts
@@ -67,7 +67,8 @@
  MBUS_ID(0x01, 0x1d) 0 0 0xfff0 0x10
  MBUS_ID(0x01, 0x2f) 0 0 0xf000 0x800
  MBUS_ID(0x09, 0x09) 0 0 0xf810 0x1
- MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1>;
+ MBUS_ID(0x09, 0x05) 0 0 0xf811 0x1
+ MBUS_ID(0x0c, 0x04) 0 0 0xd120 0x10>;
 
devbus-bootcs {
status = "okay";
@@ -176,21 +177,29 @@
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <0>;
};
ethernet@74000 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <1>;
};
ethernet@3 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <2>;
};
ethernet@34000 {
status = "okay";
phy = <>;
phy-mode = "sgmii";
+   buffer-manager = <>;
+   bm,pool-long = <3>;
};
i2c@11000 {
status = "okay";
@@ -219,6 +228,14 @@
usb@51000 {
status = "okay";
};
+
+   bm@c {
+   status = "okay";
+   };
+   };
+
+   bm-bppi {
+   status = "okay";
};
};
 };
-- 
2.5.0

[PATCH v5 net-next 04/10] ARM: dts: armada-xp: add buffer manager nodes

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada XP network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-xp.dtsi - for the actual common BM unit (bm@c) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-xp.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/armada-xp.dtsi b/arch/arm/boot/dts/armada-xp.dtsi
index be23196829bb..553349c07f28 100644
--- a/arch/arm/boot/dts/armada-xp.dtsi
+++ b/arch/arm/boot/dts/armada-xp.dtsi
@@ -253,6 +253,14 @@
marvell,crypto-sram-size = <0x800>;
};
 
+   bm: bm@c {
+   compatible = "marvell,armada-380-neta-bm";
+   reg = <0xc 0xac>;
+   clocks = < 13>;
+   internal-mem = <_bppi>;
+   status = "disabled";
+   };
+
xor@f0900 {
compatible = "marvell,orion-xor";
reg = <0xF0900 0x100
@@ -291,6 +299,17 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x05) 0 0x800>;
};
+
+   bm_bppi: bm-bppi {
+   compatible = "mmio-sram";
+   reg = <MBUS_ID(0x0c, 0x04) 0 0x10>;
+   ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < 13>;
+   no-memory-wc;
+   status = "disabled";
+   };
};
 
clocks {
-- 
2.5.0

[PATCH v5 net-next 02/10] ARM: dts: armada-38x: add buffer manager nodes

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

Armada 38x network controller supports hardware buffer management (BM).
Since it is now enabled in mvneta driver, appropriate nodes can be added
to armada-38x.dtsi - for the actual common BM unit (bm@c8000) and its
internal SRAM (bm-bppi), which is used for indirect access to buffer
pointer ring residing in DRAM.

Pools - ports mapping, bm-bppi entry in 'soc' node's ranges and optional
parameters are supposed to be set in board files.

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 arch/arm/boot/dts/armada-38x.dtsi | 19 +++
 1 file changed, 19 insertions(+)

diff --git a/arch/arm/boot/dts/armada-38x.dtsi 
b/arch/arm/boot/dts/armada-38x.dtsi
index e8b7f6726772..066a8f06405c 100644
--- a/arch/arm/boot/dts/armada-38x.dtsi
+++ b/arch/arm/boot/dts/armada-38x.dtsi
@@ -540,6 +540,14 @@
status = "disabled";
};
 
+   bm: bm@c8000 {
+   compatible = "marvell,armada-380-neta-bm";
+   reg = <0xc8000 0xac>;
+   clocks = < 13>;
+   internal-mem = <_bppi>;
+   status = "disabled";
+   };
+
sata@e {
compatible = "marvell,armada-380-ahci";
reg = <0xe 0x2000>;
@@ -618,6 +626,17 @@
#size-cells = <1>;
ranges = <0 MBUS_ID(0x09, 0x15) 0 0x800>;
};
+
+   bm_bppi: bm-bppi {
+   compatible = "mmio-sram";
+   reg = <MBUS_ID(0x0c, 0x04) 0 0x10>;
+   ranges = <0 MBUS_ID(0x0c, 0x04) 0 0x10>;
+   #address-cells = <1>;
+   #size-cells = <1>;
+   clocks = < 13>;
+   no-memory-wc;
+   status = "disabled";
+   };
};
 
clocks {
-- 
2.5.0

[PATCH v5 net-next 07/10] bus: mvebu-mbus: provide api for obtaining IO and DRAM window information

[Gregory CLEMENT]

From: Marcin Wojtas <m...@semihalf.com>

This commit enables finding appropriate mbus window and obtaining its
target id and attribute for given physical address in two separate
routines, both for IO and DRAM windows. This functionality
is needed for Armada XP/38x Network Controller's Buffer Manager and
PnC configuration.

[gregory.clem...@free-electrons.com: Fix size test for
mvebu_mbus_get_dram_win_info]

Signed-off-by: Marcin Wojtas <m...@semihalf.com>
[DRAM window information reference in LKv3.10]
Signed-off-by: Evan Wang <xsw...@marvell.com>
Signed-off-by: Gregory CLEMENT <gregory.clem...@free-electrons.com>
---
 drivers/bus/mvebu-mbus.c | 52 
 include/linux/mbus.h |  3 +++
 2 files changed, 55 insertions(+)

diff --git a/drivers/bus/mvebu-mbus.c b/drivers/bus/mvebu-mbus.c
index c43c3d2baf73..c2e52864bb03 100644
--- a/drivers/bus/mvebu-mbus.c
+++ b/drivers/bus/mvebu-mbus.c
@@ -948,6 +948,58 @@ void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
*res = mbus_state.pcie_io_aperture;
 }
 
+int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr)
+{
+   const struct mbus_dram_target_info *dram;
+   int i;
+
+   /* Get dram info */
+   dram = mv_mbus_dram_info();
+   if (!dram) {
+   pr_err("missing DRAM information\n");
+   return -ENODEV;
+   }
+
+   /* Try to find matching DRAM window for phyaddr */
+   for (i = 0; i < dram->num_cs; i++) {
+   const struct mbus_dram_window *cs = dram->cs + i;
+
+   if (cs->base <= phyaddr &&
+   phyaddr <= (cs->base + cs->size - 1)) {
+   *target = dram->mbus_dram_target_id;
+   *attr = cs->mbus_attr;
+   return 0;
+   }
+   }
+
+   pr_err("invalid dram address 0x%x\n", phyaddr);
+   return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mvebu_mbus_get_dram_win_info);
+
+int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
+  u8 *attr)
+{
+   int win;
+
+   for (win = 0; win < mbus_state.soc->num_wins; win++) {
+   u64 wbase;
+   int enabled;
+
+   mvebu_mbus_read_window(_state, win, , ,
+  size, target, attr, NULL);
+
+   if (!enabled)
+   continue;
+
+   if (wbase <= phyaddr && phyaddr <= wbase + *size)
+   return win;
+   }
+
+   return -EINVAL;
+}
+EXPORT_SYMBOL_GPL(mvebu_mbus_get_io_win_info);
+
 static __init int mvebu_mbus_debugfs_init(void)
 {
struct mvebu_mbus_state *s = _state;
diff --git a/include/linux/mbus.h b/include/linux/mbus.h
index 1f7bc630d225..ea34a867caa0 100644
--- a/include/linux/mbus.h
+++ b/include/linux/mbus.h
@@ -69,6 +69,9 @@ static inline const struct mbus_dram_target_info 
*mv_mbus_dram_info_nooverlap(vo
 int mvebu_mbus_save_cpu_target(u32 *store_addr);
 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
 void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
+int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
+int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
+  u8 *attr);
 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
  unsigned int attribute,
  phys_addr_t base, size_t size,
-- 
2.5.0