MPIC allows the use of private interrupt for each CPUs. The 28th first
interrupts are per-cpu. This patch adds support to use them.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/irq-armada-370-xp.c | 15 +++
1 file changed, 11 insertions
Now that the time-armada-370-xp support local timers, updated the
device tree to take it into account.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm
On 01/25/2013 09:51 AM, Linus Walleij wrote:
On Fri, Jan 25, 2013 at 9:36 AM, Gregory CLEMENT
gregory.clem...@free-electrons.com wrote:
Well, at the beginning I thought adding support for pca9505 was just a matter
of a couple of lines to add. Then I realized that I need to handle the 40
The Armada 370 and Armada XP SoCs don't use the TWD timers, so don't
select it by default if CONFIG_LOCAL_TIMERS is selected
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/Kconfig |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm
Now that the time-armada-370-xp support local timers, updated the
device tree to take it into account.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370-xp.dtsi |5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/arm
MPIC allows the use of private interrupt for each CPUs. The 28th first
interrupts are per-cpu. This patch adds support to use them.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/irq-armada-370-xp.c | 18 +-
1 file changed, 13
.
This patch set is based on 3.8-rc4 and is obviously 3.9 material. The
git branch called local_timer is available at:
https://github.com/MISL-EBU-System-SW/mainline-public.git.
Thanks,
Gregory CLEMENT (6):
arm: mvebu: Add support for local interrupt
clocksource: time-armada-370-xp: add local
On the SOCs Armada 370 and Armada XP, each CPU comes with two private
timers. This patch use the timer 0 of each CPU as local timer for the
clockevent if CONFIG_LOCAL_TIMER is selected. In the other case, use
only the private Timer 0 of CPU 0.
Signed-off-by: Gregory CLEMENT gregory.clem...@free
On 01/08/2013 09:58 AM, Gregory CLEMENT wrote:
On 01/08/2013 09:32 AM, Maxime Ripard wrote:
Hi Gregory,
Hi Maxime,
thanks for testing
On 07/01/2013 23:51, Gregory CLEMENT wrote:
-static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
+static int pca953x_read_single
because
Thomas is currently in on vacations, so I apply this patch and the
first of the series, I built, compiled and tested it on an Aramda XP DB
board. Everything is OK for me.
So for sure you can have my
Tested-by: Gregory CLEMENT gregory.clem...@free-electrons.com
and as the code looks good, so
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio-pca953x.c |2 ++
1 file changed, 2 insertions(+)
diff --git
The Globalscale Mirabox platform can be connected to the JTAG/GPIO box
through the Multi-IO port. The GPIO box use the NXP PCA9505 I/O port
expansion IC to provide 40-bit parallel input/output GPIOs. This patch
enable the use of this expander on the Mirabox.
Signed-off-by: Gregory CLEMENT
part which appeared once I have
enable CONFIG_GPIO_PCA953X_IRQ!
V2-V3:
- Rebased on v3.8-rc4
- Fix the interrupt handler and not try to call an handler if there is
no irq pending on a gpio bank
Gregory CLEMENT (3):
gpio: pca953x: make the register access by GPIO bank
gpio: pca953x: add
variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Tested-by: Maxime
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Expose the DMA operations functions. Until now only the dma_ops
structs in a whole or some dma operation were exposed. This patch
exposes all the dma coherents operations. They can be reused when an
architecture or a driver need to create its own set of dma_operation.
Signed-off-by: Gregory
, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
Acked-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/plat-orion/addr-map.c |4
arch/arm
mvebu_hwcc
- removed the non SMP case during init
- spelling and wording issues
- updating the binding documentation for coherency fabric
Gregory CLEMENT (3):
arm: dma mapping: Export dma ops functions
arm: plat-orion: Add coherency attribute when setup mbus target
arm: mvebu: Add hardware I
struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
---
.../devicetree/bindings/arm/coherency-fabric.txt |9 ++-
arch/arm/boot/dts/armada-370-xp.dtsi
- already exposed arm DMA related functions
- the arm_dma_set_mask which was not exposed yet.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/include/asm/dma-mapping.h |2 ++
arch/arm/mm/dma-mapping.c |4 +---
2 files changed, 3 insertions(+), 3
struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
---
.../devicetree/bindings/arm/coherency-fabric.txt |9 ++-
arch/arm/boot/dts/armada-370-xp.dtsi
, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
Acked-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/plat-orion/addr-map.c |4
arch/arm
functions
- Renamed the function for a more generic name mvebu_hwcc
- removed the non SMP case during init
- spelling and wording issues
- updating the binding documentation for coherency fabric
Gregory CLEMENT (3):
arm: dma mapping: Export a dma ops function arm_dma_set_mask
arm: plat-orion: Add
for coherency fabric
Gregory CLEMENT (3):
arm: dma mapping: Export dma ops functions
arm: plat-orion: Add coherency attribute when setup mbus target
arm: mvebu: Add hardware I/O Coherency support
.../devicetree/bindings/arm/coherency-fabric.txt |9 ++-
arch/arm/boot/dts/armada-370-xp.dtsi
-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/include/asm/dma-mapping.h | 62
arch/arm/mm/dma-mapping.c | 36 +
2 files changed, 70 insertions(+), 28 deletions(-)
diff --git a/arch/arm/include/asm/dma
struct filled during the early initialization of
the platform.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
---
.../devicetree/bindings/arm/coherency-fabric.txt |9 ++-
arch/arm/boot/dts/armada-370-xp.dtsi
, in other case transaction is driven
directly to DRAM.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Yehuda Yitschak yehu...@marvell.com
Acked-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
arch/arm/plat-orion/addr-map.c |4
arch/arm
Hi Andrew,
With this 2 patches I added clock gating support for Armada 370 and
Armada XP. I compiled and tested on the boards, and managed to see the
new clock using debugfs.
Feel free to squash them in your series if you want.
Regards,
Gregory CLEMENT (2):
clk: mvebu: armada 370/XP add
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../bindings/clock/mvebu-gated-clock.txt | 43 ++
arch/arm/mach-mvebu/Kconfig|1 +
drivers/clk/mvebu/clk-gating-ctrl.c| 61
3 files
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/dts/armada-370.dtsi |8
arch/arm/boot/dts/armada-xp.dtsi |7 +++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/armada-370.dtsi
b/arch/arm/boot/dts/armada-370.dtsi
index
Hi Andrew
On 11/17/2012 09:26 AM, Andrew Lunn wrote:
Hi Gregory
Nice work
Thanks!
On Fri, Nov 16, 2012 at 07:01:59PM +0100, Gregory CLEMENT wrote:
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
.../bindings/clock/mvebu-gated-clock.txt | 43
On 11/19/2012 04:12 AM, Jason Cooper wrote:
On Fri, Nov 16, 2012 at 10:46:15PM +0100, Gregory CLEMENT wrote:
On 11/14/2012 11:31 PM, Gregory CLEMENT wrote:
Hello Russell,
With the 2 changes I have done on according your comments
do you think you can give your acked-by for this patch
Dear Cong Ding,
On 01/14/2013 06:18 PM, Cong Ding wrote:
the variable cpuclk and clk_name should be properly freed.
Thanks for reporting this memory leak and for your patch but I think
we could do even better, see below:
Signed-off-by: Cong Ding ding...@gmail.com
---
...@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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On 01/15/2013 07:26 PM, Cong Ding wrote:
On Tue, Jan 15, 2013 at 05:33:57PM +0100, Gregory CLEMENT wrote:
On 01/15/2013 04:37 PM, Jason Cooper wrote:
Mike,
On Tue, Jan 15, 2013 at 03:23:08PM +, Cong Ding wrote:
From 75c73077905b822be6e8a32a09d6b0cdb5e61763 Mon Sep 17 00:00:00 2001
From
On 01/15/2013 07:44 PM, Cong Ding wrote:
the variable cpuclk and clk_name should be properly freed when error happens.
Dear Cong Ding,
Thanks for you efforts!
I am happy with this patch and I tested it on the Armada XP DB board, so
you can now add my:
Acked-by: Gregory CLEMENT gregory.clem
it will have a conflict here. Currently my patch set is
based on v3.8-rc2, but I am willing to rebase onto gpio-for-next once
the GPIO block will be merged into it.
I also expected some tested-by as I was only able to test the pca9505
and I didn't test the IRQ part.
Thanks!
Gregory CLEMENT (3):
gpio
variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio
The Globalscale Mirabox platform can be connected to the JTAG/GPIO box
through the Multi-IO port. The GPIO box use the NXP PCA9505 I/O port
expansion IC to provide 40-bit parallel input/output GPIOs. This patch
enable the use of this expander on the Mirabox.
Signed-off-by: Gregory CLEMENT
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio-pca953x.c |2 ++
1 file changed, 2 insertions(+)
diff --git
On 01/06/2013 06:34 PM, Gregory CLEMENT wrote:
Hello,
This patch set adds the support for the i2c gpio expander pca9505 used
on the JTAG/GPIO box which can be connected to the Mirabox.
To be able to use the pca9505 I had to do several changes in the
driver. Indeed, until now the pca953x
variables. This fits exactly the way the
registers are represented in the hardware.
It also adds helpers to access to a single register of a bank instead
of reading or writing all the banks for a given register.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio
The Globalscale Mirabox platform can be connected to the JTAG/GPIO box
through the Multi-IO port. The GPIO box use the NXP PCA9505 I/O port
expansion IC to provide 40-bit parallel input/output GPIOs. This patch
enable the use of this expander on the Mirabox.
Signed-off-by: Gregory CLEMENT
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/gpio/gpio-pca953x.c |2 ++
1 file changed, 2 insertions(+)
diff --git
to calculate the shift used to apply to register to
access a given bank.
- Fix all the pending issue in the IRQ part which appeared once I have
enable CONFIG_GPIO_PCA953X_IRQ!
Gregory CLEMENT (3):
gpio: pca953x: make the register access by GPIO bank
gpio: pca953x: add support for pca9505
arm
On 01/08/2013 09:32 AM, Maxime Ripard wrote:
Hi Gregory,
Hi Maxime,
thanks for testing
On 07/01/2013 23:51, Gregory CLEMENT wrote:
-static int pca953x_write_reg(struct pca953x_chip *chip, int reg, u32 val)
+static int pca953x_read_single(struct pca953x_chip *chip, int reg, u32 *val
On 01/10/2013 12:15 PM, Linus Walleij wrote:
On Sun, Jan 6, 2013 at 6:34 PM, Gregory CLEMENT
gregory.clem...@free-electrons.com wrote:
Now that pca953x driver can handle GPIO expanders with more than 32
bits this patch adds the support for the pca9505 which cam with 40
GPIOs.
Signed-off
.
Cc: Gregory Clement gregory.clem...@free-electrons.com
Cc: Andrew Lunn and...@lunn.ch
Cc: Jason Cooper ja...@lakedaemon.net
Signed-off-by: Sudeep KarkadaNagesha sudeep.karkadanage...@arm.com
Hi Gregory/Andrew/Jason,
Does this change look fine for mvebu?
If yes, can I have your ACKs
On 19/07/2013 01:21, Stephen Boyd wrote:
The 32 bit sched_clock interface now supports 64 bits. Upgrade to
the 64 bit function to allow us to remove the 32 bit registration
interface.
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Cc: Gregory CLEMENT gregory.clem...@free
On 07/08/2013 03:33, Stepan Moskovchenko wrote:
Update the reg property of the memory node in
skeleton64.dtsi to reflect the fact that the root node uses
address-cells=2 and size-cells=2.
Good catch
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Change-Id
...@gmail.com
---
Notes:
- coherency, mbus, and cache init are moved to .init_machine hook
- time-armada-370-xp is converted to clocksource_of_init compatible init
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd Bergmann a...@arndb.de
Cc: Gregory Clement gregory.clem...@free-electrons.com
On 23/08/2013 12:32, Sebastian Hesselbarth wrote:
On 08/23/13 12:06, Gregory CLEMENT wrote:
On 20/08/2013 04:04, Sebastian Hesselbarth wrote:
With arch/arm calling of_clk_init(NULL) from time_init(), we can now
remove custom .init_time hooks.
As a feared it won't work on Armada XP. You moved
On 23/08/2013 14:13, Sebastian Hesselbarth wrote:
On 08/23/13 13:39, Gregory CLEMENT wrote:
On 23/08/2013 12:32, Sebastian Hesselbarth wrote:
On 08/23/13 12:06, Gregory CLEMENT wrote:
On 20/08/2013 04:04, Sebastian Hesselbarth wrote:
With arch/arm calling of_clk_init(NULL) from time_init
On 23/08/2013 16:23, Gregory CLEMENT wrote:
On 23/08/2013 14:13, Sebastian Hesselbarth wrote:
On 08/23/13 13:39, Gregory CLEMENT wrote:
On 23/08/2013 12:32, Sebastian Hesselbarth wrote:
On 08/23/13 12:06, Gregory CLEMENT wrote:
On 20/08/2013 04:04, Sebastian Hesselbarth wrote:
With arch/arm
Hesselbarth sebastian.hesselba...@gmail.com
---
Changelog:
v1-v2:
- only remove of_clk_init from custom timer hook, further cleanup
will be carried out later (Reported by Gregory Clement)
Cc: Gregory Clement gregory.clem...@free-electrons.com
Cc: Russell King li...@arm.linux.org.uk
Cc: Arnd
On 07/11/2013 09:59, Jisheng Zhang wrote:
This symbol is used only in this file. The patch fix the following
sparse warning:
warning: symbol 'of_cpu_clk_setup' was not declared. Should it be static?
Signed-off-by: Jisheng Zhang jszh...@marvell.com
Acked-by: Gregory CLEMENT gregory.clem
-by: Jisheng Zhang jszh...@marvell.com
There will be some conflicts with my CPU Idle series. I will see how to handle
it with Jason.As all these change are fine:
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Thanks,
Gregory
---
arch/arm/mach-mvebu/coherency.c | 1
On 07/11/2013 04:08, Jisheng Zhang wrote:
Add of_node_put to properly decrement the refcount when we are
done using a given node.
Signed-off-by: Jisheng Zhang jszh...@marvell.com
Reviewed-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
Seems ok for me too
Acked-by: Gregory CLEMENT
On 07/11/2013 04:08, Jisheng Zhang wrote:
Add of_node_put to properly decrement the refcount when we are
done using a given node.
Signed-off-by: Jisheng Zhang jszh...@marvell.com
Reviewed-by: Ezequiel Garcia ezequiel.gar...@free-electrons.com
Acked-by: Gregory CLEMENT gregory.clem...@free
...@free-electrons.com
Acked-by: Jason Cooper ja...@lakedaemon.net
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Thanks,
Gregory
---
drivers/pinctrl/mvebu/pinctrl-mvebu.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/mvebu
Hi Thomas,
On 07/03/2014 18:17, Thomas Gleixner wrote:
On Fri, 7 Mar 2014, Gregory CLEMENT wrote:
On 06/03/2014 20:05, Jason Cooper wrote:
Thomas,
nit: s/armanda/armada/ in the patch subject.
Gregory,
Mind providing an Ack on this?
Well sorry but with this patch the kernel doesn't
Hi Tomasz,
On 23/02/2014 19:46, Tomasz Figa wrote:
Hi Gregory,
On 10.02.2014 18:42, Gregory CLEMENT wrote:
Until now the clock providers were initialized in the order found in
the device tree. This led to have the dependencies between the clocks
not respected: children clocks could
BREZILLON
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Signed-off-by: Boris BREZILLON b.brezil...@overkiz.com
---
Mike,
This patch depend on the patch clk: return probe defer when DT clock
not yet ready: http://article.gmane.org/gmane.linux.kernel/1643466
If for any reason
.
I got this issue in the driver drivers/i2c/busses/i2c-mv64xxx.c.
Thanks,
Gregory
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Hi Mike,
On 24/02/2014 19:10, Gregory CLEMENT wrote:
Until now the clock providers were initialized in the order found in
the device tree. This led to have the dependencies between the clocks
not respected: children clocks could be initialized before their
parent clocks.
Instead of forcing
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix a regression during gadget driver
unbinding, it was no more always true. This lead to a kernel crash.
This commit now use the
On 28/02/2014 16:50, Alexandre Belloni wrote:
Hi Gregory,
On 28/02/2014 at 15:34:01 +0100, Gregory CLEMENT wrote :
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix
On 03/03/2014 17:33, Felipe Balbi wrote:
On Fri, Feb 28, 2014 at 03:34:01PM +0100, Gregory CLEMENT wrote:
The debug trace in the atmel_usba_stop function made the assumption
that the driver pointer passed in parameter was not NULL. Since the
commit usb: gadget: udc-core: fix a regression
: sta...@vger.kernel.org # v3.2+
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
Changelog:
v1 - v2
Fixed the signature block in the commit log
drivers/usb/gadget/atmel_usba_udc.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/gadget
-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
Hi,
I have received this board only recently, so that why its device tree
comes only now. This patch should not cause any trouble to other part
of the kernel, so that's why I think it is reasonable to have it in
3.15.
Thanks,
Gregory
Hi Andrew,
On 06/03/2014 14:14, Andrew Lunn wrote:
On Thu, Mar 06, 2014 at 01:11:08PM +0100, Gregory CLEMENT wrote:
The Armada 385 RD board is the reference design board from Marvell
for the Armada 385 SoC. This commit adds a Device Tree description for
this board, which enables the following
;
};
eth1: ethernet@3 {
}
eth2: ethernet@34000 {
}
eth0: ethernet@7 {
}
Thanks,
Gregory
Andrew
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Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http
I did, didn't work as I expected. The order should have been
changed in
the dsi file.
I will have a look on the ethernet driver.
Thanks,
Gregory
Andrew
--
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Kernel, drivers, real-time and embedded Linux
development, consulting, training and support
-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
Changelog:
v1 - v2:
- used the phy-mode rgmii-id to be able to work with the Marvell PHY
driver enabled
- put the ethernet nodes in the address order, as it has no effect to
change ti at this level (should be done at dtsi level
On 06/03/2014 15:51, Gregory CLEMENT wrote:
On 06/03/2014 15:46, Andrew Lunn wrote:
I think you can use aliases to get the order correct, independent of
how you list them in DT. That should be a lot safer than assuming
things are instantiated from top to bottom.
It sounds interesting, how
this in the dtsi.
Thanks,
Gregory
Right, makes perfect sense!
So we can just keep the nodes address-ordered, without caring about the name?
--
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Kernel, drivers, real-time and embedded Linux
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Cc: Gregory CLEMENT gregory.clem...@free-electrons.com
Cc: Jason Cooper ja...@lakedaemon.net
---
drivers/irqchip/irq-armada-370-xp.c | 38
1 file changed, 5 insertions(+), 33 deletions(-)
Index: tip/drivers/irqchip/irq-armada-370-xp.c
will be in v3.14, so maybe we
can spend some time considering a cleaner option.
Or is this just rubbish?
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Petazzoni wrote:
Hello,
On Mon, 10 Feb 2014 18:42:59 +0100, Gregory CLEMENT wrote:
Until now the clock providers were initialized in the order found in
the device tree. This led to have the dependencies between the clocks
not respected: children clocks could be initialized before their
parent
as parent tclk will be used.
I hope this example will show you, what I disagree with this proposal and why it
introduce some regression.
Regards,
Gregory
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Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free
On 17/02/2014 16:21, Ezequiel Garcia wrote:
On Mon, Feb 17, 2014 at 03:25:22PM +0100, Gregory CLEMENT wrote:
On 17/02/2014 15:13, Ezequiel Garcia wrote:
On Wed, Feb 05, 2014 at 01:34:57PM -0500, Jason Cooper wrote:
On Sat, Jan 25, 2014 at 07:19:06PM +0100, Sebastian Hesselbarth wrote
On 17/02/2014 16:44, Ezequiel Garcia wrote:
On Mon, Feb 17, 2014 at 04:28:41PM +0100, Gregory CLEMENT wrote:
On 17/02/2014 16:21, Ezequiel Garcia wrote:
On Mon, Feb 17, 2014 at 03:25:22PM +0100, Gregory CLEMENT wrote:
On 17/02/2014 15:13, Ezequiel Garcia wrote:
On Wed, Feb 05, 2014 at 01:34
On 17/02/2014 19:19, Ezequiel Garcia wrote:
On Mon, Feb 17, 2014 at 04:59:01PM +0100, Gregory CLEMENT wrote:
[..]
Right. If you think it adds a regression, then that's a perfectly valid
reasons
for nacking.
However, I'd like to double-check we have such a regression. I guess you're
the SoC ID of a board without any PCI device and
then without the PCI core support.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
drivers/of/Kconfig | 4
drivers/of/address.c | 8 +---
2 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/drivers/of/Kconfig
available even without the
PCI support. It should go to the mvebu tree.
Thanks,
Gregory CLEMENT (2):
of: Allows to use the PCI translator without the PCI core
ARM: mvebu: Allows to get the SoC ID even without PCI enabled
arch/arm/mach-mvebu/Kconfig | 1 +
drivers/of/Kconfig | 4
platforms.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/mach-mvebu/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 5e269d7263ce..df9e7d270810 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
arch/arm/boot/compressed/atags_to_fdt.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/compressed/atags_to_fdt.c
b/arch/arm/boot/compressed/atags_to_fdt.c
index d1153c8..75b64da 100644
for 3.15 if possible.
Thanks,
Gregory
Gregory CLEMENT (4):
clk: mvebu: add clock support for Armada 375
dt: Update binding information for mvebu core clocks with Armada 375
dt: Update binding information for mvebu gating clocks with Armada 375
clk: mvebu: add clock support for Armada 380/385
Add the binding information for the gating clocks of the Armada 375 SoCs
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
.../bindings/clock/mvebu-gated-clock.txt | 31 +-
1 file
Add the clock support for the new SoCs Armada 380 and Armada 385:
core clocks and gating clocks.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Add the binding information for the core clocks of the Armada 380 and
Armada 385 SoCs
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Add the binding information for the core clocks of the Armada 375 SoCs
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
Documentation/devicetree/bindings/clock/mvebu-core-clock.txt | 7 +++
1 file changed
From: Thomas Petazzoni thomas.petazz...@free-electrons.com
Add the binding information for the gating clocks of the Armada 380
SoCs and the Armada 385 SoCs.
Signed-off-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Add the clock support for the new SoC Armada 375: core clocks and
gating clocks.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Reviewed-by: Thomas Petazzoni thomas.petazz...@free-electrons.com
---
drivers/clk/mvebu/Kconfig | 4 +
drivers/clk/mvebu/Makefile | 1
BREZILLON
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
Since the v1, I have merged the strict dependency check from Boris.
And of course tested on my Armada 370 and Armada XP based board
drivers/clk/clk.c | 109 --
1
,
.data = (void *) bar_controller,
},
[...]
This test is very paranoid, so I agree to remove it.
Acked-by: Gregory CLEMENT gregory.clem...@free-electrons.com
Thanks,
Gregory
Thomas
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development
();
at91_dt_ramc();
at91_dt_shdwc();
+ at91_dt_matrix();
/* Init clock subsystem */
at91_dt_clock_init();
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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arch/arm/boot/dts/at91sam9261.dtsi
create mode 100644 arch/arm/boot/dts/at91sam9261ek.dts
--
Gregory Clement, Free Electrons
Kernel, drivers, real-time and embedded Linux
development, consulting, training and support.
http://free-electrons.com
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On 18/03/2014 21:55, Thomas Gleixner wrote:
On Tue, 18 Mar 2014, Gregory CLEMENT wrote:
On 07/03/2014 18:17, Thomas Gleixner wrote:
It might be the readback of the routing register. I don't have the
datasheet of this.
Sorry for the delay, I was on vacation without the hardware to test
are bigger for Armada XP and for this SoCs we add a new flag
for the i2c-bridge capability.
The Device Tree binding documentation is updated accordingly.
Signed-off-by: Gregory CLEMENT gregory.clem...@free-electrons.com
---
Documentation/devicetree/bindings/i2c/i2c-mv64xxx.txt | 6 ++
arch/arm/boot
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