: address the same as Signed-off-by address.
V3:
1, Send to Alex Deucher since this is radeon specific;
2, Add Reviewed-by email addresses.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Reviewed-by: Michel Dänzer
, Fix a #ifdef issue in dma-coherence.h.
9, Some other small fixes.
V6 - V7:
1, Fix boot failure when NR_CPUS is more than present cpus.
2, Fix error messages after poweroff reboot.
3, Update the default config file.
4, Sync the code to upstream.
Huacai Chen(15):
MIPS: Loongson: Add basic Loongson
(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include
Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/kernel/Makefile|1 +
arch/mips/kernel/cpu-probe.c | 14
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.
The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.
Signed-off-by: Huacai
Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.
With UEFI-like firmware interface, We don't need fixup for PCI irq
routing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta
controller.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++
arch/mips/include/asm/mach-loongson/loongson.h |9 +++
arch/mips/loongson/Makefile
of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in Local Bus, both CPU UART and LPC UART
are called CPU provided serial port.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed
a
platform-specific dma_map_ops::set_dma_mask() to make sure each
driver's dma_mask and coherent_dma_mask is below 32-bit.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/dma-mapping.h
Added Kconfig options include: Loongson-3 CPU and machine definition,
CPU cache features, UEFI-like firmware interface, HT-linked PCI, and
big memory support.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_vm.c |2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c |2 +-
2 files changed, 2 insertions(+), 2
-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/loongson/common/init.c |5 +
arch/mips/loongson/common/setup.c |8 +-
arch/mips/loongson/loongson-3/Makefile |2 +
arch/mips/loongson
(both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed-off-by: Huacai
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/configs/loongson3_defconfig | 317 +
1 files changed, 317 insertions(+), 0 deletions(-)
create mode 100644 arch/mips
-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: alsa-de...@alsa-project.org
---
sound/pci/hda/patch_conexant.c | 44
1 files changed, 44 insertions(+), 0 deletions(-)
diff
/2F series.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/boot_param.h | 151 ++
arch/mips/include/asm/mach-loongson/loongson.h |4 +-
arch/mips
] [8072b598] take_cpu_down+0x5c/0x70
[ 83.066406] [80299ba4] stop_machine_cpu_stop+0x104/0x1e8
[ 83.066406] [802997cc] cpu_stopper_thread+0x110/0x1ac
[ 83.066406] [8024c940] kthread+0x88/0x90
[ 83.066406] [80205ee4] kernel_thread_helper+0x10/0x18
Signed-off-by: Huacai
On Mon, Oct 8, 2012 at 4:22 PM, Takashi Iwai ti...@suse.de wrote:
At Fri, 5 Oct 2012 21:25:09 +0800,
Huacai Chen wrote:
Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
this patch modify patch_conexant.c to add Lemote specific code.
Both A1004 and A1205 use the same pin
since it is already in upstream code.
6, Use LZMA compression and do some adjustment of config file to reduce
kernel size.
Huacai Chen(13):
MIPS: Loongson: Add basic Loongson-3 definition.
MIPS: Loongson: Add basic Loongson-3 CPU support.
MIPS: Loongson: Introduce and use
(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include
Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/kernel/cpu-probe.c | 14 +++---
arch/mips/mm/c-r4k.c | 62
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.
The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.
Signed-off-by: Huacai
/2F series.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/boot_param.h | 151 ++
arch/mips/include/asm/mach-loongson/loongson.h |4 +-
arch/mips
Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.
With UEFI-like firmware interface, We don't need fixup for PCI irq
routing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta
controller.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++
arch/mips/include/asm/mach-loongson/loongson.h |9 +++
arch/mips/loongson/Makefile
of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in Local Bus, both CPU UART and LPC UART
are called CPU provided serial port.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed
a
platform-specific dma_map_ops::set_dma_mask() to make sure each
driver's dma_mask and coherent_dma_mask is below 32-bit.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/dma-mapping.h
Added Kconfig options include: Loongson-3 CPU and machine definition,
CPU cache features, UEFI-like firmware interface, HT-linked PCI, and
big memory support.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/loongson/common/init.c |5 +
arch/mips/loongson/common/setup.c |8 +-
arch/mips/loongson/loongson-3/Makefile |2 +
arch/mips/loongson
(both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed-off-by: Huacai
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/configs/loongson3_defconfig | 328 +
1 files changed, 328 insertions(+), 0 deletions(-)
create mode 100644 arch/mips
. This patch call
syscore_shutdown() a little later (after disable_nonboot_cpus()) to
avoid reboot failure, this is the same way as poweroff does.
BTW, add disable_nonboot_cpus() in kernel_halt() for consistency.
Signed-off-by: Huacai Chen che...@lemote.com
Cc: sta...@vger.kernel.org
---
kernel
. This patch call
syscore_shutdown() a little later (after disable_nonboot_cpus()) to
avoid reboot failure.
Signed-off-by: Huacai Chen che...@lemote.com
Cc: sta...@vger.kernel.org
---
kernel/sys.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/kernel/sys.c b/kernel/sys.c
it in cpu_cache_init()).
For similar reasons we modify build_tlb_refill_handler()'s invocation.
V2:
1, Rework the code to make CPU#0 can be online/offline.
2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU
need a per-CPU tlb_refill_handler().
Signed-off-by: Huacai Chen che
on CPU#1, memory corruption (e.g.
segfault, bus error, etc.) will occur.
Signed-off-by: Huacai Chen che...@lemote.com
---
arch/mips/include/asm/mmu_context.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/mips/include/asm/mmu_context.h
b/arch/mips/include/asm
On Thu, Mar 21, 2013 at 11:53 PM, David Daney ddaney.c...@gmail.com wrote:
On 03/20/2013 04:14 PM, David Daney wrote:
On 03/17/2013 05:49 AM, Huacai Chen wrote:
This and the next patch resolve memory corruption problems while CPU
hotplug. Without these patches, memory corruption can
.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongbing Hu h...@lemote.com
---
arch/mips/mm/c-octeon.c|6 --
arch/mips/mm/c-r3k.c |6 --
arch/mips/mm/c-r4k.c |6 --
arch/mips/mm/c-tx39.c |6 --
arch/mips/mm/tlb-r3k.c
OK, I'm reworking...
On Tue, Mar 5, 2013 at 2:39 AM, David Daney ddaney.c...@gmail.com wrote:
On 03/04/2013 04:56 AM, Huacai Chen wrote:
Currently, clear_page()/copy_page() are generated by Micro-assembler
dynamically. But they are unavailable until uasm_resolve_relocs() has
finished because
:
1, Rework the code to make CPU#0 can be online/offline.
2, Introduce cpu_has_local_ebase feature since some types of MIPS CPU
need a per-CPU tlb_refill_handler().
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongbing Hu h...@lemote.com
---
arch/mips/include/asm/cpu-features.h
I'm sorry, this is the only patch, please ignore [01/14].
On Mon, Mar 4, 2013 at 8:56 PM, Huacai Chen che...@lemote.com wrote:
Currently, clear_page()/copy_page() are generated by Micro-assembler
dynamically. But they are unavailable until uasm_resolve_relocs() has
finished because jump labels
I'm sorry, this is the only patch, please ignore [01/14].
On Tue, Mar 5, 2013 at 12:37 PM, Huacai Chen che...@lemote.com wrote:
Currently, clear_page()/copy_page() are generated by Micro-assembler
dynamically. But they are unavailable until uasm_resolve_relocs() has
finished because jump
-loongson3.c.
4, Update the default config file.
5, Sync the code to upstream.
Huacai Chen(13):
MIPS: Loongson: Add basic Loongson-3 definition.
MIPS: Loongson: Add basic Loongson-3 CPU support.
MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature.
MIPS: Loongson 3: Add Lemote-3A machtypes
(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include
Basic Loongson-3 CPU support include CPU probing and TLB/cache
initializing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/kernel/cpu-probe.c | 14 +++---
arch/mips/mm/c-r4k.c | 62
Loongson-3 maintains cache coherency by hardware. So we introduce a cpu
feature named cpu_has_coherent_cache and use it to modify MIPS's cache
flushing functions.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.
The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.
Signed-off-by: Huacai
/2F series.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/boot_param.h | 151 ++
arch/mips/include/asm/mach-loongson/loongson.h |4 +-
arch/mips
controller.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++
arch/mips/include/asm/mach-loongson/loongson.h |9 +++
arch/mips/loongson/Makefile
of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in Local Bus, both CPU UART and LPC UART
are called CPU provided serial port.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed
a
platform-specific dma_map_ops::set_dma_mask() to make sure each
driver's dma_mask and coherent_dma_mask is below 32-bit.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/dma-mapping.h
Added Kconfig options include: Loongson-3 CPU and machine definition,
CPU cache features, UEFI-like firmware interface, HT-linked PCI, and
big memory support.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/loongson/common/init.c |5 +
arch/mips/loongson/common/setup.c |8 +-
arch/mips/loongson/loongson-3/Makefile |2 +
arch/mips/loongson
Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.
With UEFI-like firmware interface, We don't need fixup for PCI irq
routing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta
(both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed-off-by: Huacai
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/configs/loongson3_defconfig | 330 +
1 files changed, 330 insertions(+), 0 deletions(-)
create mode 100644 arch/mips
schrieb Huacai Chen:
When SWIOTLB is configured, if without this patch kernel compilation
fails.
Secondly, could you please always paste part of the error message into
the commit message so that people hitting this problem and searching for
it on the WWW have a higher chance finding your patch
On Mon, Aug 13, 2012 at 3:50 PM, Paul Menzel
paulepan...@users.sourceforge.net wrote:
Dear Huacai,
Am Montag, den 13.08.2012, 15:16 +0800 schrieb Huacai Chen:
On Mon, Aug 13, 2012 at 3:00 PM, Paul Menzel wrote:
thanks for your patch.
Firstly, is Chen your first or last name
OK, I will improve the code.
On Mon, Aug 13, 2012 at 4:00 PM, Takashi Iwai ti...@suse.de wrote:
At Sat, 11 Aug 2012 17:32:19 +0800,
Huacai Chen wrote:
Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
this patch modify patch_conexant.c to add Lemote specific code.
Signed
: address the same as Signed-off-by address.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/radeon/radeon_ttm.c |4
1 files changed, 4 insertions(+), 0
disable_nonboot_cpus() hangs. Therefore, we make this patch to avoid
poweroff failure.
V2:
Make the From: address the same as Signed-off-by address.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: Yong Zhang yong.zh
Most of the code are copied from arch/mips/cavium-octeon/dma-octeon.c
and they work well.
Anyway, I'll try your suggestions, thank you.
On Tue, Aug 14, 2012 at 1:54 AM, Konrad Rzeszutek Wilk
konrad.w...@oracle.com wrote:
+static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
Hi, David,
Seems like you are the original author of code in
arch/mips/cavium-octeon/dma-octeon.c. Could you please tell me why we
need mb() in alloc_coherent(), map_page(), map_sg()? It seems like
because of cache coherency (CPU write some data, then map the page for
a device, if without mb(),
On Tue, Aug 14, 2012 at 7:48 PM, Ralf Baechle r...@linux-mips.org wrote:
On Mon, Aug 13, 2012 at 08:52:24PM +0800, Huacai Chen wrote:
When poweroff machine, kernel_power_off() call disable_nonboot_cpus().
And if we have HOTPLUG_CPU configured, disable_nonboot_cpus() is not an
empty function
On Tue, Aug 14, 2012 at 1:54 AM, Konrad Rzeszutek Wilk
konrad.w...@oracle.com wrote:
+static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp, struct
dma_attrs *attrs)
+{
+ void *ret;
+
+ if
On Thu, Aug 16, 2012 at 5:31 AM, Ralf Baechle r...@linux-mips.org wrote:
On Sat, Aug 11, 2012 at 05:32:18PM +0800, Huacai Chen wrote:
Subject: [PATCH V5 13/18] drm: Define SAREA_MAX for Loongson (PageSize =
16KB).
But your code doesn't define it just for Loongsson as the log message claims
On Thu, Aug 16, 2012 at 4:24 AM, Ralf Baechle r...@linux-mips.org wrote:
On Mon, Aug 13, 2012 at 01:54:47PM -0400, Konrad Rzeszutek Wilk wrote:
+static void *loongson_dma_alloc_coherent(struct device *dev, size_t size,
+ dma_addr_t *dma_handle, gfp_t gfp, struct
On Thu, Aug 16, 2012 at 9:58 AM, Matt Turner matts...@gmail.com wrote:
On Sat, Aug 11, 2012 at 2:32 AM, Huacai Chen chenhua...@gmail.com wrote:
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de
On Tue, Aug 14, 2012 at 7:48 PM, Ralf Baechle r...@linux-mips.org wrote:
On Mon, Aug 13, 2012 at 08:52:24PM +0800, Huacai Chen wrote:
When poweroff machine, kernel_power_off() call disable_nonboot_cpus().
And if we have HOTPLUG_CPU configured, disable_nonboot_cpus() is not an
empty function
to replace old alsa quirks.
Huacai Chen(18):
MIPS: Loongson: Add basic Loongson-3 definition.
MIPS: Loongson: Add basic Loongson-3 CPU support.
MIPS: Loongson 3: Add Lemote-3A machtypes definition.
MIPS: Loongson: Make Loongson-3 to use BCD format for RTC.
MIPS: Loongson: Add UEFI-like
-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include
of UARTs:
CPU UART: REG_BASE + OFFSET;
LPC UART: LIO1_BASE + OFFSET;
PCI UART: PCIIO_BASE + OFFSET.
Since LPC UART are linked in Local Bus, both CPU UART and LPC UART
are called CPU provided serial port.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed
Basic Loongson-3 CPU support include: CPU probing, TLB and cache
initializing, cache flushing method, etc.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/kernel/Makefile|1 +
arch/mips/kernel
a
platform-specific dma_map_ops::set_dma_mask() to make sure each
driver's dma_mask and coherent_dma_mask is below 32-bit.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/dma-mapping.h
Added Kconfig options include: Loongson-3 CPU and machine definition,
UEFI-like firmware interface, HT-linked PCI, big memory support, etc.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/Kconfig
Loongson has SWIOTLB configured, if without this patch kernel
compilation fails.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/radeon/radeon_ttm.c |4
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/drm_vm.c |2 +-
drivers/gpu/drm/ttm/ttm_bo_util.c |2 +-
2 files changed, 2 insertions(+), 2
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
---
include/drm/drm_sarea.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/include/drm/drm_sarea.h b
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/configs/loongson3_defconfig | 283 +
1 files changed, 283 insertions(+), 0 deletions(-)
create mode 100644 arch/mips
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/mc146818rtc.h |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/arch/mips/include/asm/mach-loongson
/2F series.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/boot_param.h | 151 ++
arch/mips/include/asm/mach-loongson/loongson.h |4 +-
arch/mips
Loongson family machines use Hyper-Transport bus for inter-core
connection and device connection. The PCI bus is a subordinate
linked at HT1.
With UEFI-like firmware interface, We don't need fixup for PCI irq
routing.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta
controller.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++
arch/mips/include/asm/mach-loongson/loongson.h |9 +++
arch/mips/loongson/Makefile
disable_nonboot_cpus() hangs. Therefore, we make this patch to avoid
poweroff failure.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: sta...@vger.kernel.org
---
arch/mips/kernel/process.c |4 +---
1 files changed, 1
(both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed-off-by: Huacai
Add four Loongson-3 based machine types:
MACH_LEMOTE_A1004/MACH_LEMOTE_A1201 are laptops;
MACH_LEMOTE_A1101 is mini-itx;
MACH_LEMOTE_A1205 is all-in-one machine.
The most significant differrent between A1004/A1201 and A1101/A1205 is
the laptops have EC but others don't.
Signed-off-by: Huacai
-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/loongson/common/init.c |5 +
arch/mips/loongson/common/setup.c |8 +-
arch/mips/loongson/loongson-3/Makefile |2 +
arch/mips/loongson
Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
this patch modify patch_conexant.c to add Lemote specific code.
Signed-off-by: Jie Chen ch...@lemote.com
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y
-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include
Sorry, this is sent by mistake, please ignore it.
On Mon, Aug 13, 2012 at 10:04 AM, Huacai Chen chenhua...@gmail.com wrote:
Loongson-3 is a multi-core MIPS family CPU, it support MIPS64R2
fully. Loongson-3 has the same IMP field (0x6300) as Loongson-2.
Loongson-3 has a hardware-maintained
disable_nonboot_cpus() hangs. Therefore, we make this patch to avoid
poweroff failure.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: Yong Zhang yong.zh...@windriver.com
Cc: sta...@vger.kernel.org
---
arch/mips/kernel
When SWIOTLB is configured, if without this patch kernel compilation
fails.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
---
drivers/gpu/drm/radeon/radeon_ttm.c |4
1
version of Loongson
patches will not modify radeon_ttm.c.
On Fri, Jun 22, 2012 at 1:59 PM, Huacai Chen chenhua...@gmail.com wrote:
On Fri, Jun 22, 2012 at 1:25 PM, Lucas Stach d...@lynxeye.de wrote:
Hello Huacai,
Am Freitag, den 22.06.2012, 11:01 +0800 schrieb Huacai Chen:
1, Handle io prot
-3A(including so-called Loongson-2Gq), they are
64-bit multi-core MIPS CPUs.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/addrspace.h|6 ++
arch/mips/include
controller.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/mach-loongson/irq.h | 24 +++
arch/mips/include/asm/mach-loongson/loongson.h |9 +++
arch/mips/loongson/Makefile
a
platform-specific dma_map_ops::set_dma_mask() to make sure each
driver's dma_mask and coherent_dma_mask is below 32-bit.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
---
arch/mips/include/asm/dma-mapping.h
1, Handle io prot correctly for MIPS.
2, Define SAREA_MAX as the size of one page.
3, Include swiotlb.h if SWIOTLB configured.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: dri-de...@lists.freedesktop.org
Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
this patch modify patch_conexant.c to add Lemote specific code.
Signed-off-by: Huacai Chen che...@lemote.com
Signed-off-by: Hongliang Tao ta...@lemote.com
Signed-off-by: Hua Yan y...@lemote.com
Cc: alsa-de...@alsa-project.org
(both uncached and
unmmaped).
2, The default clocksource of Loongson is MIPS. Since clock source is a
global device, timekeeping need the CP0' Count registers of each core
be synchronous. Thus, when a core is up, we use a SMP_ASK_C0COUNT IPI
to ask Core-0's Count.
Signed-off-by: Huacai
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