[PATCH v6 01/13] dt-bindings: add binding for the Allwinner DE2 CCU

Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring

[PATCH v6 09/13] drm/sun4i: Add compatible string for V3s display engine

Allwinner V3s features the new "Display Engine 2.0", which can now also be driven with our subdrivers in sun4i-drm. Add the compatible string for in sun4i_drv.c, in order to make the display engine and its components probed. Signed-off-by: Icenowy Zheng <icen...@aosc.io> ---

[PATCH v2 02/10] pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver

Allwinner A10, A20 and R40 SoCs have similar GPIO layout. Add SoC definitions in pinctrl-sunxi.h, in order to merge A20 support into A10 driver, and add R40 support into it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 3 +++ 1 file chan

[PATCH v6 12/13] ARM: dts: sun8i: add pinmux for LCD pins of V3s SoC

Allwinner V3s SoC features a set of pins that have functionality of RGB LCD, the pins are at different pin ban than other SoCs. Add pinctrl node for them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 9 + 1 file changed, 9 insertions(+)

[PATCH v6 11/13] ARM: dts: sun8i: add DE2 nodes for V3s SoC

Allwinner V3s SoC features a "Display Engine 2.0" with only one TCON which have RGB LCD output. Add device nodes for it as well as the TCON. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v3s.dtsi | 87 1

[PATCH v6 06/13] drm/sun4i: add a dedicated module for sun4i-backend and sun4i-layer

Currently the direct call from CRTC code to layer code has disappeared, instead the layer's init function is called via the backend's ops. Add a dedicated module for sun4i-backend and sun4i-layer, and drop the EXPORT_SYMBOL from backend code to layer code. Signed-off-by: Icenowy Zheng <i

[PATCH v2 10/10] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

power, reset, and boot control buttons This patch adds a dts file that enables debug UART and MMC support. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/boot/dts/Makefile| 1 + arch/arm/boot/dts/sun

[PATCH v2 00/10] Initial Allwinner R40 support

file for Allwinner R40 ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (8): arm: sunxi: add support for R40 SoC pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver pinctrl: sunxi: add A20 support to A10 driver pinctrl: sunxi: switch A20's

Re: [PATCH v6 08/13] drm/sun4i: add support for Allwinner DE2 mixers

于 2017年5月5日 GMT+08:00 下午8:36:18, Maxime Ripard 写到: >On Fri, May 05, 2017 at 12:50:51AM +0800, icen...@aosc.io wrote: >> > > +void sun8i_mixer_layer_enable(struct sun8i_mixer *mixer, >> > > +int layer, bool enable) >> > > +{ >> >

Re: [linux-sunxi] [PATCH v6 11/13] ARM: dts: sun8i: add DE2 nodes for V3s SoC

于 2017年5月5日 GMT+08:00 下午8:30:35, Maxime Ripard 写到: >On Fri, May 05, 2017 at 04:53:43PM +0800, icen...@aosc.io wrote: >> > > + de2_clocks: clock@100 { >> > > + compatible = >"allwinner,sun50i-h5-de2-clk"; >> > >> > I am

[PATCH v2 01/10] arm: sunxi: add support for R40 SoC

From: Icenowy Zheng <icen...@aosc.xyz> Allwinner R40 is a new SoC, with Quad Core Cortex-A7 and peripherals like A20. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- Documentation/arm/sunxi/README | 4 Documentation/devicetree/

[PATCH v2 08/10] clk: sunxi-ng: support R40 SoC

From: Icenowy Zheng <icen...@aosc.xyz> Allwinner R40 SoC have a clock controller module in the style of the SoCs beyond sun6i, however, it's more rich and complex. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Fixes according to the SoC's

Re: [PATCH v2 02/10] pinctrl: sunxi: add definitions for add A20 and R40 support to A10 driver

于 2017年5月4日 GMT+08:00 下午10:04:31, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Thu, May 04, 2017 at 09:49:58PM +0800, Icenowy Zheng wrote: >> Allwinner A10, A20 and R40 SoCs have similar GPIO layout. >> >> Add SoC definitions in pinctrl-sunxi.h, in

[PATCH v2 07/10] dt-bindings: add compatible string for Allwinner R40 CCU

Allwinner R40 has a clock controlling unit like the ones on other Allwinner SoCs after sun6i, and can also use a CCU-based driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 1 + 1 file chan

Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver

于 2017年5月4日 GMT+08:00 下午10:41:52, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Thu, May 04, 2017 at 10:03:26PM +0800, Icenowy Zheng wrote: >> >> >> 于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard ><maxime.rip...@free-electrons.com> 写到: >>

[PATCH v2 09/10] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

00 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/boot/

Re: [PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver

于 2017年5月4日 GMT+08:00 下午10:02:20, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Thu, May 04, 2017 at 09:49:59PM +0800, Icenowy Zheng wrote: >> static const struct of_device_id sun4i_a10_pinctrl_match[] = { >> -{ .compatible = "a

[PATCH v2 06/10] pinctrl: sunxi: add support of R40 to A10 pinctrl driver

R40 is said to be an upgrade of A20, and its pin configuration is also similar to A20 (and thus similar to A10). Add support for R40 to the A10 pinctrl driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/Kconfig | 2 +- drivers/pinctrl/sunxi/p

[PATCH v2 03/10] pinctrl: sunxi: add A20 support to A10 driver

As A20 is designed as a pin-compatible upgrade of A10, their pin controller are very similar, and can share one driver. Add A20 support to the A10 driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 287 +++---

[PATCH v2 04/10] pinctrl: sunxi: switch A20's pinctrl driver to use the A10 version

As we added A20 support to A10 pinctrl driver, now we can delete the dedicated A20 pinctrl driver, and enable A10 driver for A20. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/pinctrl/sunxi/Kconfig |6 +- drivers/pinctrl/sunxi/Makefile|1 - d

[PATCH v2 05/10] dt-bindings: add compatible string for Allwinner R40 pinctrl

Allwinner R40 has a pin controller like the ones in older Allwinner SoCs (especially A20), and can use modified version of the A10/A20 pinctrl driver. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/pinctrl/allwinner

[PATCH 02/13] clk: sunxi-ng: add support for DE2 CCU

The "Display Engine 2.0" in Allwinner newer SoCs contains a clock management unit for its subunits, like the DE CCU in A80. Add a sunxi-ng style driver for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/Kconfig | 5 + drivers/clk/s

[PATCH 04/13] drm/sun4i: return only planes for layers created

in sun4i_crtc struct. Doing these things makes the CRTC code independent to the type of layer (the sun4i_layers_init function name is still hardcoded and will be changed in the next patch), so that we can finally gain support for the mixer in DE2, which will has different layers. Signed-off-by: Icenowy Zheng

[PATCH 03/13] dt-bindings: add bindings for DE2 on V3s SoC

Allwinner V3s SoC have a display engine which have a different pipeline with older SoCs. Add document for it (new compatibles and the new "mixer" part). Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring <r...@kernel.org> --- .../bindings/displ

[PATCH 01/13] dt-bindings: add binding for the Allwinner DE2 CCU

Allwinner "Display Engine 2.0" contains some clock controls in it. In order to add them as clock drivers, we need a device tree binding. Add the binding here. Also add the device tree binding headers. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring

[PATCH v6 05/13] drm/sun4i: abstract a engine type

Abstract the engine type to a new struct with an ops struct, which contains functions that should be called outside the engine-specified code (in TCON, CRTC or TV Encoder code). Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v6: - Rebased on wens's multi-pipeline patchset. - Sp

[PATCH v6 13/13] [DO NOT MERGE] ARM: dts: sun8i: enable LCD panel of Lichee Pi Zero

A 480x272 QiaoDian QD43003C0-40-7LED panel is available from Lichee Pi. This commit connects this panel to Lichee Pi Zero. Lichee Pi also provides a 800x480 panel without accurate model number, so do not merge this patch. It will finally come as device tree overlay. Signed-off-by: Icenowy Zheng

[PATCH v6 08/13] drm/sun4i: add support for Allwinner DE2 mixers

ng -- more investigations are needed to gain enough information for them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v6: - Rebased on wens's multi-pipeline patchset. Changes in v5: - Changed some code alignment. - Request real 32-bit DMA (prepare for 64-bit SoCs). Changes

[PATCH v6 10/13] drm/sun4i: tcon: add support for V3s TCON

Allwinner V3s SoC features a TCON without channel 1. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/gpu/drm/sun4i/sun4i_drv.c | 3 ++- drivers/gpu/drm/sun4i/sun4i_tcon.c | 5 + 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/g

Re: [linux-sunxi] Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i

于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai 写到: >On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard > wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series)

Re: [PATCH v6 05/21] net-next: stmmac: Add dwmac-sun8i

于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara 写到: >Hi, > >On 27/06/17 10:41, Maxime Ripard wrote: >> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote: >>> Hi, >>> >>> (CC:ing some people from that Rockchip dmwac series) >>> >>> On 27/06/17 09:21,

[PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device tree binding for H3

Allwinner H3 features a thermal sensor like the one in A33, but has its register re-arranged, the clock divider moved to CCU (originally the clock divider is in ADC) and added a pair of bus clock and reset. Update the binding document to cover H3. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v4 2/6] iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain A33

SUN8I", not "SUN8I_A33". Add "_A33" after "SUN8I" on the register names. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v4: - Change A23 to A33, as the driver never supports A23. drivers/iio/a

[PATCH v4 0/6] IIO-based thermal sensor driver for Allwinner H3 SoC

ady merged. Icenowy Zheng (6): dt-bindings: update the Allwinner GPADC device tree binding for H3 iio: adc: sun4i-gpadc-iio: rename A33-specified registers to contain A33 iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS variants iio: adc: sun4i-gpadc-iio: add supp

[PATCH v4 4/6] iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor

on A64 and H5 is like the one on H3, but with of course different formula factors. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v4: - Splitted out some code refactors. - Code sequence changed back. (The gpadc_data went back to the start of the source file) drivers/iio/adc

[PATCH v4 5/6] ARM: sun8i: h3: add support for the thermal sensor in H3

some differences, and will be added furtherly. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Reviewed-by: Chen-Yu Tsai <w...@csie.org> --- Changes in v4: - Mention calibration data in commit message. Changes in v3: - Clock name changes. - Splited out thermal zone addition. arch/

[PATCH v4 6/6] ARM: sun8i: h3: add partial CPU thermal zone

are also not added yet. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-h3.dtsi | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi index 3220da3ad790..687c6457d214 100644 --- a/arch/arm/boot/dts

[PATCH v4 3/6] iio: adc: sun4i-gpadc-iio: rework code for supporting newer THS variants

readout register to be altered. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/iio/adc/sun4i-gpadc-iio.c | 123 +++--- 1 file changed, 116 insertions(+), 7 deletions(-) diff --git a/drivers/iio/adc/sun4i-gpadc-iio.c b/drivers/iio/adc/sun4i-gpadc

[PATCH] nvmem: sunxi-sid: add support for A64/H5's SID controller

Allwinner A64/H5 SoCs come with a SID controller like the one in H3, but without the silicon bug that makes the initial value at 0x200 wrong, so the value at 0x200 can be directly read. Add support for this kind of SID controller. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documen

Re: [linux-sunxi] Re: [PATCH] nvmem: sunxi-sid: add support for A64/H5's SID controller

于 2017年9月19日 GMT+08:00 下午4:20:19, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Mon, Sep 18, 2017 at 11:42:04PM +0800, Icenowy Zheng wrote: >> Allwinner A64/H5 SoCs come with a SID controller like the one in H3, >but >> without the silicon bug that makes th

Re: [linux-sunxi] Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device tree binding for H3

于 2017年9月20日 GMT+08:00 下午3:52:23, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Mon, Sep 18, 2017 at 03:47:25PM +, icen...@aosc.io wrote: >> 在 2017-09-18 16:30，Maxime Ripard 写道： >> > On Mon, Sep 18, 2017 at 03:36:43PM +0800, Icenowy Zheng wrote: >>

[PATCH 2/3] arm64: allwinner: a64: add CPU opp table

Add the operating table for the CPU (ARM cores) on Allwinner A64 SoC. OPPs higher to 816MHz is temporarily dropped, to prevent overheat on boards with AXP803 support and undervoltage on boards without AXP803 support. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/bo

[PATCH 0/3] Simple DVFS support for Allwinner A64 SoC

driver of A64, and the remaining patches set up the device tree bits of the DVFS on Pine64. Icenowy Zheng (3): clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock arm64: allwinner: a64: add CPU opp table arm64: allwinner: a64: set CPU regulator for Pine64 .../arm64/boot/dts/allwinner

[PATCH 1/3] clk: sunxi-ng: add mux and pll notifiers for A64 CPU clock

The A64 PLL_CPU clock has the same instability if some factor changed without the PLL gated like other SoCs with sun6i-style CCU, e.g. A33, H3. Add the mux and pll notifiers for A64 CPU clock to workaround the problem. Fixes: c6a0637460c2 ("clk: sunxi-ng: Add A64 clocks") Signed-off-b

[PATCH 3/3] arm64: allwinner: a64: set CPU regulator for Pine64

The DCDC2 regulator of the AXP803 PMIC is used for the voltage scaling of the ARM cores on the A64 SoC. Add this definition to enable it on Pine64. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 4 1 file changed, 4 inse

[RFC PATCH 2/7] iio: adc: axp20x-adc: allow to skip ADC rate setup now

The ADC rate setup on AXP803 is more complex than AXP20x/22x. As it's not a necessary setup, allow it to be skipped, to allow simpler AXP803 support now. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/iio/adc/axp20x_adc.c | 6 -- 1 file changed, 4 insertions(+), 2 del

[RFC PATCH 3/7] iio: adc: axp20x-adc: add support for AXP803

and GPADC channels are complex and will be support after more investigation. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/iio/adc/axp20x_adc.c | 108 +++ 1 file changed, 108 insertions(+) diff --git a/drivers/iio/adc/axp20x_adc.c b/drivers/i

[RFC PATCH 4/7] power: supply: axp20x-battery: support AXP803

The AXP803 PMIC has battery support like other AXP PMICs, but with different definition of max target charging voltage and constant charging current. Add support for AXP803 battery in axp20x-battery driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/power/supply/axp20x_bat

[RFC PATCH 0/7] AXP803 AC/Battery support

in this patchset because it's not present on Pine series boards. In order to enable battery monitoring the ADC for battery is also enabled for AXs. In order to enable battery monitoring the ADC for battery is also enabled for AXP803. Icenowy Zheng (7): dt-bindings: add compatibles for AXP803 Battery/USB

[RFC PATCH 1/7] dt-bindings: add compatibles for AXP803 Battery/USB power supplies

for the AXP803 Battery/USB power supplies. For AC power supply the one on AXP803 is compatible with the one on AXP22x. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/power/supply/axp20x_battery.txt | 1 + Documentation/devicetree/bindings/power/

[RFC PATCH 6/7] arm64: allwinner: a64: add power supply nodes in AXP803 DTSI

AXP803 PMIC features AC/USB/Battery power supplies. As we have now the device tree bindings for them, add device tree nodes for them. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/axp803.dtsi | 15 +++ 1 file changed, 15 insertions(+) diff

[RFC PATCH 7/7] arm64: allwinner: a64: enable AC and Battery for Pine64

-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts b/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts index d06e34b5d192..955f392af6a2

[RFC PATCH 5/7] mfd: axp20x: add cells for AXP803 ADC/AC Power/Battery

As we have now support for AXP803 ADC/Battery, and the AC Power part of AXP803 is the same as AXP22x, add MFD cells for these drivers. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/mfd/axp20x.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/drivers/mfd/axp2

Re: [RFC PATCH 0/7] AXP803 AC/Battery support

于 2017年9月21日 GMT+08:00 下午10:46:21, Jonathan Cameron <jonathan.came...@huawei.com> 写到: >On Wed, 20 Sep 2017 23:18:07 +0800 >Icenowy Zheng <icen...@aosc.io> wrote: > >> The AXP803 PMIC, used by most Allwinner A64 boards, features 3 power >inputs: >> AC, USB an

Re: [PATCH v4 1/6] dt-bindings: update the Allwinner GPADC device tree binding for H3

于 2017年9月18日 GMT+08:00 下午3:33:36, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Thu, Sep 14, 2017 at 10:52:46PM +0800, Icenowy Zheng wrote: >> Allwinner H3 features a thermal sensor like the one in A33, but has >its >> register re-arranged, the clock divider

[PATCH 5/6] ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra

From: Icenowy Zheng <icen...@aosc.xyz> Banana Pi M2 Ultra board features two USB host ports, connected to the two USB host ports on the SoC. Add support for them. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ul

[PATCH 4/6] ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry

On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA and USB) is controlled via a GPIO. Add regulator node for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 + 1 file changed, 9 insertions(+) diff

[PATCH 6/6] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 + 1 file changed, 13 insertions(+)

[PATCH 2/6] ARM: sun8i: r40: add USB host port nodes for R40

From: Icenowy Zheng <icen...@aosc.xyz> Allwinner R40 SoC features a USB OTG port and two USB HOST ports. Add support for the host ports in the DTSI file. The OTG controller still cannot work with existing compatibles, and needs more investigation. So it's not added yet. Signed-off-by: I

[PATCH 3/6] ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra

. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 + 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts index 7b5260

[PATCH 0/6] Allwinner R40 USB host support

for the two boards, and the fifth and sixth patch finally adds USB host ports support. Icenowy Zheng (6): phy: sun4i-usb: add support for R40 USB PHY ARM: sun8i: r40: add USB host port nodes for R40 ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra ARM: sun8i: v40: add 5V regulator

[PATCH 1/6] phy: sun4i-usb: add support for R40 USB PHY

Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 + drivers/phy/allwinner/phy-sun4i-usb.c | 12 2

[PATCH 2/2] ata: ahci_sunxi: add support for R40 SATA controller

Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20, but with a reset control and two dedicated VDD pins for this controller (one 1.2v and one 2.5v). Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/ata/ahci_sunxi.c

[PATCH 1/2] dt-bindings: add binding for Allwinner R40 SATA AHCI controller

generic platform AHCI controller binding document. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../devicetree/bindings/ata/ahci-platform.txt | 1 - .../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++ 2 files changed, 40 insertions(+), 1 deletion(-)

Re: [PATCH review for 4.4 14/24] dmaengine: sun6i: allow build on ARM64 platforms (sun50i)

于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)" <alexander.le...@verizon.com> 写到: >From: Icenowy Zheng <icen...@aosc.xyz> > >[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ] > >As 64-bit Allwinner H5 SoC has the same DMA e

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo <kv...@codeaurora.org> 写到: >Icenowy Zheng <icen...@aosc.io> writes: > >> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to >use >> an out-of-band interrupt pin instead of SDIO in-band interrupt.

Re: [PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote: >> On 10/4/2017 11:03 AM, Icenowy Zheng wrote: >> > >> > >> > 于 2017年10月4日 GMT+08:00 下午5:02

[PATCH] staging: rtl8723bs: hide "nolinked power save" info when not debugging

Currently the rtl8723bs driver will print "nolinked power save enter" and "nolinked power save leave" per minute if it's not connected to any network. These messages are meaningless and annoying to regular users. Hide them when it's not debugging. Signed-off-by: Icenowy Zh

[PATCH] ARM: sun8i: r40: add watchdog device node

The R40 SoC has a watchdog like the one on A20, in the timer memory zone (which is also the same on A20). Add the device tree node for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun8i-r40.dtsi | 5 + 1 file changed, 5 insertions(+) diff --git a/arch/ar

[PATCH 1/2] clk: sunxi-ng: r40: rewrite init code to a platform driver

As we need to register a regmap on the R40 CCU, there needs to be a device structure bound to the CCU device node. Rewrite the R40 CCU driver initial code to make it a proper platform driver, thus we will have a platform device bound to it. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH 2/2] clk: sunxi-ng: r40: export a regmap to access the GMAC register

There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in the syscon part, in the CCU of R40 SoC. Export a regmap of the CCU. Read access is not restricted to all registers, but only the GMAC register is allowed to be written. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH 0/2] Add a regmap to Allwinner R40 CCU to export GMAC register

patch does the conversion of the driver to a platform driver, and the second patch adds the regmap. Icenowy Zheng (2): clk: sunxi-ng: r40: rewrite init code to a platform driver clk: sunxi-ng: r40: export a regmap to access the GMAC register drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 69

[PATCH v3 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

power, reset, and boot control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Added 3.3V vqmmc regulator for mmc2 (eMMC). Changes in v2: -

[PATCH v3 0/3] Basical device tree parts for Allwinner R40 SoC

: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (1): ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry arch/arm/boot/dts/Makefile| 4 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++ arch/arm/boot/dts/sun8i-r40.dtsi

[PATCH v3 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

00 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3:

[PATCH v3 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Dropped the vcc5v0 regulator, a

[PATCH 2/2] clk: sunxi-ng: add support for Allwinner A64 DE2 CCU

Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work. Add support for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32 1 file changed, 24 insertions(+), 8 deletions(-) diff --git a/drive

[PATCH 1/2] dt-bindings: add binding for A64 DE2 CCU with SRAM section

A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed. Add binding for this. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 + 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bi

[PATCH 0/4] Add SimpleFB support for Allwinner H3 SoC

CCU device node for H3 SoC, and the skeleton of the node enters the H3/H5 common DTSI; the H5 support is splited into the third patch, as they will enter different tree. The fourth patch finally adds simplefb nodes, using the pipeline strings introduced in the first patch. Icenowy Zheng (4): dt

[PATCH 4/4] ARM: sunxi: h3/h5: add simplefb nodes

The H3/H5 SoCs have a HDMI output and a TV Composite output. Add simplefb nodes for these outputs. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sunxi-h3-h5.dtsi | 29 + 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/su

[PATCH 3/4] arm64: allwinner: h5: add compatible string for DE2 CCU

The DE2 CCU on Allwinner H5 SoC has a slightly different behavior than the one on H3, so the compatible string is not set in the common DTSI file. Add the compatible string of H5 DE2 CCU in H5 DTSI file. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun

[PATCH 2/4] ARM: sun8i: h3/h5: add DE2 CCU device node for H3

The DE2 in H3/H5 has a clock control unit in it, and the behavior is slightly different between H3 and H5. Add the common parts in H3/H5 DTSI, and add the compatible string in H3 DTSI. The compatible string of H5 DE2 CCU will be added in a separated patch. Signed-off-by: Icenowy Zheng <i

[PATCH 1/4] dt-bindings: simplefb-sunxi: add pipelines for DE2

As we're going to add simplefb support for Allwinner SoCs with DE2, add suitable pipeline strings in the device tree binding. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../devicetree/bindings/display/simple-framebuffer-sunxi.txt | 4 1 file changed, 4 insertions(+)

[PATCH] ARM: sun7i: a20: enable ac/battery power supplies for Lamobo R1 board

The Lamobo R1 board connected the ACIN of the AXP209 PMIC to a MicroUSB port, and the battery input is connected to a generic connector. Enable these two power supplies in the device tree. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm/boot/dts/sun7i-a20-lamobo-r1.d

[PATCH 2/2] clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock

locks") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c index 7a81c4885836..543c46d0e045 100644 --- a/drivers/

[PATCH 1/2] clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs

The PLLs on H3 have a lock bit, which will only be set to 1 when the PLL is really working. Add CLK_SET_RATE_UNGATE to the PLLs, otherwise it will timeout when trying to set PLL clock frequency without enabling it. Fixes: 0577e4853bfb ("clk: sunxi-ng: Add H3 clocks") Signed-off-by: Ice

[PATCH 0/2] clk: sunxi-ng: Add several flags to H3 CCU

for lock by adds CLK_SET_RATE_UNGATE flag. The second patch solves the problem that H3 GPU clock is not really tweaked by add CLK_SET_RATE_PARENT flag to it. Icenowy Zheng (2): clk: sunxi-ng: add CLK_SET_RATE_UNGATE to all H3 PLLs clk: sunxi-ng: add CLK_SET_RATE_PARENT flag to H3 GPU clock

Re: [linux-sunxi] Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC

于 2017年9月25日 GMT+08:00 下午6:27:44, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Mon, Sep 25, 2017 at 10:12:09AM +, Icenowy Zheng wrote: >> 于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard ><maxime.rip...@free-electrons.com> 写到: >> >Hi, >> &

Re: [PATCH v2 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >On Thu, Sep 28, 2017 at 09:25:42AM +, Icenowy Zheng wrote: >> + { >> +vmmc-supply = <_dcdc1>; >> +bus-width = <8>; >> +non-removable; >> +

Re: [PATCH v2 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >Hi, > >On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote: >> +/* >> + * The max-frequency properties in all MMC controller nodes >>

[PATCH v2 2/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Ultra

power, reset, and boot control buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Dropped the vcc5v0 regulator, as it's not used yet. arch/arm

[PATCH v2 3/3] ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry

headphone jack - red and green LEDs - debug UART pins - Raspberry Pi B+ compatible GPIO header - power and reset buttons This patch adds a dts file that enables UART, MMC and PMIC support. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Dropped the vcc5v0 regulator, a

[PATCH v2 1/3] ARM: dts: sun8i: Add basic dtsi file for Allwinner R40

00 MP2 GPU. It retains most if not all features from the A20, while adding some new features, such as MIPI DSI output, or updating various hardware blocks, such as DE 2.0. Signed-off-by: Chen-Yu Tsai <w...@csie.org> Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2

[PATCH v2 0/3] Basical device tree parts for Allwinner R40 SoC

: Add board dts file for Banana Pi M2 Ultra Icenowy Zheng (1): ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry arch/arm/boot/dts/Makefile| 4 +- arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++ arch/arm/boot/dts/sun8i-r40.dtsi

[PATCH v3 0/2] Allwinner XR819 SDIO Wi-Fi DT binding and OPi Zero XR819 IRQ

, then adds the interrupt to the device tree of Orange Pi Zero. Icenowy Zheng (1): dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi Sergey Matyukevich (1): ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero .../bindings/net/wireless/allwinner,xr819.txt | 38

[PATCH v3 2/2] ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero

endor prefix to allwinner and modify commit message] Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3 by Icenowy: - Change the compatible string vendor prefix to "allwinner". - Modify the commit message. Changes in v2 by Sergey: - Adds the compatible string. arch/arm/boo

[PATCH v3 1/2] dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi

Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use an out-of-band interrupt pin instead of SDIO in-band interrupt. Add the device tree binding of this chip, in order to make it possible to add this interrupt pin to device trees. Signed-off-by: Icenowy Zheng <icen...@aosc

Re: [PATCH 0/3] Simple DVFS support for Allwinner A64 SoC

于 2017年9月25日 GMT+08:00 下午6:10:27, Maxime Ripard <maxime.rip...@free-electrons.com> 写到: >Hi, > >On Sat, Sep 23, 2017 at 12:15:28AM +, Icenowy Zheng wrote: >> This patchset imports simple DVFS support for Allwinner A64 SoC. >> >> As the thermal sensor drive

Re: [RFC PATCH 6/7] arm64: allwinner: a64: add power supply nodes in AXP803 DTSI

于 2017年9月25日 GMT+08:00 下午5:11:57, Quentin Schulz <quentin.sch...@free-electrons.com> 写到: >Hi Icenowy, > >On 20/09/2017 17:18, Icenowy Zheng wrote: >> AXP803 PMIC features AC/USB/Battery power supplies. >> >> As we have now the device tree bindings for them,

[PATCH v2 2/4] net: phy: realtek: change macro name for page select register

From: Icenowy Zheng <icen...@aosc.xyz> The page select register also exists on RTL8211E PHY (although it behaves slightly differently). Change the register macro name to remove the F. Signed-off-by: Icenowy Zheng <icen...@aosc.xyz> --- drivers/net/phy/realtek.c | 12 +++-

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