Add support for the newly imported compatible for the A64 R_INTC in
irq-sunxi-nmi driver
Signed-off-by: Icenowy Zheng
---
New patch in v4, which is part of NMI refactor.
drivers/irqchip/irq-sunxi-nmi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/irqchip/irq-sunxi
GPIO (so it's with 2.0mm pitch, not 2.54mm as
other GPIO headers).
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boo
The A31 NMI driver seems to be using wrong base address.
As we're going to convert to use a correct NMI base address (and
correctly name it to R_INTC as the datasheet suggests), add a new
compatible string for the "correct" R_INTC, which we will use for A64
SoC.
Signed-off-by
Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.
Signed-off-by: Icenowy Zheng
---
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
1 file changed, 109 insertions(+)
diff --git a/arch/arm64
As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Re-sorted the nodes.
arch/arm64/boot/dts/allwinner/axp803.dtsi | 150
AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.
Add support for them.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v4:
- Fixed somewhere which mention AXP806 before 803.
Changes in v2:
- Place AXP803 codes before AXP806/809 ones
The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
Add its device node.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
As axp20x-regulator now supports AXP803, add a cell for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v4:
- Added a trailing comma for new cell, for easier further cell addition.
Changes in v3:
- Make the new cell one-liner.
drivers/mfd/axp20x.c | 3
Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Changes it to use R_INTC binding and change node label to r_intc.
- Fixed MMIO region
于 2017年4月25日 GMT+08:00 下午3:57:17, Lee Jones 写到:
>On Tue, 25 Apr 2017, Icenowy Zheng wrote:
>
>> As axp20x-regulator now supports AXP803, add a cell for it.
>>
>> Signed-off-by: Icenowy Zheng
>> Acked-by: Chen-Yu Tsai
>> ---
>> Changes in v4:
>
于 2017年4月25日 GMT+08:00 下午5:24:13, Andre Przywara 写到:
>Hi,
>
>On 24/04/17 17:01, Icenowy Zheng wrote:
>> Add support of AXP803 regulators in the Pine64 device tree, in order
>to
>> enable many future functionalities, e.g. Wi-Fi.
>
>In general that's quite so
于 2017年6月27日 GMT+08:00 下午6:11:47, Chen-Yu Tsai 写到:
>On Tue, Jun 27, 2017 at 5:41 PM, Maxime Ripard
> wrote:
>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>> Hi,
>>>
>>> (CC:ing some people from that Rockchip dmwac series)
>>>
>>> On 27/06/17 09:21, Corentin Labbe wrote:
>>>
于 2017年6月27日 GMT+08:00 下午6:15:58, Andre Przywara 写到:
>Hi,
>
>On 27/06/17 10:41, Maxime Ripard wrote:
>> On Tue, Jun 27, 2017 at 10:02:45AM +0100, Andre Przywara wrote:
>>> Hi,
>>>
>>> (CC:ing some people from that Rockchip dmwac series)
>>>
>>> On 27/06/17 09:21, Corentin Labbe wrote:
On Tu
AXP20x regulatoe driver.
(The binding is already applied)
PATCH 6 enables the AXP803 regulator cell in MFD driver.
PATCH 7 adds a DTSI file for AXP803, like other older AXP PMICs.
PATCH 8 enables AXP803 regulators in Pine64 device tree.
PATCH 9 enables Wi-Fi for Pine64.
Icenowy Zheng (9
The A31 NMI driver seems to be using wrong base address.
As we're going to convert to use a correct NMI base address (and
correctly name it to R_INTC as the datasheet suggests), add a new
compatible string for the "correct" R_INTC, which we will use for A64
SoC.
Signed-off-by
The Pine64 (including Pine64+) boards have an AXP803 as its main PMIC.
Add its device node.
Signed-off-by: Icenowy Zheng
---
Changes in v6:
- Rebase on next-20170517.
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch
As nearly all A64 boards are using AXP803 PMIC, add a DTSI file for it,
like the old DTSI files for AXP20x/22x, for the common parts of the
PMIC.
Signed-off-by: Icenowy Zheng
Acked-by: Mark Brown
---
Changes in v5:
- Added Mark Brown's ACK.
Changes in v4:
- Re-sorted the nodes.
arch/
AXP803 PMIC also have a series of regulators (DCDCs and LDOs)
controllable via I2C/RSB bus.
Add support for them.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v4:
- Fixed somewhere which mention AXP806 before 803.
Changes in v2:
- Place AXP803 codes before AXP806/809 ones
As axp20x-regulator now supports AXP803, add a cell for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v5:
- Removed wrong snippet.
Changes in v4:
- Added a trailing comma for new cell, for easier further cell addition.
Changes in v3:
- Make the new cell one-liner
Add support of AXP803 regulators in the Pine64 device tree, in order to
enable many future functionalities, e.g. Wi-Fi.
Signed-off-by: Icenowy Zheng
---
Changes in v6:
- Rebased on next-20170517.
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 109 +
1 file changed
GPIO (so it's with 2.0mm pitch, not 2.54mm as
other GPIO headers).
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-pine64.dts
b/arch/arm64/boo
Allwinner A64 SoC features a R_INTC controller, which controls the NMI
line, and this interrupt line is usually connected to the AXP PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Changes it to use R_INTC binding and change node label to r_intc.
- Fixed MMIO region
Add support for the newly imported compatible for the A64 R_INTC in
irq-sunxi-nmi driver.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Fix A64 R_INTC compatible.
drivers/irqchip/irq-sunxi-nmi.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/irqchip/irq-sunxi
于 2017年5月19日 GMT+08:00 上午10:54:21, Chen-Yu Tsai 写到:
>Hi,
>
>On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
>> Add support of AXP803 regulators in the Pine64 device tree, in order
>to
>> enable many future functionalities, e.g. Wi-Fi.
>>
>> Signed-off-
于 2017年5月19日 GMT+08:00 上午11:01:39, Chen-Yu Tsai 写到:
>Hi,
>
>On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng wrote:
>> The Wi-Fi module of Pine64 is powered via DLDO4 and ELDO1 (the latter
>> one provides I/O voltage).
>>
>> Add device node for it.
>>
>
于 2017年5月19日 GMT+08:00 上午11:10:36, Chen-Yu Tsai 写到:
>On Fri, May 19, 2017 at 11:00 AM, Icenowy Zheng
>wrote:
>>
>>
>> 于 2017年5月19日 GMT+08:00 上午10:54:21, Chen-Yu Tsai 写到:
>>>Hi,
>>>
>>>On Thu, May 18, 2017 at 3:16 PM, Icenowy Zheng
>wrot
于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara 写到:
>Hi,
>
>On 18/05/17 08:16, Icenowy Zheng wrote:
>> Add support of AXP803 regulators in the Pine64 device tree, in order
>to
>> enable many future functionalities, e.g. Wi-Fi.
>>
>> Signed-off-by: Ic
于 2017年5月20日 GMT+08:00 上午1:47:29, Maxime Ripard
写到:
>On Thu, May 18, 2017 at 12:43:45AM +0800, Icenowy Zheng wrote:
>> From: Icenowy Zheng
>>
>> Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI
>channels,
>> and the other has 1 VI and 1 UI.
&g
于 2017年5月20日 GMT+08:00 上午1:57:53, Maxime Ripard
写到:
>On Thu, May 18, 2017 at 12:43:46AM +0800, Icenowy Zheng wrote:
>> Some SoC's DE2 has two mixers. Defaultly the mixer0 is connected to
>> tcon0 and mixer1 is connected to tcon1; however by setting a bit
>> the
于 2017年5月20日 GMT+08:00 上午2:02:15, Maxime Ripard
写到:
>On Thu, May 18, 2017 at 12:43:44AM +0800, Icenowy Zheng wrote:
>> -On SoCs other than the A33 and V3s, there is one more clock
>required:
>> +For the following compatibles:
>> + * allwinner,sun5i-a13-tcon
>>
于 2017年5月20日 GMT+08:00 上午2:03:30, Maxime Ripard
写到:
>On Thu, May 18, 2017 at 12:43:50AM +0800, Icenowy Zheng wrote:
>> Allwinner H3 features a TV encoder similar to the one in earlier
>SoCs,
>> but with some different points about clocks:
>> - It has a mod clock and a
于 2017年5月20日 GMT+08:00 上午2:06:16, Maxime Ripard
写到:
>On Thu, May 18, 2017 at 12:43:53AM +0800, Icenowy Zheng wrote:
>> As we have already the support for the TV encoder on Allwinner H3,
>add
>> the display engine pipeline device tree nodes to its DTSI file.
>>
>
于 2017年5月24日 GMT+08:00 下午1:24:29, Chen-Yu Tsai 写到:
>On Thu, May 18, 2017 at 12:43 AM, Icenowy Zheng
>wrote:
>> As we have already the support for the TV encoder on Allwinner H3,
>add
>> the display engine pipeline device tree nodes to its DTSI file.
>>
>> The
于 2017年5月24日 GMT+08:00 下午1:34:58, Chen-Yu Tsai 写到:
>On Wed, May 24, 2017 at 1:28 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月24日 GMT+08:00 下午1:24:29, Chen-Yu Tsai 写到:
>>>On Thu, May 18, 2017 at 12:43 AM, Icenowy Zheng
>>>wrote:
>>>> A
t; > > Dne sobota, 20. maj 2017 ob 03:37:53 CEST je Chen-Yu Tsai
>napisal(a):
>> > > > On Sat, May 20, 2017 at 2:23 AM, Jernej Škrabec
>
>> > > wrote:
>> > > > > Hi,
>> > > > >
>> > >
adds three parts of device tree: DMA engine, codec support
and enable the codec for Lichee Pi Zero dock.
Icenowy Zheng (9):
ASoC: sun8i-codec-analog: split out mbias
ASoC: sun8i-codec-analog: prepare a mixer control/widget/route set for
V3s
ASoC: sun8i-codec-analog: add support for V3s SoC
The Lichee Pi Zero Dock board has an audio jack and an onboard MIC.
Enable them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero-dock.dts
b/arch/arm/boot
From: Icenowy Zheng
Allwinner V3s SoC features a DMA engine.
Add it in the DTSI file.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v3:
- Added Chen-Yu's ACK.
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm
From: Icenowy Zheng
Allwinner V3s SoC features an internal audio codec like the one in H3,
and a analog codec like the one in H3/A23 (but much simpler).
Add them in the DTSI file.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v3:
- Added Chen-Yu's ACK.
arch/arm
Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
and only one TCON connected to this mixer, which have RGB LCD output.
Add device nodes for this display pipeline.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s
Allwinner V3s SoC features a set of pins that have functionality of RGB
LCD, the pins are at different pin ban than other SoCs.
Add pinctrl node for them.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 9 +
1 file changed, 9 insertions
: Icenowy Zheng
---
New patch in v3.
sound/soc/sunxi/sun8i-codec-analog.c | 97 +++-
1 file changed, 96 insertions(+), 1 deletion(-)
diff --git a/sound/soc/sunxi/sun8i-codec-analog.c
b/sound/soc/sunxi/sun8i-codec-analog.c
index edcc3eb7cd9a..4c34a12b3739 100644
--- a
From: Icenowy Zheng
The V3s SoC features an analog codec with headphone support but without
mic2 and linein.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/sound/sun8i-codec-analog.txt | 1 +
sound/soc/sunxi/sun8i-codec-analog.c
From: Icenowy Zheng
The codec in the V3s is similar to the one found on the A31. One key
difference is the analog path controls are routed through the PRCM
block. This is supported by the sun8i-codec-analog driver, and tied
into this codec driver with the audio card's aux_dev.
In addition
Allwinner V3s have two PWM channels, the first channel can be only at
PB4 pin, and the second channel PB5.
Add their pinmux configurations.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i
attached. The LCD device tree overlay files can enable these controllers
and make use of them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
b/arch
As we have already the support for the PWM controller on V3s SoC, add
its device node in the SoC's DTSI file.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/
From: Icenowy Zheng
Originally we enable a special gate bit when the compatible indicates
A23/33.
But according to BSP sources and user manuals, more SoCs will need this
gate bit.
So make it a common quirk configured in the config struct.
Signed-off-by: Icenowy Zheng
---
Changes in v3
From: Icenowy Zheng
Allwinner V3s has a DMA engine similar to the ones from A31, but with
fewer channels and DRQs.
Add support for it.
Signed-off-by: Icenowy Zheng
Acked-by: Chen-Yu Tsai
---
Changes in v3:
- Added Chen-Yu's ACK.
Documentation/devicetree/bindings/dma/sun6i-dma.txt
From: Icenowy Zheng
Allwinner V3s features an analog codec without MBIAS pin.
Split out this part, in order to prepare for the V3s analog codec.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Fixed a missing line in v2.
sound/soc/sunxi/sun8i-codec-analog.c | 35
于 2017年5月25日 GMT+08:00 下午4:37:31, Chen-Yu Tsai 写到:
>On Wed, May 24, 2017 at 7:17 PM, Icenowy Zheng wrote:
>> Allwinner V3s SoC features a "Display Engine 2.0" with only one mixer
>> and only one TCON connected to this mixer, which have RGB LCD output.
>>
>&
于 2017年5月25日 GMT+08:00 下午10:20:33, Chen-Yu Tsai 写到:
>On Thu, May 25, 2017 at 9:54 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2017年5月25日 GMT+08:00 下午4:37:31, Chen-Yu Tsai 写到:
>>>On Wed, May 24, 2017 at 7:17 PM, Icenowy Zheng
>wrote:
>>>> Allwinner V3s
于 2017年7月10日 GMT+08:00 下午4:44:00, Maxime Ripard
写到:
>On Fri, Jul 07, 2017 at 07:21:19AM +0800, icen...@aosc.io wrote:
>> 在 2017-07-07 04:46，Maxime Ripard 写道：
>> > Hi,
>> >
>> > On Thu, Jul 06, 2017 at 10:28:21PM +0800, Icenowy Zheng wrote:
>> >
This patchset contains only two patches.
The first one is a minor fix for the A10 pinctrl driver, add a function
of a pin, which used to be missing in A10/A20 pinctrl driver.
The second one is the real R40 pinctrl part, with fixes suggested by
Chen-Yu.
Icenowy Zheng (2):
pinctrl: sunxi: add a
iver to the A10
one, we need to only fix the A10 driver now.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
b/drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c
index 159580c04b1
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 280
于 2017年7月7日 GMT+08:00 上午4:50:30, Maxime Ripard
写到:
>On Thu, Jul 06, 2017 at 10:28:22PM +0800, Icenowy Zheng wrote:
>> SUNXI_PIN(SUNXI_PINCTRL_PIN(B, 0),
>>SUNXI_FUNCTION(0x0, "gpio_in"),
>>SUNXI_FUNCTION(0x1, "gpio_out
于 2017年7月7日 GMT+08:00 下午5:18:38, Maxime Ripard
写到:
>On Fri, Jul 07, 2017 at 07:13:30AM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2017年7月7日 GMT+08:00 上午4:50:30, Maxime Ripard
> 写到:
>> >On Thu, Jul 06, 2017 at 10:28:22PM +0800, Icenowy Zheng wrote:
>>
于 2017年7月18日 GMT+08:00 上午10:58:52, Chen-Yu Tsai 写到:
>On Fri, May 19, 2017 at 4:55 PM, Andre Przywara
> wrote:
>> Hi,
>>
>> On 19/05/17 09:29, Icenowy Zheng wrote:
>>>
>>>
>>> 于 2017年5月19日 GMT+08:00 下午4:27:21, Andre Przywara
> 写到:
>
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Allwinner H5 has a Mali-450 MP4 GPU, which has a reset line like other
Allwinner SoCs with Mali Utgard, but it's a Mali-450, so it needs a new
compatible.
Add the new compatible to Mali Utgard binding document.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/gpu/arm
A20 Datasheet V1.41 contain this pin function, and
it's discovered during implementing R40 pinctrl driver.
Add it to the driver. As we now merged A20 pinctrl driver to the A10
one, we need to only fix the A10 driver now.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Commit message changes.
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Fixed some lines' format.
drivers/pinctrl/sunxi/Kconfig
, with fixes suggested by
Chen-Yu and Maxime.
Icenowy Zheng (2):
pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver
pinctrl: sunxi: add support of R40 to A10 pinctrl driver
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274
d now.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 0d1f026
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now proper regulators support, missing or dummy regulators
are changed to the correct ones.
Signed-off-by: Icenowy Zheng
---
.../boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 116
.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index 51d67c0a0edf
于 2017年7月21日 GMT+08:00 下午3:42:07, Chen-Yu Tsai 写到:
>On Fri, Jul 21, 2017 at 7:07 AM, Icenowy Zheng wrote:
>> Banana Pi M64 board uses an AXP803 PMIC.
>>
>> Enable the PMIC and its regulators.
>>
>> As we have now proper regulators support, missing or dummy
regulators in v1 are removed.
Icenowy Zheng (2):
arm64: allwinner: a64: enable AXP803 regulators for Pine64
arm64: allwinner: a64: add AXP803 PMIC support to SoPine and the
baseboard
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 102 +
.../dts/allwinner/sun50i-a64
The SoPine SoM has an AXP803 PMIC connected to the RSB bus of the A64
SoC, and the regulators of the PMIC are used both on the SoM itself and
on the official baseboard
Add related device tree parts to the SoPine SoM DTSI file and the
baseboard DT.
Signed-off-by: Icenowy Zheng
---
Changes in v2
Add support of AXP803 regulators in the Pine64 device tree.
The phy-supply regulator is also set in EMAC device node, in order to
prevent Ethernet regression by regulator get disabled by regulator
framework.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the min voltage of vdd-cpux to
The Banana Pi M64 board uses the A64 chip's EMAC to provide Ethernet
link.
Add the ethernet0 alias in the device tree, in order to let U-Boot
generate a MAC address from the chip's SID.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1
Add the ethernet0 aliases to these boards.
I hope this patchset can be queued in 4.13, otherwise 4.13 kernels
won't get non-volatile MAC addresses, and will use random ones
instead, which is annoying to many users.
Icenowy Zheng (3):
arm64: allwinner: a64: add ethernet0 alias for BPi M6
The Pine64 (including the Plus models) board uses the A64 chip's
EMAC to provide Ethernet link.
Add the ethernet0 alias in the device tree, in order to let U-Boot
generate a MAC address from the chip's SID.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-
The SoPine official baseboard uses the A64 chip's EMAC to provide an
Ethernet link.
Add the ethernet0 alias in the device tree, in order to let U-Boot
generate a MAC address from the chip's SID.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-sopine-baseboa
driver to a driver of its own")
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v3:
- Added Chen-Yu's review tag.
- Added fix tag suggested by Chen-Yu.
Changes in v2:
- Commit message changes. (mentioning the datasheet versions which are
used to discover this pin fu
R40 is said to be an upgrade of A20, and its pin configuration is also
similar to A20 (and thus similar to A10).
Add support for R40 to the A10 pinctrl driver.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v3:
- Fixed a missing comma in v2.
- Added Chen-Yu's revie
, with fixes suggested by
Chen-Yu and Maxime.
Icenowy Zheng (2):
pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver
pinctrl: sunxi: add support of R40 to A10 pinctrl driver
drivers/pinctrl/sunxi/Kconfig | 2 +-
drivers/pinctrl/sunxi/pinctrl-sun4i-a10.c | 274
From: Ondrej Jirman
SY8106A is an I2C-controlled adjustable voltage regulator made by
Silergy Corp.
Add its device tree binding.
Signed-off-by: Ondrej Jirman
[Icenowy: Change commit message]
Signed-off-by: Icenowy Zheng
---
.../bindings/regulator/sy8106a-regulator.txt| 21
From: Ondrej Jirman
SY8106A is an I2C attached single output regulator made by Silergy Corp,
which is used on several Allwinner H3/H5 SBCs to control the power
supply of the ARM cores.
Add a driver for it.
Signed-off-by: Ondrej Jirman
[Icenowy: Change commit message]
Signed-off-by: Icenowy
mentioned.
Chen-Yu Tsai (1):
clk: sunxi-ng: h3: gate then ungate PLL CPU clk after rate change
Icenowy Zheng (4):
clk: sunxi-ng: allow set parent clock (PLL_CPUX) for CPUX clock on H3
cpufreq: dt: Add support for some new Allwinner SoCs
ARM: sun8i: h3: add operating-points-v2 table for CPU
ARM
From: Ondrej Jirman
Allwinner H3/H5 SoCs have an I2C controller at PL GPIO bank.
Add support for it in the device tree.
Signed-off-by: Ondrej Jirman
[Icenowy: Change to use r_ccu and change pinmux node name]
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sunxi-h3-h5.dtsi | 14
From: Ondrej Jirman
H3/H5 SoCs contain an I2C controller optionally available
on the PL0 and PL1 pins. This patch adds pinmux configuration
for this controller.
Signed-off-by: Ondrej Jirman
[Icenowy: change commit message and node name]
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts
The CPUX clock, which is the main clock of the ARM core on Allwinner H3,
can be adjusted by changing the frequency of the PLL_CPUX clock.
Allowing setting parent clock for the CPUX clock, thus the PLL_CPUX
clock can be adjusted when adjusting the CPUX clock.
Signed-off-by: Icenowy Zheng
From: Chen-Yu Tsai
This patch utilizes the new PLL clk notifier to gate then ungate the
PLL CPU clock after rate changes. This should prevent any system hangs
resulting from cpufreq changes to the clk.
Reported-by: Ondrej Jirman
Signed-off-by: Chen-Yu Tsai
Tested-by: Icenowy Zheng
Some new Allwinner SoCs get supported in the kernel after the
compatibles are added to cpufreq-dt-platdev driver.
Add their compatible strings in the cpufreq-dt-platdev driver.
Cc: "Rafael J. Wysocki"
Cc: Viresh Kumar
Signed-off-by: Icenowy Zheng
---
drivers/cpufreq/cpufreq-dt-pla
8113B.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 38 +-
1 file changed, 37 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index b36f9f423c39..a0cee17fe44b 100644
--- a/arch/arm/boo
regulator and set the cpu's cpu-supply
property to it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 +
1 file changed, 21 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts
b/arch/arm/boot/dts/sun8i-h2
]
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
b/arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts
index 998b60f8d295..d855f8b6254e 100644
--- a/arch/arm/boot
ula factors.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Clock name changes.
- Fixed some small issues pointed out by Quentin.
drivers/iio/adc/sun4i-gpadc-iio.c | 228 +++---
include/linux/mfd/sun4i-gpadc.h | 27 +
2 files changed, 215 inserti
As we have gained the support for the thermal sensor in H3, we can now
add its device nodes to the device tree.
Add them to the H3 device tree.
The H5 thermal sensor has some differences, and will be added furtherly.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Clock name changes
SUN8I", not "SUN8I_A23".
Add "_A23" after "SUN8I" on the register names.
Signed-off-by: Icenowy Zheng
---
drivers/iio/adc/sun4i-gpadc-iio.c | 2 +-
include/linux/mfd/sun4i-gpadc.h | 6 +++---
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/driv
ady merged.
Icenowy Zheng (5):
dt-bindings: update the Allwinner GPADC device tree binding for H3
iio: adc: sun4i-gpadc-iio: rename A23/A33-specified registers to
contain A23
iio: adc: sun4i-gpadc-iio: add support for H3 thermal sensor
ARM: sun8i: h3: add support for the thermal sensor i
Allwinner H3 features a thermal sensor like the one in A33, but has its
register re-arranged, the clock divider moved to CCU (originally the
clock divider is in ADC) and added a pair of bus clock and reset.
Update the binding document to cover H3.
Signed-off-by: Icenowy Zheng
---
Changes in v3
points are also not added yet.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index efe3a8e4f2af..551efecaab5d 100644
--- a/arch/arm/boot/dts/sun8i-h3.
The critical shutdown notice string used to have some spaces missing,
which makes it not so pretty.
Add the spaces to satisfy usual English space rules.
Reported-by: Mingcong Bai
Signed-off-by: Icenowy Zheng
---
drivers/thermal/thermal_core.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
于 2017年7月23日 GMT+08:00 下午11:15:04, Chen-Yu Tsai 写到:
>On Fri, Jul 21, 2017 at 7:38 PM, wrote:
>> 在 2017-07-21 15:49，Chen-Yu Tsai 写道：
>>>
>>> On Fri, Jul 21, 2017 at 3:44 PM, Icenowy Zheng
>wrote:
>>>>
>>>>
>>>>
>>>&g
在 2018-02-08 17:00，Maxime Ripard 写道：
On Tue, Feb 06, 2018 at 09:16:47PM +0800, Icenowy Zheng wrote:
Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form
factor and GPIO holes similar to Raspberry Pi Zero.
It features:
- Allwinner H2+ SoC
- Single-chip (16-bit) 512MiB DDR3 DRAM
to power the board and
the other features OTG functionality)
- Two keys, a reset and a GPIO-connected key.
- HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+.
- CSI connector to connect the camera sensor provided by Sinovoip.
Signed-off-by: Icenowy Zheng
---
Changes in v5
one is A80).
This patchset adds the most basical support for it, including the main pin
controller, the main CCU and the basical device tree.
Icenowy Zheng (7):
pinctrl: sunxi: refactor irq related register function to have desc
pinctrl: sunxi: support pin controllers with holes among IRQ banks
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