Add compatible string to use this generic glue layer to support
Allwinner H6 platform's dwc3 controller.
Signed-off-by: Icenowy Zheng
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-simple.c
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts
Pine H64 board have a USB3 port, which is connected to the USB3 pins of
the H6 SoC, and the 5V power supply is controlled via GPIO (shared with
the power USB ports).
Enable this port.
Signed-off-by: Icenowy Zheng
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 23 +++
1
于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard 写到:
>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>> DE2 in A64 has clock control unit and behavior is
>> same like H3/H5, so reuse the same in A64.
>>
>> Signed-off-by: Jagan Teki
>> ---
>>
于 2018年5月2日 GMT+08:00 下午7:48:43, Maxime Ripard 写到:
>On Mon, Apr 30, 2018 at 05:10:52PM +0530, Jagan Teki wrote:
>> From: Icenowy Zheng
>>
>> Allwinner SoCs with DWC HDMI controller have a "HVCC" power pin for
>the
>> HDMI part, and on some boards
于 2018年5月2日 GMT+08:00 下午7:50:19, Jagan Teki 写到:
>On Wed, May 2, 2018 at 5:04 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard
> 写到:
>>>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>>>> DE2 in A64 has
CCU driver is introduced. As the
PRCM clock part is totally different with older SoCs (from A31 to H5),
the driver for H6 is a new one, not reusing the old code.
Icenowy Zheng (7):
clk: sunxi-ng: add support for H6 PRCM CCU
arm64: allwinner: h6: add PRCM CCU device node
pinctrl: sunxi: add supp
. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt| 3 +-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile | 1
Allwinner H6 has also a PRCM CCU.
Add its device node into the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.
Add support for it.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers
Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
GPIO banks.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b
Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
A64 SoC, but has its base address changed due to the memory map change
in H6.
Add it into the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +
1 file changed, 9
Pine H64 board has a PCF8563 dedicated RTC connected to its R_I2C bus.
Enable the R_I2C bus and add the RTC to the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot
Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
are used in the reference design to connect AXP805 PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20
1 file changed, 20 insertions(+)
diff
driver still has some problems to support the LCDs, the
real LCD device nodes are not added to the device tree files.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/Makefile | 2 +
arch/arm/boot/dts/sun8i-a33-q8-tablet-1024x600.dts | 49 ++
arch/arm
于 2017年8月18日 GMT+08:00 下午2:21:07, Chen-Yu Tsai 写到:
>Hi,
>
>On Wed, Aug 9, 2017 at 4:56 PM, Icenowy Zheng wrote:
>> When claiming SRAM, if the base is set to an error, it means that the
>> SRAM controller has been probed, but failed to remap the controller
>> memor
.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
adds USB host ports support.
Icenowy Zheng (5):
ARM: sun8i: r40: add USB host port nodes for R40
ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
ARM: sun8i: v40: add 5V regulator for Banana Pi M2 Berry
ARM: sun8i: r40: enable USB host for Banana Pi M2 Ultra
ARM: sun8i: v40: enable
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
Changes
.
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
---
Changes in v2:
- Added Chen-Yu's review tag.
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 12
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64
Banana Pi M64 board uses an AXP803 PMIC.
Enable the PMIC and its regulators.
As we have now proper regulators support, missing or dummy regulators
are changed to the correct ones.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed vdd-cpux constraints.
- Added vcc-1v2-hsic regulator
.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
b/arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts
index ec72ca8c8b30
于 2017年7月25日 GMT+08:00 下午10:31:27, Maxime Ripard
写到:
>On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote:
>> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io wrote:
>> > 在 2017-07-24 15:58，Maxime Ripard 写道：
>> > > On Sat, Jul 22, 2017 at 1
patch does the conversion of the driver to a platform driver,
and the second patch adds the regmap.
Icenowy Zheng (2):
clk: sunxi-ng: r40: rewrite init code to a platform driver
clk: sunxi-ng: r40: export a regmap to access the GMAC register
drivers/clk/sunxi-ng/ccu-sun8i-r40.c | 69
There's a GMAC configuration register, which exists on A64/A83T/H3/H5 in
the syscon part, in the CCU of R40 SoC.
Export a regmap of the CCU.
Read access is not restricted to all registers, but only the GMAC
register is allowed to be written.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi
As we need to register a regmap on the R40 CCU, there needs to be a
device structure bound to the CCU device node.
Rewrite the R40 CCU driver initial code to make it a proper platform
driver, thus we will have a platform device bound to it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 178 ++
arch/arm/boot/dts/sun8i-r40.dtsi
. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Dropped all max-frequency properties in MMC nodes.
Changes in v2
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Added 3.3V vqmmc regulator for mmc2 (eMMC).
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts
于 2017年10月5日 GMT+08:00 下午2:58:01, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> 于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
>> 写到:
>>>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>>>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>
于 2017年10月8日 GMT+08:00 上午6:37:46, "Levin, Alexander (Sasha Levin)"
写到:
>From: Icenowy Zheng
>
>[ Upstream commit c429ceb1e18252122ba96b52e689dcf87103c186 ]
>
>As 64-bit Allwinner H5 SoC has the same DMA engine with H3, the DMA
>driver should be allowed to be built
Allwinner R40 features a USB PHY like the one in A64, but with 3 PHYs.
Add support for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
drivers/phy/allwinner/phy-sun4i-usb.c | 12
2 files changed, 13 insertions
for the two boards, and
the fifth and sixth patch finally adds USB host ports support.
Icenowy Zheng (6):
phy: sun4i-usb: add support for R40 USB PHY
ARM: sun8i: r40: add USB host port nodes for R40
ARM: sun8i: r40: add 5V regulator for Banana Pi M2 Ultra
ARM: sun8i: v40: add 5V regulator
From: Icenowy Zheng
Banana Pi M2 Ultra board features two USB host ports, connected to the
two USB host ports on the SoC.
Add support for them.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 22 ++
1 file changed, 22 insertions
From: Icenowy Zheng
Allwinner R40 SoC features a USB OTG port and two USB HOST ports.
Add support for the host ports in the DTSI file.
The OTG controller still cannot work with existing compatibles, and needs
more investigation. So it's not added yet.
Signed-off-by: Icenowy Zheng
---
arch
.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
b/arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts
index 7b52608cebe6..035599d870b9 100644
On the Banana Pi M2 Berry board, the 5V power output (used by HDMI, SATA
and USB) is controlled via a GPIO.
Add regulator node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot
Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A
ports, and it's connected to the USB1 port of the SoC.
Enable it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm
Allwinner R40 SoC has an AHCI SATA controller like the one in A10/A20,
but with a reset control and two dedicated VDD pins for this controller
(one 1.2v and one 2.5v).
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/ata/ahci_sunxi.c | 118
generic platform AHCI
controller binding document.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/ata/ahci-platform.txt | 1 -
.../bindings/ata/allwinner,sun4i-a10-ahci.txt | 40 ++
2 files changed, 40 insertions(+), 1 deletion(-)
create mode 100644
in
mainline kernel so I think it's safe to change the name.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun6i-a31-r.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-a23-r.c | 4 ++--
drivers/pinctrl/sunxi/pinctrl-sun8i-h3-r.c | 4 ++--
3 files changed, 6 insertions(+), 6 deleti
ty now due to no TVE)
The last 6 patches are only used for testing this patchset, and they're
going to be sent by Jernej Skrabec after this patchset is applied.
Icenowy Zheng (9):
dt-bindings: update the binding for Allwinner H3 DE2 support
drm: sun4i: add support for H3 mixers
drm: sun4i: a
From: Icenowy Zheng
Allwinner H3 has two special TCONs without channel 0.
Add support for this kind of TCON.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
drivers/gpu/drm/sun4i/sun4i_tcon.c | 43 +++---
drivers/gpu/drm/sun4i
Add a compatible string for H3 display engine in sun4i_drv code.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/sun4i/sun4i_drv.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/sun4i/sun4i_drv.c
b/drivers/gpu/drm/sun4i/sun4i_drv.c
index fd99fe8a4df7..02c80bb7b385 100644
The CLK_PLL_DE is needed to be referenced in device tree for H3, for
both forcing the parent of PLL_DE.
So export it to the device tree binding header.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.h | 3 +--
include/dt-bindings/clock/sun8i-h3-ccu.h | 2 ++
2 files
_DE to set CLK_PLL_DE (add CLK_SET_RATE_PARENT to it).
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
b/drivers/clk/sunxi-ng/ccu-sun8i-h3.c
index d1ab0d713fa6..b1127e862
As we have already the support for the DE2 on Allwinner H3, add the
display engine pipeline device tree nodes to its DTSI file.
The H5 pipeline has some differences and will be enabled later.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 170
From: Jernej Skrabec
Some custom phys don't support hpd interrupts. Add support for polling
such events.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
From: Jernej Skrabec
Some platform glues of DesignWare HDMI controller require some
initialization to be performed before probing the main HDMI controller.
Add a pre_init function for this kind of work.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 3 +++
From: Jernej Skrabec
When setting the HDMI clock of H3, the PLL_VIDEO clock needs to be set.
Add CLK_SET_RATE_PARENT flag for H3 HDMI clock.
Signed-off-by: Jernej Skrabec
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-h3.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion
From: Jernej Skrabec
Allwinner H3 features DesignWare HDMI Transmitter paired with custom
PHY.
For now, only video is supported by the driver. However, audio and CEC
are also supported by the hardware.
Signed-off-by: Jernej Skrabec
---
drivers/gpu/drm/sun4i/Kconfig | 9 +
The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glues.
Add the related device nodes.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3
Orange Pi PC board has a HDMI-A port connected to the HDMI controller of
Allwinner H3 SoC.
Enable the HDMI output in Orange Pi PC device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI. There's also some graphics post-process
function that is missing on mixer1, however, as we currently support
none of these functions, the only difference that is shown
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++
1 file changed, 21 insert
kernel.org
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index c86d3c42a905..496ba34e1f5f 100644
--- a/drivers/pinctrl/sunxi/pin
, then adds the interrupt to the device tree of
Orange Pi Zero.
Icenowy Zheng (1):
dt-bindings: add device tree binding for Allwinner XR819 SDIO Wi-Fi
Sergey Matyukevich (1):
ARM: sun8i: h2+: specify wifi interrupts for Orange Pi Zero
.../bindings/net/wireless/allwinner,xr819.txt | 38
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
Acked-by: Rob
-by: Icenowy Zheng
---
Changes in v3 by Icenowy:
- Change the compatible string vendor prefix to "allwinner".
- Modify the commit message.
Changes in v2 by Sergey:
- Adds the compatible string.
arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 3 +++
1 file changed, 3 insertions(+)
于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo 写到:
>Icenowy Zheng writes:
>
>> Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to
>use
>> an out-of-band interrupt pin instead of SDIO in-band interrupt.
>>
>> Add the device tree bindi
于 2017年10月4日 GMT+08:00 下午6:11:45, Maxime Ripard
写到:
>On Wed, Oct 04, 2017 at 10:02:48AM +, Arend van Spriel wrote:
>> On 10/4/2017 11:03 AM, Icenowy Zheng wrote:
>> >
>> >
>> > 于 2017年10月4日 GMT+08:00 下午5:02:17, Kalle Valo
>写到:
>> > >
The R40 SoC has a watchdog like the one on A20, in the timer memory zone
(which is also the same on A20).
Add the device tree node for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-r40.dtsi | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-r40.dtsi
Currently the rtl8723bs driver will print "nolinked power save enter"
and "nolinked power save leave" per minute if it's not connected to any
network.
These messages are meaningless and annoying to regular users.
Hide them when it's not debugging.
Signed-off-by: Icenowy
Allwinner A64's DE2 needs to claim a section of SRAM (SRAM C) to work.
Add support for it.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 32
1 file changed, 24 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun8i
A64's Display Engine 2.0 needs a section of SRAM (SRAM C) to be claimed.
Add binding for this.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/sun8i-de2.txt
. It retains most if not all features from the A20, while adding
some new features, such as MIPI DSI output, or updating various
hardware blocks, such as DE 2.0.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Change the MMC frequencies to conservative verified values.
- Add
: Add board dts file for Banana Pi M2 Ultra
Icenowy Zheng (1):
ARM: dts: sun8i: Add board dts file for Banana Pi M2 Berry
arch/arm/boot/dts/Makefile| 4 +-
arch/arm/boot/dts/sun8i-r40-bananapi-m2-ultra.dts | 177 ++
arch/arm/boot/dts/sun8i-r40.dtsi
control buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Chen-Yu Tsai
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet.
arch/arm/boot/dts/Makefile| 1 +
arch/arm/boot/dts
headphone jack
- red and green LEDs
- debug UART pins
- Raspberry Pi B+ compatible GPIO header
- power and reset buttons
This patch adds a dts file that enables UART, MMC and PMIC support.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the vcc5v0 regulator, as it's not used yet
于 2017年9月28日 GMT+08:00 下午11:12:25, Maxime Ripard
写到:
>On Thu, Sep 28, 2017 at 09:25:42AM +0000, Icenowy Zheng wrote:
>> + {
>> +vmmc-supply = <_dcdc1>;
>> +bus-width = <8>;
>> +non-removable;
>> +status = "okay";
&
于 2017年9月28日 GMT+08:00 下午11:11:03, Maxime Ripard
写到:
>Hi,
>
>On Thu, Sep 28, 2017 at 09:25:41AM +, Icenowy Zheng wrote:
>> +/*
>> + * The max-frequency properties in all MMC controller nodes
>> + * are conservative values pro
于 2018年1月7日 GMT+08:00 上午6:12:57, Hans de Goede 写到:
>Hi,
>
>On 05-01-18 17:56, Icenowy Zheng wrote:
>> The UAS mode of Norelsys NS1068(X) is reported to fail to work on
>> several platforms with the following error message:
>>
>> xhci-hcd xhci-hcd.0.auto: ERROR
As DE2 support for more SoCs are introducing, there's many reports that
the DE2 is not functional due to DE2 CCU code not included in kernel.
Defaultly enable DE2 CCU for sun8i/sun50i to reduce this kind of
problems.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/Kconfig | 2 ++
1 file
在 2018年1月11日星期四 CST 下午5:36:39，Linus Walleij 写道：
> On Sat, Jan 6, 2018 at 5:18 AM, Icenowy Zheng wrote:
> > This patchset adds initial support for the Allwinner H6 SoC.
>
> Can I apply the pin control patches without the clock patches?
I think it's OK.
Note: on H6 now the pi
于 2018年1月11日 GMT+08:00 下午6:08:19, Andre Przywara 写到:
>Hi,
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs one)
>> have no bus gate clocks.
>>
>> Add support for this kind of pin controllers.
&g
在 2018年1月11日星期四 CST 下午6:41:00，Maxime Ripard 写道：
> On Thu, Jan 11, 2018 at 10:23:52AM +, Andre Przywara wrote:
> > Hi,
> >
> > On 11/01/18 10:14, Chen-Yu Tsai wrote:
> > > On Thu, Jan 11, 2018 at 6:08 PM, Andre Przywara
wrote:
> > >> Hi,
> > &
于 2018年1月11日 GMT+08:00 下午7:48:40, Andre Przywara 写到:
>Hi,
>
>another take to avoid this patch at all, I just remembered this from an
>IRC discussion before:
>
>On 06/01/18 04:23, Icenowy Zheng wrote:
>> The Allwinner H6 pin controllers (both the main one and the CPUs
-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 525 +
4 files
在 2017-11-28 17:02，Maxime Ripard 写道：
Hi,
On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
>
在 2017-11-28 04:57，Jernej Skrabec 写道：
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or
not.
This new property will tell which set of base addresses to take.
0 - first mixer or second mixer with VEP support
于 2018年1月5日 GMT+08:00 上午2:52:10, Maxime Ripard
写到:
>On Wed, Jan 03, 2018 at 10:32:26PM +0100, Jernej Škrabec wrote:
>> Hi Rob,
>>
>> Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> > On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > > This commit
于 2018年1月4日 GMT+08:00 上午5:32:26, "Jernej Škrabec" 写到:
>Hi Rob,
>
>Dne sreda, 03. januar 2018 ob 21:21:54 CET je Rob Herring napisal(a):
>> On Sat, Dec 30, 2017 at 10:01:58PM +0100, Jernej Skrabec wrote:
>> > This commit adds all necessary compatibles and descriptions needed
>to
>> > implement
-by: Icenowy Zheng
---
The NS1066 chip from the same vendor seems to also suffer from this
problem (its USB ID is 2537:1066) according to the report of Armbian
community. However I don't have such device (I have a USB HDD enclosure
with USB ID 2537:1066, but it doesn't report UAS function at all
).
This patchset adds the most basical support for it, including the main pin
controller, the main CCU and the basical device tree.
Icenowy Zheng (7):
pinctrl: sunxi: add support for pin controllers without bus gate
pinctrl: sunxi: support pin controllers with holes among IRQ banks
pinctrl
The Allwinner H6 pin controllers (both the main one and the CPUs one)
have no bus gate clocks.
Add support for this kind of pin controllers.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sunxi.c | 30 --
drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1
to hardware IRQ bank map, so
the new situation in H6 main pin controller can be processed. The old
special situation which uses a constant offset (on A33 and V3s, both
with a offset of 1) can be also processed with the new code.
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-a33.c
t.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 4 +-
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 679
On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks
(modelled as NKMP with no K) and have fixed post-dividers.
Add fixed post divider support to the NKMP style clocks.
Signed-off-by: Icenowy Zheng
---
drivers/clk/sunxi-ng/ccu_nkmp.c | 20 +---
drivers/clk/sunxi-ng
The Allwinner H6 SoC has a CCU which has been largely rearranged.
Add support for it in the sunxi-ng CCU framework.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt|1 +
drivers/clk/sunxi-ng/Kconfig |5 +
drivers/clk/sunxi-ng
Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its
memory map fully reworked and some high-speed peripherals (PCIe, USB
3.0) introduced.
This commit adds the basical DTSI file of it, including the clock
support and UART support.
Signed-off-by: Icenowy Zheng
---
arch/arm64
and "Expansion" pin header
- 2 USB 2.0 ports and 1 USB 3.0 ports
- Audio jack
- MicroSD slot and eMMC module slot
- on-board SPI NOR flash
- 1Gbps Ethernet port (via RTL8211E PHY)
- HDMI port
Adds initial support for it, including the UART on the Expansion pin
header.
Signed-off-by: Icenowy Z
As the PHY dual-route property is added to 4.15-rc, the EHCI/OHCI nodes
are now necessary.
Please apply these patches to 4.15, Thanks!
Icenowy Zheng (2):
ARM: sun8i: v3s: add EHCI/OHCI0 device nodes
ARM: sun8i: v3s: enable EHCI/OHCI for Lichee Pi Zero
arch/arm/boot/dts/sun8i-v3s-licheepi
The USB PHY 0 on V3s SoC can also be routed to a pair of EHCI/OHCI
controllers.
Add the device nodes for the controllers.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s.dtsi | 19 +++
1 file changed, 19 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi
As the USB port on Lichee Pi Zero works in the OTG mode, enable the
EHCI/OHCI controllers for it.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-v3s-licheepi-zero.dts
b/arch/arm
CH 8 to 11 are for Allwinner A64 SoC to enable SimpleFB.
Icenowy Zheng (11):
dt-bindings: fix the binding of Allwinner DE2 CCU of A83T and H3
clk: sunxi-ng: add support for Allwinner H3 DE2 CCU
clk: sunxi-ng: fix the A64/H5 clock description of DE2 CCU
dt-bindings: simplefb-sunxi: add pipelin
the binding example's
compatible from A83T to H3 (as it specifies the DE module clock).
Fixes: ed74f8a8a679 ("dt-bindings: add binding for the Allwinner DE2 CCU")
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/clock/sun8i-de2.txt | 5 +++--
1 file changed, 3 insert
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