The H3 SoC has a DesignWare HDMI controller with some Allwinner-specific
glues.
Add the related device nodes.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/boot/dts/sun8i-h3
Orange Pi PC board has a HDMI-A port connected to the HDMI controller of
Allwinner H3 SoC.
Enable the HDMI output in Orange Pi PC device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-h3-orangepi-pc.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch
From: Icenowy Zheng
Allwinner H3 SoC has two mixers, one has 1 VI channel and 3 UI channels,
and the other has 1 VI and 1 UI. There's also some graphics post-process
function that is missing on mixer1, however, as we currently support
none of these functions, the only difference that is sho
Allwinner H3 features a "Display Engine 2.0".
Add device tree bindings for the following parts:
- H3 TCONs
- H3 Mixers
- H3 Display engine
Signed-off-by: Icenowy Zheng
---
.../bindings/display/sunxi/sun4i-drm.txt | 25 ++
1 file changed, 21 insert
vger.kernel.org
Signed-off-by: Icenowy Zheng
---
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
b/drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c
index c86d3c42a905..496ba34e1f5f 100644
--- a/drivers/pinctrl/sunx
于 2017年8月3日 GMT+08:00 上午3:06:26, "Jernej Škrabec" 写到:
>Hi,
>
>Dne sreda, 02. avgust 2017 ob 07:02:39 CEST je icen...@aosc.io
>napisal(a):
>> 在 2017-08-02 12:53，Jernej Škrabec 写道：
>>
>> > Hi Icenowy,
>> >
>> > Dne torek, 01. avgus
Allwinner XR819 is a SDIO Wi-Fi chip, which has the functionality to use
an out-of-band interrupt pin instead of SDIO in-band interrupt.
Add the device tree binding of this chip, in order to make it possible
to add this interrupt pin to device trees.
Signed-off-by: Icenowy Zheng
---
Changes in
于 2017年6月15日 GMT+08:00 上午11:54:08, Vinod Koul 写到:
>On Wed, Jun 14, 2017 at 11:04:39AM +0200, Maxime Ripard wrote:
>> On Wed, Jun 14, 2017 at 02:15:29PM +0530, Vinod Koul wrote:
>> > > SoC info is in compatible, so there's no reason to make it a
>property.
>> >
>> > that's why it would need to b
SoCs doesn't have extra xtal input for EPHY, and the
main xtal is 24MHz. The default value of H3 is set to 24MHz, but the V3s
default value is set to 25MHz).
First two patches are device tree binding patches, the third forces
the frequency to 24MHz and the fourth really add the V3s support.
Ic
Allwinner V3s SoC has a Ethernet MAC like the one in Allwinner H3, but
have no external MII capability. That means that it can only use the
EPHY and cannot do Gbps transmission.
Add binding for it.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/net/dwmac-sun8i.txt | 10
Allwinner V3s SoC has a syscon like the one in H3.
Add its compatible string.
Signed-off-by: Icenowy Zheng
---
Documentation/devicetree/bindings/misc/allwinner,syscon.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/misc/allwinner,syscon.txt
b
rly.
Force the EPHY clock frequency to 24MHz.
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
ind
-related register seems to have
changed from H3, but it seems to be a harmless change.
Signed-off-by: Icenowy Zheng
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 8
drivers/net/ethernet/stmicro/stmmac/stmmac_platform.c | 1 +
2 files changed, 9 insertions(+)
diff --git a/drivers
于 2017年7月25日 GMT+08:00 下午10:31:27, Maxime Ripard
写到:
>On Tue, Jul 25, 2017 at 05:18:19AM +0200, Adam Borowski wrote:
>> On Tue, Jul 25, 2017 at 11:04:24AM +0800, icen...@aosc.io wrote:
>> > 在 2017-07-24 15:58，Maxime Ripard 写道：
>> > > On Sat, Jul 22, 2017 at 1
于 2017年7月26日 GMT+08:00 下午3:08:06, Chen-Yu Tsai 写到:
>On Sun, Jul 23, 2017 at 6:27 PM, Icenowy Zheng wrote:
>> From: Ondrej Jirman
>>
>> Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on
>> Orange Pi PC, then set the power supply of the ARM cores to thi
于 2017年7月28日 GMT+08:00 下午5:44:51, Chen-Yu Tsai 写到:
>On Fri, Jul 28, 2017 at 5:28 PM, Corentin Labbe
> wrote:
>> This patch adds the sun8i-h3-ephy compatible to the internal PHY.
>>
>> Signed-off-by: Corentin Labbe
>> ---
>> arch/arm/boot/dts/sunxi-h3-h5.dtsi | 3 ++-
>
>To avoid repeating the p
-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers/pinctrl/sunxi/Makefile | 1 +
drivers/pinctrl/sunxi/pinctrl-sun50i-h6.c | 525 +
4 files
在 2017-11-28 17:02，Maxime Ripard 写道：
Hi,
On Mon, Nov 27, 2017 at 05:01:49PM +0100, Jernej Škrabec wrote:
Dne ponedeljek, 27. november 2017 ob 16:41:35 CET je Maxime Ripard
napisal(a):
> Add support for the A83T display pipeline.
>
> Reviewed-by: Chen-Yu Tsai
> Signed-off-by: Maxime Ripard
>
在 2017-11-28 04:57，Jernej Skrabec 写道：
Base addresses of channel output CSC (CCSC) depends whether mixer in
question is first or second and if it is second, if supports VEP or
not.
This new property will tell which set of base addresses to take.
0 - first mixer or second mixer with VEP support
在 2017-11-08 18:56，Maxime Ripard 写道：
Hi,
On Tue, Nov 07, 2017 at 05:38:55PM +0100, Giulio Benetti wrote:
Board could be any with A20,
for example Olinuxino A20.
Or our Q027, S027 boards, but final dts still are not complete.
Therefore no upstream boards are using it right now, so we'll merge
On several A64 boards the Ethernet PHY is powered by the DC1SW regulator
on the AXP803 PMIC.
Add phy-handle property to these boards' emac node.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 1 +
arch/arm64/boot/dts/allwinner/sun50i-a64-p
于 2017年11月7日 GMT+08:00 上午11:13:23, Chen-Yu Tsai 写到:
On Tue, Nov 7, 2017 at 6:39 AM, Martin Blumenstingl
wrote:
Hello,
recently I discovered that there are some X-Powers AXP chips that
support both, Allwinner's own "RSB" as well as the I2C ("TWSI" in the
datasheet) busses.
one chip that supp
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