[PATCH v3 1/3] alpha: Use OPTIMIZE_INLINING instead of asm/compiler.h

44 +16 cap_capset 488 500 +12 nonroot_raised_pE.constprop 348 --348 Total: Before=5823709, After=5823625, chg -0.00% Suggested-by: Arnd Bergmann Signed-off-by: James Hogan Cc: Richard Henderson Cc: Ivan Kokshaysky Cc: Matt

[PATCH v3 2/3] compiler.h: Allow arch-specific overrides

for all architectures except alpha, arm, arm64, and mips (which already have an asm/compiler.h) and leaves the architecture specifics to a further patch. Signed-off-by: Paul Burton [jho...@kernel.org: Forward port and use asm/compiler.h instead of asm/compiler-gcc.h] Signed-off-by: James Hogan

Re: [PATCH 2/2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote: > The __clear_user function is defined to return the number of bytes that > could not be cleared. From the underlying memset / bzero implementation > this means setting register a2 to that number on return. Currently if a > page fault

Re: [PATCH 2/2] MIPS: memset.S: Fix return of __clear_user from Lpartial_fixup

On Thu, Mar 29, 2018 at 10:28:24AM +0100, Matt Redfearn wrote: > The __clear_user function is defined to return the number of bytes that > could not be cleared. From the underlying memset / bzero implementation > this means setting register a2 to that number on return. Currently if a > page fault

Re: [PATCH 1/2] MIPS: memset.S: EVA & fault support for small_memset

On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote: > @@ -260,6 +260,11 @@ > jr ra > andiv1, a2, STORMASK This patch looks good, well spotted! But whats that v1 write about? Any ideas? Seems to go back to the git epoch, and $3 isn't in the clobber

Re: [PATCH 1/2] MIPS: memset.S: EVA & fault support for small_memset

On Thu, Mar 29, 2018 at 10:28:23AM +0100, Matt Redfearn wrote: > @@ -260,6 +260,11 @@ > jr ra > andiv1, a2, STORMASK This patch looks good, well spotted! But whats that v1 write about? Any ideas? Seems to go back to the git epoch, and $3 isn't in the clobber

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote: > On 4/12/2018 10:30 PM, Sinan Kaya wrote: > > + /* prevent prefetching of coherent DMA dma prematurely */ \ > > I tried to write DMA data but my keyboard is not cooperating. I'll hold onto > posting another version until I hear

Re: [PATCH v4 2/2] MIPS: io: add a barrier after register read in readX()

On Thu, Apr 12, 2018 at 10:33:42PM -0400, Sinan Kaya wrote: > On 4/12/2018 10:30 PM, Sinan Kaya wrote: > > + /* prevent prefetching of coherent DMA dma prematurely */ \ > > I tried to write DMA data but my keyboard is not cooperating. I'll hold onto > posting another version until I hear

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Thu, Apr 12, 2018 at 10:51:49PM +0100, James Hogan wrote: > On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote: > > While a barrier is present in writeX() function before the register write, > > a similar barrier is missing in the readX() function after the register >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Thu, Apr 12, 2018 at 10:51:49PM +0100, James Hogan wrote: > On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote: > > While a barrier is present in writeX() function before the register write, > > a similar barrier is missing in the readX() function after the register >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote: > While a barrier is present in writeX() function before the register write, > a similar barrier is missing in the readX() function after the register > read. This could allow memory accesses following readX() to observe > stale data. >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Tue, Apr 03, 2018 at 08:55:04AM -0400, Sinan Kaya wrote: > While a barrier is present in writeX() function before the register write, > a similar barrier is missing in the readX() function after the register > read. This could allow memory accesses following readX() to observe > stale data. >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Wed, Apr 11, 2018 at 01:10:41PM -0400, Sinan Kaya wrote: > How is the likelihood of getting this fixed on 4.17 kernel? High. Thanks James signature.asc Description: Digital signature

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Wed, Apr 11, 2018 at 01:10:41PM -0400, Sinan Kaya wrote: > How is the likelihood of getting this fixed on 4.17 kernel? High. Thanks James signature.asc Description: Digital signature

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

On Wed, Apr 11, 2018 at 12:08:51PM +0200, Arnd Bergmann wrote: > On Wed, Apr 11, 2018 at 11:54 AM, James Hogan <jho...@kernel.org> wrote: > > On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote: > >> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan <jho...@kernel.

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

On Wed, Apr 11, 2018 at 12:08:51PM +0200, Arnd Bergmann wrote: > On Wed, Apr 11, 2018 at 11:54 AM, James Hogan wrote: > > On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote: > >> On Wed, Apr 11, 2018 at 12:48 AM, James Hogan wrote: > >> > Before I for

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote: > On Wed, Apr 11, 2018 at 12:48 AM, James Hogan <jho...@kernel.org> wrote: > > Before I forward port those patches to add .insn for MIPS, is that sort > > of approach (an arch specific asm/compiler-gcc.h to allow

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

On Wed, Apr 11, 2018 at 09:30:56AM +0200, Arnd Bergmann wrote: > On Wed, Apr 11, 2018 at 12:48 AM, James Hogan wrote: > > Before I forward port those patches to add .insn for MIPS, is that sort > > of approach (an arch specific asm/compiler-gcc.h to allow MIPS

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

Hi Arnd, On Tue, Dec 19, 2017 at 12:39:33PM +0100, Arnd Bergmann wrote: > diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h > index 5d595cfdb2c4..66cfdad68f7e 100644 > --- a/include/linux/compiler-gcc.h > +++ b/include/linux/compiler-gcc.h > @@ -205,6 +205,15 @@ > #endif >

Re: [PATCH] bug.h: Work around GCC PR82365 in BUG()

Hi Arnd, On Tue, Dec 19, 2017 at 12:39:33PM +0100, Arnd Bergmann wrote: > diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h > index 5d595cfdb2c4..66cfdad68f7e 100644 > --- a/include/linux/compiler-gcc.h > +++ b/include/linux/compiler-gcc.h > @@ -205,6 +205,15 @@ > #endif >

Re: [PATCH AUTOSEL for 4.9 173/293] MIPS: Handle tlbex-tlbp race condition

On Mon, Apr 09, 2018 at 12:25:09AM +, Sasha Levin wrote: > From: Paul Burton > > [ Upstream commit f39878cc5b09c75d35eaf52131e920b872e3feb4 ] > > In systems where there are multiple actors updating the TLB, the > potential exists for a race condition wherein a CPU

Re: [PATCH AUTOSEL for 4.9 173/293] MIPS: Handle tlbex-tlbp race condition

On Mon, Apr 09, 2018 at 12:25:09AM +, Sasha Levin wrote: > From: Paul Burton > > [ Upstream commit f39878cc5b09c75d35eaf52131e920b872e3feb4 ] > > In systems where there are multiple actors updating the TLB, the > potential exists for a race condition wherein a CPU hits a TLB exception > but

Re: [PATCH AUTOSEL for 4.9 160/293] MIPS: Give __secure_computing() access to syscall arguments.

On Mon, Apr 09, 2018 at 12:24:58AM +, Sasha Levin wrote: > From: David Daney > > [ Upstream commit 669c4092225f0ed5df12ebee654581b558a5e3ed ] > > KProbes of __seccomp_filter() are not very useful without access to > the syscall arguments. > > Do what x86 does, and

Re: [PATCH AUTOSEL for 4.9 160/293] MIPS: Give __secure_computing() access to syscall arguments.

On Mon, Apr 09, 2018 at 12:24:58AM +, Sasha Levin wrote: > From: David Daney > > [ Upstream commit 669c4092225f0ed5df12ebee654581b558a5e3ed ] > > KProbes of __seccomp_filter() are not very useful without access to > the syscall arguments. > > Do what x86 does, and populate a struct

Re: [PATCH AUTOSEL for 4.15 048/189] clk: ingenic: Fix recalc_rate for clocks with fixed divider

On Mon, Apr 09, 2018 at 12:17:24AM +, Sasha Levin wrote: > From: Paul Cercueil > > [ Upstream commit e6cfa64375d34a6c8c1861868a381013b2d3b921 ] > > Previously, the clocks with a fixed divider would report their rate > as being the same as the one of their parent,

Re: [PATCH AUTOSEL for 4.15 048/189] clk: ingenic: Fix recalc_rate for clocks with fixed divider

On Mon, Apr 09, 2018 at 12:17:24AM +, Sasha Levin wrote: > From: Paul Cercueil > > [ Upstream commit e6cfa64375d34a6c8c1861868a381013b2d3b921 ] > > Previously, the clocks with a fixed divider would report their rate > as being the same as the one of their parent, independently of the >

Re: [PATCH AUTOSEL for 4.14 043/161] MIPS: JZ4770: Work around config2 misreporting associativity

On Mon, Apr 09, 2018 at 12:20:20AM +, Sasha Levin wrote: > From: Maarten ter Huurne > > [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ] > > According to config2, the associativity would be 5-ways, but the > documentation states 4-ways, which also matches

Re: [PATCH AUTOSEL for 4.14 043/161] MIPS: JZ4770: Work around config2 misreporting associativity

On Mon, Apr 09, 2018 at 12:20:20AM +, Sasha Levin wrote: > From: Maarten ter Huurne > > [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ] > > According to config2, the associativity would be 5-ways, but the > documentation states 4-ways, which also matches the documented > L2

Re: [PATCH AUTOSEL for 4.14 041/161] MIPS: Fix clean of vmlinuz.{32,ecoff,bin,srec}

Hi Sasha, On Mon, Apr 09, 2018 at 12:20:18AM +, Sasha Levin wrote: > From: James Hogan <jho...@kernel.org> > > [ Upstream commit 5f2483eb2423152445b39f2db59d372f523e664e ] > > Make doesn't expand shell style "vmlinuz.{32,ecoff,bin,srec}" to the 4 > separate

Re: [PATCH AUTOSEL for 4.14 041/161] MIPS: Fix clean of vmlinuz.{32,ecoff,bin,srec}

Hi Sasha, On Mon, Apr 09, 2018 at 12:20:18AM +, Sasha Levin wrote: > From: James Hogan > > [ Upstream commit 5f2483eb2423152445b39f2db59d372f523e664e ] > > Make doesn't expand shell style "vmlinuz.{32,ecoff,bin,srec}" to the 4 > separate files, so none of these

Re: [PATCH] MIPS: vmlinuz: Fix compiler intrinsics location and build directly

On Thu, Apr 05, 2018 at 10:42:19PM +0100, James Hogan wrote: > On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote: > > Actually, this patch would be better inserted as patch 3 in the series > > since it can pull in the generic ashldi3 before the MIPS one is removed &

Re: [PATCH] MIPS: vmlinuz: Fix compiler intrinsics location and build directly

On Thu, Apr 05, 2018 at 10:42:19PM +0100, James Hogan wrote: > On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote: > > Actually, this patch would be better inserted as patch 3 in the series > > since it can pull in the generic ashldi3 before the MIPS one is removed &

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Fri, Apr 06, 2018 at 02:15:57PM -0400, Sinan Kaya wrote: > On 4/5/2018 9:34 PM, Sinan Kaya wrote: > > Can we get these merged to 4.17? > > > > There was a consensus to fix the architectures having API violation issues. > > https://www.mail-archive.com/netdev@vger.kernel.org/msg225971.html > >

Re: [PATCH v3 2/2] MIPS: io: add a barrier after register read in readX()

On Fri, Apr 06, 2018 at 02:15:57PM -0400, Sinan Kaya wrote: > On 4/5/2018 9:34 PM, Sinan Kaya wrote: > > Can we get these merged to 4.17? > > > > There was a consensus to fix the architectures having API violation issues. > > https://www.mail-archive.com/netdev@vger.kernel.org/msg225971.html > >

Re: [PATCH] MIPS: vmlinuz: Fix compiler intrinsics location and build directly

On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote: > Actually, this patch would be better inserted as patch 3 in the series > since it can pull in the generic ashldi3 before the MIPS one is removed > in the final patch. Here's an updated commit message: Thanks Matt, applied. Cheers

Re: [PATCH] MIPS: vmlinuz: Fix compiler intrinsics location and build directly

On Thu, Apr 05, 2018 at 11:13:14AM +0100, Matt Redfearn wrote: > Actually, this patch would be better inserted as patch 3 in the series > since it can pull in the generic ashldi3 before the MIPS one is removed > in the final patch. Here's an updated commit message: Thanks Matt, applied. Cheers

Re: [PATCH v5 2/3] lib: Rename compiler intrinsic selects to GENERIC_LIB_*

On Tue, Apr 03, 2018 at 03:39:34PM -0700, Palmer Dabbelt wrote: > Sorry, I'm not sure if this is the right patch -- someone suggested acking > this, but it's already Review-By me and if I understand correctly it's going > through your tree. I'm a bit new to this, but if it helps then here's a >

Re: [PATCH v5 2/3] lib: Rename compiler intrinsic selects to GENERIC_LIB_*

On Tue, Apr 03, 2018 at 03:39:34PM -0700, Palmer Dabbelt wrote: > Sorry, I'm not sure if this is the right patch -- someone suggested acking > this, but it's already Review-By me and if I understand correctly it's going > through your tree. I'm a bit new to this, but if it helps then here's a >

Re: [GIT PULL] arch: remove obsolete architecture ports

On Wed, Apr 04, 2018 at 10:38:41AM +0200, Arnd Bergmann wrote: > Also, now that the other architectures are gone, a lot of changes can > be done more easily that will be incompatible with a pure revert, so > the more time passes, the harder it will get to do that. Yes, and an out-of-tree arch

Re: [GIT PULL] arch: remove obsolete architecture ports

On Wed, Apr 04, 2018 at 10:38:41AM +0200, Arnd Bergmann wrote: > Also, now that the other architectures are gone, a lot of changes can > be done more easily that will be incompatible with a pure revert, so > the more time passes, the harder it will get to do that. Yes, and an out-of-tree arch

Re: [PATCH v5 3/3] MIPS: use generic GCC library routines from lib/

ff-by: Matt Redfearn <matt.redfe...@mips.com> > Cc: Palmer Dabbelt <pal...@sifive.com> > Cc: Matt Redfearn <matt.redfe...@mips.com> > Cc: James Hogan <jho...@kernel.org> > Cc: Ralf Baechle <r...@linux-mips.org> > Cc: linux-m...@linux-mips.org > Cc:

Re: [PATCH v5 3/3] MIPS: use generic GCC library routines from lib/

commit removes several generic GCC library routines from > arch/mips/lib/ in favour of similar routines from lib/. > > Signed-off-by: Antony Pavlov > [Matt Redfearn] Use GENERIC_LIB_* named Kconfig entries > Signed-off-by: Matt Redfearn > Cc: Palmer Dabbelt > Cc: Matt R

Re: [PATCH v4 1/3] Add notrace to lib/ucmpdi2.c

On Tue, Apr 03, 2018 at 02:51:06PM +0100, Matt Redfearn wrote: > On 29/03/18 22:59, Palmer Dabbelt wrote: > > Ah, thanks, I think I must have forgotten about this.  I assume these > > three are going through your tree? > > Yeah I think that's the plan - James will need your ack to patch 2 if >

Re: [PATCH v4 1/3] Add notrace to lib/ucmpdi2.c

On Tue, Apr 03, 2018 at 02:51:06PM +0100, Matt Redfearn wrote: > On 29/03/18 22:59, Palmer Dabbelt wrote: > > Ah, thanks, I think I must have forgotten about this.  I assume these > > three are going through your tree? > > Yeah I think that's the plan - James will need your ack to patch 2 if >

Re: [PATCH v4 3/3] MIPS: use generic GCC library routines from lib/

On Thu, Mar 29, 2018 at 11:41:23AM +0100, Matt Redfearn wrote: > This commit removes several generic GCC library routines from > arch/mips/lib/ in favour of similar routines from lib/. > diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile > index e84e12655fa8..6537e022ef62 100644 > ---

Re: [PATCH v4 3/3] MIPS: use generic GCC library routines from lib/

On Thu, Mar 29, 2018 at 11:41:23AM +0100, Matt Redfearn wrote: > This commit removes several generic GCC library routines from > arch/mips/lib/ in favour of similar routines from lib/. > diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile > index e84e12655fa8..6537e022ef62 100644 > ---

Re: [PATCH V4 Resend] ZBOOT: fix stack protector in compressed boot phase

rt = (unsigned long)(&__image_begin); > zimage_size = (unsigned long)(&__image_end) - > (unsigned long)(&__image_begin); This looks good to me, though I've Cc'd Kees as apparently the original author from commit 8779657d29c0 ("stackprotector: Introduce CONFIG_CC_STAC

Re: [PATCH V4 Resend] ZBOOT: fix stack protector in compressed boot phase

rt = (unsigned long)(&__image_begin); > zimage_size = (unsigned long)(&__image_end) - > (unsigned long)(&__image_begin); This looks good to me, though I've Cc'd Kees as apparently the original author from commit 8779657d29c0 ("stackprotector: Introduce CONFIG_CC_STAC

Re: [PATCH V3] ZBOOT: fix stack protector in compressed boot phase

On Fri, Mar 23, 2018 at 11:50:55AM +0800, Jiaxun Yang wrote: > 在 2018-03-22四的 22:21 +0000，James Hogan写道： > > Also I think it worth mentioning in the commit message the MIPS > > configuration you hit this with, presumably a Loongson one? For me > > decompress_kernel

Re: [PATCH V3] ZBOOT: fix stack protector in compressed boot phase

On Fri, Mar 23, 2018 at 11:50:55AM +0800, Jiaxun Yang wrote: > 在 2018-03-22四的 22:21 +0000，James Hogan写道： > > Also I think it worth mentioning in the commit message the MIPS > > configuration you hit this with, presumably a Loongson one? For me > > decompress_kernel

Re: [PATCH V3] ZBOOT: fix stack protector in compressed boot phase

On Fri, Mar 16, 2018 at 03:55:16PM +0800, Huacai Chen wrote: > diff --git a/arch/mips/boot/compressed/decompress.c > b/arch/mips/boot/compressed/decompress.c > index fdf99e9..5ba431c 100644 > --- a/arch/mips/boot/compressed/decompress.c > +++ b/arch/mips/boot/compressed/decompress.c > @@ -78,11

Re: [PATCH V3] ZBOOT: fix stack protector in compressed boot phase

On Fri, Mar 16, 2018 at 03:55:16PM +0800, Huacai Chen wrote: > diff --git a/arch/mips/boot/compressed/decompress.c > b/arch/mips/boot/compressed/decompress.c > index fdf99e9..5ba431c 100644 > --- a/arch/mips/boot/compressed/decompress.c > +++ b/arch/mips/boot/compressed/decompress.c > @@ -78,11

Re: [PATCH 1/2] MIPS: Introduce has_cpu_mips*_user in cpu-features.h

On Wed, Mar 21, 2018 at 10:53:03PM +0800, Jiaxun Yang wrote: > Some processors support user mode instructions ISA level witch is nit: s/witch/which/ here, below, and in the comment. Otherwise it doesn't look unreasonable. Cheers James > different with the ISA level it should be treated in

Re: [PATCH 1/2] MIPS: Introduce has_cpu_mips*_user in cpu-features.h

On Wed, Mar 21, 2018 at 10:53:03PM +0800, Jiaxun Yang wrote: > Some processors support user mode instructions ISA level witch is nit: s/witch/which/ here, below, and in the comment. Otherwise it doesn't look unreasonable. Cheers James > different with the ISA level it should be treated in

Re: [PATCH 2/2] MIPS: Loongson64: Define has_cpu_mips64r2_user for Loongson-3

On Wed, Mar 21, 2018 at 10:53:04PM +0800, Jiaxun Yang wrote: > All loongson-3 processors support mips64r2 usermode instructions. > However 3A1000 3B1000 3B1500 should be treated as mips64r1 in kernel. > > Signed-off-by: Jiaxun Yang > --- >

Re: [PATCH 2/2] MIPS: Loongson64: Define has_cpu_mips64r2_user for Loongson-3

On Wed, Mar 21, 2018 at 10:53:04PM +0800, Jiaxun Yang wrote: > All loongson-3 processors support mips64r2 usermode instructions. > However 3A1000 3B1000 3B1500 should be treated as mips64r1 in kernel. > > Signed-off-by: Jiaxun Yang > --- >

Re: [PATCH] MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770

On Sat, Mar 17, 2018 at 09:11:09PM +0100, Paul Cercueil wrote: > Since the UART addresses are the same across all Ingenic SoCs, we just > use a #ifdef CONFIG_MACH_INGENIC instead of checking for indifidual > Ingenic SoCs. s/indifidual/individual/ > --- a/arch/mips/boot/compressed/uart-16550.c >

Re: [PATCH] MIPS: Fix build with DEBUG_ZBOOT and MACH_JZ4770

On Sat, Mar 17, 2018 at 09:11:09PM +0100, Paul Cercueil wrote: > Since the UART addresses are the same across all Ingenic SoCs, we just > use a #ifdef CONFIG_MACH_INGENIC instead of checking for indifidual > Ingenic SoCs. s/indifidual/individual/ > --- a/arch/mips/boot/compressed/uart-16550.c >

Re: [PATCH v3] MIPS: ralink: fix booting on mt7621

On Wed, Mar 21, 2018 at 02:02:10PM +1100, NeilBrown wrote: > > Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 > has not been able to boot. > > This patched caused mips_cm_probe() to be called before > mt7621.c::proc_soc_init(). > > prom_soc_init() has a comment explaining

Re: [PATCH v3] MIPS: ralink: fix booting on mt7621

On Wed, Mar 21, 2018 at 02:02:10PM +1100, NeilBrown wrote: > > Since commit 3af5a67c86a3 ("MIPS: Fix early CM probing") the MT7621 > has not been able to boot. > > This patched caused mips_cm_probe() to be called before > mt7621.c::proc_soc_init(). > > prom_soc_init() has a comment explaining

Re: [PATCH] MIPS: ralink: remove ralink_halt()

On Tue, Mar 20, 2018 at 07:29:51PM +1100, NeilBrown wrote: > > ralink_halt() does nothing that machine_halt() > doesn't already do, so it adds no value. > > It actually causes incorrect behaviour due to the > "unreachable()" at the end. This tell the compiler that the > end of the function will

Re: [PATCH] MIPS: ralink: remove ralink_halt()

On Tue, Mar 20, 2018 at 07:29:51PM +1100, NeilBrown wrote: > > ralink_halt() does nothing that machine_halt() > doesn't already do, so it adds no value. > > It actually causes incorrect behaviour due to the > "unreachable()" at the end. This tell the compiler that the > end of the function will

Re: [PATCH v6 0/6] MIPS: add support for Microsemi MIPS SoCs

On Tue, Mar 20, 2018 at 02:07:55PM +0100, Alexandre Belloni wrote: > Hi, > > This patch series adds initial support for the Microsemi MIPS SoCs. It > is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514). > > Changes in v6: > - Fixup SPDX identifiers > - remove unit-address for

Re: [PATCH v6 0/6] MIPS: add support for Microsemi MIPS SoCs

On Tue, Mar 20, 2018 at 02:07:55PM +0100, Alexandre Belloni wrote: > Hi, > > This patch series adds initial support for the Microsemi MIPS SoCs. It > is currently focusing on the Microsemi Ocelot (VSC7513, VSC7514). > > Changes in v6: > - Fixup SPDX identifiers > - remove unit-address for

Re: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available

On Wed, Mar 14, 2018 at 11:15:47AM +, Marc Zyngier wrote: > Hi Matt, > > On 05/01/18 10:31, Matt Redfearn wrote: > > > > This series enables the MIPS GIC driver to make use of the EIC mode > > supported in some MIPS cores. In this mode, the cores 6 interrupt lines > > are switched to

Re: [PATCH 0/6] irqchip/mips-gic: Enable & use VEIC mode if available

On Wed, Mar 14, 2018 at 11:15:47AM +, Marc Zyngier wrote: > Hi Matt, > > On 05/01/18 10:31, Matt Redfearn wrote: > > > > This series enables the MIPS GIC driver to make use of the EIC mode > > supported in some MIPS cores. In this mode, the cores 6 interrupt lines > > are switched to

Re: [PATCH 1/2] MIPS: Allow including mach-generic/dma-coherence.h

On Tue, Jan 23, 2018 at 05:40:09PM -0800, Florian Fainelli wrote: > @@ -71,15 +83,19 @@ static inline void plat_post_dma_flush(struct device *dev) > #endif > > #ifdef CONFIG_SWIOTLB > +#ifndef phys_to_dma > static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) > { >

Re: [PATCH 1/2] MIPS: Allow including mach-generic/dma-coherence.h

On Tue, Jan 23, 2018 at 05:40:09PM -0800, Florian Fainelli wrote: > @@ -71,15 +83,19 @@ static inline void plat_post_dma_flush(struct device *dev) > #endif > > #ifdef CONFIG_SWIOTLB > +#ifndef phys_to_dma > static inline dma_addr_t phys_to_dma(struct device *dev, phys_addr_t paddr) > { >

Re: [PATCH 2/2] MIPS: Update dma-coherence.h files

On Tue, Jan 23, 2018 at 05:40:10PM -0800, Florian Fainelli wrote: > diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h > b/arch/mips/include/asm/mach-ath25/dma-coherence.h > index d5defdde32db..63bce15fa54d 100644 > --- a/arch/mips/include/asm/mach-ath25/dma-coherence.h > +++

Re: [PATCH 2/2] MIPS: Update dma-coherence.h files

On Tue, Jan 23, 2018 at 05:40:10PM -0800, Florian Fainelli wrote: > diff --git a/arch/mips/include/asm/mach-ath25/dma-coherence.h > b/arch/mips/include/asm/mach-ath25/dma-coherence.h > index d5defdde32db..63bce15fa54d 100644 > --- a/arch/mips/include/asm/mach-ath25/dma-coherence.h > +++

Re: [RFC PATCH] MIPS: Provide cmpxchg64 for 32-bit builds

On Wed, Feb 14, 2018 at 09:36:33PM +, Keller, Jacob E wrote: > > -Original Message- > > From: Michael, Alice > > Sent: Wednesday, February 14, 2018 1:03 PM > > To: Guenter Roeck <li...@roeck-us.net>; James Hogan <jho...@kernel.org>; > > Keller,

Re: [RFC PATCH] MIPS: Provide cmpxchg64 for 32-bit builds

On Wed, Feb 14, 2018 at 09:36:33PM +, Keller, Jacob E wrote: > > -Original Message- > > From: Michael, Alice > > Sent: Wednesday, February 14, 2018 1:03 PM > > To: Guenter Roeck ; James Hogan ; > > Keller, Jacob E > > Cc: Ralf Baechle ; linux

Re: [PATCH v4 1/8] SOC: brcmstb: add memory API

On Mon, Jan 15, 2018 at 06:28:38PM -0500, Jim Quinlan wrote: > From: Florian Fainelli > > This commit adds a memory API suitable for ascertaining the sizes of > each of the N memory controllers in a Broadcom STB chip. Its first > user will be the Broadcom STB PCIe root

Re: [PATCH v4 1/8] SOC: brcmstb: add memory API

On Mon, Jan 15, 2018 at 06:28:38PM -0500, Jim Quinlan wrote: > From: Florian Fainelli > > This commit adds a memory API suitable for ascertaining the sizes of > each of the N memory controllers in a Broadcom STB chip. Its first > user will be the Broadcom STB PCIe root complex driver, which

Re: [PATCH v4 7/8] MIPS: BMIPS: Add PCI bindings for 7425, 7435

On Mon, Jan 15, 2018 at 06:28:44PM -0500, Jim Quinlan wrote: > diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi > b/arch/mips/boot/dts/brcm/bcm7425.dtsi > index e4fb9b6..02168d0 100644 > --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi > +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi > @@ -495,4 +495,30

Re: [PATCH v4 7/8] MIPS: BMIPS: Add PCI bindings for 7425, 7435

On Mon, Jan 15, 2018 at 06:28:44PM -0500, Jim Quinlan wrote: > diff --git a/arch/mips/boot/dts/brcm/bcm7425.dtsi > b/arch/mips/boot/dts/brcm/bcm7425.dtsi > index e4fb9b6..02168d0 100644 > --- a/arch/mips/boot/dts/brcm/bcm7425.dtsi > +++ b/arch/mips/boot/dts/brcm/bcm7425.dtsi > @@ -495,4 +495,30

Re: [PATCH v3] MIPS: pm-cps: Block system suspend when a JTAG probe is present

On Tue, Feb 20, 2018 at 09:58:16AM +, Matt Redfearn wrote: > If a JTAG probe is connected to a MIPS cluster, then the CPC detects it > and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set, > attempting to send a power-down command to a core will be blocked, and > the CPC will instead

Re: [PATCH v3] MIPS: pm-cps: Block system suspend when a JTAG probe is present

On Tue, Feb 20, 2018 at 09:58:16AM +, Matt Redfearn wrote: > If a JTAG probe is connected to a MIPS cluster, then the CPC detects it > and latches the CPC.STAT_CONF.EJTAG_PROBE bit to 1. While set, > attempting to send a power-down command to a core will be blocked, and > the CPC will instead

Re: [PATCH 0/4] MIPS: Introduce isa-rev.h to define MIPS_ISA_REV

On Mon, Feb 26, 2018 at 05:02:41PM +, Matt Redfearn wrote: > There are multiple instances in the kernel where we need to include or > exclude particular instructions based on the ISA revision of the target > processor. For MIPS32 / MIPS64, the compiler exports a __mips_isa_rev > define.

Re: [PATCH 0/4] MIPS: Introduce isa-rev.h to define MIPS_ISA_REV

On Mon, Feb 26, 2018 at 05:02:41PM +, Matt Redfearn wrote: > There are multiple instances in the kernel where we need to include or > exclude particular instructions based on the ISA revision of the target > processor. For MIPS32 / MIPS64, the compiler exports a __mips_isa_rev > define.

[PATCH v2] kbuild: Handle builtin dtb file names containing hyphens

really build all the dtb.o files, but thats a separate issue). Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to bcm6358-neufbox4-sercom") Signed-off-by: James Hogan <jho...@kernel.org> Reviewed-by: Frank Rowand <frowand.l...@gmail.com> Cc: Rob Herring <robh...@kernel

[PATCH v2] kbuild: Handle builtin dtb file names containing hyphens

really build all the dtb.o files, but thats a separate issue). Fixes: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to bcm6358-neufbox4-sercom") Signed-off-by: James Hogan Reviewed-by: Frank Rowand Cc: Rob Herring Cc: Masahiro Yamada Cc: Michal Marek Cc: Ralf Baechle Cc: Florian Fa

Re: [PATCH] kbuild: Handle builtin dtb files containing hyphens

On Wed, Mar 07, 2018 at 03:19:11PM -0800, Frank Rowand wrote: > On 03/07/18 12:25, James Hogan wrote: > > On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote: > >> On 03/07/18 06:06, James Hogan wrote: > >>> Quite a lot of dts files have hyphens, but its only

Re: [PATCH] kbuild: Handle builtin dtb files containing hyphens

On Wed, Mar 07, 2018 at 03:19:11PM -0800, Frank Rowand wrote: > On 03/07/18 12:25, James Hogan wrote: > > On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote: > >> On 03/07/18 06:06, James Hogan wrote: > >>> Quite a lot of dts files have hyphens, but its only

MIPS DT W=1 warnings (was Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi)

Hi Rob, On Wed, Mar 07, 2018 at 10:08:28AM -0600, Rob Herring wrote: > Please compile with W=1 and fix any issues like this one which is a > unit-address without a reg property. Drop the unit-address. I was just giving the BMIPS W=1 DT warnings a look, and a few look spurious. I'd value your

MIPS DT W=1 warnings (was Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi)

Hi Rob, On Wed, Mar 07, 2018 at 10:08:28AM -0600, Rob Herring wrote: > Please compile with W=1 and fix any issues like this one which is a > unit-address without a reg property. Drop the unit-address. I was just giving the BMIPS W=1 DT warnings a look, and a few look spurious. I'd value your

Re: [PATCH] kbuild: Handle builtin dtb files containing hyphens

On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote: > I initially misread the patch description (and imagined an entirely > different problem). > > > On 03/07/18 06:06, James Hogan wrote: > > On dtb files which contain hyphens, the dt_S_dtb command to build the>

Re: [PATCH] kbuild: Handle builtin dtb files containing hyphens

On Wed, Mar 07, 2018 at 12:11:41PM -0800, Frank Rowand wrote: > I initially misread the patch description (and imagined an entirely > different problem). > > > On 03/07/18 06:06, James Hogan wrote: > > On dtb files which contain hyphens, the dt_S_dtb command to build the>

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote: > On 07/03/2018 at 15:17:56 +0000, James Hogan wrote: > > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote: > > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > > > b/arch/mip

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

On Wed, Mar 07, 2018 at 04:27:51PM +0100, Alexandre Belloni wrote: > On 07/03/2018 at 15:17:56 +0000, James Hogan wrote: > > On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote: > > > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > > > b/arch/mip

Re: [PATCH v5 4/5] MIPS: generic: Add support for Microsemi Ocelot

On Tue, Mar 06, 2018 at 01:16:06PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index d1ca839c3981..d2882244cf1f 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -543,6 +543,10 @@ generic_defconfig: > # now that the boards have been

Re: [PATCH v5 4/5] MIPS: generic: Add support for Microsemi Ocelot

On Tue, Mar 06, 2018 at 01:16:06PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/Makefile b/arch/mips/Makefile > index d1ca839c3981..d2882244cf1f 100644 > --- a/arch/mips/Makefile > +++ b/arch/mips/Makefile > @@ -543,6 +543,10 @@ generic_defconfig: > # now that the boards have been

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > b/arch/mips/boot/dts/mscc/ocelot.dtsi > new file mode 100644 > index ..8c3210577410 > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi > @@ -0,0 +1,117 @@ >

Re: [PATCH v5 2/5] MIPS: mscc: add ocelot dtsi

On Tue, Mar 06, 2018 at 01:16:04PM +0100, Alexandre Belloni wrote: > diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi > b/arch/mips/boot/dts/mscc/ocelot.dtsi > new file mode 100644 > index ..8c3210577410 > --- /dev/null > +++ b/arch/mips/boot/dts/mscc/ocelot.dtsi > @@ -0,0 +1,117 @@ >

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote: > On 7 March 2018 at 20:05, James Hogan <jho...@kernel.org> wrote: > > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote: > >> > Does X1000 use a different PRID, or is

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

On Wed, Mar 07, 2018 at 08:35:00PM +0530, PrasannaKumar Muralidharan wrote: > On 7 March 2018 at 20:05, James Hogan wrote: > > On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote: > >> > Does X1000 use a different PRID, or is it basical

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote: > > Does X1000 use a different PRID, or is it basically just a JZ4780 core > > with different SoC peripherals? > > Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has Right, so thats 0x2e00 |

Re: [RFC 3/4] MIPS: Ingenic: Initial X1000 SoC support

On Wed, Mar 07, 2018 at 07:14:49PM +0530, PrasannaKumar Muralidharan wrote: > > Does X1000 use a different PRID, or is it basically just a JZ4780 core > > with different SoC peripherals? > > Yes X1000 does have a different PRID (PRID = 0x2ed1024f). X1000 has Right, so thats 0x2e00 |

[PATCH] kbuild: Handle builtin dtb files containing hyphens

: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to bcm6358-neufbox4-sercom") Signed-off-by: James Hogan <jho...@kernel.org> Cc: Rob Herring <robh...@kernel.org> Cc: Frank Rowand <frowand.l...@gmail.com> Cc: Masahiro Yamada <yamada.masah...@socionext.

[PATCH] kbuild: Handle builtin dtb files containing hyphens

: 695835511f96 ("MIPS: BMIPS: rename bcm96358nb4ser to bcm6358-neufbox4-sercom") Signed-off-by: James Hogan Cc: Rob Herring Cc: Frank Rowand Cc: Masahiro Yamada Cc: Michal Marek Cc: Ralf Baechle Cc: Florian Fainelli Cc: Kevin Cernekee Cc: devicet...@vger.kernel.org Cc:

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