Support for the OCX alignment counters.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/uncore/Makefile| 3 +-
arch/arm64/kernel/uncore/uncore_cavium.c | 3 +
arch/arm64/kernel/uncore/uncore_cavium.h | 4 +
arch/arm64/kernel/uncore/uncore_cavium_ocx_frc.c
uld be put somewhere under drivers/
instead.
Feedback welcome!
Jan
Jan Glauber (7):
arm64/perf: Basic uncore counter support for Cavium ThunderX
arm64/perf: Cavium ThunderX L2C TAD uncore support
arm64/perf: Cavium ThunderX L2C CBC uncore support
arm64/perf: Cavium ThunderX LMC unco
Support counters on the DRAM controllers.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/uncore/Makefile| 3 +-
arch/arm64/kernel/uncore/uncore_cavium.c | 3 +
arch/arm64/kernel/uncore/uncore_cavium.h | 4 +
arch/arm64/kernel/uncore/uncore_cavium_lmc.c | 201
+1,210 @@
+/*
+ * Cavium Thunder uncore PMU support. Derived from Intel and AMD uncore code.
+ *
+ * Copyright (C) 2015,2016 Cavium Inc.
+ * Author: Jan Glauber
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+#include
+
+#include "uncore_cav
Support counters for the CCPI Interface controller (OCX) lanes.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/uncore/Makefile| 3 +-
arch/arm64/kernel/uncore/uncore_cavium.c | 3 +
arch/arm64/kernel/uncore/uncore_cavium.h | 4 +
arch/arm64/kernel/uncore
Support counters of the L2 cache crossbar connect.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/uncore/Makefile| 3 +-
arch/arm64/kernel/uncore/uncore_cavium.c | 3 +
arch/arm64/kernel/uncore/uncore_cavium.h | 4 +
arch/arm64/kernel/uncore
Support counters of the L2 Cache tag and data units.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/uncore/Makefile| 3 +-
arch/arm64/kernel/uncore/uncore_cavium.c | 6 +-
arch/arm64/kernel/uncore/uncore_cavium.h | 6 +-
arch/arm64/kernel/uncore
On Mon, Feb 29, 2016 at 03:39:35PM +, Will Deacon wrote:
> Hi Jan,
>
> I've queued this lot on my perf/updates branch, but I just noticed an
> oddity whilst dealing with some potential conflicts with the kvm tree.
>
> On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glau
: Jan Glauber
---
drivers/i2c/busses/i2c-cavium.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/i2c/busses/i2c-cavium.h b/drivers/i2c/busses/i2c-cavium.h
index 8357997..c7398f4 100644
--- a/drivers/i2c/busses/i2c-cavium.h
+++ b/drivers/i2c/busses/i2c-cavium.h
@@ -8,7
On Mon, Feb 29, 2016 at 03:39:35PM +, Will Deacon wrote:
> Hi Jan,
>
> I've queued this lot on my perf/updates branch, but I just noticed an
> oddity whilst dealing with some potential conflicts with the kvm tree.
>
> On Thu, Feb 18, 2016 at 05:50:13PM +0100, Jan Glau
The implemented Cortex A57 events are not A57 specific.
They are recommended by ARM and can be found on other
ARMv8 SOCs like Cavium ThunderX too. Therefore move
these events to the common PMUv3 table.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 28
counter always sets the upper
32 bits so overflow interrupts are generated as before.
Original patch from Andrew Pinksi
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel
icache prefetch counters
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 69 +-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 32fe656..c038e4e 100644
ARMv8.1 increases the PMU event number space. Detect the
presence of this PMUv3 type and extend the event mask.
The event mask is moved to struct arm_pmu so different event masks
can exist, depending on the PMU type.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 33
Add a compatible string for the Cavium ThunderX PMU.
Signed-off-by: Jan Glauber
---
Documentation/devicetree/bindings/arm/pmu.txt | 1 +
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
b
Hi Mark & Will,
I'm resending the arm64 PMU patches. The only difference to the first
version is that I dropped the x on thunder in order to be consistent
with the existing device tree name.
Thanks,
Jan
Jan Glauber (5):
arm64/perf: Rename Cortex A57 events
arm64/perf: Add Cavium
ARMv8.1 increases the PMU event number space. Detect the
presence of this PMUv3 type and extend the event mask.
The event mask is moved to struct arm_pmu so different event masks
can exist, depending on the PMU type.
Signed-off-by: Jan Glauber
---
arch/arm/kernel/perf_event_v6.c | 6
a note to
> help improving the system]
>
> url:
> https://github.com/0day-ci/linux/commits/Jan-Glauber/Cavium-ThunderX-PMU-support/20160128-225855
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux for-next
> config: arm-corgi_defconfig (attached as .config)
anges. Without this change perf does not work at all on ThunderX.
Patch 5 extends the event mask according to ARMv8.1 and also affects arm32.
Changes to v2:
- fixed arm compile errors
Changes to v1:
- renamed thunderx dt pmu binding to thunder
--Jan
Jan Glauber (5):
arm64/perf: Rename Corte
icache prefetch counters
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 69 +-
1 file changed, 68 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 32fe656..c038e4e 100644
counter always sets the upper
32 bits so overflow interrupts are generated as before.
Original patch from Andrew Pinksi
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/arch/arm64/kernel
Add a compatible string for the Cavium ThunderX PMU.
Signed-off-by: Jan Glauber
---
Documentation/devicetree/bindings/arm/pmu.txt | 1 +
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 5 +
2 files changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt
b
ARMv8.1 increases the PMU event number space. Detect the
presence of this PMUv3 type and extend the event mask.
The event mask is moved to struct arm_pmu so different event masks
can exist, depending on the PMU type.
Signed-off-by: Jan Glauber
---
arch/arm/kernel/perf_event_v6.c | 6
The implemented Cortex A57 events are not A57 specific.
They are recommended by ARM and can be found on other
ARMv8 SOCs like Cavium ThunderX too. Therefore move
these events to the common PMUv3 table.
Signed-off-by: Jan Glauber
---
arch/arm64/kernel/perf_event.c | 28
impact any hardware
that does not have this issue.
With the retry limit the performance of an open-close testcase
improved between 60-70% on ThunderX2.
Suggested-by: Linus Torvalds
Signed-off-by: Jan Glauber
---
lib/lockref.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/lib/lockref.c b
On Wed, Jun 05, 2019 at 01:16:46PM -0700, Linus Torvalds wrote:
> On Wed, Jun 5, 2019 at 6:49 AM Jan Glauber wrote:
> >
> > Add an upper bound to the loop to force the fallback to spinlocks
> > after some time. A retry value of 100 should not impact any hardware
> > th
Fix a typo that disabled the MCI interrupts using the wrong bitmask.
Signed-off-by: Jan Glauber
---
drivers/edac/thunderx_edac.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/edac/thunderx_edac.c b/drivers/edac/thunderx_edac.c
index 2eae2b2..8844aef 100644
--- a
for all MMC devices is required because the host
controller is shared.
Signed-off-by: Jan Glauber
Signed-off-by: David Daney
Signed-off-by: Steven J. Hill
---
drivers/mmc/host/cavium.c | 982 ++
drivers/mmc/host/cavium.h | 192 +
2 files cha
Add support for switching to DDR mode for eMMC devices.
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c
index eebb387..d842b69 100644
--- a/drivers/mmc
ail-archive.com/linux-kernel@vger.kernel.org/msg1295316.html
v9: http://marc.info/?l=linux-mmc&m=147431759215233&w=2
Cheers,
Jan
---
Jan Glauber (6):
dt-bindings: mmc: Add Cavium SOCs MMC bindings
mmc: cavium: Add core MMC driver for Cavium SOCs
mmc: cavium: Add MMC PCI dr
Signed-off-by: Jan Glauber
Signed-off-by: David Daney
Signed-off-by: Steven J. Hill
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index c776906..25c3009 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3041,6 +3041,14 @@ S: Supported
Add Support for the scatter-gather DMA available in the
ThunderX MMC units. Up to 16 DMA requests can be processed
together.
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium-thunderx.c | 5 +-
drivers/mmc/host/cavium.c | 104 +++--
drivers/mmc
Add a platform driver for ThunderX ARM SOCs.
Signed-off-by: Jan Glauber
---
drivers/mmc/host/Kconfig | 10 ++
drivers/mmc/host/Makefile | 2 +
drivers/mmc/host/cavium-thunderx.c | 195 +
drivers/mmc/host/cavium.h | 7 ++
4
Add description of Cavium Octeon and ThunderX SOC device tree bindings.
CC: Ulf Hansson
CC: Rob Herring
CC: Mark Rutland
CC: devicet...@vger.kernel.org
Signed-off-by: Jan Glauber
Signed-off-by: David Daney
Signed-off-by: Steven J. Hill
Acked-by: Rob Herring
---
.../devicetree/bindings
e system]
>
> url:
> https://github.com/0day-ci/linux/commits/Jan-Glauber/Cavium-MMC-driver/20170401-055302
> config: sparc64-allmodconfig (attached as .config)
> compiler: sparc64-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
> reproduce:
> wget
> https://raw.githubu
Hi Ulf,
here are two cosmetical changes for the reported smatch errors.
Jan Glauber (2):
mmc: cavium: Remove redundant pointer check
mmc: cavium: Check pointer before de-reference
drivers/mmc/host/cavium.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
--
2.9.0.rc0.21.g322
ess checking cmd->data
before using it improves readability.
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c
index ddf902c..d89c2eb 100644
--- a/drivers/mmc/host/cav
Remove redundant mmc->card check reported by smatch:
drivers/mmc/host/cavium.c:694 cvm_mmc_dma_request()
warn: variable dereferenced before check 'mmc->card' (see line 675)
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium.c | 2 +-
1 file changed, 1 insertio
On Thu, May 18, 2017 at 02:52:54AM +0300, Sergei Temerkhanov wrote:
> On Wed, May 17, 2017 at 8:23 PM, Jan Glauber
> wrote:
> > On Wed, May 17, 2017 at 06:35:05PM +0300, Sergei Temerkhanov wrote:
> >> CIL...
> >>
> >> On Tue, May 16, 2017 at 12:54 PM,
On Wed, May 17, 2017 at 03:41:12PM +0200, Jan Glauber wrote:
> On Tue, May 16, 2017 at 09:37:48AM -0500, Rob Herring wrote:
> > On Tue, May 16, 2017 at 8:38 AM, Jan Glauber
> > wrote:
> > > On Tue, May 16, 2017 at 08:07:50AM -0500, Rob Herring wrote:
> > >>
On Fri, May 19, 2017 at 10:30:22AM +0200, Ulf Hansson wrote:
> On 16 May 2017 at 11:36, Jan Glauber wrote:
> > Hi Ulf,
> >
> > here are some bug fixes for the new mmc driver. The only
> > non-trivial fix should be the platform thing in patch #4 and #5.
> >
>
Add support for the transmit-link (OCX TLK) PMU counters found
on Caviums SOCs with a processor interconnect.
Properties of the OCX TLK counters:
- per-unit control
- fixed purpose
- writable
- one PCI device with multiple TLK units
Signed-off-by: Jan Glauber
---
drivers/perf/cavium_pmu.c
_add error case
Jan Glauber (3):
perf: cavium: Support memory controller PMU counters
perf: cavium: Support transmit-link PMU counters
perf: cavium: Add Documentation
Documentation/perf/cavium-pmu.txt | 74 +
drivers/perf/Kconfig | 8 +
drivers/perf/Makefile
ms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright Cavium, Inc. 2017
+ * Author(s): Jan Glauber
+ *
+ */
+#include
+#include
+#include
+#include
+#include
+#include
+
Document Cavium SoC PMUs.
Signed-off-by: Jan Glauber
---
Documentation/perf/cavium-pmu.txt | 74 +++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/perf/cavium-pmu.txt
diff --git a/Documentation/perf/cavium-pmu.txt
b/Documentation/perf
Hi Will,
I just hit the same issue with 4.16-rc2. The patch makes it compilable
again.
--Jan
On Mon, Feb 19, 2018 at 11:02:39AM +, Will Deacon wrote:
> Hi John,
>
> On Mon, Feb 19, 2018 at 10:19:35AM +, John Garry wrote:
> > On 19/02/2018 06:39, Bhupesh Sharma wrote:
> > >Since commit e
The error message:
[Fri Feb 16 13:42:13 2018] i2c-thunderx :01:09.4: unhandled state: 0
is mis-leading as state 0 (bus error) is not an unknown state.
Return -EIO as before but avoid printing the message. Also rename
STAT_ERROR to STATE_BUS_ERROR.
Signed-off-by: Jan Glauber
---
drivers
On Wed, Nov 15, 2017 at 11:54:20AM +0100, Marc Kleine-Budde wrote:
> On 11/14/2017 01:02 PM, Mark Brown wrote:
> > On Mon, Nov 13, 2017 at 01:17:42PM -0800, Tim Harvey wrote:
> >
> >> When a register is read from the mcp251x driver the
> >> octeon_spi_do_transfer() gets a spi_message with a single
On Wed, Nov 15, 2017 at 02:31:45PM +0100, Marc Kleine-Budde wrote:
> On 11/15/2017 01:40 PM, Marc Kleine-Budde wrote:
> > mcp251x_spi_trans() is called with len=3,
> > priv->spi_tx_buf and priv->spi_rx_buf point to previously allocared memory
> >
> > priv->spi_tx_buf has been filled before calling
.
The same mechanism will be used later to call the PMU driver.
The ThunderX EDAC driver is limited to only build as module
with this patch. The reason is that with multiple users of the
multi-plexer all users must be either builtin or modules.
Signed-off-by: Jan Glauber
---
drivers/edac
o avoid code duplication
and support adding more device PMUs (like L2 cache) in the future.
Changes to v8:
- Wrapper for PCI devices
Jan Glauber (7):
edac: thunderx: Remove suspend/resume support
edac,soc: thunderx: Add wrapper for EDAC LMC PCI device
edac,soc: thunderx: Add wrapper for EDAC O
Document Cavium SoC PMUs.
Signed-off-by: Jan Glauber
---
Documentation/perf/cavium-pmu.txt | 75 +++
1 file changed, 75 insertions(+)
create mode 100644 Documentation/perf/cavium-pmu.txt
diff --git a/Documentation/perf/cavium-pmu.txt
b/Documentation/perf
+ * Cavium ARM SOC "uncore" PMU counters
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright Cavium, Inc. 2017
+ * Author(s): Jan
Export perf_event_update_userpage(). This change is needed to allow
building a PMU driver as a kernel module.
Cc: Peter Zijlstra
Cc: Ingo Molnar
Cc: Arnaldo Carvalho de Melo
Signed-off-by: Jan Glauber
---
kernel/events/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/events
driver.
Signed-off-by: Jan Glauber
---
drivers/edac/Kconfig| 1 +
drivers/edac/thunderx_edac.c| 42 +++---
drivers/soc/cavium/Kconfig | 4
drivers/soc/cavium/Makefile | 1 +
drivers/soc/cavium/cavium_ocx.c | 45
Add support for the transmit-link (OCX TLK) PMU counters found
on Caviums SOCs with a processor interconnect.
Properties of the OCX TLK counters:
- per-unit control
- fixed purpose
- writable
- one PCI device with multiple TLK units
Signed-off-by: Jan Glauber
---
drivers/perf/Kconfig
The memory controller on ThunderX/OcteonTX systems does not
support power management. Therefore remove the suspend/resume
callbacks.
Signed-off-by: Jan Glauber
---
drivers/edac/thunderx_edac.c | 21 -
1 file changed, 21 deletions(-)
diff --git a/drivers/edac/thunderx_edac.c
.
Signed-off-by: David Daney
[jglau...@cavium.com: fixed typo]
Signed-off-by: Jan Glauber
---
drivers/pci/pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index af0cc34..d9abbc9 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4290,6 +4290,10
path for
pci_bus_resetable() and pci_slot_resetable().
With this series both checks indicate that the reset is not possible
preventing the kernel panic.
David Daney (2):
PCI: Allow PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device
PCI: Avoid bus reset for Cavium cn8xxx root ports
Jan Glaub
Root ports of cn8xxx do not function after a slot reset when used with
some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on
these root ports.
Signed-off-by: Jan Glauber
---
drivers/pci/quirks.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/pci
From: David Daney
Root ports of cn8xxx do not function after bus reset when used with
some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on
these root ports.
Signed-off-by: David Daney
[jglau...@cavium.com: fixed typo and whitespaces]
Signed-off-by: Jan Glauber
---
drivers/pci
On Wed, Aug 30, 2017 at 07:54:06PM +0200, Borislav Petkov wrote:
> On Tue, Aug 29, 2017 at 03:12:32PM +0200, Jan Glauber wrote:
> > The memory controller on ThunderX/OcteonTX systems does not
> > support power management. Therefore remove the suspend/resume
> > callbacks.
&
On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:
> On Wed, 30 Aug 2017 16:24:54 +0200
> Jan Glauber wrote:
>
> > Root ports of cn8xxx do not function after a slot reset when used with
> > some e1000e and LSI HBA devices. Add a quirk to prevent slot reset on
On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:
> Hi Jan,
>
> Some trivial things i noticed, please consider if you are glad.
>
> Thanks,
> Shaokun
Hi Shaokun, thanks for the review.
> On 2017/8/29 21:12, Jan Glauber wrote:
> > Add support for the
On Thu, Aug 31, 2017 at 11:31:20AM +0100, Mark Rutland wrote:
> On Thu, Aug 31, 2017 at 11:57:46AM +0200, Jan Glauber wrote:
> > On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:
> > > On 2017/8/29 21:12, Jan Glauber wrote:
> > > > Add support for the PMU
On Thu, Aug 31, 2017 at 11:31:20AM +0100, Mark Rutland wrote:
> On Thu, Aug 31, 2017 at 11:57:46AM +0200, Jan Glauber wrote:
> > On Wed, Aug 30, 2017 at 10:54:03AM +0800, Zhangshaokun wrote:
> > > On 2017/8/29 21:12, Jan Glauber wrote:
[...]
> > > > diff --git
On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:
> On 29/08/17 14:12, Jan Glauber wrote:
> >Add support for the PMU counters on Cavium SOC memory controllers.
> >
> >This patch also adds generic functions to allow supporting more
> >devices with PMU cou
So what about the general idea with the wrapper, does this look sane?
Any objections to that?
thanks,
Jan
On Tue, Aug 29, 2017 at 03:12:31PM +0200, Jan Glauber wrote:
> I'm posting this as RFC following this discussion:
> https://marc.info/?l=linux-arm-kernel&m=15009952692383
On Fri, Aug 18, 2017 at 09:55:53PM -0600, Alex Williamson wrote:
> On Fri, 18 Aug 2017 08:57:09 -0700
> David Daney wrote:
>
> > On 08/18/2017 07:12 AM, Alex Williamson wrote:
[...]
> > You previously rejected the idea to silently ignore bus reset requests
> > on buses that do not support it.
PCI_DEV_FLAGS_NO_BUS_RESET to be used on bus device
PCI: Avoid bus reset for Cavium cn8xxx root ports
Jan Glauber (1):
PCI: Avoid slot reset if bus reset is not possible
drivers/pci/pci.c| 8
drivers/pci/quirks.c | 8
2 files changed, 16 insertions(+)
--
2.9.0.rc0.21.g322
PCI_DEV_FLAGS_NO_BUS_RESET flag being set in the
bridge device to prevent the slot from being reset.
Signed-off-by: Jan Glauber
---
drivers/pci/pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index b2a46ca7f133..45a086fc3592 100644
--- a/drivers/pci
.
Signed-off-by: David Daney
[jglau...@cavium.com: fixed typo]
Signed-off-by: Jan Glauber
---
drivers/pci/pci.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index fdf65a6c13f6..b2a46ca7f133 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -4325,6
From: David Daney
Root ports of cn8xxx do not function after bus reset when used with
some e1000e and LSI HBA devices. Add a quirk to prevent bus reset on
these root ports.
Signed-off-by: David Daney
[jglau...@cavium.com: fixed typo and whitespaces]
Signed-off-by: Jan Glauber
---
drivers/pci
On Thu, Aug 31, 2017 at 02:26:22PM +0100, Suzuki K Poulose wrote:
> On 31/08/17 12:35, Jan Glauber wrote:
> >On Wed, Aug 30, 2017 at 11:03:00AM +0100, Suzuki K Poulose wrote:
> >>On 29/08/17 14:12, Jan Glauber wrote:
[...]
> >>>+/* LMC events */
> >>&g
On Thu, Aug 31, 2017 at 10:01:30AM -0600, Alex Williamson wrote:
> On Thu, 31 Aug 2017 11:40:52 +0200
> Jan Glauber wrote:
>
> > On Wed, Aug 30, 2017 at 08:40:12AM -0600, Alex Williamson wrote:
> > > On Wed, 30 Aug 2017 16:24:54 +0200
> > > Jan Glauber wrot
On Thu, Sep 07, 2017 at 09:40:11AM +0200, Jan Glauber wrote:
> So what if we add an additional check like:
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index fdf65a6..389db4b 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4389,6 +
e calling
of_platform_device_destroy() so freeing the device is postponed after
the call.
Fixes: 8fb83b142823 ("mmc: cavium: Fix probing race with regulator")
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium-thunderx.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git
Thanks Uffe. The fix would only be required for 4.13, as only with that the
Cavium GPIO driver became available.
--Jan
On Thu, Sep 07, 2017 at 02:07:01PM +0200, Ulf Hansson wrote:
> On 7 September 2017 at 13:24, Jan Glauber wrote:
> > KASAN reported the following:
> >
&g
On Thu, Sep 07, 2017 at 02:21:17PM +0200, Ulf Hansson wrote:
> On 7 September 2017 at 14:19, Jan Glauber
> wrote:
> > Thanks Uffe. The fix would only be required for 4.13, as only with that the
> > Cavium GPIO driver became available.
>
> Okay, I drop the fixes tag then
On Thu, Sep 07, 2017 at 11:58:58AM -0500, Rob Herring wrote:
> On Thu, Sep 7, 2017 at 6:24 AM, Jan Glauber wrote:
> > KASAN reported the following:
> >
> > [ 19.338655]
> > ==
> > [ 19.3459
On Thu, Aug 17, 2017 at 07:00:17AM -0600, Alex Williamson wrote:
> On Thu, 17 Aug 2017 10:14:23 +0200
> Jan Glauber wrote:
>
> > If a PCI device supports neither function-level reset, nor slot
> > or bus reset then refuse to probe it. A line is printed to inform
> > th
64_cmpxchg
- Simplify cvm_pmu_lmc_event_valid
- Fix list_add error case
Jan Glauber (3):
perf: cavium: Support memory controller PMU counters
perf: cavium: Support transmit-link PMU counters
perf: cavium: Add Documentation
Documentation/perf/cavium-pmu.txt | 74 +
drivers/edac/thunderx_edac.c
@@ -0,0 +1,418 @@
+/*
+ * Cavium ARM SOC "uncore" PMU counters
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright Cavium, Inc.
Add support for the transmit-link (OCX TLK) PMU counters found
on Caviums SOCs with a processor interconnect.
Properties of the OCX TLK counters:
- per-unit control
- fixed purpose
- writable
- one PCI device with multiple TLK units
Signed-off-by: Jan Glauber
---
drivers/edac/thunderx_edac.c
Document Cavium SoC PMUs.
Signed-off-by: Jan Glauber
---
Documentation/perf/cavium-pmu.txt | 74 +++
1 file changed, 74 insertions(+)
create mode 100644 Documentation/perf/cavium-pmu.txt
diff --git a/Documentation/perf/cavium-pmu.txt
b/Documentation/perf
uot;)
Signed-off-by: David Daney
[jglau...@cavium.com: removed point after subject line]
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium-octeon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/host/cavium-octeon.c b/drivers/mmc/host/cavium-octeon.c
index d
name for power control
Jan Glauber (3):
mmc: cavium: Prevent crash with incomplete DT
of/platform: Make of_platform_device_destroy globally visible
mmc: cavium: Fix probing race with regulator
drivers/mmc/host/cavium-octeon.c | 4 ++--
drivers/mmc/host/cavium-thunderx.c | 4 +++-
drivers/mmc
of_platform_device_destroy globally visible.
Cc: Rob Herring
Cc: Frank Rowand
Cc: devicet...@vger.kernel.org
Signed-off-by: Jan Glauber
---
drivers/of/platform.c | 3 ++-
include/linux/of_platform.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/of/platform.c b
.
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/host/cavium.c b/drivers/mmc/host/cavium.c
index 58b51ba..63f96dc 100644
--- a/drivers/mmc/host/cavium.c
+++ b/drivers/mmc/host/cavium.c
@@ -839,14
resolves
this bug.
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium-thunderx.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/mmc/host/cavium-thunderx.c
b/drivers/mmc/host/cavium-thunderx.c
index fe3d772..257535e 100644
--- a/drivers/mmc/host/cavium-thunderx.c
proper
action on these SoCs is not to touch this register.
Fixes: 01d95843335c ("mmc: cavium: Add MMC support for Octeon SOCs.")
Signed-off-by: David Daney
[jglau...@cavium.com: removed point after subject line]
Signed-off-by: Jan Glauber
---
drivers/mmc/host/cavium-octeon.c | 2 +-
1 fi
Replace the deprecated pci_alloc_msix_exact() with
pci_alloc_irq_vectors().
Avoid the container_of usage in the interrupt handler
by simply passing the required struct as data to the interrupt
handler.
Signed-off-by: Jan Glauber
---
drivers/edac/thunderx_edac.c | 91
On Tue, May 16, 2017 at 08:07:50AM -0500, Rob Herring wrote:
> On Tue, May 16, 2017 at 4:36 AM, Jan Glauber wrote:
> > If the regulator probing is not yet finished this driver
> > might catch a -EPROBE_DEFER. Returning after this condition
> > did not remove the created
Add support for the transmit-link (TLK) PMU counters found
on Caviums SOCs with an interconnect.
Signed-off-by: Jan Glauber
---
drivers/edac/thunderx_edac.c| 7 ++
drivers/perf/cavium_pmu.c | 223 +++-
include/linux/perf/cavium_pmu.h | 1 +
3
Export perf_event_update_userpage() to make it usable from a module.
Signed-off-by: Jan Glauber
---
kernel/events/core.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/kernel/events/core.c b/kernel/events/core.c
index 6e75a5c..6578b9f 100644
--- a/kernel/events/core.c
+++ b/kernel/events
ux-arm-kernel&m=147940675216946&w=4
Jan Glauber (3):
perf: export perf_event_update_userpage()
perf: cavium: Support memory controller PMU counters
perf: cavium: Support transmit-link PMU counters
drivers/edac/thunderx_edac.c| 19 +-
drivers/perf/Kconfig| 8 +
drivers/perf/M
Add support for the PMU counters on Cavium SOC memory controllers.
This patch also adds generic functions to allow supporting more
devices with PMU counters.
Signed-off-by: Jan Glauber
---
drivers/edac/thunderx_edac.c| 12 +-
drivers/perf/Kconfig| 8 +
drivers/perf/Makefile
On Tue, May 16, 2017 at 09:37:48AM -0500, Rob Herring wrote:
> On Tue, May 16, 2017 at 8:38 AM, Jan Glauber
> wrote:
> > On Tue, May 16, 2017 at 08:07:50AM -0500, Rob Herring wrote:
> >> On Tue, May 16, 2017 at 4:36 AM, Jan Glauber wrote:
> >> > If the regulator
On Wed, May 17, 2017 at 06:35:05PM +0300, Sergei Temerkhanov wrote:
> CIL...
>
> On Tue, May 16, 2017 at 12:54 PM, Jan Glauber wrote:
> > Replace the deprecated pci_alloc_msix_exact() with
> > pci_alloc_irq_vectors().
> >
> > Avoid the container_of usage in th
Changes to v1:
- Fixed platform device leak, apply fix also to Octeon driver
- Use mmc_regulator_get_supply
Jan Glauber (3):
mmc: cavium: Prevent crash with incomplete DT
of/platform: Make of_platform_device_destroy globally visible
mmc: cavium: Fix probing race with regulator
drivers/mmc
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