[PATCH 4/7] spi: meson: Add GXBB compatible
From: Neil Armstrong
Signed-off-by: Neil Armstrong
---
drivers/spi/spi-meson-spifc.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/spi-meson-spifc.c b/drivers/spi/spi-meson-spifc.c
index 2465259..616566e 100644
--- a/drivers/spi/spi-meson-spifc.c
+++ b/drivers/spi/spi-meson-spifc.c
@@ -442,6 +442,7 @@ static const struct dev_pm_ops meson_spifc_pm_ops = {
static const struct of_device_id meson_spifc_dt_match[] = {
{ .compatible = "amlogic,meson6-spifc", },
+ { .compatible = "amlogic,meson-gxbb-spifc", },
{ },
};
MODULE_DEVICE_TABLE(of, meson_spifc_dt_match);
--
2.7.4
[PATCH 2/7] pinctrl: amlogic: gxbb: add nand pins
Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index 802ad83..08e6cdd 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -168,6 +168,15 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4,
EE_OFF) };
static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) };
+
static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
static const unsigned int uart_cts_a_pins[]= { PIN(GPIOX_14, EE_OFF) };
@@ -402,6 +411,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[]
= {
GROUP(spifc_q, 5, 3),
GROUP(spifc_c, 5, 2),
GROUP(spifc_cs, 5, 0),
+ GROUP(nand_ce0, 4, 26),
+ GROUP(nand_ce1, 4, 27),
+ GROUP(nand_rb0, 4, 25),
+ GROUP(nand_ale, 4, 24),
+ GROUP(nand_cle, 4, 23),
+ GROUP(nand_wen_clk, 4, 22),
+ GROUP(nand_ren_wr, 4, 21),
+ GROUP(nand_dqs, 4, 20),
/* Bank CARD */
GROUP(sdcard_d1,2, 14),
@@ -493,6 +510,11 @@ static const char * const sdcard_groups[] = {
"sdcard_cmd", "sdcard_clk",
};
+static const char * const nand_groups[] = {
+ "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+ "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
};
@@ -539,6 +561,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[]
= {
FUNCTION(emmc),
FUNCTION(spifc),
FUNCTION(sdcard),
+ FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
--
2.7.4
[PATCH 3/7] clk: gxbb: expose spifc clock
SPI clock is needed for the spifc driver, expose to DT (and comment out in the clk driver) Signed-off-by: Jerome Brunet --- drivers/clk/meson/gxbb.h | 2 +- include/dt-bindings/clock/gxbb-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h index a2adf34..5abe266 100644 --- a/drivers/clk/meson/gxbb.h +++ b/drivers/clk/meson/gxbb.h @@ -202,7 +202,7 @@ #define CLKID_ABUF 31 #define CLKID_HIU_IFACE 32 #define CLKID_ASSIST_MISC33 -#define CLKID_SPI34 +/* CLKID_SPI */ #define CLKID_I2S_SPDIF 35 #define CLKID_ETH36 #define CLKID_DEMUX 37 diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h index f889d80..dcf3776 100644 --- a/include/dt-bindings/clock/gxbb-clkc.h +++ b/include/dt-bindings/clock/gxbb-clkc.h @@ -7,6 +7,7 @@ #define CLKID_CPUCLK 1 #define CLKID_CLK8112 +#define CLKID_SPI 34 #define CLKID_ETH 36 #endif /* __GXBB_CLKC_H */ -- 2.7.4
[PATCH 5/7] dt-bindings: spi-meson: Add GXBB Compatible string
From: Neil Armstrong Signed-off-by: Neil Armstrong --- Documentation/devicetree/bindings/spi/spi-meson.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/spi-meson.txt b/Documentation/devicetree/bindings/spi/spi-meson.txt index bb52a86..dc6d031 100644 --- a/Documentation/devicetree/bindings/spi/spi-meson.txt +++ b/Documentation/devicetree/bindings/spi/spi-meson.txt @@ -7,7 +7,7 @@ NOR memories, without DMA support and a 64-byte unified transmit / receive buffer. Required properties: - - compatible: should be "amlogic,meson6-spifc" + - compatible: should be "amlogic,meson6-spifc" or "amlogic,meson-gxbb-spifc" - reg: physical base address and length of the controller registers - clocks: phandle of the input clock for the baud rate generator - #address-cells: should be 1 -- 2.7.4
[PATCH 7/7] ARM64: dts: meson-gxbb: Add SPIFC node
From: Neil Armstrong
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index b35fc94..3d12044 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -193,6 +193,15 @@
reg = <0x0 0x098d0 0x0 0x10>;
clocks = <&xtal>;
};
+
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SPI>;
+ status = "disabled";
+ };
};
gic: interrupt-controller@c4301000 {
--
2.7.4
[PATCH 6/7] ARM64: dts: amlogic: add pins for spifc
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 762f368..b35fc94 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,6 +333,16 @@
};
};
+ spifc_pins: spifc {
+ mux {
+ groups = "spifc_d",
+ "spifc_q",
+ "spifc_c",
+ "spifc_cs";
+ function = "spifc";
+ };
+ };
+
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
--
2.7.4
[PATCH 0/7] ARM: amlogic: Add spifc support to Amlogic's GXBB family
This patch series adds the necessary pins, clocks and device tree nodes to enable the spifc controller on the GXBB family. I had to add the nand pins in pintctrl as the pinmux setting left by u-boot was conflicting with the spifc pinmux during my test on the P200. Jerome Brunet (4): pinctrl: amlogic: gxbb: add spifc pins pinctrl: amlogic: gxbb: add nand pins clk: gxbb: expose spifc clock ARM64: dts: amlogic: add pins for spifc Neil Armstrong (3): spi: meson: Add GXBB compatible dt-bindings: spi-meson: Add GXBB Compatible string ARM64: dts: meson-gxbb: Add SPIFC node .../devicetree/bindings/spi/spi-meson.txt | 2 +- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi| 19 +++ drivers/clk/meson/gxbb.h | 2 +- drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 37 ++ drivers/spi/spi-meson-spifc.c | 1 + include/dt-bindings/clock/gxbb-clkc.h | 1 + 6 files changed, 60 insertions(+), 2 deletions(-) -- 2.7.4
[PATCH 1/7] pinctrl: amlogic: gxbb: add spifc pins
Add EE domains pins for the SPI flash controller
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index cb4d6ad..802ad83 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8,
EE_OFF) };
static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+static const unsigned int spifc_d_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int spifc_q_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int spifc_c_pins[] = { PIN(BOOT_13, EE_OFF) };
+static const unsigned int spifc_cs_pins[] = { PIN(BOOT_15, EE_OFF) };
+
static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -393,6 +398,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[]
= {
GROUP(emmc_clk, 4, 18),
GROUP(emmc_cmd, 4, 19),
GROUP(emmc_ds, 4, 31),
+ GROUP(spifc_d, 5, 1),
+ GROUP(spifc_q, 5, 3),
+ GROUP(spifc_c, 5, 2),
+ GROUP(spifc_cs, 5, 0),
/* Bank CARD */
GROUP(sdcard_d1,2, 14),
@@ -475,6 +484,10 @@ static const char * const emmc_groups[] = {
"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
};
+static const char * const spifc_groups[] = {
+ "spifc_d", "spifc_q", "spifc_c", "spifc_cs",
+};
+
static const char * const sdcard_groups[] = {
"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
"sdcard_cmd", "sdcard_clk",
@@ -524,6 +537,7 @@ static const char * const i2c_slave_ao_groups[] = {
static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
+ FUNCTION(spifc),
FUNCTION(sdcard),
FUNCTION(uart_a),
FUNCTION(uart_b),
--
2.7.4
[PATCH v2 0/4] ARM: amlogic: Add spifc support to Amlogic's GXBB family
This patch series adds the necessary pins, clocks and device tree nodes to enable the spifc controller on the GXBB family. I had to add the nand pins in pintctrl as the pinmux setting left by u-boot was conflicting with the spifc pinmux during my test on the P200. Changes since v1 at : http://lkml.kernel.org/r/1473261223-15412-1-git-send-email-jbru...@baylibre.com * Omit patches : - dt-bindings: spi-meson: Add GXBB Compatible string - spi: meson: Add GXBB compatible Sent as dedicated series * Omit patch: - clk: gxbb: expose spifc clock Already applied * Rename SPI flash controller pins from spifc_* to nor_* to keep the name aligned with the datasheet Jerome Brunet (3): pinctrl: amlogic: gxbb: add spi nor pins pinctrl: amlogic: gxbb: add nand pins ARM64: dts: amlogic: add spi nor pins Neil Armstrong (1): ARM64: dts: meson-gxbb: Add SPIFC node arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 19 +++ drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 37 + 2 files changed, 56 insertions(+) -- 2.7.4
[PATCH v2 3/4] ARM64: dts: amlogic: add spi nor pins
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 762f3681a49c..49e803e42e10 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -333,6 +333,16 @@
};
};
+ nor_pins: nor {
+ mux {
+ groups = "nor_d",
+ "nor_q",
+ "nor_c",
+ "nor_cs";
+ function = "nor";
+ };
+ };
+
sdcard_pins: sdcard {
mux {
groups = "sdcard_d0",
--
2.7.4
[PATCH v2 4/4] ARM64: dts: meson-gxbb: Add SPIFC node
From: Neil Armstrong
Signed-off-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 49e803e42e10..8d3bf3c7345e 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -193,6 +193,15 @@
reg = <0x0 0x098d0 0x0 0x10>;
clocks = <&xtal>;
};
+
+ spifc: spi@8c80 {
+ compatible = "amlogic,meson-gxbb-spifc";
+ reg = <0x0 0x08c80 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_SPI>;
+ status = "disabled";
+ };
};
gic: interrupt-controller@c4301000 {
--
2.7.4
[PATCH v2 1/4] pinctrl: amlogic: gxbb: add spi nor pins
Add EE domains pins for the SPI flash controller
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index cb4d6ad30530..f74dbd5d350b 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -156,6 +156,11 @@ static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8,
EE_OFF) };
static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+static const unsigned int nor_d_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nor_q_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nor_c_pins[] = { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nor_cs_pins[]= { PIN(BOOT_15,
EE_OFF) };
+
static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
@@ -393,6 +398,10 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[]
= {
GROUP(emmc_clk, 4, 18),
GROUP(emmc_cmd, 4, 19),
GROUP(emmc_ds, 4, 31),
+ GROUP(nor_d,5, 1),
+ GROUP(nor_q,5, 3),
+ GROUP(nor_c,5, 2),
+ GROUP(nor_cs, 5, 0),
/* Bank CARD */
GROUP(sdcard_d1,2, 14),
@@ -475,6 +484,10 @@ static const char * const emmc_groups[] = {
"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
};
+static const char * const nor_groups[] = {
+ "nor_d", "nor_q", "nor_c", "nor_cs",
+};
+
static const char * const sdcard_groups[] = {
"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
"sdcard_cmd", "sdcard_clk",
@@ -524,6 +537,7 @@ static const char * const i2c_slave_ao_groups[] = {
static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
FUNCTION(gpio_periphs),
FUNCTION(emmc),
+ FUNCTION(nor),
FUNCTION(sdcard),
FUNCTION(uart_a),
FUNCTION(uart_b),
--
2.7.4
[PATCH v2 2/4] pinctrl: amlogic: gxbb: add nand pins
Add EE domains pins for the NAND flash controller.
Even tough we have no driver for the NAND flash controller yet, we need
to have these pins in pinctrl as the actual pin are shared with the spifc
controller. The bootloader on the S905-P200 setup pinmux for the NAND
controller so we need the kernel to properly deactivate this if necessary.
Signed-off-by: Jerome Brunet
Acked-by: Kevin Hilman
---
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 23 +++
1 file changed, 23 insertions(+)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index f74dbd5d350b..699f93c51040 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -168,6 +168,15 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4,
EE_OFF) };
static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+static const unsigned int nand_ce0_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int nand_ce1_pins[] = { PIN(BOOT_9, EE_OFF) };
+static const unsigned int nand_rb0_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int nand_ale_pins[] = { PIN(BOOT_11, EE_OFF) };
+static const unsigned int nand_cle_pins[] = { PIN(BOOT_12, EE_OFF) };
+static const unsigned int nand_wen_clk_pins[] = { PIN(BOOT_13, EE_OFF) };
+static const unsigned int nand_ren_wr_pins[] = { PIN(BOOT_14, EE_OFF) };
+static const unsigned int nand_dqs_pins[] = { PIN(BOOT_15, EE_OFF) };
+
static const unsigned int uart_tx_a_pins[] = { PIN(GPIOX_12, EE_OFF) };
static const unsigned int uart_rx_a_pins[] = { PIN(GPIOX_13, EE_OFF) };
static const unsigned int uart_cts_a_pins[]= { PIN(GPIOX_14, EE_OFF) };
@@ -402,6 +411,14 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[]
= {
GROUP(nor_q,5, 3),
GROUP(nor_c,5, 2),
GROUP(nor_cs, 5, 0),
+ GROUP(nand_ce0, 4, 26),
+ GROUP(nand_ce1, 4, 27),
+ GROUP(nand_rb0, 4, 25),
+ GROUP(nand_ale, 4, 24),
+ GROUP(nand_cle, 4, 23),
+ GROUP(nand_wen_clk, 4, 22),
+ GROUP(nand_ren_wr, 4, 21),
+ GROUP(nand_dqs, 4, 20),
/* Bank CARD */
GROUP(sdcard_d1,2, 14),
@@ -493,6 +510,11 @@ static const char * const sdcard_groups[] = {
"sdcard_cmd", "sdcard_clk",
};
+static const char * const nand_groups[] = {
+ "nand_ce0", "nand_ce1", "nand_rb0", "nand_ale", "nand_cle",
+ "nand_wen_clk", "nand_ren_wr", "nand_dqs",
+};
+
static const char * const uart_a_groups[] = {
"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
};
@@ -539,6 +561,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[]
= {
FUNCTION(emmc),
FUNCTION(nor),
FUNCTION(sdcard),
+ FUNCTION(nand),
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
--
2.7.4
[PATCH] pintctrl: amlogic: gxbb: add i2c pins
Add EE domains pins for the i2c devices A,B,C
Signed-off-by: Jerome Brunet
---
drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
index b06cc12f2500..c3928aa3fefa 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-gxbb.c
@@ -200,6 +200,15 @@ static const unsigned int uart_rx_c_pins[] = {
PIN(GPIOY_14, EE_OFF) };
static const unsigned int uart_cts_c_pins[]= { PIN(GPIOX_11, EE_OFF) };
static const unsigned int uart_rts_c_pins[]= { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int i2c_sck_a_pins[] = { PIN(GPIODV_25, EE_OFF) };
+static const unsigned int i2c_sda_a_pins[] = { PIN(GPIODV_24, EE_OFF) };
+
+static const unsigned int i2c_sck_b_pins[] = { PIN(GPIODV_27, EE_OFF) };
+static const unsigned int i2c_sda_b_pins[] = { PIN(GPIODV_26, EE_OFF) };
+
+static const unsigned int i2c_sck_c_pins[] = { PIN(GPIODV_29, EE_OFF) };
+static const unsigned int i2c_sda_c_pins[] = { PIN(GPIODV_28, EE_OFF) };
+
static const unsigned int eth_mdio_pins[] = { PIN(GPIOZ_0, EE_OFF) };
static const unsigned int eth_mdc_pins[] = { PIN(GPIOZ_1, EE_OFF) };
static const unsigned int eth_clk_rx_clk_pins[]= { PIN(GPIOZ_2,
EE_OFF) };
@@ -438,6 +447,12 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[]
= {
GROUP(uart_rts_b, 2, 26),
GROUP(pwm_b,3, 21),
GROUP(pwm_d,3, 20),
+ GROUP(i2c_sck_a,7, 27),
+ GROUP(i2c_sda_a,7, 26),
+ GROUP(i2c_sck_b,7, 25),
+ GROUP(i2c_sda_b,7, 24),
+ GROUP(i2c_sck_c,7, 23),
+ GROUP(i2c_sda_c,7, 22),
/* Bank BOOT */
GROUP(emmc_nand_d07,4, 30),
@@ -574,6 +589,18 @@ static const char * const uart_c_groups[] = {
"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
};
+static const char * const i2c_a_groups[] = {
+ "i2c_sck_a", "i2c_sda_a",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_sck_b", "i2c_sda_b",
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_sck_c", "i2c_sda_c",
+};
+
static const char * const eth_groups[] = {
"eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
"eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
@@ -661,6 +688,9 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[]
= {
FUNCTION(uart_a),
FUNCTION(uart_b),
FUNCTION(uart_c),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(i2c_c),
FUNCTION(eth),
FUNCTION(pwm_a_x),
FUNCTION(pwm_a_y),
--
2.7.4
Re: [RFC] gpio: about the need to manage irq mapping dynamically.
On Tue, 2017-06-20 at 10:39 +0200, Linus Walleij wrote: > On Thu, Jun 15, 2017 at 6:20 PM, Jerome Brunet wrote: > > > To handle this we tried: > > - [0]: To create the mapping in the gpio_to_irq. Linus, you pointed out that > > this is not allowed as gpio_to_irq is callable in irq context, therefore it > > should not sleep. Actually 3 drivers [2] are calling gpio_to_irq in irq > > handlers. > > This is not the problem. The problem is that gpio_to_irq() is entirely > optional: it is not at all requires to have called gpio_to_irq() before using > an IRQ from a GPIO line, as the interrupt chips and gpio chips are > orthogonal. Agreed. no problem with this If you don't use gpio_to_irq, they are *completely* orthogonal. If you do use gpio_to_irq, you are creating this tiny relationship which makes all the difference, IMO. > > So if gpio_to_irq() is called, then a mapping needs to be retrieved, using > an irqdomain or similar, and if one does not already exist, it should be > mapped > at this point. > > But actually doing the mapping/unmapping of IRQs and related resource > management should be handled by the irqchip/irqdomain, not ever by > gpio_to_irq(). > > And someone may just be requesting an IRQ from the irqchip without > calling gpio_to_irq(). Anytime. And with devicetree this happens all of the > time. Yes, for sure. But in this case there no issue as the mapping creation is handled in device-tree code. PSB > > > I would also add that "gpio_to_irq" has no "free" counter part, so this > > approach > > leaks mappings. > > Exactly. > > > The fact that 26 gpio drivers [3] create mapping in the > > gpio_to_irq callback shows that the problem of managing the irq mapping is > > not > > specific to Amlogic and that an evolution might be useful. > > Calling irq_create_mapping() in gpio_to_irq() is not a problem if > the mapping is free:ed elsewhere. But yeah, there are lots of old > drivers with old and erroneous solutions to this problem. A lot of these drivers are old indeed, and dealing with all this history must be quite a challenge ;) However, some are fairly recent. > > > - [1]: To create an empty domain to get a virq for each pins but delay the > > setup > > of the interrupt hierarchy to the "irq_request_resources" callback. Testing > > this > > approach led me to some nasty race conditions in the interrupt handlers. I > > discussed this solution with Marc and he told me that doing the setup of the > > interrupt hierarchy in the irqchip callbacks is "too late" . If I understood > > correctly (Marc feel to correct me if necessary), you should only get a virq > > when the full interrupt hierarchy is setup, from the triggering device to > > the > > CPU. > > OK I am as always confused by "virq" which I guess means "virtual IRQ" > which is confusing since all Linux IRQ numbers are in some sense > virtual, and since this has nothing to do with virtualization, which is > another > area where IRQchips are very delicate. > Just using the usual irq wording (hwirq for the numbers specific to the controller, virq for the linux interrupt numbers) > But I get it. > > > With this last comment, I don't think there is a (clean) way ATM for a gpio > > driver to create the mapping "on demand". By "on-demand", I mean the > > consumer > > drivers doing this kind of thing: > > > > ret = request_irq(gpio_to_irq(GPIOX_Y), ... ) > > > > I would to like propose a way to fix that. > > OK solutions are good > > > It is not going to be a oneline fix, > > but I'm convinced we can do it w/o breaking anything: > > > > 1) Introduce new gpio driver callbacks (.irq_prepare, .irq_unprepare): > > Drivers > > will be free to implement those callbacks or not. Driver which can create > > all > > their mappings at probe time would obviously skip those. > > > > 2) Introduce gpio_irq_prepare and gpio_irq_unprepare to the gpio API: This > > functions would do refcounting to handle shared irq and avoid wrongly > > disposing > > of used mappings. Then call the new drivers callbacks, if defined. A devm > > version of gpio_irq_prepare might be usefull > > > > 3) Add calls to gpio_irq_prepare to consumer drivers probe/init which use > > the > > gpio_to_irq callback. I don't think this is going to be that hard to do, but > > it's going be to long and boring ... > > So how are you intending to deal with mixed semantics when, as in the > devicetree case, the GPIO driver is also flag
Re: [RFC] gpio: about the need to manage irq mapping dynamically.
On Tue, 2017-06-20 at 18:37 +0200, Linus Walleij wrote: > On Tue, Jun 20, 2017 at 12:26 PM, Jerome Brunet wrote: > > So I finally understood that what you want is to handle those cases > where gpio_to_irq() is currently in use, and not expand the use of that > function. And that is good. Indeed > > > On Tue, 2017-06-20 at 10:39 +0200, Linus Walleij wrote: > > > > The fact that 26 gpio drivers [3] create mapping in the > > > > gpio_to_irq callback shows that the problem of managing the irq mapping > > > > is > > > > not > > > > specific to Amlogic and that an evolution might be useful. > > > > > > Calling irq_create_mapping() in gpio_to_irq() is not a problem if > > > the mapping is free:ed elsewhere. But yeah, there are lots of old > > > drivers with old and erroneous solutions to this problem. > > > > A lot of these drivers are old indeed, and dealing with all this history > > must be > > quite a challenge ;) > > However, some are fairly recent. > > Unfortunately the API has merits. Like for keys: OK there is a key > for an GPIO line, and then it asks "can I have an IRQ for that"? > There are cases where the IRQ is really optional, not a required > feature. > I think you misunderstood me. I have nothing against the API. I absolutely want to keep it. I'd like to extend it. > > So there is 2 use cases: > > * What you described above: This is indeed completely orthogonal to gpio > > framework. It will be using the irqchip callbacks only. In this particular > > case, > > it is the device tree platform code which will handle the mapping creation > > for > > us. > > OK > > So the problem is really to use drivers that cannot do all their > mappings at probe > time with drivers that use gpio_to_irq(), right? Yep > > So, if the idea is to patch *ALL* drivers using gpio_to_irq(), I think > for each case > it should be investigated whether that should really be using gpio_to_irq() > but I suspect they are all pretty solid. > > Well you're probably right, the API has to change for the case where the > number > of IRQs are limited and cannot just be handled out to the left and right, but > we > should really replace *ALL* occurences of gpio_to_irq() with a pair of > gpio_irq_prepare() that also returns the valid IRQ if found, and > gpio_irq_unprepare() > that removes it. > > For the transitional period, gpio_to_irq() should *FAIL* if gpio_irq_prepare() > was called first for the same GPIO line. > > Eventually gpio_to_irq() should be DELETED and replaced in full with > the prepare/unprepare calls. Woahh, that's not what I meant. gpio_to_irq should stay. Getting rid of it would be a mess and it is a useful call. The gpio_irq_prepare is meant so that the consumer can tell the gpio driver it will want to get irq from a particular gpio at some point. IOW, it's the consumer saying to the gpio driver "please do whatever you need to do, if anything, so this gpio can generate an interrupt" This is a much simpler change. Using devm, all we need is to put a devm_gpio_irq_prepare() in the probe of the drivers using gpio_to_irq. Mandating call to gpio_irq_prepare before any call to gpio_to_irq will be fairly easy. > > And I would like strong confidence that the change will be carried all the way > through, not half-done and left to me to complete. I already have too many > problems of that type. Fair enough. > > Yours, > Linus Walleij
Re: [PATCH] clk: meson-gxbb: Add EE 32K Clock for CEC
On Wed, 2017-05-24 at 11:43 +0200, Neil Armstrong wrote:
> On Amlogic GX SoCs, there is two CEC controllers :
> - An Amlogic CEC custom in the AO domain
> - The Synopsys HDMI-TX Controller in the EE domain
>
> Each of these controllers needs a 32.768KHz clock, but there is two paths :
> - In the EE domain, the "32k_clk" this patchs is adding
> - In the AO domain, with a more complex dual divider more precise setup
>
> The AO 32K clock support will be pushed later in the corresponding
> gxbb-aoclk driver when the AE CEC driver is ready.
>
> The EE 32k_clk must be pushed earlier since mainline support for CEC in the
> Synopsys HDMI-TX controller is nearby.
>
> Signed-off-by: Neil Armstrong
Rebased and applied.
Thx
Jerome
> ---
> drivers/clk/meson/gxbb.c | 54
>
> drivers/clk/meson/gxbb.h | 5 -
> 2 files changed, 58 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
> index ad5f027..4b7d85a 100644
> --- a/drivers/clk/meson/gxbb.c
> +++ b/drivers/clk/meson/gxbb.c
> @@ -951,6 +951,51 @@ struct pll_params_table gxl_gp0_params_table[] = {
> },
> };
>
> +static struct clk_divider gxbb_32k_clk_div = {
> + .reg = (void *)HHI_32K_CLK_CNTL,
> + .shift = 0,
> + .width = 14,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "32k_clk_div",
> + .ops = &clk_divider_ops,
> + .parent_names = (const char *[]){ "32k_clk_sel" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT | CLK_DIVIDER_ROUND_CLOSEST,
> + },
> +};
> +
> +static struct clk_gate gxbb_32k_clk = {
> + .reg = (void *)HHI_32K_CLK_CNTL,
> + .bit_idx = 15,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "32k_clk",
> + .ops = &clk_gate_ops,
> + .parent_names = (const char *[]){ "32k_clk_div" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static const char *gxbb_32k_clk_parent_names[] = {
> + "xtal", "cts_slow_oscin", "fclk_div3", "fclk_div5"
> +};
> +
> +static struct clk_mux gxbb_32k_clk_sel = {
> + .reg = (void *)HHI_32K_CLK_CNTL,
> + .mask = 0x3,
> + .shift = 16,
> + .lock = &clk_lock,
> + .hw.init = &(struct clk_init_data){
> + .name = "32k_clk_sel",
> + .ops = &clk_mux_ops,
> + .parent_names = gxbb_32k_clk_parent_names,
> + .num_parents = 4,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> /* Everything Else (EE) domain gates */
> static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
> static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
> @@ -1158,6 +1203,9 @@ struct pll_params_table gxl_gp0_params_table[] = {
> [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
> [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
> [CLKID_CTS_I958]= &gxbb_cts_i958.hw,
> + [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
> + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
> + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
> },
> .num = NR_CLKS,
> };
> @@ -1278,6 +1326,9 @@ struct pll_params_table gxl_gp0_params_table[] = {
> [CLKID_CTS_MCLK_I958_SEL] = &gxbb_cts_mclk_i958_sel.hw,
> [CLKID_CTS_MCLK_I958_DIV] = &gxbb_cts_mclk_i958_div.hw,
> [CLKID_CTS_I958]= &gxbb_cts_i958.hw,
> + [CLKID_32K_CLK] = &gxbb_32k_clk.hw,
> + [CLKID_32K_CLK_SEL] = &gxbb_32k_clk_sel.hw,
> + [CLKID_32K_CLK_DIV] = &gxbb_32k_clk_div.hw,
> },
> .num = NR_CLKS,
> };
> @@ -1392,6 +1443,7 @@ struct pll_params_table gxl_gp0_params_table[] = {
> &gxbb_mali_1,
> &gxbb_cts_amclk,
> &gxbb_cts_mclk_i958,
> + &gxbb_32k_clk,
> };
>
> static struct clk_mux *const gxbb_clk_muxes[] = {
> @@ -1403,6 +1455,7 @@ struct pll_params_table gxl_gp0_params_table[] = {
> &gxbb_cts_amclk_sel,
> &gxbb_cts_mclk_i958_sel,
> &gxbb_cts_i958,
> + &gxbb_32k_clk_sel,
> };
>
> static struct clk_divider *const gxbb_clk_dividers[] = {
> @@ -1411,6 +1464,7 @@ struct pll_params_table gxl_gp0_params_table[] = {
> &gxbb_mali_0_div,
> &gxbb_mali_1_div,
> &gxbb_cts_mclk_i958_div,
> + &gxbb_32k_clk_div,
> };
>
> static struct meson_clk_audio_divider *const gxbb_audio_dividers[] = {
> diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
> index 93b8f07..de5fad0 100644
> --- a/drivers/clk/meson/gxbb.h
> +++ b/drivers/clk/meson/gxbb.h
> @@ -284,8 +284,11 @@
> #define CLKID_CTS_MCLK_I958_SEL 111
> #define CLKID_CTS_MCLK_I958_DIV 112
> #define CLKID_CTS_I958 113
> +#define CLKID_32K_CLK 114
> +#define C
Re: [PATCH v4 09/10] clk: add clk_rate_exclusive api
On Thu, 2017-10-26 at 07:26 +0200, Michael Turquette wrote: > Hi Jerome, > > Quoting Jerome Brunet (2017-09-24 22:00:29) > > @@ -1778,6 +1867,50 @@ int clk_set_rate(struct clk *clk, unsigned long rate) > > EXPORT_SYMBOL_GPL(clk_set_rate); > > > > /** > > + * clk_set_rate_exclusive - specify a new rate get exclusive control > > + * @clk: the clk whose rate is being changed > > + * @rate: the new rate for clk > > + * > > + * This is a combination of clk_set_rate() and clk_rate_exclusive_get() > > + * within a critical section > > + * > > + * This can be used initially to ensure that at least 1 consumer is > > + * statisfied when several consumers are competing for exclusivity over the > > + * same clock provider. > > Please add the following here: > > Calls to clk_rate_exclusive_get() should be balanced with calls to > clk_rate_exclusive_put(). Oh indeed ! I can do a resend with it or, if you prefer, you may directly amend the patch. As you prefer Thanks > > Otherwise looks good to me. > > Best regards, > Mike
Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA
On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: > According to the datasheet, in Meson-GXBB/GXL series, > The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], > while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. > > Test passed at gxl_skt dev board. I think this refer to a board naming used in amlogic vendor kernel ? Would you mind telling what it is ? > > Tested-by: Xingyu Chen > Signed-off-by: Yixun Lan Subject is missing "v2" tag and a reference to the previous message: 20171103181703.30434-1-yixun@amlogic.com > > --- > I think this error was introduced by a copy & paste from meson8 code? > and we didn't notice them due to the SANA clock is also enabled by > DTS (so SAR_ADC works fine)? > --- > drivers/clk/meson/gxbb.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c > index b2d1e8ed7152..92168348ffa6 100644 > --- a/drivers/clk/meson/gxbb.c > +++ b/drivers/clk/meson/gxbb.c > @@ -1139,7 +1139,7 @@ static MESON_GATE(gxbb_pl301, HHI_GCLK_MPEG0, 6); > static MESON_GATE(gxbb_periphs, HHI_GCLK_MPEG0, 7); > static MESON_GATE(gxbb_spicc, HHI_GCLK_MPEG0, 8); > static MESON_GATE(gxbb_i2c, HHI_GCLK_MPEG0, 9); > -static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG0, 10); > +static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG0, 10); > static MESON_GATE(gxbb_smart_card, HHI_GCLK_MPEG0, 11); > static MESON_GATE(gxbb_rng0, HHI_GCLK_MPEG0, 12); > static MESON_GATE(gxbb_uart0, HHI_GCLK_MPEG0, 13); > @@ -1190,7 +1190,7 @@ static MESON_GATE(gxbb_usb0_ddr_bridge, HHI_GCLK_MPEG2, > 9); > static MESON_GATE(gxbb_mmc_pclk, HHI_GCLK_MPEG2, 11); > static MESON_GATE(gxbb_dvin, HHI_GCLK_MPEG2, 12); > static MESON_GATE(gxbb_uart2, HHI_GCLK_MPEG2, 15); > -static MESON_GATE(gxbb_sana, HHI_GCLK_MPEG2, 22); > +static MESON_GATE(gxbb_sar_adc, HHI_GCLK_MPEG2, 22); The value currently used in the driver are with respect to the Datasheet of GXBB (v1.1.4) and GXL (S905X - V0.3-20170314), which are available to the public at http://http://linux-meson.com the adc driver is claiming both clock, so this patch should not change anything to the adc operation. * Is this patch fixing any issue ? * Is it an error in the published datasheets ? > static MESON_GATE(gxbb_vpu_intr, HHI_GCLK_MPEG2, 25); > static MESON_GATE(gxbb_sec_ahb_ahb3_bridge, HHI_GCLK_MPEG2, 26); > static MESON_GATE(gxbb_clk81_a53, HHI_GCLK_MPEG2, 29);
Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote: > > > > > > Tested-by: Xingyu Chen > > > Signed-off-by: Yixun Lan > > > > Subject is missing "v2" tag and a reference to the previous message: > > 20171103181703.30434-1-yixun@amlogic.com > > > > Ok.. > I was considering this patch as a new one, so didn't add a v2 tag It is clearly the same topic and this patch obsolete the previous one. The v2 tag is required here ... as the v3 will be for the next one.
Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA
On Mon, 2017-11-06 at 17:38 +0800, Yixun Lan wrote: > > * Is it an error in the published datasheets ? > > then, I think the published datasheet need to be updated. This needs to be clearly explained in your patch description/comment, or maybe directly in the code.
Re: [PATCH] firmware: meson-sm: use generic compatible
On Tue, 2017-10-17 at 15:50 -0500, Rob Herring wrote: > On Thu, Oct 12, 2017 at 03:47:43PM +0200, Jerome Brunet wrote: > > The meson secure monitor seems to be compatible with more SoCs than > > initially thought. Let's use the most generic compatible he have in > > DT instead of the gxbb specific one > > > > Signed-off-by: Jerome Brunet > > --- > > Documentation/devicetree/bindings/firmware/meson/meson_sm.txt | 4 ++-- > > drivers/firmware/meson/meson_sm.c | 4 ++-- > > 2 files changed, 4 insertions(+), 4 deletions(-) > > Seems like a pointless, not backwards compatible The related DTS have both the SoC family compatible and the SoC specific compatible. So it is backward compatible (even if this contraints is relaxed on meson because we are figuring out what is shared between SoCs) We are asked to put SoC family and SoC specific compatibles in DTS. What's the point of that if we are going to match on whatever was there first ? > change to me. In the > end, it's just a string to match on. Who cares what the string is. > The matched string has to keep some sort of logic to be maintainable. It should be clear what the data (or the absence of data) attached to a string relates to. If we really don't care what the string is, we could pick words at random in the dictionary ... it would be chaos, but at least it would not be confusing > Rob
Re: [PATCH] nvmem: meson: use generic compatible
On Tue, 2017-10-17 at 15:52 -0500, Rob Herring wrote: > On Fri, Oct 13, 2017 at 09:39:13PM +0200, Jerome Brunet wrote: > > On Fri, 2017-10-13 at 21:14 +0200, Martin Blumenstingl wrote: > > > Hi Jerome, > > > > > > On Thu, Oct 12, 2017 at 5:24 PM, Jerome Brunet > > > wrote: > > > > The meson efuse driver seems to be compatible with more SoCs than > > > > initially thought. Let's use the most generic compatible he have in > > > > DT instead of the gxbb specific one > > > > > > > > Signed-off-by: Jerome Brunet > > > > --- > > > > Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt | 4 ++-- > > > > drivers/nvmem/meson-efuse.c | 2 +- > > > > 2 files changed, 3 insertions(+), 3 deletions(-) > > > > > > > > diff --git a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt > > > > b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt > > > > index fafd85bd67a6..0260524292fe 100644 > > > > --- a/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt > > > > +++ b/Documentation/devicetree/bindings/nvmem/amlogic-efuse.txt > > > > @@ -1,7 +1,7 @@ > > > > = Amlogic eFuse device tree bindings = > > > > > > > > Required properties: > > > > -- compatible: should be "amlogic,meson-gxbb-efuse" > > > > +- compatible: should be "amlogic,meson-gx-efuse" > > Same comment as for the firmware. > > > > > > > have you checked with the devicetree maintainers how they want the > > > documentation to look like in this case? > > > > You mean "Should we put every compatible existing (in DT) in the > > documentation" > > From what I've seen, at least in meson drivers, only the matched ones are > > listed. > > > > That's a good question though. > > We tend to put soc specific compatible "in case" we need them later on. > > Should > > we document those ? > > Absolutely. My understanding is that this documentation is the documentation of the bindings used by the driver. If I understand your point, we should document bindings (compatible in that case) that are in fact not fact by the driver. This means that if someone refer only to the documentation, he might be surprised by the result. > > Rob
[PATCH 3/5] ARM: dts: meson8b: enable gpio interrupt controller
Add gpio interrupt controller node to the meson8b boards
Signed-off-by: Jerome Brunet
---
arch/arm/boot/dts/meson.dtsi | 9 +
arch/arm/boot/dts/meson8b.dtsi | 6 ++
2 files changed, 15 insertions(+)
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi
index 290a183e87c5..3d18ecc2bef1 100644
--- a/arch/arm/boot/dts/meson.dtsi
+++ b/arch/arm/boot/dts/meson.dtsi
@@ -85,6 +85,15 @@
reg = <0x7c00 0x200>;
};
+ gpio_intc: interrupt-controller@9880 {
+ compatible = "amlogic,meson-gpio-intc";
+ reg = <0xc1109880 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <64 65 66 67 68 69
70 71>;
+ status = "disabled";
+ };
+
hwrng: rng@8100 {
compatible = "amlogic,meson-rng";
reg = <0x8100 0x8>;
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi
index 40cfe5c8df6a..574aafa3db83 100644
--- a/arch/arm/boot/dts/meson8b.dtsi
+++ b/arch/arm/boot/dts/meson8b.dtsi
@@ -179,6 +179,12 @@
clock-names = "stmmaceth";
};
+&gpio_intc {
+ compatible = "amlogic,meson-gpio-intc",
+"amlogic,meson8b-gpio-intc";
+ status = "okay";
+};
+
&hwrng {
compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;
--
2.13.6
[PATCH 5/5] ARM64: dts: meson-gx: add external PHY interrupt on some platforms
Add the external PHY interrupt on the nanopi-k2, odroid-c2, p200, p230
and q200
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 2 ++
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 2 ++
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++
5 files changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
index 2e853c082a65..4a4251001bfd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts
@@ -168,6 +168,8 @@
eth_phy0: ethernet-phy@0 {
/* Realtek RTL8211F (0x001cc916) */
reg = <0>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
index 1deaa53c9fb5..fac5c3eeb07d 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts
@@ -157,6 +157,8 @@
eth_phy0: ethernet-phy@0 {
reg = <0>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
eee-broken-1000t;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
index 2054a474e0a9..9bf16bb7c491 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts
@@ -117,6 +117,8 @@
eth_phy0: ethernet-phy@3 {
/* Micrel KSZ9031 (0x00221620) */
reg = <3>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
index 6827f235d7cf..4f3f03fc31b0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts
@@ -128,6 +128,8 @@
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
index b65776b01911..66c6da7e112c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts
@@ -110,6 +110,8 @@
compatible = "ethernet-phy-id001c.c916",
"ethernet-phy-ieee802.3-c22";
reg = <0>;
max-speed = <1000>;
+ interrupt-parent = <&gpio_intc>;
+ interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
};
};
--
2.13.6
[PATCH 1/5] ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b
select MESON_IRQ_GPIO in Kconfig for Amlogic's meson8b SoC Signed-off-by: Jerome Brunet --- arch/arm/mach-meson/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig index ee30511849ca..dc4830bb80fc 100644 --- a/arch/arm/mach-meson/Kconfig +++ b/arch/arm/mach-meson/Kconfig @@ -28,5 +28,6 @@ config MACH_MESON8B default ARCH_MESON select MESON6_TIMER select COMMON_CLK_MESON8B + select MESON_IRQ_GPIO endif -- 2.13.6
[PATCH 4/5] ARM64: dts: meson-gx: add gpio interrupt controller
Add gpio interrupt controller to Amlogic GX family SoCs
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 9 +
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 6 ++
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ++
3 files changed, 21 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index b7723436a04b..ab7ce1644cdc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -218,6 +218,15 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xc110 0x0 0x10>;
+ gpio_intc: interrupt-controller@9880 {
+ compatible = "amlogic,meson-gpio-intc";
+ reg = <0x0 0x9880 0x0 0x10>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ amlogic,channel-interrupts = <64 65 66 67 68 69
70 71>;
+ status = "disabled";
+ };
+
reset: reset-controller@4404 {
compatible = "amlogic,meson-gx-reset",
"amlogic,meson-gxbb-reset";
reg = <0x0 0x04404 0x0 0x20>;
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
index 3d41db9c9d22..ead895a4e9a5 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi
@@ -323,6 +323,12 @@
clock-names = "stmmaceth", "clkin0", "clkin1";
};
+&gpio_intc {
+ compatible = "amlogic,meson-gpio-intc",
+"amlogic,meson-gxbb-gpio-intc";
+ status = "okay";
+};
+
&hdmi_tx {
compatible = "amlogic,meson-gxbb-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
index d3a51031a711..0aa71a35ce64 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl.dtsi
@@ -225,6 +225,12 @@
compatible = "amlogic,meson-gxl-aoclkc", "amlogic,meson-gx-aoclkc";
};
+&gpio_intc {
+ compatible = "amlogic,meson-gpio-intc",
+"amlogic,meson-gxl-gpio-intc";
+ status = "okay";
+};
+
&hdmi_tx {
compatible = "amlogic,meson-gxl-dw-hdmi", "amlogic,meson-gx-dw-hdmi";
resets = <&reset RESET_HDMITX_CAPB3>,
--
2.13.6
[PATCH 0/5] ARM: meson: enable gpio interrupt controller
This patchset enables gpio interrupt controller found on the meson SoC family. ATM, it supports meson8b, gxbb and gxl. The meson8 has been left out because I don't have the documentation of this particular SoC. The last patch uses the interrupts provided by this controller with the external ethernet PHY found on a few platforms. Jerome Brunet (5): ARM: meson: enable MESON_IRQ_GPIO in Kconfig for meson8b ARM64: meson: enable MESON_IRQ_GPIO in Kconfig ARM: dts: meson8b: enable gpio interrupt controller ARM64: dts: meson-gx: add gpio interrupt controller ARM64: dts: meson-gx: add external PHY interrupt on some platforms arch/arm/boot/dts/meson.dtsi | 9 + arch/arm/boot/dts/meson8b.dtsi | 6 ++ arch/arm/mach-meson/Kconfig | 1 + arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/amlogic/meson-gx.dtsi| 9 + arch/arm64/boot/dts/amlogic/meson-gxbb-nanopi-k2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 6 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 12 files changed, 48 insertions(+) -- 2.13.6
[PATCH 2/5] ARM64: meson: enable MESON_IRQ_GPIO in Kconfig
select MESON_IRQ_GPIO in Kconfig for Amlogic's meson SoC family Signed-off-by: Jerome Brunet --- arch/arm64/Kconfig.platforms | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/Kconfig.platforms b/arch/arm64/Kconfig.platforms index 6b54ee8c1262..5d5e79e8d556 100644 --- a/arch/arm64/Kconfig.platforms +++ b/arch/arm64/Kconfig.platforms @@ -104,6 +104,7 @@ config ARCH_MESON select PINCTRL_MESON select COMMON_CLK_AMLOGIC select COMMON_CLK_GXBB + select MESON_IRQ_GPIO help This enables support for the Amlogic S905 SoCs. -- 2.13.6
Re: [PATCH v2 1/4] soc: amlogic: add meson-canvas driver
On Wed, 2018-08-08 at 00:00 +0200, Maxime Jourdan wrote:
> Amlogic SoCs have a repository of 256 canvas which they use to
> describe pixel buffers.
>
> They contain metadata like width, height, block mode, endianness [..]
>
> Many IPs within those SoCs like vdec/vpu rely on those canvas to read/write
> pixels.
>
> Signed-off-by: Maxime Jourdan
> Tested-by: Neil Armstrong
Thanks for making the changes Martin, I do prefer this version. You did not have
to drop the ops, until it is really needed because of some SoC quirks, I guess
it is simpler this way
With some answers to the nitpicks below, feel free to add :
Reviewed-by: Jerome Brunet
> ---
> drivers/soc/amlogic/Kconfig | 7 +
> drivers/soc/amlogic/Makefile | 1 +
> drivers/soc/amlogic/meson-canvas.c | 185 +++
> include/linux/soc/amlogic/meson-canvas.h | 65
> 4 files changed, 258 insertions(+)
> create mode 100644 drivers/soc/amlogic/meson-canvas.c
> create mode 100644 include/linux/soc/amlogic/meson-canvas.h
>
> diff --git a/drivers/soc/amlogic/Kconfig b/drivers/soc/amlogic/Kconfig
> index b04f6e4aedbc..2f282b472912 100644
> --- a/drivers/soc/amlogic/Kconfig
> +++ b/drivers/soc/amlogic/Kconfig
> @@ -1,5 +1,12 @@
> menu "Amlogic SoC drivers"
>
> +config MESON_CANVAS
> + tristate "Amlogic Meson Canvas driver"
> + depends on ARCH_MESON || COMPILE_TEST
> + default n
> + help
> + Say yes to support the canvas IP for Amlogic SoCs.
> +
> config MESON_GX_SOCINFO
> bool "Amlogic Meson GX SoC Information driver"
> depends on ARCH_MESON || COMPILE_TEST
> diff --git a/drivers/soc/amlogic/Makefile b/drivers/soc/amlogic/Makefile
> index 8fa321893928..0ab16d35ac36 100644
> --- a/drivers/soc/amlogic/Makefile
> +++ b/drivers/soc/amlogic/Makefile
> @@ -1,3 +1,4 @@
> +obj-$(CONFIG_MESON_CANVAS) += meson-canvas.o
> obj-$(CONFIG_MESON_GX_SOCINFO) += meson-gx-socinfo.o
> obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
> obj-$(CONFIG_MESON_MX_SOCINFO) += meson-mx-socinfo.o
> diff --git a/drivers/soc/amlogic/meson-canvas.c
> b/drivers/soc/amlogic/meson-canvas.c
> new file mode 100644
> index ..c461334b36d4
> --- /dev/null
> +++ b/drivers/soc/amlogic/meson-canvas.c
> @@ -0,0 +1,185 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright (C) 2018 Maxime Jourdan
> + * Copyright (C) 2016 BayLibre, SAS
> + * Author: Neil Armstrong
> + * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
> + * Copyright (C) 2014 Endless Mobile
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#define NUM_CANVAS 256
> +
> +/* DMC Registers */
> +#define DMC_CAV_LUT_DATAL0x48 /* 0x12 offset in data sheet */
> + #define CANVAS_WIDTH_LBIT 29
> + #define CANVAS_WIDTH_LWID 3
> +#define DMC_CAV_LUT_DATAH0x4c /* 0x13 offset in data sheet */
> + #define CANVAS_WIDTH_HBIT 0
> + #define CANVAS_HEIGHT_BIT 9
> + #define CANVAS_BLKMODE_BIT 24
> +#define DMC_CAV_LUT_ADDR 0x50 /* 0x14 offset in data sheet */
> + #define CANVAS_LUT_WR_EN(0x2 << 8)
> + #define CANVAS_LUT_RD_EN(0x1 << 8)
> +
> +struct meson_canvas {
> + struct device *dev;
> + struct regmap *regmap_dmc;
> + spinlock_t lock; /* canvas device lock */
> + u8 used[NUM_CANVAS];
> +};
> +
> +struct meson_canvas *meson_canvas_get(struct device *dev)
> +{
> + struct device_node *canvas_node;
> + struct platform_device *canvas_pdev;
> + struct meson_canvas *canvas;
> +
> + canvas_node = of_parse_phandle(dev->of_node, "amlogic,canvas", 0);
> + if (!canvas_node)
> + return ERR_PTR(-ENODEV);
> +
> + canvas_pdev = of_find_device_by_node(canvas_node);
> + if (!canvas_pdev) {
> + dev_err(dev, "Unable to find canvas pdev\n");
> + return ERR_PTR(-ENODEV);
> + }
> +
> + canvas = dev_get_drvdata(&canvas_pdev->dev);
> + if (!canvas)
> + return ERR_PTR(-ENODEV);
You've got your device at this point, maybe EINVAL instead ?
> +
> + return canvas;
> +}
> +EXPORT_SYMBOL_GPL(meson_canvas_get);
> +
> +int meson_canvas_setup(struct meson_canvas *canvas, u8 canvas_index,
> +u32 addr, u32 stride, u32 height,
> +unsigned int wrap,
> +unsigned int blkmode,
> +unsigned int endian)
> +{
> + struct regmap *regmap = canvas->regmap_
Re: [PATCH] clk: meson: audio-divider is one based
On Wed, 2018-06-20 at 10:31 +0200, Neil Armstrong wrote:
> On 19/06/2018 17:47, Jerome Brunet wrote:
> > The audio divider is one based. This offset was mistakenly dropped from
> > recalc_rate() when migrating to clk_regmap.
> >
> > Fixes: 88a4e1283681 ("clk: meson: migrate the audio divider clock to
> > clk_regmap")
> > Signed-off-by: Jerome Brunet
> > ---
> > drivers/clk/meson/clk-audio-divider.c | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/meson/clk-audio-divider.c
> > b/drivers/clk/meson/clk-audio-divider.c
> > index 58f546e04807..e4cf96ba704e 100644
> > --- a/drivers/clk/meson/clk-audio-divider.c
> > +++ b/drivers/clk/meson/clk-audio-divider.c
> > @@ -51,7 +51,7 @@ static unsigned long audio_divider_recalc_rate(struct
> > clk_hw *hw,
> > struct meson_clk_audio_div_data *adiv = meson_clk_audio_div_data(clk);
> > unsigned long divider;
> >
> > - divider = meson_parm_read(clk->map, &adiv->div);
> > + divider = meson_parm_read(clk->map, &adiv->div) + 1;
> >
> > return DIV_ROUND_UP_ULL((u64)parent_rate, divider);
> > }
> >
>
> Acked-by: Neil Armstrong
>
Applied for fixes
Re: [PATCH] clk: meson: remove obsolete register access
On Wed, 2018-06-20 at 10:31 +0200, Neil Armstrong wrote: > On 19/06/2018 18:00, Jerome Brunet wrote: > > The legacy method to access the hhi register space is not longer used. > > We can safely drop it now. > > > > Signed-off-by: Jerome Brunet > > --- > > drivers/clk/meson/axg.c | 37 ++--- > > drivers/clk/meson/gxbb.c | 36 ++-- > > 2 files changed, 4 insertions(+), 69 deletions(-) > > > > [...] > > Acked-by: Neil Armstrong Applied for next
Re: [PATCH v2 0/6] clk: meson: axg: add audio clock controller support
On Tue, 2018-05-22 at 18:34 +0200, Jerome Brunet wrote: > The purpose of this patchset is to add support for the clock controller > dedicated to the audio subsystem found on A113 based SoCs > > The series depends on the CLK_MUX_ROUND_CLOSEST fixes [merged in clk-next] > and the duty cycle support [1] making their way into CCF. > > First patch is a clean-up of the meson clk Kconfig. > Then, there is 3 clock provider drivers for clocks found in the audio > The last 3 are for the clock controller itself. > > Changes since v1: [2] > * Rebase clk-meson's next/drivers > * Correct typo in documentation and squash DT patches > > [1]: https://lkml.kernel.org/r/20180420211141.28929-1-jbru...@baylibre.com > [2]: https://lkml.kernel.org/r/20180425163304.10852-1-jbru...@baylibre.com > > Jerome Brunet (6): > clk: meson: clean-up meson clock configuration > clk: meson: add clk-phase clock driver > clk: meson: add triple phase clock driver > clk: meson: add axg audio sclk divider driver > dt-bindings: clock: add meson axg audio clock controller bindings > clk: meson: axg: add the audio clock controller driver Applied for next on top of mike's clk-core-duty-cycle branch.
[PATCH] ASoC: dpcm: improve runtime update predictability
As it is, dpcm_runtime_update() performs the old path and new path
update of a frontend before going on to the next frontend DAI.
Depending the order of the FEs within the rtd list, the result of
the update might be different.
For example:
* Frontend A connected to backend C, with a 48kHz playback
* Frontend B connected to backend D, with a 44.1kHz playback
* FE A appears before FE B in the rtd list of the card.
If we reparent BE C to FE B (disconnecting BE D):
* old path update of FE A will run first, and BE C will get hw_free()
and shutdown()
* new path update of FE B will run after and BE C, which is stopped,
so it will be configured at 44.1kHz, as expected
If we reparent BE D to FE A (disconnecting BE C):
* new path update of FE A will run first but since BE D is still running
at 44.1kHz, it won't be reconfigured (no call to startup() or
hw_params())
* old path update of FE B runs after, nothing happens
* In this case, we end up with a BE playing at 44.1kHz a stream which is
supposed to be played at 48Khz (too slow)
To improve this situation, this patch performs all the FE old paths update
before going on to update the new paths. With this, the result should
no longer depend on the order of the FE within the card rtd list.
Please note that there might be a small performance penalty since
dpcm_process_paths() is called twice per stream direction.
Signed-off-by: Jerome Brunet
---
sound/soc/soc-pcm.c | 165 +++-
1 file changed, 86 insertions(+), 79 deletions(-)
diff --git a/sound/soc/soc-pcm.c b/sound/soc/soc-pcm.c
index 5e7ae47a9658..5c2534414478 100644
--- a/sound/soc/soc-pcm.c
+++ b/sound/soc/soc-pcm.c
@@ -2543,106 +2543,113 @@ static int dpcm_run_old_update(struct
snd_soc_pcm_runtime *fe, int stream)
return ret;
}
-/* Called by DAPM mixer/mux changes to update audio routing between PCMs and
- * any DAI links.
- */
-int soc_dpcm_runtime_update(struct snd_soc_card *card)
+int soc_dpcm_fe_runtime_update(struct snd_soc_pcm_runtime *fe, int new)
{
- struct snd_soc_pcm_runtime *fe;
- int old, new, paths;
+ struct snd_soc_dapm_widget_list *list;
+ int count, paths;
- mutex_lock_nested(&card->mutex, SND_SOC_CARD_CLASS_RUNTIME);
- list_for_each_entry(fe, &card->rtd_list, list) {
- struct snd_soc_dapm_widget_list *list;
+ if (!fe->dai_link->dynamic)
+ return 0;
- /* make sure link is FE */
- if (!fe->dai_link->dynamic)
- continue;
+ /* only check active links */
+ if (!fe->cpu_dai->active)
+ return 0;
- /* only check active links */
- if (!fe->cpu_dai->active)
- continue;
+ /* DAPM sync will call this to update DSP paths */
+ dev_dbg(fe->dev, "ASoC: DPCM %s runtime update for FE %s\n",
+ new ? "new" : "old", fe->dai_link->name);
- /* DAPM sync will call this to update DSP paths */
- dev_dbg(fe->dev, "ASoC: DPCM runtime update for FE %s\n",
- fe->dai_link->name);
+ /* skip if FE doesn't have playback capability */
+ if (!fe->cpu_dai->driver->playback.channels_min ||
+ !fe->codec_dai->driver->playback.channels_min)
+ goto capture;
- /* skip if FE doesn't have playback capability */
- if (!fe->cpu_dai->driver->playback.channels_min
- || !fe->codec_dai->driver->playback.channels_min)
- goto capture;
-
- /* skip if FE isn't currently playing */
- if (!fe->cpu_dai->playback_active
- || !fe->codec_dai->playback_active)
- goto capture;
-
- paths = dpcm_path_get(fe, SNDRV_PCM_STREAM_PLAYBACK, &list);
- if (paths < 0) {
- dev_warn(fe->dev, "ASoC: %s no valid %s path\n",
- fe->dai_link->name, "playback");
- mutex_unlock(&card->mutex);
- return paths;
- }
+ /* skip if FE isn't currently playing */
+ if (!fe->cpu_dai->playback_active || !fe->codec_dai->playback_active)
+ goto capture;
- /* update any new playback paths */
- new = dpcm_process_paths(fe, SNDRV_PCM_STREAM_PLAYBACK, &list,
1);
- if (new) {
- dpcm_run_new_update(fe, SNDRV_PCM_STREAM_PLAYBACK);
- dpcm_clear_pending_state(fe, SNDRV_PCM_STREAM_PLAYBACK);
- dpcm_be_disconnect(fe, SNDRV_PCM_STREAM_PLAYBACK);
-
Re: [PATCH] clk: meson-axg: add clocks required by pcie driver
On Thu, 2018-06-21 at 12:26 +, Yixun Lan wrote:
> Adding clocks for pcie driver, due to the ASIC design,
Adding clocks for the pcie driver. Due to the ASIC design,
> the pcie controller re-use part of the mipi clock logic,
> so the mipi clock is also required.
>
> Tested-by: Jianxin Qin
> Signed-off-by: Yixun Lan
> ---
> drivers/clk/meson/axg.c | 145 +++
> drivers/clk/meson/axg.h | 6 +-
> include/dt-bindings/clock/axg-clkc.h | 3 +
> 3 files changed, 153 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
> index bd4dbc696b88..f1dc5433b69d 100644
> --- a/drivers/clk/meson/axg.c
> +++ b/drivers/clk/meson/axg.c
> @@ -626,6 +626,137 @@ static struct clk_regmap axg_mpll3 = {
> },
> };
>
> +static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
> + {
> + .rate = 1,
> + .m = 200,
> + .n = 3,
> + .od = 1,
> + .od2= 3,
> + },
> + { /* sentinel */ },
> +};
> +
> +static const struct reg_sequence axg_pcie_init_regs[] = {
> + { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
> + { .reg = HHI_PCIE_PLL_CNTL1,.def = 0x0084a2aa },
> + { .reg = HHI_PCIE_PLL_CNTL2,.def = 0xb75020be },
> + { .reg = HHI_PCIE_PLL_CNTL3,.def = 0x0a47488e },
> + { .reg = HHI_PCIE_PLL_CNTL4,.def = 0xc04d },
> + { .reg = HHI_PCIE_PLL_CNTL5,.def = 0x00078000 },
> + { .reg = HHI_PCIE_PLL_CNTL6,.def = 0x002323c6 },
> +};
> +
> +static struct clk_regmap axg_pcie_pll = {
> + .data = &(struct meson_clk_pll_data){
> + .m = {
> + .reg_off = HHI_PCIE_PLL_CNTL,
> + .shift = 0,
> + .width = 9,
> + },
> + .n = {
> + .reg_off = HHI_PCIE_PLL_CNTL,
> + .shift = 9,
> + .width = 5,
> + },
> + .od = {
> + .reg_off = HHI_PCIE_PLL_CNTL,
> + .shift = 16,
> + .width = 2,
> + },
> + .od2 = {
> + .reg_off = HHI_PCIE_PLL_CNTL6,
> + .shift = 6,
> + .width = 2,
> + },
> + .frac = {
> + .reg_off = HHI_PCIE_PLL_CNTL1,
> + .shift = 0,
> + .width = 12,
> + },
> + .l = {
> + .reg_off = HHI_PCIE_PLL_CNTL,
> + .shift = 31,
> + .width = 1,
> + },
> + .rst = {
> + .reg_off = HHI_PCIE_PLL_CNTL,
> + .shift = 29,
> + .width = 1,
> + },
> + .table = axg_pcie_pll_rate_table,
> + .init_regs = axg_pcie_init_regs,
> + .init_count = ARRAY_SIZE(axg_pcie_init_regs),
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie_pll",
> + .ops = &meson_clk_pll_ops,
> + .parent_names = (const char *[]){ "xtal" },
> + .num_parents = 1,
> + },
> +};
> +
> +static struct clk_regmap axg_pcie_mux = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HHI_PCIE_PLL_CNTL6,
> + .mask = 0x1,
> + .shift = 2,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie_mux",
> + .ops = &clk_regmap_mux_ops,
> + .parent_names = (const char *[]){ "mpll3", "pcie_pll" },
> + .num_parents = 2,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap axg_pcie_ref = {
> + .data = &(struct clk_regmap_mux_data){
> + .offset = HHI_PCIE_PLL_CNTL6,
> + .mask = 0x1,
> + .shift = 1,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "pcie_ref",
> + .ops = &clk_regmap_mux_ops,
> + /* do not select the first partent, debug only */
> + .parent_names = (const char *[]){ "",
> + "pcie_mux" },
A) No declaring a clock name "" is not the way to do it.
Either declare a mux with just one parent and provide a table with the index of
the said parent (have a look around, other clocks mux are using table), OR just
declare what parent 0 is.
Looking at your clock, the pcie driver will have to call
clk_set_rate(clk, 1) to make sure everything is setup properly,
including this mux - otherwise you are relying on the setting provided by the
bootloader, which should be avoided whenever possible.
In this case, CCF should pick the right parent anyway, so there should be no
harm describing what your clock tree is.
B) Please fix the indentation.
C) This mux deal with bit "CML_INPUT_
[PATCH] ARM64: dts: meson-axg: fix ethernet stability issue
Like the odroid-c2 and wetek, the s400 uses the RTL8211F and seems to
suffer from the kind of stability issue.
Doing an iperf3 download test, we can see a significant number of LPI
interrupts on the tx path. After a short while (5 to 15 seconds), the
network connection dies. If using rootfs over NFS, the connection may
also break during the boot sequence.
We still don't have a real explanation for this problem so let's disable
EEE once again.
Fixes: f6f6ac914b82 ("ARM64: dts: meson-axg: enable ethernet for A113D S400
board")
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 4b3331fbfe39..dff9b15eb3c0 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -66,9 +66,22 @@
ðmac {
status = "okay";
- phy-mode = "rgmii";
pinctrl-0 = <ð_rgmii_y_pins>;
pinctrl-names = "default";
+ phy-handle = <ð_phy0>;
+ phy-mode = "rgmii";
+
+ mdio {
+ compatible = "snps,dwmac-mdio";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ eth_phy0: ethernet-phy@0 {
+ /* Realtek RTL8211F (0x001cc916) */
+ reg = <0>;
+ eee-broken-1000t;
+ };
+ };
};
&uart_A {
--
2.14.4
Re: [PATCH v2 0/4] clk: meson: clk-pll driver update
On Sun, 2018-08-12 at 20:26 +0200, Martin Blumenstingl wrote: > Hi Jerome, > > On Wed, Aug 1, 2018 at 4:00 PM Jerome Brunet wrote: > > > > This patchset is yet another round of update to the amlogic pll driver. > > > > 1) Enable bit is added so we don't rely on the bootloader or the init > > value to enable to pll device. > > 2) Remove unnecessary CLK_GET_RATE_NOCACHE flags. > > 3) OD post dividers are removed from the pll driver. This simplify the > > driver and let us provide the clocks which exist between those > > dividers. Some device are actually using these clocks. > > 4) The rates hard coded in parameter tables are remove. Instead, we > > only rely on the parent rate and the parameters to calculate the > > output rate, which is a lot better. > > > > This series has been tested on the gxl libretech cc and axg s400. > > I did not test it on meson8b yet. > > > > Changes since v1: [0] > > - improve commit description of patch 1 > > - remove unnecessary CLK_GET_RATE_NOCACHE flags. > > - add missing CLK_SET_RATE_PARENT. > > > > [0]: https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com > > > > Jerome Brunet (4): > > clk: meson: clk-pll: add enable bit > > clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary > > clk: meson: clk-pll: remove od parameters > > clk: meson: clk-pll: drop hard-coded rates from pll tables > > for the whole series: > Reviewed-by: Martin Blumenstingl > > as well as: > Tested-by: Martin Blumenstingl > (tested on Meson8b / Odroid-C1, even CPU frequency scaling still works > with my out-of-tree patches) Collected tags, rebased and queued for 4.20 > > > Regards > Martin
Re: [PATCH] clk: meson: axg: round audio system master clocks down
On Wed, 2018-08-01 at 16:07 +0200, Jerome Brunet wrote: > Some of the master clocks provided by the axg audio clock controller are > system clock (spdifin and pdm sysclk). They are used to clock an internal > DSP of the related devices. Having them constantly rounded down instead > of closest is preferable. > > Signed-off-by: Jerome Brunet > --- > drivers/clk/meson/axg-audio.c | 34 +++--- > 1 file changed, 23 insertions(+), 11 deletions(-) queued for 4.20
Re: [PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
On Fri, 2018-08-24 at 21:34 +0800, Jian Hu wrote: > > > > I am confued about aoclk81's parent clocks. > > I can not get the example of axg audio clock driver, Could you provide > the link? Had it merged into clk-meson.git? Yes and mainline as well : drivers/clk/meson/axg-audio.c Basically this driver is creating bypass input clocks (audio_pclk, mst_in[0-9], etc...) . This allows to collect input clocks from DT (like any consumer should) will keeping constant in the controller clock tree. >From what I've seen of your controller drivers, the EE controller should have one input, the AO should have 3.
Re: [PATCH] clk: meson-axg: pcie: drop the mpll3 clock parent
On Wed, 2018-08-01 at 12:16 +, Yixun Lan wrote:
> We found the PCIe driver doesn't really work with
> the mpll3 clock which is actually reserved for debug,
> So drop it from the mux list.
>
> Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
> Tested-by: Jianxin Qin
> Signed-off-by: Yixun Lan
>
> ---
Applied, Thx
[PATCH] ASoC: meson: axg-fifo: report interrupt request failure
Return value of request_irq() was irgnored. Fix this and report
the failure if any
Fixes: 6dc4fa179fb8 ("ASoC: meson: add axg fifo base driver")
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-fifo.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c
index 30262550e37b..0e4f65e654c4 100644
--- a/sound/soc/meson/axg-fifo.c
+++ b/sound/soc/meson/axg-fifo.c
@@ -203,6 +203,8 @@ static int axg_fifo_pcm_open(struct snd_pcm_substream *ss)
ret = request_irq(fifo->irq, axg_fifo_pcm_irq_block, 0,
dev_name(dev), ss);
+ if (ret)
+ return ret;
/* Enable pclk to access registers and clock the fifo ip */
ret = clk_prepare_enable(fifo->pclk);
--
2.17.1
[PATCH] ASoC: meson: axg-tdm: restrict formats depending on slot width
Restrict the formats possible on the TDM interface depending on the width
of the TDM slot and let dpcm merging do the rest.
Fixes: d60e4f1e4be5 ("ASoC: meson: add tdm interface driver")
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-tdm-interface.c | 50 +
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/sound/soc/meson/axg-tdm-interface.c
b/sound/soc/meson/axg-tdm-interface.c
index 7b8baf46d968..585ce030b79b 100644
--- a/sound/soc/meson/axg-tdm-interface.c
+++ b/sound/soc/meson/axg-tdm-interface.c
@@ -42,6 +42,7 @@ int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32
*tx_mask,
struct axg_tdm_stream *rx = (struct axg_tdm_stream *)
dai->capture_dma_data;
unsigned int tx_slots, rx_slots;
+ unsigned int fmt = 0;
tx_slots = axg_tdm_slots_total(tx_mask);
rx_slots = axg_tdm_slots_total(rx_mask);
@@ -52,38 +53,45 @@ int axg_tdm_set_tdm_slots(struct snd_soc_dai *dai, u32
*tx_mask,
return -EINVAL;
}
- /*
-* Amend the dai driver channel number and let dpcm channel merge do
-* its job
-*/
- if (tx) {
- tx->mask = tx_mask;
- dai->driver->playback.channels_max = tx_slots;
- }
-
- if (rx) {
- rx->mask = rx_mask;
- dai->driver->capture.channels_max = rx_slots;
- }
-
iface->slots = slots;
switch (slot_width) {
case 0:
- /* defaults width to 32 if not provided */
- iface->slot_width = 32;
- break;
- case 8:
- case 16:
- case 24:
+ slot_width = 32;
+ /* Fall-through */
case 32:
- iface->slot_width = slot_width;
+ fmt |= SNDRV_PCM_FMTBIT_S32_LE;
+ /* Fall-through */
+ case 24:
+ fmt |= SNDRV_PCM_FMTBIT_S24_LE;
+ fmt |= SNDRV_PCM_FMTBIT_S20_LE;
+ /* Fall-through */
+ case 16:
+ fmt |= SNDRV_PCM_FMTBIT_S16_LE;
+ /* Fall-through */
+ case 8:
+ fmt |= SNDRV_PCM_FMTBIT_S8;
break;
default:
dev_err(dai->dev, "unsupported slot width: %d\n", slot_width);
return -EINVAL;
}
+ iface->slot_width = slot_width;
+
+ /* Amend the dai driver and let dpcm merge do its job */
+ if (tx) {
+ tx->mask = tx_mask;
+ dai->driver->playback.channels_max = tx_slots;
+ dai->driver->playback.formats = fmt;
+ }
+
+ if (rx) {
+ rx->mask = rx_mask;
+ dai->driver->capture.channels_max = rx_slots;
+ dai->driver->capture.formats = fmt;
+ }
+
return 0;
}
EXPORT_SYMBOL_GPL(axg_tdm_set_tdm_slots);
--
2.17.1
[PATCH] ASoC: meson: imply clock and reset controllers
Add audio clock controller and ARB reset controller module implication for the device using them Signed-off-by: Jerome Brunet --- sound/soc/meson/Kconfig | 4 1 file changed, 4 insertions(+) diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig index 8af8bc358a90..2ccbadc387de 100644 --- a/sound/soc/meson/Kconfig +++ b/sound/soc/meson/Kconfig @@ -4,6 +4,8 @@ menu "ASoC support for Amlogic platforms" config SND_MESON_AXG_FIFO tristate select REGMAP_MMIO + imply COMMON_CLK_AXG_AUDIO + imply RESET_MESON_AUDIO_ARB config SND_MESON_AXG_FRDDR tristate "Amlogic AXG Playback FIFO support" @@ -22,6 +24,7 @@ config SND_MESON_AXG_TODDR config SND_MESON_AXG_TDM_FORMATTER tristate select REGMAP_MMIO + imply COMMON_CLK_AXG_AUDIO config SND_MESON_AXG_TDM_INTERFACE tristate @@ -58,6 +61,7 @@ config SND_MESON_AXG_SPDIFOUT tristate "Amlogic AXG SPDIF Output Support" select SND_PCM_IEC958 imply SND_SOC_SPDIF + imply COMMON_CLK_AXG_AUDIO help Select Y or M to add support for SPDIF output serializer embedded in the Amlogic AXG SoC family -- 2.17.1
[PATCH] arm64: defconfig: enable modules for amlogic s400 sound card
Compile the necessary drivers as modules, including codecs, for the s400 sound card. Signed-off-by: Jerome Brunet --- arch/arm64/configs/defconfig | 4 1 file changed, 4 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index f67e8d5e93ad..6b1daea53bd3 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -464,6 +464,7 @@ CONFIG_SND_SOC_ROCKCHIP_I2S=m CONFIG_SND_SOC_ROCKCHIP_SPDIF=m CONFIG_SND_SOC_ROCKCHIP_RT5645=m CONFIG_SND_SOC_RK3399_GRU_SOUND=m +CONFIG_SND_MESON_AXG_SOUND_CARD=m CONFIG_SND_SOC_SAMSUNG=y CONFIG_SND_SOC_RCAR=m CONFIG_SND_SOC_AK4613=m @@ -475,6 +476,9 @@ CONFIG_SND_SOC_RT5514_SPI=m CONFIG_SND_SOC_RT5645=m CONFIG_SND_SIMPLE_CARD=m CONFIG_SND_AUDIO_GRAPH_CARD=m +CONFIG_SND_SOC_ES7134=m +CONFIG_SND_SOC_ES7241=m +CONFIG_SND_SOC_TAS571X=m CONFIG_I2C_HID=m CONFIG_USB=y CONFIG_USB_OTG=y -- 2.17.1
[PATCH 1/4] ASoC: dmic: add Kconfig prompt for the generic dmic codec.
Add Kconfig prompt for the generic digital mic to make it configurable through menuconfig Signed-off-by: Jerome Brunet --- sound/soc/codecs/Kconfig | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/sound/soc/codecs/Kconfig b/sound/soc/codecs/Kconfig index adaf26e1989c..9989d35e0fc6 100644 --- a/sound/soc/codecs/Kconfig +++ b/sound/soc/codecs/Kconfig @@ -578,7 +578,11 @@ config SND_SOC_DA9055 tristate config SND_SOC_DMIC - tristate + tristate "Generic Digital Microphone CODEC" + depends on GPIOLIB + help + Enable support for the Generic Digital Microphone CODEC. + Select this if your sound card has DMICs. config SND_SOC_HDMI_CODEC tristate -- 2.17.1
[PATCH 0/4] ASoC: meson-axg: add pdm input support
The purpose of this patchset is to add the support for PDM input backend found on the AXG SoC family. The first 2 patches, for the dmic, are not specific to this amlogic driver but it is useful to have them since the PDM input will use this dmic codec. Jerome Brunet (4): ASoC: dmic: add Kconfig prompt for the generic dmic codec. ASoC: dmic: add DT module alias ASoC: meson: add axg pdm input DT binding documentation ASoC: meson: add axg pdm input .../bindings/sound/amlogic,axg-pdm.txt| 24 + sound/soc/codecs/Kconfig | 6 +- sound/soc/codecs/dmic.c | 1 + sound/soc/meson/Kconfig | 9 + sound/soc/meson/Makefile | 2 + sound/soc/meson/axg-pdm.c | 654 ++ 6 files changed, 695 insertions(+), 1 deletion(-) create mode 100644 Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt create mode 100644 sound/soc/meson/axg-pdm.c -- 2.17.1
[PATCH 3/4] ASoC: meson: add axg pdm input DT binding documentation
Add the DT binding documentation for axg's PDM input
Signed-off-by: Jerome Brunet
---
.../bindings/sound/amlogic,axg-pdm.txt| 24 +++
1 file changed, 24 insertions(+)
create mode 100644 Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt
diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt
b/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt
new file mode 100644
index ..5672d0bc5b16
--- /dev/null
+++ b/Documentation/devicetree/bindings/sound/amlogic,axg-pdm.txt
@@ -0,0 +1,24 @@
+* Amlogic Audio PDM input
+
+Required properties:
+- compatible: 'amlogic,axg-pdm'
+- reg: physical base address of the controller and length of memory
+ mapped region.
+- clocks: list of clock phandle, one for each entry clock-names.
+- clock-names: should contain the following:
+ * "pclk" : peripheral clock.
+ * "dclk" : pdm digital clock
+ * "sysclk" : dsp system clock
+- #sound-dai-cells: must be 0.
+
+Example of PDM on the A113 SoC:
+
+pdm: audio-controller@ff632000 {
+ compatible = "amlogic,axg-pdm";
+ reg = <0x0 0xff632000 0x0 0x34>;
+ #sound-dai-cells = <0>;
+ clocks = <&clkc_audio AUD_CLKID_PDM>,
+<&clkc_audio AUD_CLKID_PDM_DCLK>,
+<&clkc_audio AUD_CLKID_PDM_SYSCLK>;
+ clock-names = "pclk", "dclk", "sysclk";
+};
--
2.17.1
[PATCH 4/4] ASoC: meson: add axg pdm input
Add pdm input driver for the device found on the amlogic AXG SoC family
Signed-off-by: Jerome Brunet
---
sound/soc/meson/Kconfig | 9 +
sound/soc/meson/Makefile | 2 +
sound/soc/meson/axg-pdm.c | 654 ++
3 files changed, 665 insertions(+)
create mode 100644 sound/soc/meson/axg-pdm.c
diff --git a/sound/soc/meson/Kconfig b/sound/soc/meson/Kconfig
index 2ccbadc387de..8b8426ed2363 100644
--- a/sound/soc/meson/Kconfig
+++ b/sound/soc/meson/Kconfig
@@ -54,6 +54,7 @@ config SND_MESON_AXG_SOUND_CARD
imply SND_MESON_AXG_TDMIN
imply SND_MESON_AXG_TDMOUT
imply SND_MESON_AXG_SPDIFOUT
+ imply SND_MESON_AXG_PDM
help
Select Y or M to add support for the AXG SoC sound card
@@ -66,4 +67,12 @@ config SND_MESON_AXG_SPDIFOUT
Select Y or M to add support for SPDIF output serializer embedded
in the Amlogic AXG SoC family
+config SND_MESON_AXG_PDM
+ tristate "Amlogic AXG PDM Input Support"
+ imply SND_SOC_DMIC
+ imply COMMON_CLK_AXG_AUDIO
+ help
+ Select Y or M to add support for PDM input embedded
+ in the Amlogic AXG SoC family
+
endmenu
diff --git a/sound/soc/meson/Makefile b/sound/soc/meson/Makefile
index c5e003b093db..4cd25104029d 100644
--- a/sound/soc/meson/Makefile
+++ b/sound/soc/meson/Makefile
@@ -9,6 +9,7 @@ snd-soc-meson-axg-tdmin-objs := axg-tdmin.o
snd-soc-meson-axg-tdmout-objs := axg-tdmout.o
snd-soc-meson-axg-sound-card-objs := axg-card.o
snd-soc-meson-axg-spdifout-objs := axg-spdifout.o
+snd-soc-meson-axg-pdm-objs := axg-pdm.o
obj-$(CONFIG_SND_MESON_AXG_FIFO) += snd-soc-meson-axg-fifo.o
obj-$(CONFIG_SND_MESON_AXG_FRDDR) += snd-soc-meson-axg-frddr.o
@@ -19,3 +20,4 @@ obj-$(CONFIG_SND_MESON_AXG_TDMIN) += snd-soc-meson-axg-tdmin.o
obj-$(CONFIG_SND_MESON_AXG_TDMOUT) += snd-soc-meson-axg-tdmout.o
obj-$(CONFIG_SND_MESON_AXG_SOUND_CARD) += snd-soc-meson-axg-sound-card.o
obj-$(CONFIG_SND_MESON_AXG_SPDIFOUT) += snd-soc-meson-axg-spdifout.o
+obj-$(CONFIG_SND_MESON_AXG_PDM) += snd-soc-meson-axg-pdm.o
diff --git a/sound/soc/meson/axg-pdm.c b/sound/soc/meson/axg-pdm.c
new file mode 100644
index ..9d5684493ffc
--- /dev/null
+++ b/sound/soc/meson/axg-pdm.c
@@ -0,0 +1,654 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+//
+// Copyright (c) 2018 BayLibre, SAS.
+// Author: Jerome Brunet
+
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+#include
+
+#define PDM_CTRL 0x00
+#define PDM_CTRL_EN BIT(31)
+#define PDM_CTRL_OUT_MODE BIT(29)
+#define PDM_CTRL_BYPASS_MODE BIT(28)
+#define PDM_CTRL_RST_FIFO BIT(16)
+#define PDM_CTRL_CHAN_RSTN_MASK GENMASK(15, 8)
+#define PDM_CTRL_CHAN_RSTN(x) ((x) << 8)
+#define PDM_CTRL_CHAN_EN_MASK GENMASK(7, 0)
+#define PDM_CTRL_CHAN_EN(x) ((x) << 0)
+#define PDM_HCIC_CTRL1 0x04
+#define PDM_FILTER_EN BIT(31)
+#define PDM_HCIC_CTRL1_GAIN_SFT_MASK GENMASK(29, 24)
+#define PDM_HCIC_CTRL1_GAIN_SFT(x)((x) << 24)
+#define PDM_HCIC_CTRL1_GAIN_MULT_MASK GENMASK(23, 16)
+#define PDM_HCIC_CTRL1_GAIN_MULT(x) ((x) << 16)
+#define PDM_HCIC_CTRL1_DSR_MASK GENMASK(8, 4)
+#define PDM_HCIC_CTRL1_DSR(x) ((x) << 4)
+#define PDM_HCIC_CTRL1_STAGE_NUM_MASK GENMASK(3, 0)
+#define PDM_HCIC_CTRL1_STAGE_NUM(x) ((x) << 0)
+#define PDM_HCIC_CTRL2 0x08
+#define PDM_F1_CTRL0x0c
+#define PDM_LPF_ROUND_MODE_MASK GENMASK(17, 16)
+#define PDM_LPF_ROUND_MODE(x) ((x) << 16)
+#define PDM_LPF_DSR_MASK GENMASK(15, 12)
+#define PDM_LPF_DSR(x)((x) << 12)
+#define PDM_LPF_STAGE_NUM_MASKGENMASK(8, 0)
+#define PDM_LPF_STAGE_NUM(x) ((x) << 0)
+#define PDM_LPF_MAX_STAGE 336
+#define PDM_LPF_NUM 3
+#define PDM_F2_CTRL0x10
+#define PDM_F3_CTRL0x14
+#define PDM_HPF_CTRL 0x18
+#define PDM_HPF_SFT_STEPS_MASKGENMASK(20, 16)
+#define PDM_HPF_SFT_STEPS(x) ((x) << 16)
+#define PDM_HPF_OUT_FACTOR_MASK GENMASK(15, 0)
+#define PDM_HPF_OUT_FACTOR(x) ((x) << 0)
+#define PDM_CHAN_CTRL 0x1c
+#define PDM_CHAN_CTRL_POINTER_WIDTH 8
+#define PDM_CHAN_CTRL_POINTER_MAX ((1 << PDM_CHAN_CTRL_POINTER_WIDTH) - 1)
+#define PDM_CHAN_CTRL_NUM 4
+#define PDM_CHAN_CTRL1 0x20
+#define PDM_COEFF_ADDR 0x24
+#define PDM_COEFF_DATA 0x28
+#define PDM_CLKG_CTRL 0x2c
+#define PDM_STS0x30
+
+struct axg_pdm_lpf {
+ unsigned int ds;
+ unsigned int round_mode;
+ const unsigned int *tap;
+ unsigned int tap_num;
[PATCH 2/4] ASoC: dmic: add DT module alias
Before this patch the only alias provided by the dmic module is:
alias: platform:dmic-codec
Device instantiated from DT will not probe automatically with this
After this patch, here is the new alias list:
alias: platform:dmic-codec
alias: of:N*T*Cdmic-codecC*
alias: of:N*T*Cdmic-codec
Now the dmic codec probes automatically when instantiated from DT.
Signed-off-by: Jerome Brunet
---
sound/soc/codecs/dmic.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/sound/soc/codecs/dmic.c b/sound/soc/codecs/dmic.c
index 8c4926df9286..71322e0410ee 100644
--- a/sound/soc/codecs/dmic.c
+++ b/sound/soc/codecs/dmic.c
@@ -148,6 +148,7 @@ static const struct of_device_id dmic_dev_match[] = {
{.compatible = "dmic-codec"},
{}
};
+MODULE_DEVICE_TABLE(of, dmic_dev_match);
static struct platform_driver dmic_driver = {
.driver = {
--
2.17.1
[PATCH] arm64: dts: meson-axg: sort nodes consistently
Sort DT nodes by address when possible, by node node name otherwise.
Signed-off-by: Jerome Brunet
---
Hi Kevin,
This patch is same kind of clean-up we already did on gxbb and gxl some
time ago. In the same fashion, it ends up being and ugly and almost unreadable
patch, sorry about that :( I don't think there was a way to avoid it.
The patch applies on top v4.19-rc1 + 3 DT audio patches which are in your
v4.19/dt64 branch [0]
There should be no functional change after applying this patch.
I've tested it in on the s400 and so far, so good.
[0]: https://lkml.kernel.org/r/20180801134033.21739-1-jbru...@baylibre.com
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 212 +-
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 1758 -
2 files changed, 985 insertions(+), 985 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index d399078d1f0c..ff64c429d432 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -60,6 +60,37 @@
serial1 = &uart_A;
};
+ linein: audio-codec@0 {
+ #sound-dai-cells = <0>;
+ compatible = "everest,es7241";
+ VDDA-supply = <&vcc_3v3>;
+ VDDP-supply = <&vcc_3v3>;
+ VDDD-supply = <&vcc_3v3>;
+ status = "okay";
+ sound-name-prefix = "Linein";
+ };
+
+ lineout: audio-codec@1 {
+ #sound-dai-cells = <0>;
+ compatible = "everest,es7154";
+ VDD-supply = <&vcc_3v3>;
+ PVDD-supply = <&vcc_5v>;
+ status = "okay";
+ sound-name-prefix = "Lineout";
+ };
+
+ spdif_dit: audio-codec@2 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
+ };
+
main_12v: regulator-main_12v {
compatible = "regulator-fixed";
regulator-name = "12V";
@@ -68,15 +99,26 @@
regulator-always-on;
};
- vddio_boot: regulator-vddio_boot {
+ vcc_3v3: regulator-vcc_3v3 {
compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <180>;
- regulator-max-microvolt = <180>;
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <330>;
+ regulator-max-microvolt = <330>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
vddao_3v3: regulator-vddao_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDDAO_3V3";
@@ -95,26 +137,15 @@
regulator-always-on;
};
- vcc_3v3: regulator-vcc_3v3 {
+ vddio_boot: regulator-vddio_boot {
compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <330>;
- regulator-max-microvolt = <330>;
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <180>;
+ regulator-max-microvolt = <180>;
vin-supply = <&vddao_3v3>;
regulator-always-on;
};
- vcc_5v: regulator-vcc_5v {
- compatible = "regulator-fixed";
- regulator-name = "VCC5V";
- regulator-min-microvolt = <500>;
- regulator-max-microvolt = <500>;
- vin-supply = <&main_12v>;
-
- gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
- enable-active-high;
- };
-
usb_pwr: regulator-usb_pwr {
compatible = "regulator-fixed";
regulator-name = "USB_PWR";
@@ -126,11 +157,6 @@
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On Thu, 2018-08-30 at 15:37 +0800, Hanjie Lin wrote: > > On 2018/8/29 8:41, Rob Herring wrote: > > On Mon, Aug 27, 2018 at 04:55:20PM +0800, Hanjie Lin wrote: > > > > > > > > > On 2018/8/24 16:22, Jerome Brunet wrote: > > > > On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote: > > > > > From: Yue Wang > > > > > > > > > > The Amlogic Meson PCIe host controller is based on the Synopsys > > > > > DesignWare > > > > > PCI core. This patch adds documentation for the DT bindings in Meson > > > > > PCIe > > > > > controller. > > > > > > > > > > Signed-off-by: Yue Wang > > > > > Signed-off-by: Hanjie Lin > > > > > --- > > > > > .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63 > > > > > ++ > > > > > 1 file changed, 63 insertions(+) > > > > > create mode 100644 > > > > > Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > > > > > > > > > > diff --git > > > > > a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > > > > > b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > > > > > new file mode 100644 > > > > > index 000..8a831d1 > > > > > --- /dev/null > > > > > +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt > > > > > @@ -0,0 +1,63 @@ > > > > > +Amlogic Meson AXG DWC PCIE SoC controller > > > > > + > > > > > +Amlogic Meson PCIe host controller is based on the Synopsys > > > > > DesignWare PCI core. > > > > > +It shares common functions with the PCIe DesignWare core driver and > > > > > +inherits common properties defined in > > > > > +Documentation/devicetree/bindings/pci/designware-pci.txt. > > > > > + > > > > > +Additional properties are described here: > > > > > + > > > > > +Required properties: > > > > > +- compatible: > > > > > + should contain "amlogic,axg-pcie" to identify the core. > > > > > +- reg: > > > > > + Should contain the configuration address space. > > > > > +- reg-names: Must be > > > > > + - "elbi"External local bus interface registers > > > > > + - "cfg" Meson specific registers > > > > > + - "config" PCIe configuration space > > > > > +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert > > > > > signal. > > > > > +- clocks: Must contain an entry for each entry in clock-names. > > > > > +- clock-names: Must include the following entries: > > > > > + - "pclk" PCIe GEN 100M PLL clock > > > > > + - "port" PCIe_x(A or B) RC clock gate > > > > > + - "general"PCIe Phy clock > > > > > + - "mipi" PCIe_x(A or B) 100M ref clock gate > > > > > +- resets: phandle to the reset lines. > > > > > +- reset-names: must contain "phy" and "peripheral" > > > > > + - "port" Port A or B reset > > > > > + - "apb" APB reset > > > > > > > > The above description is not coherent (phy <=> port) > > > > > > > > > > Yes, this should be port and apb here. > > > We'll integrate phy driver into ctrl driver, and move phy reset to here > > > also. > > > > Why? That's the wrong thing to do if they are separate h/w blocks. You > > can do whatever you like in the drivers, but the DT should reflect the > > h/w. > > > > Rob > > > > . > > > > We have the dedicated phy driver which only process reset job, > and we consider that it's too overkill to do just these things . > So we will integrate phy reset job into the controller driver int the next > version. Rob has a point there. Even if overkill, it does model the HW as it is. + I spotted in your v2 that there is also a register access, so not only the reset > > thanks.
[PATCH] arm64: dts: meson: libretech: update board model
There is actually several different libretech board with the CC suffix
so the model name is not appropriate here. Update to something more
specific
Reported-by: Da Xue
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
index f63bceb88caa..90a56af967a7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905x-libretech-cc.dts
@@ -13,7 +13,7 @@
/ {
compatible = "libretech,cc", "amlogic,s905x", "amlogic,meson-gxl";
- model = "Libre Technology CC";
+ model = "Libre Computer Board AML-S905X-CC";
aliases {
serial0 = &uart_AO;
--
2.17.1
Re: [PATCH v2 3/4] ARM64: dts: meson-gx: add dmcbus and canvas nodes.
On Wed, 2018-08-08 at 00:00 +0200, Maxime Jourdan wrote:
> Wrap the canvas node in a syscon node.
>
> Signed-off-by: Maxime Jourdan
> ---
> arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 17 +
> 1 file changed, 17 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> index b8dc4dbb391b..c98198662ae2 100644
> --- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> +++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
> @@ -423,6 +423,23 @@
> };
> };
>
> + dmcbus: bus@c8838000 {
> + compatible = "simple-bus";
> + reg = <0x0 0xc8838000 0x0 0x1000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0x0 0x0 0x0 0xc8838000 0x0 0x1000>;
> +
> + sysctrl_DMC: system-controller@0 {
> + compatible = "amlogic,gx-dmc-sysctrl",
> "syscon", "simple-mfd";
> + reg = <0x0 0x0 0x0 0x1000>;
> +
> + canvas: canvas-provider@0 {
> + compatible = "amlogic,canvas";
If there is only one canvas provider under "sysctrl_DMC" and it has no reg
property , you should not put a unit-address (@0) here. (same for the
documentation patch)
You may have seen unit-address without a reg property used elsewhere (ASoC
simple-card, my recent axg-sound-card), when there is multiple node with the
same node-name (ex: dai-link).
As Martin pointed out, the DT spec says we should not use unit-address unless
there is a reg property. We did not get Rob's view on this and we might have to
update this later on. In your case, unless I missed something, you should
definitely not have it
nitpick regarding the node-name (canvas-provider). If appropriate, we should try
to stick to one of the generic names proposed in the spec. I wonder if the
canvas provider could be viewed as a "memory" or "memory-controller"
So, what about this ? Just a proposition, feel free to comment ;)
sysctrl_DMC: system-controller@0 {
compatib
le = "amlogic,gx-dmc-sysctrl", "syscon", "simple-mfd";> reg =
<0x0 0x0 0x0 0x1000>;
canvas: memory-controller {
compatible = "amlogic,canvas";
}
[...]
> + };
> + };
> + };
> +
> hiubus: bus@c883c000 {
> compatible = "simple-bus";
> reg = <0x0 0xc883c000 0x0 0x2000>;
Re: [PATCH 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
On Thu, 2018-08-09 at 16:22 +0800, Jianxin Pan wrote:
> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
> Timer, UART. It's capable of booting up into the serial console.
>
> Signed-off-by: Jianxin
Could please fix your signoff here ? Your last name went missing
> ---
> arch/arm64/boot/dts/amlogic/Makefile| 1 +
> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 174
>
> 3 files changed, 197 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>
> diff --git a/arch/arm64/boot/dts/amlogic/Makefile
> b/arch/arm64/boot/dts/amlogic/Makefile
> index a97c0e2..c31f29d6 100644
> --- a/arch/arm64/boot/dts/amlogic/Makefile
> +++ b/arch/arm64/boot/dts/amlogic/Makefile
> @@ -1,5 +1,6 @@
> # SPDX-License-Identifier: GPL-2.0
> dtb-$(CONFIG_ARCH_MESON) += meson-axg-s400.dtb
> +dtb-$(CONFIG_ARCH_MESON) += meson-g12a-u200.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nanopi-k2.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-nexbox-a95x.dtb
> dtb-$(CONFIG_ARCH_MESON) += meson-gxbb-odroidc2.dtb
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> new file mode 100644
> index 000..d267a37
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +/dts-v1/;
> +
> +#include "meson-g12a.dtsi"
> +
> +/ {
> + compatible = "amlogic,u200", "amlogic,g12a";
> + model = "Amlogic Meson G12A U200 Development Board";
> +
> + aliases {
> + serial0 = &uart_AO;
> + };
> +};
> +
> +&uart_AO {
> + status = "okay";
> +};
> +
> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> new file mode 100644
> index 000..64a0f2e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
> @@ -0,0 +1,174 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#include
> +#include
> +#include
> +
> +/ {
Could you please order the subnodes alphabetically ?
In general, we should try to order nodes by addresses when there is one and
alphabetically when there is none. This is something we have to fix for the AXG
as well.
> + compatible = "amlogic,g12a";
> +
> + interrupt-parent = <&gic>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + /* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
It's the only one (for now at least) so it's not really an alternate, isn't it ?
> + secmon_reserved: secmon@500 {
> + reg = <0x0 0x0500 0x0 0x30>;
> + no-map;
> + };
> + };
> +
> + cpus {
> + #address-cells = <0x2>;
> + #size-cells = <0x0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x1>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x2>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x3>;
> + enable-method = "psci";
> + next-level-cache = <&l2>;
> + };
> +
> + l2: l2-cache0 {
> + compatible = "cache";
> + };
> + };
> +
> + psci {
> + compatible = "arm,psci-1.0";
> + method = "smc";
> + };
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> + + (GIC_CPU_MASK_RAW(0xff) | IRQ_TY
Re: [PATCH v4 1/3] clk: meson: add emmc sub clock phase delay driver
On Thu, 2018-08-09 at 15:07 +0800, Yixun Lan wrote:
> Export the emmc sub clock phase delay ops which will be used
> by the emmc sub clock driver itself.
>
> Signed-off-by: Yixun Lan
> ---
> drivers/clk/meson/Makefile | 2 +-
> drivers/clk/meson/clk-phase-delay.c | 96 +
> drivers/clk/meson/clkc.h| 13
> 3 files changed, 110 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/meson/clk-phase-delay.c
>
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 72ec8c40d848..39ce5661b654 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -2,7 +2,7 @@
> # Makefile for Meson specific clk
> #
>
> -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
> +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-phase.o
> clk-phase-delay.o
> obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o sclk-div.o
> obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
> obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> diff --git a/drivers/clk/meson/clk-phase-delay.c
> b/drivers/clk/meson/clk-phase-delay.c
> new file mode 100644
> index ..6f226814cfec
> --- /dev/null
> +++ b/drivers/clk/meson/clk-phase-delay.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Amlogic Meson MMC Sub Clock Controller Driver
> + *
> + * Copyright (c) 2017 Baylibre SAS.
> + * Author: Jerome Brunet
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yixun Lan
> + */
> +
> +#include
> +#include "clkc.h"
> +
> +#define SD_EMMC_CLOCK0
Drop this and use struct parm please.
> +
> +static int meson_clk_phase_delay_get_phase(struct clk_hw *hw)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_clk_phase_delay_data *ph =
> + meson_clk_get_phase_delay_data(clk);
> + unsigned int phase_num = 1 << hweight_long(ph->phase_mask);
> + unsigned long period_ps, p, d;
> + int degrees;
> + u32 val;
> +
> + regmap_read(clk->map, SD_EMMC_CLOCK, &val);
> + p = (val & ph->phase_mask) >> __ffs(ph->phase_mask);
> + degrees = p * 360 / phase_num;
> +
> + if (ph->delay_mask) {
> + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
> + clk_hw_get_rate(hw));
> + d = (val & ph->delay_mask) >> __ffs(ph->delay_mask);
> + degrees += d * ph->delay_step_ps * 360 / period_ps;
> + degrees %= 360;
> + }
> +
> + return degrees;
> +}
> +
> +static void meson_clk_apply_phase_delay(struct clk_regmap *clk,
> + unsigned int phase,
> + unsigned int delay)
> +{
> + struct meson_clk_phase_delay_data *ph = clk->data;
> + u32 val;
> +
> + regmap_read(clk->map, SD_EMMC_CLOCK, &val);
> +
> + val &= ~ph->phase_mask;
> + val |= phase << __ffs(ph->phase_mask);
> +
> + if (ph->delay_mask) {
This imply that delay is delay is optional. In such case, it would be a regular
"phase" and we already have a driver for this. Please remove all the related
code and make this parameter required for this clock type.
In the future, maybe we'll merge the 2 drivers.
> + val &= ~ph->delay_mask;
> + val |= delay << __ffs(ph->delay_mask);
> + }
> +
> + regmap_write(clk->map, SD_EMMC_CLOCK, val);
> +}
> +
> +static int meson_clk_phase_delay_set_phase(struct clk_hw *hw, int degrees)
> +{
> + struct clk_regmap *clk = to_clk_regmap(hw);
> + struct meson_clk_phase_delay_data *ph =
> + meson_clk_get_phase_delay_data(clk);
> + unsigned int phase_num = 1 << hweight_long(ph->phase_mask);
> + unsigned long period_ps, d = 0, r;
> + u64 p;
> +
> + p = degrees % 360;
> +
> + if (!ph->delay_mask) {
> + p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
> + } else {
> + period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
> + clk_hw_get_rate(hw));
> +
> + /* First compute the phase index (p), the remainder (r) is the
> + * part we'll try to acheive using the delays (d).
> + */
> + r = do_div(p, 360 / phase_num);
> + d = DIV_ROUND_CLOSEST(r * period_ps,
> + 360 * ph->delay_step_ps);
> + d = min(d,
Re: [PATCH v4 3/3] clk: meson: add sub MMC clock controller driver
On Thu, 2018-08-09 at 15:07 +0800, Yixun Lan wrote:
> The patch will add a MMC clock controller driver which used by MMC or NAND,
> It provide a mux and divider clock, and three phase clocks - core, tx, tx.
>
> Two clocks are provided as the parent of MMC clock controller from
> upper layer clock controller - eg "amlogic,axg-clkc" in AXG platform.
>
> To specify which clock the MMC or NAND driver may consume,
> the preprocessor macros in the dt-bindings/clock/amlogic,mmc-clkc.h header
> can be used in the device tree sources.
>
> Signed-off-by: Yixun Lan
> ---
> drivers/clk/meson/Kconfig| 10 ++
> drivers/clk/meson/Makefile | 1 +
> drivers/clk/meson/mmc-clkc.c | 275 +++
> 3 files changed, 286 insertions(+)
> create mode 100644 drivers/clk/meson/mmc-clkc.c
>
> diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
> index efaa70f682b4..8b8ccbcfed1d 100644
> --- a/drivers/clk/meson/Kconfig
> +++ b/drivers/clk/meson/Kconfig
> @@ -15,6 +15,16 @@ config COMMON_CLK_MESON_AO
> select COMMON_CLK_REGMAP_MESON
> select RESET_CONTROLLER
>
> +config COMMON_CLK_MMC_MESON
> + tristate "Meson MMC Sub Clock Controller Driver"
> + depends on COMMON_CLK_AMLOGIC
> + select MFD_SYSCON
> + select REGMAP
> + help
> + Support for the MMC sub clock controller on Amlogic Meson Platform,
> + which include S905 (GXBB, GXL), A113D/X (AXG) devices.
> + Say Y if you want this clock enabled.
> +
> config COMMON_CLK_REGMAP_MESON
> bool
> select REGMAP
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 39ce5661b654..31c16d524a4b 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -9,4 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
> obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> +obj-$(CONFIG_COMMON_CLK_MMC_MESON) += mmc-clkc.o
> obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)+= clk-regmap.o
> diff --git a/drivers/clk/meson/mmc-clkc.c b/drivers/clk/meson/mmc-clkc.c
> new file mode 100644
> index ..6aa055f7e62c
> --- /dev/null
> +++ b/drivers/clk/meson/mmc-clkc.c
> @@ -0,0 +1,275 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + * Amlogic Meson MMC Sub Clock Controller Driver
> + *
> + * Copyright (c) 2017 Baylibre SAS.
> + * Author: Jerome Brunet
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yixun Lan
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "clkc.h"
> +
> +/* clock ID used by internal driver */
> +#define CLKID_MMC_MUX0
> +
> +#define SD_EMMC_CLOCK0
> +#define CLK_DIV_MASK GENMASK(5, 0)
> +#define CLK_SRC_MASK GENMASK(7, 6)
> +#define CLK_CORE_PHASE_MASKGENMASK(9, 8)
> +#define CLK_TX_PHASE_MASK GENMASK(11, 10)
> +#define CLK_RX_PHASE_MASK GENMASK(13, 12)
> +#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
> +#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
> +#define CLK_V2_ALWAYS_ON BIT(24)
> +
> +#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
> +#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
> +#define CLK_V3_ALWAYS_ON BIT(28)
> +
> +#define CLK_DELAY_STEP_PS 200
> +#define CLK_PHASE_STEP 30
> +#define CLK_PHASE_POINT_NUM(360 / CLK_PHASE_STEP)
> +
> +#define MUX_CLK_NUM_PARENTS 2
> +#define MMC_MAX_CLKS 5
> +
> +struct mmc_clkc_data {
> + struct meson_clk_phase_delay_data tx;
> + struct meson_clk_phase_delay_data rx;
> +};
> +
> +static struct clk_regmap_mux_data mmc_clkc_mux_data = {
> + .offset = SD_EMMC_CLOCK,
> + .mask = 0x3,
> + .shift = 6,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST,
> +};
> +
> +static struct clk_regmap_div_data mmc_clkc_div_data = {
> + .offset = SD_EMMC_CLOCK,
> + .shift = 0,
> + .width = 6,
> + .flags = CLK_DIVIDER_ROUND_CLOSEST | CLK_DIVIDER_ONE_BASED,
> +};
> +
> +static struct meson_clk_phase_delay_data mmc_clkc_core_phase_delay = {
> + .phase_mask = CLK_CORE_PHASE_MASK,
> +};
> +
> +static const struct mmc_clkc_data mmc_clkc_gx_data = {
> +
Re: [PATCH v2 2/2] arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support
On Mon, 2018-08-13 at 19:48 +0800, Jianxin Pan wrote:
> Try to add basic DT support for the Amlogic's Meson-G12A S905D2 SoC,
> which describe components as follows: Reserve Memory, CPU, GIC, IRQ,
> Timer, UART. It's capable of booting up into the serial console.
>
> Signed-off-by: Jianxin Pan
> ---
> arch/arm64/boot/dts/amlogic/Makefile| 1 +
> arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++
> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 172
>
> 3 files changed, 195 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts
> create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
>
> +
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> + + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> + + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
> + + (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
> + };
t* should be after s*
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
Re: [PATCH 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On Tue, 2018-08-14 at 02:18 -0400, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
> controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 57
> ++
> 1 file changed, 57 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> new file mode 100644
> index 000..48233e4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> @@ -0,0 +1,57 @@
> +Amlogic Meson AXG DWC PCIE SoC controller
> +
> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
> core.
> +It shares common functions with the PCIe DesignWare core driver and
> +inherits common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties:
> +- compatible:
> + should contain "amlogic,axg-pcie" to identify the core.
> +- reg:
> + Should contain the configuration address space.
> +- reg-names: Must be
> + - "elbi"External local bus interface registers
> + - "cfg" Meson specific registers
> + - "config" PCIe configuration space
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Must include the following entries:
> + - "pcie"
> + - "pcie_bus"
> + - "pcie_general"
> + - "pcie_mipi_en"
Could you briefly describe what each clock is needed for ?
> +
> +Example configuration:
> +
> + pcie: pcie@d000 {
> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
> + reg = <0x0 0xf980 0x0 0x40
> + 0x0 0xff646000 0x0 0x2000
> + 0x0 0xf9f0 0x0 0x10>;
> + reg-names = "elbi", "cfg", "config";
> + reset-gpio = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
> + interrupts = <0 177 IRQ_TYPE_EDGE_RISING>;
replace 0 with GIC_SPI please
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 179
> IRQ_TYPE_EDGE_RISING>;
> + bus-range = <0x0 0xff>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
> + phys = <&pcie_phy>;
> + ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
> + num-lanes = <1>;
> + pcie-num = <1>;
> +
> + clocks = <&clkc CLKID_USB
> + &clkc CLKID_MIPI_ENABLE
> + &clkc CLKID_PCIE_A
> + &clkc CLKID_PCIE_CML_EN0>;
> + clock-names = "pcie_general",
> + "pcie_refpll",
> + "pcie_mipi_en",
> + "pcie",
> + "port";
Several things are disturbing above:
* pcie_general is provided by the USB clock gate ???
* pcie_refpll: I suppose this is a copy/paste error, not used in your driver
(and shouldn't be need BTW)
suggested names:
* pcie_general -> general
* pcie_mipi_en -> mipi
* pcie -> pclk
* port (OK)
> + };
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On Tue, 2018-08-14 at 02:18 -0400, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
> drivers/pci/controller/dwc/Kconfig | 12 +
> drivers/pci/controller/dwc/Makefile| 1 +
> drivers/pci/controller/dwc/pci-meson.c | 588
> +
> 3 files changed, 601 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pci-meson.c
>
> diff --git a/drivers/pci/controller/dwc/Kconfig
> b/drivers/pci/controller/dwc/Kconfig
> index 91b0194..6cb36f6 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -193,4 +193,16 @@ config PCIE_HISI_STB
> help
>Say Y here if you want PCIe controller support on HiSilicon STB
> SoCs
>
> +config PCI_MESON
> + bool "MESON PCIe controller"
> + depends on PCI
> + depends on PCI_MSI_IRQ_DOMAIN
> + select PCIEPORTBUS
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want to enable PCI controller support on Amlogic
> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware
> + and therefore the driver re-uses the DesignWare core functions to
> + implement the driver.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile
> b/drivers/pci/controller/dwc/Makefile
> index 5d2ce72..cf676bd 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
> +obj-$(CONFIG_PCI_MESON) += pci-meson.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pci-meson.c
> b/drivers/pci/controller/dwc/pci-meson.c
> new file mode 100644
> index 000..1e96e45
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -0,0 +1,588 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Amlogic MESON SoCs
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yue Wang
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pcie-designware.h"
> +
> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
> +
> +/* External local bus interface registers */
> +#define PLR_OFFSET 0x700
> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
> +#define FAST_LINK_MODE BIT(7)
> +#define LINK_CAPABLE_MASKGENMASK(21, 16)
> +#define LINK_CAPABLE_X1 BIT(16)
> +
> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
> +#define NUM_OF_LANES_MASKGENMASK(12, 8)
> +#define NUM_OF_LANES_X1 BIT(8)
> +#define DIRECT_SPEED_CHANGE BIT(17)
> +
> +#define TYPE1_HDR_OFFSET 0x0
> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
> +#define PCI_IO_ENBIT(0)
> +#define PCI_MEM_SPACE_EN BIT(1)
> +#define PCI_BUS_MASTER_ENBIT(2)
> +
> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
> +
> +#define PCIE_CAP_OFFSET 0x70
> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
> +#define PCIE_CAP_MAX_PAYLOAD_MASKGENMASK(7, 5)
> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x)((x) << 12)
> +
> +#define PCI_CLASS_REVISION_MASK GENMASK(7, 0)
> +
> +/* PCIe specific config registers */
> +#define PCIE_CFG00x0
> +#define APP_LTSSM_ENABLE BIT(7)
> +
> +#define PCIE_CFG_STATUS120x30
> +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6) ? 1 : 0)
> +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16) ? 1 : 0)
> +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11 ?
> 1 : 0)
those ternary ops are overkill
> +
> +#define PCIE_CFG_STATUS170x44
> +#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
> +
> +#define WAIT_LINKUP_TIMEOUT 2000
> +#define PORT_CLK_RATE1UL
> +#define MAX_PAYLOAD_SIZE 256
> +#define MAX_READ_REQ_SIZE256
> +
> +enum pcie_data_rate {
> + PCIE_GEN1,
> + PCIE_GEN2,
> + PCIE_GEN3,
> + PCIE_GEN4
> +};
> +
> +struct meson_pcie_mem_res {
> + void __iomem *elbi_base; /* DT 0th resource */
> + void __iomem *cfg_base; /* DT 2nd resource */
>
Re: [PATCH 2/2] PCI: meson: add the Amlogic Meson PCIe phy driver
On Tue, 2018-08-14 at 02:12 -0400, Hanjie Lin wrote:
> From: Yue Wang
>
> The Meson-PCIE-PHY controller supports the 5-Gbps data rate
> of the PCI Express Gen 2 specification and is backwardcompatible
> with the 2.5-Gbps Gen 1.1 specification with only
> inferred idle detection supported on AMLOGIC SoCs.
It looks like the sole purpose of this driver is to provide the reset lines to
pcie driver.
I wonder why we need this ? Can't the pcie driver claim the reset lines itself.
Also, an init of this phy will always reset both port. What will happen if the
first port is in use and the 2nd port comes up ??
Looks the the pcie driver should claim 'apb' and 'phy' reset lines as "shared"
reset and the required 'port' as 'exclusive'
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
> drivers/phy/amlogic/Kconfig | 8 ++
> drivers/phy/amlogic/Makefile | 1 +
> drivers/phy/amlogic/phy-meson-axg-pcie.c | 160
> +++
> 3 files changed, 169 insertions(+)
> create mode 100644 drivers/phy/amlogic/phy-meson-axg-pcie.c
>
> diff --git a/drivers/phy/amlogic/Kconfig b/drivers/phy/amlogic/Kconfig
> index 23fe1cd..3ab07f9 100644
> --- a/drivers/phy/amlogic/Kconfig
> +++ b/drivers/phy/amlogic/Kconfig
> @@ -36,3 +36,11 @@ config PHY_MESON_GXL_USB3
> Enable this to support the Meson USB3 PHY and OTG detection
> IP block found in Meson GXL and GXM SoCs.
> If unsure, say N.
> +
> +config PHY_MESON_AXG_PCIE
> + bool "Meson AXG PCIe PHY driver"
> + depends on OF && (ARCH_MESON || COMPILE_TEST)
> + select GENERIC_PHY
> + help
> + Enable PCIe PHY support for Meson AXG SoC series.
> + This driver provides PHY interface for Meson PCIe controller.
> \ No newline at end of file
> diff --git a/drivers/phy/amlogic/Makefile b/drivers/phy/amlogic/Makefile
> index 4fd8848..5ab8578 100644
> --- a/drivers/phy/amlogic/Makefile
> +++ b/drivers/phy/amlogic/Makefile
> @@ -1,3 +1,4 @@
> obj-$(CONFIG_PHY_MESON8B_USB2) += phy-meson8b-usb2.o
> obj-$(CONFIG_PHY_MESON_GXL_USB2) += phy-meson-gxl-usb2.o
> obj-$(CONFIG_PHY_MESON_GXL_USB3) += phy-meson-gxl-usb3.o
> +obj-$(CONFIG_PHY_MESON_AXG_PCIE) += phy-meson-axg-pcie.o
> diff --git a/drivers/phy/amlogic/phy-meson-axg-pcie.c
> b/drivers/phy/amlogic/phy-meson-axg-pcie.c
> new file mode 100644
> index 000..8bc5c49
> --- /dev/null
> +++ b/drivers/phy/amlogic/phy-meson-axg-pcie.c
> @@ -0,0 +1,160 @@
> +// SPDX-License-Identifier: (GPL-2.0+ or MIT)
> +/*
> + * Amlogic MESON SoC series PCIe PHY driver
> + *
> + * Phy provider for PCIe controller on MESON SoC series
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Yue Wang
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +struct meson_pcie_phy_data {
> + const struct phy_ops*ops;
> +};
> +
> +struct meson_pcie_reset {
> + struct reset_control*port_a;
> + struct reset_control*port_b;
> + struct reset_control*phy;
> + struct reset_control*apb;
> +};
> +
> +struct meson_pcie_phy {
> + const struct meson_pcie_phy_data*data;
> + struct meson_pcie_reset reset;
> + void __iomem*phy_base;
> +};
> +
> +static int meson_pcie_phy_init(struct phy *phy)
> +{
> + struct meson_pcie_phy *mphy = phy_get_drvdata(phy);
> + struct meson_pcie_reset *mrst = &mphy->reset;
> +
> + writel(0x1c, mphy->phy_base);
> + reset_control_assert(mrst->port_a);
> + reset_control_assert(mrst->port_b);
> + reset_control_assert(mrst->phy);
> + reset_control_assert(mrst->apb);
> + udelay(400);
> + reset_control_deassert(mrst->port_a);
> + reset_control_deassert(mrst->port_b);
> + reset_control_deassert(mrst->phy);
> + reset_control_deassert(mrst->apb);
> + udelay(500);
> +
> + return 0;
> +}
> +
> +static const struct phy_ops meson_phy_ops = {
> + .init = meson_pcie_phy_init,
> + .owner = THIS_MODULE,
> +};
> +
> +static const struct meson_pcie_phy_data meson_pcie_phy_data = {
> + .ops= &meson_phy_ops,
> +};
> +
> +static const struct of_device_id meson_pcie_phy_match[] = {
> + {
> + .compatible = "amlogic,axg-pcie-phy",
> + .data = &meson_pcie_phy_data,
> + },
> + {},
> +};
> +
> +static int meson_pcie_phy_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct meson_pcie_phy *mphy;
> + struct meson_pcie_reset *mrst;
> + struct phy *generic_phy;
> + struct phy_provider *phy_provider;
> + struct resource *res;
> + const struct meson_pcie_phy_data *data;
> +
> + data = of_device_get_match_data(dev);
> + if (!data)
> + return -ENODEV;
> +
> + mphy = devm_kzalloc(dev, sizeof(*mphy), GFP_KERNEL);
> + if (!mphy)
> + return -ENOMEM;
> + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>
Re: [PATCH v3 0/2] arm64: dts: meson-g12a: Introduce new DT files for Meson-G12A SoC
On Tue, 2018-08-14 at 18:38 +0800, Jianxin Pan wrote: > This attempt will try to add new DT files to support Meson-G12A SoC. > > 1) first, Please notice that, in this patch series, the DT node about 16M > reserved > memory for hwrom is removed, since it's not needed by G12A SoC. > 2) second, the pclk for uart_AO need to be fixed once G12A clock_ao driver is > merged. In this version, it rely on bootloader to enable the pclk gate which > belong to AO clock domain. Please add clk_ignore_unused to bootargs. > > Changes since v2 [1]: > - reorder subnodes > - collect Rob's Reviewed-by > > Changes since v1 [0]: > - fix signoff typo > - order subnodes by addresses when there is one and alphabetically when > there is none > > [0] > https://lore.kernel.org/lkml/1533802951-49919-2-git-send-email-jianxin@amlogic.com/ > > Jianxin Pan (2): > dt-bindings: arm: amlogic: Add Meson G12A binding > arm64: dts: meson-g12a: add initial g12a s905d2 SoC DT support > > Documentation/devicetree/bindings/arm/amlogic.txt | 6 + > arch/arm64/boot/dts/amlogic/Makefile | 1 + > arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts | 22 +++ > arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 172 > ++ > 4 files changed, 201 insertions(+) > create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a-u200.dts > create mode 100644 arch/arm64/boot/dts/amlogic/meson-g12a.dtsi > Series looks good as far as I can tell Reviewed-by: Jerome Brunet
Re: [PATCH 2/2] clk: meson-g12a: Add AO Clock controller driver
On Fri, 2018-08-10 at 17:54 +0800, Jian Hu wrote:
> Add a Clock driver for the ALways-On part
> of the Amlogic Meson-G12A SoC.
>
> Signed-off-by: Jian Hu
> ---
> drivers/clk/meson/Makefile | 2 +-
> drivers/clk/meson/g12a-aoclk.c | 170
> +
> drivers/clk/meson/g12a-aoclk.h | 36 +
> 3 files changed, 207 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/meson/g12a-aoclk.c
> create mode 100644 drivers/clk/meson/g12a-aoclk.h
>
> diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
> index 2b1a562..d5c2dcd 100644
> --- a/drivers/clk/meson/Makefile
> +++ b/drivers/clk/meson/Makefile
> @@ -9,5 +9,5 @@ obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
> obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
> obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
> obj-$(CONFIG_COMMON_CLK_AXG_AUDIO) += axg-audio.o
> -obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o
> +obj-$(CONFIG_COMMON_CLK_G12A) += g12a.o g12a-aoclk.c
> obj-$(CONFIG_COMMON_CLK_REGMAP_MESON)+= clk-regmap.o
> diff --git a/drivers/clk/meson/g12a-aoclk.c b/drivers/clk/meson/g12a-aoclk.c
> new file mode 100644
> index 000..a5cd95c
> --- /dev/null
> +++ b/drivers/clk/meson/g12a-aoclk.c
> @@ -0,0 +1,170 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Amlogic Meson-G12A Clock Controller Driver
> + *
> + * Copyright (c) 2016 Baylibre SAS.
> + * Author: Michael Turquette
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Jian Hu
> + */
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include "clkc.h"
> +#include "g12a-aoclk.h"
> +
> +#define G12A_AO_GATE0(_name, _bit) \
> +static struct clk_regmap _name##_ao = {
> \
> + .data = &(struct clk_regmap_gate_data) {\
> + .offset = (AO_CLK_GATE0), \
> + .bit_idx = (_bit), \
> + }, \
> + .hw.init = &(struct clk_init_data) {\
> + .name = #_name "_ao", \
> + .ops = &clk_regmap_gate_ops,\
> + .parent_names = (const char *[]){ "clk81" },\
> + .num_parents = 1, \
> + }, \
> +}
> +
> +G12A_AO_GATE0(ahb_bus, 0);
> +G12A_AO_GATE0(remote,1);
> +G12A_AO_GATE0(i2c_master,2);
> +G12A_AO_GATE0(i2c_slave, 3);
> +G12A_AO_GATE0(uart1, 4);
> +G12A_AO_GATE0(prod_i2c, 5);
> +G12A_AO_GATE0(uart2, 6);
> +G12A_AO_GATE0(ir_blaster,7);
> +G12A_AO_GATE0(saradc,8);
> +
> +static struct clk_regmap ao_clk81 = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_RTI_PWR_CNTL_REG0,
> + .mask = 0x1,
> + .shift = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "ao_clk81",
> + .ops = &clk_regmap_mux_ro_ops,
> + .parent_names = (const char *[]){ "clk81", "ao_alt_xtal"},
I think it is time we stop taking clock input from nowhere.
With the addition of the axg audio clock controller, there is now an example of
how do so.
This clock controller apparently has 3 inputs:
* xtal
* ao_xtal
* clk_81
I'd like to see that appear this DT bindings and the probe function
Same goes for the EE controller which should only take the xtal.
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap g12a_saradc_mux = {
> + .data = &(struct clk_regmap_mux_data) {
> + .offset = AO_SAR_CLK,
> + .mask = 0x3,
> + .shift = 9,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "g12a_saradc_mux",
> + .ops = &clk_regmap_mux_ops,
> + .parent_names = (const char *[]){ "xtal", "ao_clk81" },
> + .num_parents = 2,
> + },
> +};
> +
> +static struct clk_regmap g12a_saradc_div = {
> + .data = &(struct clk_regmap_div_data) {
> + .offset = AO_SAR_CLK,
> + .shift = 0,
> + .width = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "g12a_saradc_div",
> + .ops = &clk_regmap_divider_ops,
> + .parent_names = (const char *[]){ "g12a_saradc_mux" },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + },
> +};
> +
> +static struct clk_regmap g12a_saradc_gate = {
> + .data = &(struct clk_regmap_gate_data) {
> + .offset = AO_SAR_CLK,
> + .bit_idx = 8,
> + },
> + .hw.init = &(struct clk_init_data){
> + .name = "g12a_saradc_gate",
> +
Re: [PATCH v2 2/2] PCI: meson: add the Amlogic Meson PCIe controller driver
On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds the driver support for Meson PCIe controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
> drivers/pci/controller/dwc/Kconfig | 12 +
> drivers/pci/controller/dwc/Makefile| 1 +
> drivers/pci/controller/dwc/pci-meson.c | 613
> +
> 3 files changed, 626 insertions(+)
> create mode 100644 drivers/pci/controller/dwc/pci-meson.c
>
> diff --git a/drivers/pci/controller/dwc/Kconfig
> b/drivers/pci/controller/dwc/Kconfig
> index 91b0194..6cb36f6 100644
> --- a/drivers/pci/controller/dwc/Kconfig
> +++ b/drivers/pci/controller/dwc/Kconfig
> @@ -193,4 +193,16 @@ config PCIE_HISI_STB
> help
>Say Y here if you want PCIe controller support on HiSilicon STB
> SoCs
>
> +config PCI_MESON
> + bool "MESON PCIe controller"
> + depends on PCI
> + depends on PCI_MSI_IRQ_DOMAIN
> + select PCIEPORTBUS
> + select PCIE_DW_HOST
> + help
> + Say Y here if you want to enable PCI controller support on Amlogic
> + SoCs. The PCI controller on Amlogic is based on DesignWare hardware
> + and therefore the driver re-uses the DesignWare core functions to
> + implement the driver.
> +
> endmenu
> diff --git a/drivers/pci/controller/dwc/Makefile
> b/drivers/pci/controller/dwc/Makefile
> index 5d2ce72..cf676bd 100644
> --- a/drivers/pci/controller/dwc/Makefile
> +++ b/drivers/pci/controller/dwc/Makefile
> @@ -14,6 +14,7 @@ obj-$(CONFIG_PCIE_ARMADA_8K) += pcie-armada8k.o
> obj-$(CONFIG_PCIE_ARTPEC6) += pcie-artpec6.o
> obj-$(CONFIG_PCIE_KIRIN) += pcie-kirin.o
> obj-$(CONFIG_PCIE_HISI_STB) += pcie-histb.o
> +obj-$(CONFIG_PCI_MESON) += pci-meson.o
>
> # The following drivers are for devices that use the generic ACPI
> # pci_root.c driver but don't support standard ECAM config access.
> diff --git a/drivers/pci/controller/dwc/pci-meson.c
> b/drivers/pci/controller/dwc/pci-meson.c
> new file mode 100644
> index 000..a9edf20
> --- /dev/null
> +++ b/drivers/pci/controller/dwc/pci-meson.c
> @@ -0,0 +1,613 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * PCIe host controller driver for Amlogic MESON SoCs
> + *
> + * Copyright (c) 2018 Amlogic, inc.
> + * Author: Yue Wang
> + */
> +
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +#include
> +
> +#include "pcie-designware.h"
> +
> +#define to_meson_pcie(x) dev_get_drvdata((x)->dev)
> +
> +/* External local bus interface registers */
> +#define PLR_OFFSET 0x700
> +#define PCIE_PORT_LINK_CTRL_OFF (PLR_OFFSET + 0x10)
> +#define FAST_LINK_MODE BIT(7)
> +#define LINK_CAPABLE_MASKGENMASK(21, 16)
> +#define LINK_CAPABLE_X1 BIT(16)
> +
> +#define PCIE_GEN2_CTRL_OFF (PLR_OFFSET + 0x10c)
> +#define NUM_OF_LANES_MASKGENMASK(12, 8)
> +#define NUM_OF_LANES_X1 BIT(8)
> +#define DIRECT_SPEED_CHANGE BIT(17)
> +
> +#define TYPE1_HDR_OFFSET 0x0
> +#define PCIE_STATUS_COMMAND (TYPE1_HDR_OFFSET + 0x04)
> +#define PCI_IO_ENBIT(0)
> +#define PCI_MEM_SPACE_EN BIT(1)
> +#define PCI_BUS_MASTER_ENBIT(2)
> +
> +#define PCIE_BASE_ADDR0 (TYPE1_HDR_OFFSET + 0x10)
> +#define PCIE_BASE_ADDR1 (TYPE1_HDR_OFFSET + 0x14)
> +
> +#define PCIE_CAP_OFFSET 0x70
> +#define PCIE_DEV_CTRL_DEV_STUS (PCIE_CAP_OFFSET + 0x08)
> +#define PCIE_CAP_MAX_PAYLOAD_MASKGENMASK(7, 5)
> +#define PCIE_CAP_MAX_PAYLOAD_SIZE(x) ((x) << 5)
> +#define PCIE_CAP_MAX_READ_REQ_MASK GENMASK(14, 12)
> +#define PCIE_CAP_MAX_READ_REQ_SIZE(x)((x) << 12)
> +
> +#define PCI_CLASS_REVISION_MASK GENMASK(7, 0)
> +
> +/* PCIe specific config registers */
> +#define PCIE_CFG00x0
> +#define APP_LTSSM_ENABLE BIT(7)
> +
> +#define PCIE_CFG_STATUS120x30
> +#define IS_SMLH_LINK_UP(x) ((x) & (1 << 6))
> +#define IS_RDLH_LINK_UP(x) ((x) & (1 << 16))
> +#define IS_LTSSM_UP(x) x) >> 10) & 0x1f) == 0x11)
> +
> +#define PCIE_CFG_STATUS170x44
> +#define PM_CURRENT_STATE(x) (((x) >> 7) & 0x1)
> +
> +#define WAIT_LINKUP_TIMEOUT 2000
> +#define PORT_CLK_RATE1UL
> +#define MAX_PAYLOAD_SIZE 256
> +#define MAX_READ_REQ_SIZE256
> +
> +enum pcie_data_rate {
> + PCIE_GEN1,
> + PCIE_GEN2,
> + PCIE_GEN3,
> + PCIE_GEN4
> +};
> +
> +struct meson_pcie_mem_res {
> + void __iomem *elbi_base; /* DT 0th resource */
> + void __iomem *cfg_base; /* DT 2nd resource */
> +};
> +
> +struct meson_pcie_clk_res {
> +
Re: [PATCH v2 1/2] dt-bindings: PCI: meson: add DT bindings for Amlogic Meson PCIe controller
On Fri, 2018-08-24 at 15:36 +0800, Hanjie Lin wrote:
> From: Yue Wang
>
> The Amlogic Meson PCIe host controller is based on the Synopsys DesignWare
> PCI core. This patch adds documentation for the DT bindings in Meson PCIe
> controller.
>
> Signed-off-by: Yue Wang
> Signed-off-by: Hanjie Lin
> ---
> .../devicetree/bindings/pci/amlogic,meson-pcie.txt | 63
> ++
> 1 file changed, 63 insertions(+)
> create mode 100644
> Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
>
> diff --git a/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> new file mode 100644
> index 000..8a831d1
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/amlogic,meson-pcie.txt
> @@ -0,0 +1,63 @@
> +Amlogic Meson AXG DWC PCIE SoC controller
> +
> +Amlogic Meson PCIe host controller is based on the Synopsys DesignWare PCI
> core.
> +It shares common functions with the PCIe DesignWare core driver and
> +inherits common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt.
> +
> +Additional properties are described here:
> +
> +Required properties:
> +- compatible:
> + should contain "amlogic,axg-pcie" to identify the core.
> +- reg:
> + Should contain the configuration address space.
> +- reg-names: Must be
> + - "elbi"External local bus interface registers
> + - "cfg" Meson specific registers
> + - "config" PCIe configuration space
> +- reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
> +- clocks: Must contain an entry for each entry in clock-names.
> +- clock-names: Must include the following entries:
> + - "pclk" PCIe GEN 100M PLL clock
> + - "port" PCIe_x(A or B) RC clock gate
> + - "general"PCIe Phy clock
> + - "mipi" PCIe_x(A or B) 100M ref clock gate
> +- resets: phandle to the reset lines.
> +- reset-names: must contain "phy" and "peripheral"
> + - "port" Port A or B reset
> + - "apb" APB reset
The above description is not coherent (phy <=> port)
> +
> +Example configuration:
> +
> + pcie: pcie@f980 {
> + compatible = "amlogic,axg-pcie", "snps,dw-pcie";
> + reg = <0x0 0xf980 0x0 0x40
> + 0x0 0xff646000 0x0 0x2000
> + 0x0 0xf9f0 0x0 0x10>;
> + reg-names = "elbi", "cfg", "config";
> + reset-gpios = <&gpio GPIOX_19 GPIO_ACTIVE_HIGH>;
> + interrupts = ;
> + #interrupt-cells = <1>;
> + interrupt-map-mask = <0 0 0 0>;
> + interrupt-map = <0 0 0 0 &gic GIC_SPI 179
> IRQ_TYPE_EDGE_RISING>;
> + bus-range = <0x0 0xff>;
> + #address-cells = <3>;
> + #size-cells = <2>;
> + device_type = "pci";
Not described above - is it even used ?
> + phys = <&pcie_phy>;
Not documented and not necessary. Please remove this.
> + ranges = <0x8200 0 0 0x0 0xf9c0 0 0x0030>;
> +
> + clocks = <&clkc CLKID_USB
> + &clkc CLKID_MIPI_ENABLE
> + &clkc CLKID_PCIE_A
> + &clkc CLKID_PCIE_CML_EN0>;
> + clock-names = "general",
> + "mipi",
> + "pclk",
> + "port";
> + resets = <&reset RESET_PCIE_A>,
> + <&reset RESET_PCIE_APB>;
> + reset-names = "port",
> + "apb";
> + };
[PATCH 3/3] ASoC: meson: align axg card driver with DT bindings documentation
Drop amlogic prefix in front of the generic DT properties and change
property "name" to "model".
Signed-off-by: Jerome Brunet
---
sound/soc/meson/axg-card.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/sound/soc/meson/axg-card.c b/sound/soc/meson/axg-card.c
index d6d1081d94ad..2914ba0d965b 100644
--- a/sound/soc/meson/axg-card.c
+++ b/sound/soc/meson/axg-card.c
@@ -123,7 +123,7 @@ static int axg_card_add_aux_devices(struct snd_soc_card
*card)
struct snd_soc_aux_dev *aux;
int num, i;
- num = of_count_phandle_with_args(node, PREFIX "aux-devs", NULL);
+ num = of_count_phandle_with_args(node, "audio-aux-devs", NULL);
if (num == -ENOENT) {
/*
* It is ok to have no auxiliary devices but for this card it
@@ -144,8 +144,8 @@ static int axg_card_add_aux_devices(struct snd_soc_card
*card)
card->num_aux_devs = num;
for (i = 0; i < card->num_aux_devs; i++, aux++) {
- aux->codec_of_node = of_parse_phandle(node,
- PREFIX "aux-devs", i);
+ aux->codec_of_node =
+ of_parse_phandle(node, "audio-aux-devs", i);
if (!aux->codec_of_node)
return -EINVAL;
}
@@ -610,18 +610,18 @@ static int axg_card_probe(struct platform_device *pdev)
priv->card.owner = THIS_MODULE;
priv->card.dev = dev;
- ret = snd_soc_of_parse_card_name(&priv->card, PREFIX "name");
+ ret = snd_soc_of_parse_card_name(&priv->card, "model");
if (ret < 0)
return ret;
- ret = axg_card_parse_of_optional(&priv->card, PREFIX "routing",
+ ret = axg_card_parse_of_optional(&priv->card, "audio-routing",
snd_soc_of_parse_audio_routing);
if (ret) {
dev_err(dev, "error while parsing routing\n");
return ret;
}
- ret = axg_card_parse_of_optional(&priv->card, PREFIX "widgets",
+ ret = axg_card_parse_of_optional(&priv->card, "audio-widgets",
snd_soc_of_parse_audio_simple_widgets);
if (ret) {
dev_err(dev, "error while parsing widgets\n");
--
2.17.1
[PATCH 0/3] ASoC: meson-axg: fifo and card fixup
The purpose of this patchset is to solve the problems which have been raised since the initial axg sound support has been accepted. Jerome Brunet (3): ASoC: meson: use IRQ_RETVAL in the fifo irq handler ASoC: meson: update axg sound card bindings ASoC: meson: align axg card driver with DT bindings documentation .../bindings/sound/amlogic,axg-sound-card.txt | 68 +-- sound/soc/meson/axg-card.c| 12 ++-- sound/soc/meson/axg-fifo.c| 2 +- 3 files changed, 41 insertions(+), 41 deletions(-) -- 2.17.1
[PATCH 2/3] ASoC: meson: update axg sound card bindings
Remove the amlogic prefix in front of the generic properties and change
the card 'name' property to 'model'
Suggested-by: Rob Herring
Signed-off-by: Jerome Brunet
---
.../bindings/sound/amlogic,axg-sound-card.txt | 68 +--
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt
b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt
index 39e005da0407..80b411296480 100644
--- a/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt
+++ b/Documentation/devicetree/bindings/sound/amlogic,axg-sound-card.txt
@@ -3,19 +3,19 @@ Amlogic AXG sound card:
Required properties:
- compatible: "amlogic,axg-sound-card"
-- amlogic,name : User specified audio sound card name, one string
+- model : User specified audio sound card name, one string
Optional properties:
-- amlogic,aux-devs : List of phandles pointing to auxiliary devices
-- amlogic,widgets : Please refer to widgets.txt.
-- amlogic,routing : A list of the connections between audio components.
+- audio-aux-devs : List of phandles pointing to auxiliary devices
+- audio-widgets : Please refer to widgets.txt.
+- audio-routing : A list of the connections between audio components.
Subnodes:
-- amlogic,dai-link: Container for dai-link level properties and the
- CODEC sub-nodes. There should be at least one (and
- probably) subnode of this type.
+- dai-link: Container for dai-link level properties and the CODEC
+ sub-nodes. There should be at least one (and probably more)
+ subnode of this type.
Required dai-link properties:
@@ -57,38 +57,38 @@ Example:
sound {
compatible = "amlogic,axg-sound-card";
- amlogic,name = "AXG-S420";
- amlogic,aux-devs = <&tdmin_a>, <&tdmout_c>;
- amlogic,widgets = "Line", "Lineout",
- "Line", "Linein",
- "Speaker", "Speaker1 Left",
- "Speaker", "Speaker1 Right";
- "Speaker", "Speaker2 Left",
- "Speaker", "Speaker2 Right";
- amlogic,routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
- "SPDIFOUT IN 0", "FRDDR_A OUT 3",
- "TDM_C Playback", "TDMOUT_C OUT",
- "TDMIN_A IN 2", "TDM_C Capture",
- "TDMIN_A IN 5", "TDM_C Loopback",
- "TODDR_A IN 0", "TDMIN_A OUT",
- "Lineout", "Lineout AOUTL",
- "Lineout", "Lineout AOUTR",
- "Speaker1 Left", "SPK1 OUT_A",
- "Speaker2 Left", "SPK2 OUT_A",
- "Speaker1 Right", "SPK1 OUT_B",
- "Speaker2 Right", "SPK2 OUT_B",
- "Linein AINL", "Linein",
- "Linein AINR", "Linein";
-
- amlogic,dai-link@0 {
+ model = "AXG-S420";
+ audio-aux-devs = <&tdmin_a>, <&tdmout_c>;
+ audio-widgets = "Line", "Lineout",
+ "Line", "Linein",
+ "Speaker", "Speaker1 Left",
+ "Speaker", "Speaker1 Right";
+ "Speaker", "Speaker2 Left",
+ "Speaker", "Speaker2 Right";
+ audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "SPDIFOUT IN 0", "FRDDR_A OUT 3",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 2", "TDM_C Capture",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "Lineout", "Lineout AOUTL",
+ "Lineout", "Lineout AOUTR",
+ "Speaker1 Left", "SPK1 OUT_A",
+ "Speaker2 Left", "SPK2 OUT_A",
+ "Speaker1 Right", "SPK1 OUT_B",
+ "Speaker2 Right", "SPK2 OUT_B",
+ "Linein AINL", "Linein",
+ "Linein AINR", "Linein";
+
+ dai-link@0 {
sound-dai = <&frddr_a>;
};
- amlogic,dai-link@1 {
+ dai-link@1 {
sound-dai = <&toddr_a>;
};
- amlogic,dai-link@2 {
+ dai-link@2 {
sound-dai = <&tdmif_c>;
dai-format = "i2s";
dai-tdm-slot-tx-mask-2 = <1 1>;
@@ -114,7 +114,7 @@ sound {
};
- amlogic,dai-link@4 {
+ dai-link@3 {
sound-dai = <&spdifout>;
codec {
--
2.17.1
[PATCH 1/3] ASoC: meson: use IRQ_RETVAL in the fifo irq handler
Use IRQ_RETVAL instead of the open coded ternary operation. Suggested-by: Takashi Iwai Signed-off-by: Jerome Brunet --- sound/soc/meson/axg-fifo.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/meson/axg-fifo.c b/sound/soc/meson/axg-fifo.c index db367d85290f..30262550e37b 100644 --- a/sound/soc/meson/axg-fifo.c +++ b/sound/soc/meson/axg-fifo.c @@ -174,7 +174,7 @@ static irqreturn_t axg_fifo_pcm_irq_block(int irq, void *dev_id) /* Ack irqs */ axg_fifo_ack_irq(fifo, status); - return !status ? IRQ_NONE : IRQ_HANDLED; + return IRQ_RETVAL(status); } static int axg_fifo_pcm_open(struct snd_pcm_substream *ss) -- 2.17.1
Re: [PATCH v3 2/2] clk: meson: add sub MMC clock controller driver
On Fri, 2018-07-27 at 09:45 -0700, Stephen Boyd wrote: > Quoting Stephen Boyd (2018-07-27 09:41:40) > > Quoting Yixun Lan (2018-07-27 07:52:23) > > > HI Stephen: > > > > > > On 07/26/2018 11:20 PM, Stephen Boyd wrote: > > > > Quoting Yixun Lan (2018-07-12 14:12:44) > > > > > diff --git a/drivers/clk/meson/mmc-clkc.c > > > > > b/drivers/clk/meson/mmc-clkc.c > > > > > new file mode 100644 > > > > > index ..36c4c7cd69a6 > > > > > --- /dev/null > > > > > +++ b/drivers/clk/meson/mmc-clkc.c > > > > > @@ -0,0 +1,367 @@ > > > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > > > > > +/* > > > > > + * Amlogic Meson MMC Sub Clock Controller Driver > > > > > + * > > > > > + * Copyright (c) 2017 Baylibre SAS. > > > > > + * Author: Jerome Brunet > > > > > + * > > > > > + * Copyright (c) 2018 Amlogic, inc. > > > > > + * Author: Yixun Lan > > > > > + */ > > > > > + > > > > > +#include > > > > > > > > Is this include used? > > > > > > > > > > this is needed by clk_get_rate() > > > see drivers/clk/meson/mmc-clkc.c:204 > > > > Hmm ok. That's unfortunate. > > You should be able to read the hardware to figure out the clk frequency? > This may be a sign that the phase clk_ops are bad and should be passing > in the frequency of the parent clk to the op so that phase can be > calculated. Jerome? > It could be a away to do it but: a) if we modify the API, we would need to update every clock driver using it. There is not that many users of the phase API but still, it is annoying b) This particular driver need the parent rate, other might need something else I guess. (parent phase ??, duty cycle ??) I think the real problem here it that you are using the consumer API. You should be using the provider API like clk_hw_get_rate. Look at the clk-divider.c which use clk_hw_round_rate() on the parent clock. Clock drivers should deal with 'struct clk_hw', not 'struct clk'. I think it was mentioned in the past that the 'clk' within 'struct clk_hw' might be removed someday. Yixun, please don't put your clock driver within the controller driver. Please implement your 'phase-delay' clock in its own file and export the ops, like every other clock in the amlogic directory. Also, please review your list of '#define', some of them are unnecessary copy/paste from the MMC driver. Regards Jerome
Re: [alsa-devel] [PATCH RESEND 02/15] ASoC: meson: add axg fifo base driver
On Wed, 2018-07-18 at 17:39 +0200, Takashi Iwai wrote: > On Wed, 18 Jul 2018 13:50:54 +0200, > Mark Brown wrote: > > > > On Tue, Jul 17, 2018 at 05:42:51PM +0200, Jerome Brunet wrote: > > > > > + return !status ? IRQ_NONE : IRQ_HANDLED; > > > > Please just write normal conditional statements, it makes things a lot > > easier to read (the ! isn't helping either here). Indeed. I'll correct this in a follow up patch > > ... and there is the standard IRQ_RETVAL() macro for this purpose. I was not aware of it. Thanks for the tip Takashi > > > Takashi
Re: [PATCH 2/3] clk: meson: clk-pll: remove od parameters
On Thu, 2018-07-19 at 10:42 +0200, Neil Armstrong wrote:
> > +static struct clk_regmap gxl_hdmi_pll_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 16,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_dco" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
>
> In my code, the GXL OD1 is at bit 21
>
> > +
> > +static struct clk_regmap gxl_hdmi_pll_od2 = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 22,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od2",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_od" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
> > + },
> > +};
>
>
> In my code, the GXL OD3 is at bit 23
>
> > +
> > static struct clk_regmap gxl_hdmi_pll = {
> > - .data = &(struct meson_clk_pll_data){
> > - .en = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 30,
> > - .width = 1,
> > - },
> > - .m = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 0,
> > - .width = 9,
> > - },
> > - .n = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 9,
> > - .width = 5,
> > - },
> > - .frac = {
> > - /*
> > - * On gxl, there is a register shift due to
> > - * HHI_HDMI_PLL_CNTL1 which does not exist on gxbb,
> > - * so we compute the register offset based on the PLL
> > - * base to get it right
> > - */
> > - .reg_off = HHI_HDMI_PLL_CNTL + 4,
> > - .shift = 0,
> > - .width = 12,
> > - },
> > - .od = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 21,
> > - .width = 2,
> > - },
> > - .od2 = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 23,
> > - .width = 2,
> > - },
> > - .od3 = {
> > - .reg_off = HHI_HDMI_PLL_CNTL + 8,
> > - .shift = 19,
> > - .width = 2,
> > - },
> > - .l = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 31,
> > - .width = 1,
> > - },
> > - .rst = {
> > - .reg_off = HHI_HDMI_PLL_CNTL,
> > - .shift = 29,
> > - .width = 1,
> > - },
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL + 8,
> > + .shift = 18,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
>
>
> In my code, the GXL OD3 is at bit 19
>
> It's only a copy/paste error, the original code had the correct shifts.
Absolutely. Good catch.
Re: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables
On Thu, 2018-07-19 at 10:44 +0200, Neil Armstrong wrote: > We could even add ranges instead of table when we know the PLL supports a > well-known continuous dividers range. I was thinking about this too. I did not went for it because it would mean yet another rework of the pll driver, which I did not had time to do now. I suspect that the min and max value of 'm' the pll can lock on might depend on the input rate of the DCO, so past the 'n' prediv. So, to replace the tuple (m, n) table with ranges, I think it would be best to take the predivider 'n' out first and try to clarify the contraints on the input rate of the DCO with amlogic ... we can also try and see ;) > > Acked-by: Neil Armstrong
[PATCH v2 1/2] reset: meson: add dt-bindings for meson-axg audio arb
Add dt-bindings for the audio memory arbiter found on Amlogic's
A113 based SoCs
Reviewed-by: Rob Herring
Signed-off-by: Jerome Brunet
---
.../bindings/reset/amlogic,meson-axg-audio-arb.txt | 21 +
.../dt-bindings/reset/amlogic,meson-axg-audio-arb.h | 17 +
2 files changed, 38 insertions(+)
create mode 100644
Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
diff --git
a/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
new file mode 100644
index ..26e542eb96df
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt
@@ -0,0 +1,21 @@
+* Amlogic audio memory arbiter controller
+
+The Amlogic Audio ARB is a simple device which enables or
+disables the access of Audio FIFOs to DDR on AXG based SoC.
+
+Required properties:
+- compatible: 'amlogic,meson-axg-audio-arb'
+- reg: physical base address of the controller and length of memory
+ mapped region.
+- clocks: phandle to the fifo peripheral clock provided by the audio
+ clock controller.
+- #reset-cells: must be 1.
+
+Example on the A113 SoC:
+
+arb: reset-controller@280 {
+ compatible = "amlogic,meson-axg-audio-arb";
+ reg = <0x0 0x280 0x0 0x4>;
+ #reset-cells = <1>;
+ clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
+};
diff --git a/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
new file mode 100644
index ..05c36367875c
--- /dev/null
+++ b/include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0 OR MIT)
+ *
+ * Copyright (c) 2018 Baylibre SAS.
+ * Author: Jerome Brunet
+ */
+
+#ifndef _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+#define _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H
+
+#define AXG_ARB_TODDR_A0
+#define AXG_ARB_TODDR_B1
+#define AXG_ARB_TODDR_C2
+#define AXG_ARB_FRDDR_A3
+#define AXG_ARB_FRDDR_B4
+#define AXG_ARB_FRDDR_C5
+
+#endif /* _DT_BINDINGS_AMLOGIC_MESON_AXG_AUDIO_ARB_H */
--
2.14.4
[PATCH v2 0/2] reset: meson: add audio arb controller
This patchset adds the audio ARB controller which is necessary to enable or disable the DDR access for the FIFOs of the audio subsystem. Changes since v1 [0]: * Fix typo s/arbitror/arbiter * Collect Rob's tag [0]: https://lkml.kernel.org/r/20180706143122.7612-1-jbru...@baylibre.com Jerome Brunet (2): reset: meson: add dt-bindings for meson-axg audio arb reset: meson: add meson audio arb driver .../bindings/reset/amlogic,meson-axg-audio-arb.txt | 21 +++ drivers/reset/Kconfig | 7 + drivers/reset/Makefile | 1 + drivers/reset/reset-meson-audio-arb.c | 168 + .../reset/amlogic,meson-axg-audio-arb.h| 17 +++ 5 files changed, 214 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/amlogic,meson-axg-audio-arb.txt create mode 100644 drivers/reset/reset-meson-audio-arb.c create mode 100644 include/dt-bindings/reset/amlogic,meson-axg-audio-arb.h -- 2.14.4
[PATCH v2 2/2] reset: meson: add meson audio arb driver
The Amlogic Audio ARB is a simple device which enables or
disables the access of Audio FIFOs to DDR on AXG based SoC.
Signed-off-by: Jerome Brunet
---
drivers/reset/Kconfig | 7 ++
drivers/reset/Makefile| 1 +
drivers/reset/reset-meson-audio-arb.c | 168 ++
3 files changed, 176 insertions(+)
create mode 100644 drivers/reset/reset-meson-audio-arb.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index c0b292be1b72..782dc59b3855 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -73,6 +73,13 @@ config RESET_MESON
help
This enables the reset driver for Amlogic Meson SoCs.
+config RESET_MESON_AUDIO_ARB
+ tristate "Meson Audio Memory Arbiter Reset Driver"
+ depends on ARCH_MESON || COMPILE_TEST
+ help
+ This enables the reset driver for Audio Memory Arbiter of
+ Amlogic's A113 based SoCs
+
config RESET_OXNAS
bool
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index c1261dcfe9ad..aca2240b48aa 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
obj-$(CONFIG_RESET_MESON) += reset-meson.o
+obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
obj-$(CONFIG_RESET_SIMPLE) += reset-simple.o
diff --git a/drivers/reset/reset-meson-audio-arb.c
b/drivers/reset/reset-meson-audio-arb.c
new file mode 100644
index ..91751617b37a
--- /dev/null
+++ b/drivers/reset/reset-meson-audio-arb.c
@@ -0,0 +1,168 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+// Copyright (c) 2018 BayLibre, SAS.
+// Author: Jerome Brunet
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+struct meson_audio_arb_data {
+ struct reset_controller_dev rstc;
+ void __iomem *regs;
+ struct clk *clk;
+ const unsigned int *reset_bits;
+ spinlock_t lock;
+};
+
+#define ARB_GENERAL_BIT31
+
+static const unsigned int axg_audio_arb_reset_bits[] = {
+ [AXG_ARB_TODDR_A] = 0,
+ [AXG_ARB_TODDR_B] = 1,
+ [AXG_ARB_TODDR_C] = 2,
+ [AXG_ARB_FRDDR_A] = 4,
+ [AXG_ARB_FRDDR_B] = 5,
+ [AXG_ARB_FRDDR_C] = 6,
+};
+
+static int meson_audio_arb_update(struct reset_controller_dev *rcdev,
+ unsigned long id, bool assert)
+{
+ u32 val;
+ struct meson_audio_arb_data *arb =
+ container_of(rcdev, struct meson_audio_arb_data, rstc);
+
+ spin_lock(&arb->lock);
+ val = readl(arb->regs);
+
+ if (assert)
+ val &= ~BIT(arb->reset_bits[id]);
+ else
+ val |= BIT(arb->reset_bits[id]);
+
+ writel(val, arb->regs);
+ spin_unlock(&arb->lock);
+
+ return 0;
+}
+
+static int meson_audio_arb_status(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ u32 val;
+ struct meson_audio_arb_data *arb =
+ container_of(rcdev, struct meson_audio_arb_data, rstc);
+
+ val = readl(arb->regs);
+
+ return !(val & BIT(arb->reset_bits[id]));
+}
+
+static int meson_audio_arb_assert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return meson_audio_arb_update(rcdev, id, true);
+}
+
+static int meson_audio_arb_deassert(struct reset_controller_dev *rcdev,
+ unsigned long id)
+{
+ return meson_audio_arb_update(rcdev, id, false);
+}
+
+static const struct reset_control_ops meson_audio_arb_rstc_ops = {
+ .assert = meson_audio_arb_assert,
+ .deassert = meson_audio_arb_deassert,
+ .status = meson_audio_arb_status,
+};
+
+static const struct of_device_id meson_audio_arb_of_match[] = {
+ { .compatible = "amlogic,meson-axg-audio-arb", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, meson_audio_arb_of_match);
+
+static int meson_audio_arb_remove(struct platform_device *pdev)
+{
+ struct meson_audio_arb_data *arb = platform_get_drvdata(pdev);
+
+ /* Disable all access */
+ spin_lock(&arb->lock);
+ writel(0, arb->regs);
+ spin_unlock(&arb->lock);
+
+ clk_disable_unprepare(arb->clk);
+
+ return 0;
+}
+
+static int meson_audio_arb_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct meson_audio_arb_data *arb;
+ struct resource *res;
+ int ret;
+
+ arb = devm_kzalloc(dev, sizeof(*arb), GFP_KERNEL);
+ if (!arb)
+ return -ENOMEM;
+ platform_set_drvdata(pdev, arb);
+
+ arb->clk = devm_clk_get(dev
Re: [PATCH 1/3] clk: meson: clk-pll: add enable bit
On Sat, 2018-07-21 at 21:48 +0200, Martin Blumenstingl wrote:
> > @@ -250,11 +264,15 @@ static const struct reg_sequence axg_hifi_init_regs[]
> > = {
> > { .reg = HHI_HIFI_PLL_CNTL3,.def = 0x0a6a3a88 },
> > { .reg = HHI_HIFI_PLL_CNTL4,.def = 0xc04d },
> > { .reg = HHI_HIFI_PLL_CNTL5,.def = 0x00058000 },
> > - { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
>
> is this change on purpose? this line set en, m, n, l and od before
> maybe you can document it in the commit message
Yes the change is on purpose, but as you pointed out it is worth a comment
Actually, when taking od out of the pll driver, I remembered this 'initial
setting' and it kinda bothered me
If the od divider registers after the DCO, the value could have changed with it,
which is why I wanted to remove the write on this register
As you pointed out, in this register, we find m, n, od ... and enable. In a way,
removing this register setting was the reason why I wanted to add the enable bit
to begin with :)
Re: [PATCH 2/3] clk: meson: clk-pll: remove od parameters
On Sat, 2018-07-21 at 22:01 +0200, Martin Blumenstingl wrote:
> > +static struct clk_regmap gxbb_hdmi_pll_od = {
> > + .data = &(struct clk_regmap_div_data){
> > + .offset = HHI_HDMI_PLL_CNTL2,
> > + .shift = 16,
> > + .width = 2,
> > + .flags = CLK_DIVIDER_POWER_OF_TWO,
> > + },
> > + .hw.init = &(struct clk_init_data){
> > + .name = "hdmi_pll_od",
> > + .ops = &clk_regmap_divider_ro_ops,
> > + .parent_names = (const char *[]){ "hdmi_pll_dco" },
> > + .num_parents = 1,
> > + .flags = CLK_GET_RATE_NOCACHE,
>
> why do we need CLK_GET_RATE_NOCACHE here?
> also, shouldn't all _od clocks use CLK_SET_RATE_PARENT?
> (this applies to all new _od clocks, not just this one)
The goal was to retain the original behavior of the clock.
The pll has CLK_GET_RATE_NOCACHE, which is why I put it again in the od
dividers. Same goes for ro_ops
For the particular case of the HDMI PLL, the display driver still set the pll
parameters m, n and ods directly which justify CLK_GET_RATE_NOCACHE for now.
Of course, the goal is to remove this flag someday. I think there has been some
good progress in the DRM driver to reach this goal.
If we think the use CLK_GET_RATE_NOCACHE is not justified for some other plls, I
would prefer if it was addressed in another patchset.
Regarding SET_RATE_PARENT, with the pll set with ro_ops, it does not change
anything but, I agree, it would be better to set flag for the future.
Cheers
Jerome
Re: [PATCH 3/3] clk: meson: clk-pll: drop hard-coded rates from pll tables
On Sat, 2018-07-21 at 22:16 +0200, Martin Blumenstingl wrote: > > We could even add ranges instead of table when we know the PLL supports a > > well-known continuous dividers range. > > I had a look at the sys_pll settings on Meson8b, here's what > Meson8/Meson8b/Meson8m2 support for sys_pll: > - 50..74 > - 76 > - 78 > - 80 > - 82 > - 84 > - 86 > - 88 > - 90 > - 92 > - 94 > - 96 > - 98 Are those values with the same predivider (n) value ? I suspect the ability of the DCO to lock might depends on its input rate and an m range So if n change, it might possible that the m range will be different. ... at least, that's my guess :) > > (I'm providing this info because it may help finding a decision > whether ranges are good or not. I have no preference)
Re: [PATCH 0/3] clk: meson: clk-pll driver update
On Sat, 2018-07-21 at 22:17 +0200, Martin Blumenstingl wrote: > > This series has been tested on the gxl libretech cc and axg s400. > > I did not test it on meson8b yet. > > I had some comments on patch #2 > once that is fixed I can help testing on Meson8b (if you give me a few > days...) I don't intend to make another PR to clk in this cycle, unless something critical comes up. No rush.
[PATCH] pwm: meson: fix mux clock names
Current clock name looks like this:
/soc/bus@ffd0/pwm@1b000#mux0
This is bad because CCF uses the clock to create a directory in clk debugfs.
With such name, the directory creation (silently) fails and the debugfs
entry end up being created at the debugfs root.
With this change, the clock name will now be:
ffd1b000.pwm#mux0
This matches the clock naming scheme used in the ethernet and mmc driver.
It also fixes the problem with debugfs.
Fixes: 36af66a79056 ("pwm: Convert to using %pOF instead of full_name")
Signed-off-by: Jerome Brunet
---
drivers/pwm/pwm-meson.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 822860b4801a..c1ed641b3e26 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -458,7 +458,6 @@ static int meson_pwm_init_channels(struct meson_pwm *meson,
struct meson_pwm_channel *channels)
{
struct device *dev = meson->chip.dev;
- struct device_node *np = dev->of_node;
struct clk_init_data init;
unsigned int i;
char name[255];
@@ -467,7 +466,7 @@ static int meson_pwm_init_channels(struct meson_pwm *meson,
for (i = 0; i < meson->chip.npwm; i++) {
struct meson_pwm_channel *channel = &channels[i];
- snprintf(name, sizeof(name), "%pOF#mux%u", np, i);
+ snprintf(name, sizeof(name), "%s#mux%u", dev_name(dev), i);
init.name = name;
init.ops = &clk_mux_ops;
--
2.17.1
[PATCH v2 1/3] arm64: dts: meson-axg: add audio fifos
Add TODDR and FRDDR audio fifos of the AXG SoC.
These fifos are the capture and playback memory interfaces of audio
subsystem of the AXG.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 67 ++
1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index c518130e5ce7..32f6dcacc2bc 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
/ {
compatible = "amlogic,meson-axg";
@@ -223,6 +224,72 @@
resets = <&reset RESET_AUDIO>;
};
+ toddr_a: audio-controller@100 {
+ compatible = "amlogic,axg-toddr";
+ reg = <0x0 0x100 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_A";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+ resets = <&arb AXG_ARB_TODDR_A>;
+ status = "disabled";
+ };
+
+ toddr_b: audio-controller@140 {
+ compatible = "amlogic,axg-toddr";
+ reg = <0x0 0x140 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_B";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+ resets = <&arb AXG_ARB_TODDR_B>;
+ status = "disabled";
+ };
+
+ toddr_c: audio-controller@180 {
+ compatible = "amlogic,axg-toddr";
+ reg = <0x0 0x180 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_C";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+ resets = <&arb AXG_ARB_TODDR_C>;
+ status = "disabled";
+ };
+
+ frddr_a: audio-controller@1c0 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x1c0 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_A";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+ resets = <&arb AXG_ARB_FRDDR_A>;
+ status = "disabled";
+ };
+
+ frddr_b: audio-controller@200 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x200 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_B";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+ resets = <&arb AXG_ARB_FRDDR_B>;
+ status = "disabled";
+ };
+
+ frddr_c: audio-controller@240 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x240 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_C";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+ resets = <&arb AXG_ARB_FRDDR_C>;
+ status = "disabled";
+ };
+
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
--
2.17.1
[PATCH v2 2/3] arm64: dts: meson-axg: s400: enable audio devices
Enable the audio devices on the s400.
Signed-off-by: Jerome Brunet
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 72 +++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index d5c01427a5ca..9f5d81c3ee29 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -226,6 +226,18 @@
};
};
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
@@ -334,3 +346,63 @@
status = "okay";
vref-supply = <&vddio_ao18>;
};
+
+&spdifout {
+ pinctrl-0 = <&spdif_out_a20_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmin_lb {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&tdmif_a {
+ pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
+ <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tdmif_b {
+ pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
+ <&tdmb_din3_pins>, <&mclk_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tdmif_c {
+ pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
+ <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
+ <&mclk_c_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
--
2.17.1
[PATCH v2 3/3] arm64: dts: meson-axg: s400: add sound card
Add the sound card of the s400. With it the following interface
should be working:
* Lineout
* Daugther card speaker 1 (same output as lineout)
* Linein
* SPDIF output
Signed-off-by: Jerome Brunet
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 108 ++
1 file changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 9f5d81c3ee29..d399078d1f0c 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -204,6 +204,113 @@
status = "okay";
sound-name-prefix = "DIT";
};
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ model = "AXG-S400";
+ audio-aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
+<&tdmin_lb>, <&tdmout_c>;
+ audio-widgets = "Line", "Lineout",
+ "Line", "Linein",
+ "Speaker", "Speaker1 Left",
+ "Speaker", "Speaker1 Right";
+ audio-routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "SPDIFOUT IN 0", "FRDDR_A OUT 3",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "SPDIFOUT IN 1", "FRDDR_B OUT 3",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "SPDIFOUT IN 2", "FRDDR_C OUT 3",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 2", "TDM_C Capture",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 2", "TDM_C Capture",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 2", "TDM_C Capture",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TDMIN_LB IN 2", "TDM_C Loopback",
+ "TDMIN_LB IN 5", "TDM_C Capture",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 6", "TDMIN_LB OUT",
+ "TODDR_B IN 6", "TDMIN_LB OUT",
+ "TODDR_C IN 6", "TDMIN_LB OUT",
+ "Lineout", "Lineout AOUTL",
+ "Lineout", "Lineout AOUTR",
+ "Speaker1 Left", "SPK1 OUT_A",
+ "Speaker1 Left", "SPK1 OUT_B",
+ "Speaker1 Right", "SPK1 OUT_C",
+ "Speaker1 Right", "SPK1 OUT_D",
+ "Linein AINL", "Linein",
+ "Linein AINR", "Linein";
+ assigned-clocks = <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <589824000>,
+ <270950400>,
+ <393216000>;
+ status = "okay";
+
+ dai-link@0 {
+ sound-dai = <&frddr_a>;
+ };
+
+ dai-link@1 {
+ sound-dai = <&frddr_b>;
+ };
+
+ dai-link@2 {
+
[PATCH v2 0/3] arm64: dts: meson-axg: add audio support
The main purpose of this patchset is to add the audio devices on amlogic's
AXG SoCs.
In term of dependency, apart from the clock bindings you have already
pulled for your second PR to arm-soc, this patchset requires the ARB
reset bindings [0] for patch 1.
Changes since v1 [1]:
- Dropped applied changes
- Update card bindings following Rob's comments on the card DT binding
documentation.
[0]: 3bfd2fe0ab49 ("reset: meson: add dt-bindings for meson-axg audio arb")
[1]: https://lkml.kernel.org/r/20180724125238.14567-1-jbru...@baylibre.com
Jerome Brunet (3):
arm64: dts: meson-axg: add audio fifos
arm64: dts: meson-axg: s400: enable audio devices
arm64: dts: meson-axg: s400: add sound card
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 180 ++
arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 67 +++
2 files changed, 247 insertions(+)
--
2.17.1
[PATCH v2 0/4] clk: meson: clk-pll driver update
This patchset is yet another round of update to the amlogic pll driver. 1) Enable bit is added so we don't rely on the bootloader or the init value to enable to pll device. 2) Remove unnecessary CLK_GET_RATE_NOCACHE flags. 3) OD post dividers are removed from the pll driver. This simplify the driver and let us provide the clocks which exist between those dividers. Some device are actually using these clocks. 4) The rates hard coded in parameter tables are remove. Instead, we only rely on the parent rate and the parameters to calculate the output rate, which is a lot better. This series has been tested on the gxl libretech cc and axg s400. I did not test it on meson8b yet. Changes since v1: [0] - improve commit description of patch 1 - remove unnecessary CLK_GET_RATE_NOCACHE flags. - add missing CLK_SET_RATE_PARENT. [0]: https://lkml.kernel.org/r/20180717095617.12240-1-jbru...@baylibre.com Jerome Brunet (4): clk: meson: clk-pll: add enable bit clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary clk: meson: clk-pll: remove od parameters clk: meson: clk-pll: drop hard-coded rates from pll tables drivers/clk/meson/axg.c | 326 +-- drivers/clk/meson/axg.h | 8 +- drivers/clk/meson/clk-pll.c | 156 +++ drivers/clk/meson/clkc.h| 16 +- drivers/clk/meson/gxbb.c| 518 ++-- drivers/clk/meson/gxbb.h| 10 +- drivers/clk/meson/meson8b.c | 173 ++-- drivers/clk/meson/meson8b.h | 5 +- 8 files changed, 665 insertions(+), 547 deletions(-) -- 2.17.1
[PATCH v2 1/4] clk: meson: clk-pll: add enable bit
Add the enable the bit of the pll clocks.
These pll clocks may be disabled but we can't model this as an external
gate since the pll needs to lock when enabled.
Adding this bit allows to drop the poke of the first register of PLL.
This will be useful to model the different components of the pll using
generic clocks elements
Acked-by: Neil Armstrong
Acked-by: Martin Blumenstingl
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 28 +++---
drivers/clk/meson/clk-pll.c | 47 +
drivers/clk/meson/clkc.h| 1 +
drivers/clk/meson/gxbb.c| 32 +++--
drivers/clk/meson/meson8b.c | 15
5 files changed, 113 insertions(+), 10 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 00ce62ad6416..6d8976554656 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -24,6 +24,11 @@ static DEFINE_SPINLOCK(meson_clk_lock);
static struct clk_regmap axg_fixed_pll = {
.data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_MPLL_CNTL,
+ .shift = 30,
+ .width = 1,
+ },
.m = {
.reg_off = HHI_MPLL_CNTL,
.shift = 0,
@@ -65,6 +70,11 @@ static struct clk_regmap axg_fixed_pll = {
static struct clk_regmap axg_sys_pll = {
.data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_SYS_PLL_CNTL,
+ .shift = 30,
+ .width = 1,
+ },
.m = {
.reg_off = HHI_SYS_PLL_CNTL,
.shift = 0,
@@ -197,11 +207,15 @@ static const struct reg_sequence axg_gp0_init_regs[] = {
{ .reg = HHI_GP0_PLL_CNTL3, .def = 0x0a59a288 },
{ .reg = HHI_GP0_PLL_CNTL4, .def = 0xc04d },
{ .reg = HHI_GP0_PLL_CNTL5, .def = 0x00078000 },
- { .reg = HHI_GP0_PLL_CNTL, .def = 0x40010250 },
};
static struct clk_regmap axg_gp0_pll = {
.data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_GP0_PLL_CNTL,
+ .shift = 30,
+ .width = 1,
+ },
.m = {
.reg_off = HHI_GP0_PLL_CNTL,
.shift = 0,
@@ -250,11 +264,15 @@ static const struct reg_sequence axg_hifi_init_regs[] = {
{ .reg = HHI_HIFI_PLL_CNTL3,.def = 0x0a6a3a88 },
{ .reg = HHI_HIFI_PLL_CNTL4,.def = 0xc04d },
{ .reg = HHI_HIFI_PLL_CNTL5,.def = 0x00058000 },
- { .reg = HHI_HIFI_PLL_CNTL, .def = 0x40010250 },
};
static struct clk_regmap axg_hifi_pll = {
.data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_HIFI_PLL_CNTL,
+ .shift = 30,
+ .width = 1,
+ },
.m = {
.reg_off = HHI_HIFI_PLL_CNTL,
.shift = 0,
@@ -637,7 +655,6 @@ static const struct pll_rate_table
axg_pcie_pll_rate_table[] = {
};
static const struct reg_sequence axg_pcie_init_regs[] = {
- { .reg = HHI_PCIE_PLL_CNTL, .def = 0x400106c8 },
{ .reg = HHI_PCIE_PLL_CNTL1,.def = 0x0084a2aa },
{ .reg = HHI_PCIE_PLL_CNTL2,.def = 0xb75020be },
{ .reg = HHI_PCIE_PLL_CNTL3,.def = 0x0a47488e },
@@ -648,6 +665,11 @@ static const struct reg_sequence axg_pcie_init_regs[] = {
static struct clk_regmap axg_pcie_pll = {
.data = &(struct meson_clk_pll_data){
+ .en = {
+ .reg_off = HHI_PCIE_PLL_CNTL,
+ .shift = 30,
+ .width = 1,
+ },
.m = {
.reg_off = HHI_PCIE_PLL_CNTL,
.shift = 0,
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 3e04617ac47f..8aaefe67025f 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -185,12 +185,45 @@ static void meson_clk_pll_init(struct clk_hw *hw)
}
}
+static int meson_clk_pll_enable(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to_clk_regmap(hw);
+ struct meson_clk_pll_data *pll = meson_clk_pll_data(clk);
+
+ /* Make sure the pll is in reset */
+ meson_parm_write(clk->map, &pll->rst, 1);
+
+ /* Enable the pll */
+ meson_parm_write(clk->map, &pll->en, 1);
+
+ /* Take the pll out reset */
+ meson_parm_write(clk->map, &pll->rst, 0);
+
+ if (meson_clk_pll_wait_lock(hw))
+ return -EIO;
+
+ return 0;
+}
+
+static void meson_clk_pll_disable(struct clk_hw *hw)
+{
+ struct clk_regmap *clk = to
[PATCH v2 2/4] clk: meson: clk-pll: drop CLK_GET_RATE_NOCACHE where unnecessary
CLK_GET_RATE_NOCACHE should only be necessary when the registers
controlling the rate of clock may change outside of CCF. On Amlogic,
it should only be the case for the hdmi pll which is directly controlled
by the display driver (WIP to fix this).
The other plls should not require this flag.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 1 -
drivers/clk/meson/gxbb.c| 12
drivers/clk/meson/meson8b.c | 3 ---
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 6d8976554656..991fa511c05a 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -106,7 +106,6 @@ static struct clk_regmap axg_sys_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 5ed34566917c..01e3f80e88cc 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -218,7 +218,6 @@ static struct clk_regmap gxbb_fixed_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -286,6 +285,10 @@ static struct clk_regmap gxbb_hdmi_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "hdmi_pll_pre_mult" },
.num_parents = 1,
+ /*
+* Display directly handle hdmi pll registers ATM, we need
+* NOCACHE to keep our view of the clock as accurate as possible
+*/
.flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -349,6 +352,10 @@ static struct clk_regmap gxl_hdmi_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
+ /*
+* Display directly handle hdmi pll registers ATM, we need
+* NOCACHE to keep our view of the clock as accurate as possible
+*/
.flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -391,7 +398,6 @@ static struct clk_regmap gxbb_sys_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -442,7 +448,6 @@ static struct clk_regmap gxbb_gp0_pll = {
.ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -500,7 +505,6 @@ static struct clk_regmap gxl_gp0_pll = {
.ops = &meson_clk_pll_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
diff --git a/drivers/clk/meson/meson8b.c b/drivers/clk/meson/meson8b.c
index fd4c414893f5..ec1f97725b9f 100644
--- a/drivers/clk/meson/meson8b.c
+++ b/drivers/clk/meson/meson8b.c
@@ -137,7 +137,6 @@ static struct clk_regmap meson8b_fixed_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -179,7 +178,6 @@ static struct clk_regmap meson8b_vid_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
@@ -222,7 +220,6 @@ static struct clk_regmap meson8b_sys_pll = {
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
- .flags = CLK_GET_RATE_NOCACHE,
},
};
--
2.17.1
[PATCH v2 3/4] clk: meson: clk-pll: remove od parameters
Remove od parameters from pll clocks and add post dividers clocks
instead. Some clock, especially the one which feature several ods,
may provide output between those ods. Also, some drivers, such
as the hdmi driver, may require a more detailed control of the
clock dividers, compared to what CCF would perform automatically.
One added benefit of removing ods is that it also greatly reduce the
size of the rate parameter tables.
In the future, we could possibly take the predivider 'n' out of this
driver as well. To do so, we will need to understand the constraints
for the PLL to lock and whether or not it depends on the input clock
rate.
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 284 +++--
drivers/clk/meson/axg.h | 8 +-
drivers/clk/meson/clk-pll.c | 40 +--
drivers/clk/meson/clkc.h| 9 +-
drivers/clk/meson/gxbb.c| 484 +---
drivers/clk/meson/gxbb.h| 10 +-
drivers/clk/meson/meson8b.c | 151 +--
drivers/clk/meson/meson8b.h | 5 +-
8 files changed, 493 insertions(+), 498 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 991fa511c05a..a5e4f7b22f39 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -22,7 +22,7 @@
static DEFINE_SPINLOCK(meson_clk_lock);
-static struct clk_regmap axg_fixed_pll = {
+static struct clk_regmap axg_fixed_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
.reg_off = HHI_MPLL_CNTL,
@@ -39,11 +39,6 @@ static struct clk_regmap axg_fixed_pll = {
.shift = 9,
.width = 5,
},
- .od = {
- .reg_off = HHI_MPLL_CNTL,
- .shift = 16,
- .width = 2,
- },
.frac = {
.reg_off = HHI_MPLL_CNTL2,
.shift = 0,
@@ -61,14 +56,33 @@ static struct clk_regmap axg_fixed_pll = {
},
},
.hw.init = &(struct clk_init_data){
- .name = "fixed_pll",
+ .name = "fixed_pll_dco",
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
},
};
-static struct clk_regmap axg_sys_pll = {
+static struct clk_regmap axg_fixed_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_MPLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "fixed_pll",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "fixed_pll_dco" },
+ .num_parents = 1,
+ /*
+* This clock won't ever change at runtime so
+* CLK_SET_RATE_PARENT is not required
+*/
+ },
+};
+
+static struct clk_regmap axg_sys_pll_dco = {
.data = &(struct meson_clk_pll_data){
.en = {
.reg_off = HHI_SYS_PLL_CNTL,
@@ -85,11 +99,6 @@ static struct clk_regmap axg_sys_pll = {
.shift = 9,
.width = 5,
},
- .od = {
- .reg_off = HHI_SYS_PLL_CNTL,
- .shift = 16,
- .width = 2,
- },
.l = {
.reg_off = HHI_SYS_PLL_CNTL,
.shift = 31,
@@ -102,101 +111,59 @@ static struct clk_regmap axg_sys_pll = {
},
},
.hw.init = &(struct clk_init_data){
- .name = "sys_pll",
+ .name = "sys_pll_dco",
.ops = &meson_clk_pll_ro_ops,
.parent_names = (const char *[]){ "xtal" },
.num_parents = 1,
},
};
+static struct clk_regmap axg_sys_pll = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_SYS_PLL_CNTL,
+ .shift = 16,
+ .width = 2,
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "sys_pll",
+ .ops = &clk_regmap_divider_ro_ops,
+ .parent_names = (const char *[]){ "sys_pll_dco" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
- PLL_RATE(24000, 40, 1, 2),
- PLL_RATE(24600, 41, 1, 2),
- PLL_RATE(25200, 42, 1, 2),
- PLL_RATE(25800, 4
[PATCH v2 4/4] clk: meson: clk-pll: drop hard-coded rates from pll tables
Putting hard-coded rates inside the parameter tables assumes that
the parent is known and will never change. That's a big assumption
we should not make.
We have everything we need to recalculate the output rate using
the parent rate and the rest of the parameters. Let's do so and
drop the rates from the tables.
Acked-by: Neil Armstrong
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg.c | 73 +++---
drivers/clk/meson/clk-pll.c | 69 ++---
drivers/clk/meson/clkc.h| 8 +--
drivers/clk/meson/gxbb.c| 120 ++--
drivers/clk/meson/meson8b.c | 34 +-
5 files changed, 162 insertions(+), 142 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index a5e4f7b22f39..7511b3e26d40 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -134,36 +134,36 @@ static struct clk_regmap axg_sys_pll = {
},
};
-static const struct pll_rate_table axg_gp0_pll_rate_table[] = {
- PLL_RATE(96000, 40, 1),
- PLL_RATE(98400, 41, 1),
- PLL_RATE(100800, 42, 1),
- PLL_RATE(103200, 43, 1),
- PLL_RATE(105600, 44, 1),
- PLL_RATE(108000, 45, 1),
- PLL_RATE(110400, 46, 1),
- PLL_RATE(112800, 47, 1),
- PLL_RATE(115200, 48, 1),
- PLL_RATE(117600, 49, 1),
- PLL_RATE(12, 50, 1),
- PLL_RATE(122400, 51, 1),
- PLL_RATE(124800, 52, 1),
- PLL_RATE(127200, 53, 1),
- PLL_RATE(129600, 54, 1),
- PLL_RATE(132000, 55, 1),
- PLL_RATE(134400, 56, 1),
- PLL_RATE(136800, 57, 1),
- PLL_RATE(139200, 58, 1),
- PLL_RATE(141600, 59, 1),
- PLL_RATE(144000, 60, 1),
- PLL_RATE(146400, 61, 1),
- PLL_RATE(148800, 62, 1),
- PLL_RATE(151200, 63, 1),
- PLL_RATE(153600, 64, 1),
- PLL_RATE(156000, 65, 1),
- PLL_RATE(158400, 66, 1),
- PLL_RATE(160800, 67, 1),
- PLL_RATE(163200, 68, 1),
+static const struct pll_params_table axg_gp0_pll_params_table[] = {
+ PLL_PARAMS(40, 1),
+ PLL_PARAMS(41, 1),
+ PLL_PARAMS(42, 1),
+ PLL_PARAMS(43, 1),
+ PLL_PARAMS(44, 1),
+ PLL_PARAMS(45, 1),
+ PLL_PARAMS(46, 1),
+ PLL_PARAMS(47, 1),
+ PLL_PARAMS(48, 1),
+ PLL_PARAMS(49, 1),
+ PLL_PARAMS(50, 1),
+ PLL_PARAMS(51, 1),
+ PLL_PARAMS(52, 1),
+ PLL_PARAMS(53, 1),
+ PLL_PARAMS(54, 1),
+ PLL_PARAMS(55, 1),
+ PLL_PARAMS(56, 1),
+ PLL_PARAMS(57, 1),
+ PLL_PARAMS(58, 1),
+ PLL_PARAMS(59, 1),
+ PLL_PARAMS(60, 1),
+ PLL_PARAMS(61, 1),
+ PLL_PARAMS(62, 1),
+ PLL_PARAMS(63, 1),
+ PLL_PARAMS(64, 1),
+ PLL_PARAMS(65, 1),
+ PLL_PARAMS(66, 1),
+ PLL_PARAMS(67, 1),
+ PLL_PARAMS(68, 1),
{ /* sentinel */ },
};
@@ -207,7 +207,7 @@ static struct clk_regmap axg_gp0_pll_dco = {
.shift = 29,
.width = 1,
},
- .table = axg_gp0_pll_rate_table,
+ .table = axg_gp0_pll_params_table,
.init_regs = axg_gp0_init_regs,
.init_count = ARRAY_SIZE(axg_gp0_init_regs),
},
@@ -275,7 +275,7 @@ static struct clk_regmap axg_hifi_pll_dco = {
.shift = 29,
.width = 1,
},
- .table = axg_gp0_pll_rate_table,
+ .table = axg_gp0_pll_params_table,
.init_regs = axg_hifi_init_regs,
.init_count = ARRAY_SIZE(axg_hifi_init_regs),
.flags = CLK_MESON_PLL_ROUND_CLOSEST,
@@ -631,11 +631,10 @@ static struct clk_regmap axg_mpll3 = {
},
};
-static const struct pll_rate_table axg_pcie_pll_rate_table[] = {
+static const struct pll_params_table axg_pcie_pll_params_table[] = {
{
- .rate = 16,
- .m = 200,
- .n = 3,
+ .m = 200,
+ .n = 3,
},
{ /* sentinel */ },
};
@@ -682,7 +681,7 @@ static struct clk_regmap axg_pcie_pll_dco = {
.shift = 29,
.width = 1,
},
- .table = axg_pcie_pll_rate_table,
+ .table = axg_pcie_pll_params_table,
.init_regs = axg_pcie_init_regs,
.init_count = ARRAY_SIZE(axg_pcie_init_regs),
},
diff --git a/drivers/clk/meson/clk-pll.c b/drivers/clk/meson/clk-pll.c
index 348a866f09eb..f5b5b3fabe3c 100644
--- a/drivers/clk/meson/clk-pll.c
+++ b/drivers/clk/meson/clk-pll.c
@@ -45,7 +45,7 @@ meson_clk_pll_data(struct clk_regmap *clk)
}
static unsigned long __pll_params_to_rate(unsigned long parent_rate,
- const struct pll_rate_t
[PATCH] clk: meson: axg: round audio system master clocks down
Some of the master clocks provided by the axg audio clock controller are
system clock (spdifin and pdm sysclk). They are used to clock an internal
DSP of the related devices. Having them constantly rounded down instead
of closest is preferable.
Signed-off-by: Jerome Brunet
---
drivers/clk/meson/axg-audio.c | 34 +++---
1 file changed, 23 insertions(+), 11 deletions(-)
diff --git a/drivers/clk/meson/axg-audio.c b/drivers/clk/meson/axg-audio.c
index a0ed41e73bde..5f6c860aa122 100644
--- a/drivers/clk/meson/axg-audio.c
+++ b/drivers/clk/meson/axg-audio.c
@@ -101,10 +101,16 @@ static const char * const mst_mux_parent_names[] = {
"axg_mst_in4", "axg_mst_in5", "axg_mst_in6", "axg_mst_in7",
};
-#define AXG_MST_MCLK_MUX(_name, _reg) \
- AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, CLK_MUX_ROUND_CLOSEST, \
+#define AXG_MST_MUX(_name, _reg, _flag)\
+ AXG_AUD_MUX(_name##_sel, _reg, 0x7, 24, _flag, \
mst_mux_parent_names, CLK_SET_RATE_PARENT)
+#define AXG_MST_MCLK_MUX(_name, _reg) \
+ AXG_MST_MUX(_name, _reg, CLK_MUX_ROUND_CLOSEST)
+
+#define AXG_MST_SYS_MUX(_name, _reg) \
+ AXG_MST_MUX(_name, _reg, 0)
+
static AXG_MST_MCLK_MUX(mst_a_mclk, AUDIO_MCLK_A_CTRL);
static AXG_MST_MCLK_MUX(mst_b_mclk, AUDIO_MCLK_B_CTRL);
static AXG_MST_MCLK_MUX(mst_c_mclk, AUDIO_MCLK_C_CTRL);
@@ -112,13 +118,19 @@ static AXG_MST_MCLK_MUX(mst_d_mclk, AUDIO_MCLK_D_CTRL);
static AXG_MST_MCLK_MUX(mst_e_mclk, AUDIO_MCLK_E_CTRL);
static AXG_MST_MCLK_MUX(mst_f_mclk, AUDIO_MCLK_F_CTRL);
static AXG_MST_MCLK_MUX(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
-static AXG_MST_MCLK_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
static AXG_MST_MCLK_MUX(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
-static AXG_MST_MCLK_MUX(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
+static AXG_MST_SYS_MUX(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
+static AXG_MST_SYS_MUX(pdm_sysclk,AUDIO_CLK_PDMIN_CTRL1);
+
+#define AXG_MST_DIV(_name, _reg, _flag)\
+ AXG_AUD_DIV(_name##_div, _reg, 0, 16, _flag,\
+ "axg_"#_name"_sel", CLK_SET_RATE_PARENT)\
+
+#define AXG_MST_MCLK_DIV(_name, _reg) \
+ AXG_MST_DIV(_name, _reg, CLK_DIVIDER_ROUND_CLOSEST)
-#define AXG_MST_MCLK_DIV(_name, _reg) \
- AXG_AUD_DIV(_name##_div, _reg, 0, 16, CLK_DIVIDER_ROUND_CLOSEST, \
- "axg_"#_name"_sel", CLK_SET_RATE_PARENT)\
+#define AXG_MST_SYS_DIV(_name, _reg) \
+ AXG_MST_DIV(_name, _reg, 0)
static AXG_MST_MCLK_DIV(mst_a_mclk, AUDIO_MCLK_A_CTRL);
static AXG_MST_MCLK_DIV(mst_b_mclk, AUDIO_MCLK_B_CTRL);
@@ -127,12 +139,12 @@ static AXG_MST_MCLK_DIV(mst_d_mclk, AUDIO_MCLK_D_CTRL);
static AXG_MST_MCLK_DIV(mst_e_mclk, AUDIO_MCLK_E_CTRL);
static AXG_MST_MCLK_DIV(mst_f_mclk, AUDIO_MCLK_F_CTRL);
static AXG_MST_MCLK_DIV(spdifout_clk, AUDIO_CLK_SPDIFOUT_CTRL);
-static AXG_MST_MCLK_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
static AXG_MST_MCLK_DIV(pdm_dclk, AUDIO_CLK_PDMIN_CTRL0);
-static AXG_MST_MCLK_DIV(pdm_sysclk, AUDIO_CLK_PDMIN_CTRL1);
+static AXG_MST_SYS_DIV(spdifin_clk, AUDIO_CLK_SPDIFIN_CTRL);
+static AXG_MST_SYS_DIV(pdm_sysclk,AUDIO_CLK_PDMIN_CTRL1);
-#define AXG_MST_MCLK_GATE(_name, _reg) \
- AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \
+#define AXG_MST_MCLK_GATE(_name, _reg) \
+ AXG_AUD_GATE(_name, _reg, 31, "axg_"#_name"_div", \
CLK_SET_RATE_PARENT)
static AXG_MST_MCLK_GATE(mst_a_mclk, AUDIO_MCLK_A_CTRL);
--
2.17.1
Re: [PATCH v2 2/2] reset: meson: add meson audio arb driver
On Fri, 2018-07-20 at 18:19 +0200, Philipp Zabel wrote: > Hi Jerome, > > On Fri, 2018-07-20 at 17:26 +0200, Jerome Brunet wrote: > > The Amlogic Audio ARB is a simple device which enables or > > disables the access of Audio FIFOs to DDR on AXG based SoC. > > > > Signed-off-by: Jerome Brunet > > Thank you, both applied to reset/next. Hi Philipp, I know it missed your first PR to arm-soc but I can see it 'next', so I was wondering if this was going to make it into v4.19 ? Thanks Regards Jerome > > regards > Philipp
Re: [PATCH 2/5] pinctrl: meson: Add support to set direction with a secure monitor call
On Thu, 2018-08-02 at 09:52 +0200, Neil Armstrong wrote: > On 01/08/2018 22:23, Martin Blumenstingl wrote: > > Hi Neil, > > > > On Wed, Aug 1, 2018 at 12:05 PM Neil Armstrong > > wrote: > > > > > > The Amlogic Meson GX and AXG SoCs needs to do a Secure Monitor call to > > > set the TEST_N pin direction. > > > This patch adds a "smc" boolean to the bank structure to differentiate > > > the TEST_N bank and call the Secure Monitor in the _input/_output > > > functions. > > > > > > Signed-off-by: Neil Armstrong > > > --- > > > drivers/pinctrl/meson/Kconfig | 1 + > > > drivers/pinctrl/meson/pinctrl-meson.c | 31 > > > ++- > > > drivers/pinctrl/meson/pinctrl-meson.h | 10 +- > > > 3 files changed, 36 insertions(+), 6 deletions(-) > > > > > > diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig > > > index c80951d..1b90470 100644 > > > --- a/drivers/pinctrl/meson/Kconfig > > > +++ b/drivers/pinctrl/meson/Kconfig > > > @@ -8,6 +8,7 @@ menuconfig PINCTRL_MESON > > > select GPIOLIB > > > select OF_GPIO > > > select REGMAP_MMIO > > > + select MESON_SM > > > > I wonder why PINCTRL_MESON has to select MESON_SM - shouldn't > > PINCTRL_MESON_GXBB, PINCTRL_MESON_GXL and PINCTRL_MESON_AXG select it > > instead? > > selecting MESON_SM is probably no-op on Meson8 and Meson8b (which > > don't have the GX secure monitor), but I haven't tested it yet I'm not so sure about that. meson_sm_call() symbol is used in the common pinctrl code, so it should be selected when compiled even if meson8b is not going to use it in the end. > > Hi Martin, you are right ! > > I will fix it on v2.. > > Neil > > > > > > > Regards > > Martin > > > >
[PATCH 05/14] arm64: dts: meson-axg: add audio fifos
Add TODDR and FRDDR audio fifos of the AXG SoC.
These fifos are the capture and playback memory interfaces of audio
subsystem of the AXG.
Signed-off-by: Jerome Brunet
---
Kevin,
As you will see below, this patch depends on the ARB reset bindings which
have been accepted by Philip recently.
Cheers
Jerome
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 67 ++
1 file changed, 67 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index 3893c630d969..a20189844d92 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -11,6 +11,7 @@
#include
#include
#include
+#include
/ {
compatible = "amlogic,meson-axg";
@@ -190,6 +191,72 @@
resets = <&reset RESET_AUDIO>;
};
+ toddr_a: audio-controller@100 {
+ compatible = "amlogic,axg-toddr";
+ reg = <0x0 0x100 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_A";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_A>;
+ resets = <&arb AXG_ARB_TODDR_A>;
+ status = "disabled";
+ };
+
+ toddr_b: audio-controller@140 {
+ compatible = "amlogic,axg-toddr";
+ reg = <0x0 0x140 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_B";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_B>;
+ resets = <&arb AXG_ARB_TODDR_B>;
+ status = "disabled";
+ };
+
+ toddr_c: audio-controller@180 {
+ compatible = "amlogic,axg-toddr";
+ reg = <0x0 0x180 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "TODDR_C";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_TODDR_C>;
+ resets = <&arb AXG_ARB_TODDR_C>;
+ status = "disabled";
+ };
+
+ frddr_a: audio-controller@1c0 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x1c0 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_A";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_A>;
+ resets = <&arb AXG_ARB_FRDDR_A>;
+ status = "disabled";
+ };
+
+ frddr_b: audio-controller@200 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x200 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_B";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_B>;
+ resets = <&arb AXG_ARB_FRDDR_B>;
+ status = "disabled";
+ };
+
+ frddr_c: audio-controller@240 {
+ compatible = "amlogic,axg-frddr";
+ reg = <0x0 0x240 0x0 0x1c>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "FRDDR_C";
+ interrupts = ;
+ clocks = <&clkc_audio AUD_CLKID_FRDDR_C>;
+ resets = <&arb AXG_ARB_FRDDR_C>;
+ status = "disabled";
+ };
+
arb: reset-controller@280 {
compatible = "amlogic,meson-axg-audio-arb";
reg = <0x0 0x280 0x0 0x4>;
--
2.17.1
[PATCH 03/14] arm64: dts: meson-axg: add usb power regulator
The usb power regulator is supplied by the vcc 5v regulator and
controlled by a GPIO. This will be needed to enable usb.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 5937d8c3a6ed..7489b88f27d7 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -115,6 +115,17 @@
enable-active-high;
};
+ usb_pwr: regulator-usb_pwr {
+ compatible = "regulator-fixed";
+ regulator-name = "USB_PWR";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&vcc_5v>;
+
+ gpio = <&gpio_ao GPIOAO_5 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
--
2.17.1
[PATCH 13/14] arm64: dts: meson-axg: s400: enable audio devices
Enable the audio devices on the s400.
Signed-off-by: Jerome Brunet
---
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 72 +++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index d5c01427a5ca..9f5d81c3ee29 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -226,6 +226,18 @@
};
};
+&frddr_a {
+ status = "okay";
+};
+
+&frddr_b {
+ status = "okay";
+};
+
+&frddr_c {
+ status = "okay";
+};
+
&uart_A {
status = "okay";
pinctrl-0 = <&uart_a_pins>;
@@ -334,3 +346,63 @@
status = "okay";
vref-supply = <&vddio_ao18>;
};
+
+&spdifout {
+ pinctrl-0 = <&spdif_out_a20_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tdmin_a {
+ status = "okay";
+};
+
+&tdmin_b {
+ status = "okay";
+};
+
+&tdmin_c {
+ status = "okay";
+};
+
+&tdmin_lb {
+ status = "okay";
+};
+
+&tdmout_c {
+ status = "okay";
+};
+
+&tdmif_a {
+ pinctrl-0 = <&tdma_sclk_pins>, <&tdma_fs_pins>,
+ <&tdma_din0_pins>, <&tdma_dout0_x15_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tdmif_b {
+ pinctrl-0 = <&tdmb_sclk_pins>, <&tdmb_fs_pins>,
+ <&tdmb_din3_pins>, <&mclk_b_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&tdmif_c {
+ pinctrl-0 = <&tdmc_sclk_pins>, <&tdmc_fs_pins>,
+ <&tdmc_din1_pins>, <&tdmc_dout2_pins>,
+ <&mclk_c_pins>;
+ pinctrl-names = "default";
+ status = "okay";
+};
+
+&toddr_a {
+ status = "okay";
+};
+
+&toddr_b {
+ status = "okay";
+};
+
+&toddr_c {
+ status = "okay";
+};
--
2.17.1
[PATCH 14/14] arm64: dts: meson-axg: add s400 sound card
Add the sound card of the s400. With it the following interface
should be working:
* Lineout
* Daugther card speaker 1 (same output as lineout)
* Linein
* SPDIF output
Signed-off-by: Jerome Brunet
---
Compared to what is actually available on the platform, the following
is not provided ATM:
* SPDIF input: WIP.
* PDM DMICs: WIP.
* TDM A - BT Codec: missing BT codec.
* TDM B - Speaker analog loopback: missing tlv320adc codec.
.../arm64/boot/dts/amlogic/meson-axg-s400.dts | 108 ++
1 file changed, 108 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 9f5d81c3ee29..1b89c2cc5414 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -204,6 +204,113 @@
status = "okay";
sound-name-prefix = "DIT";
};
+
+ sound {
+ compatible = "amlogic,axg-sound-card";
+ amlogic,name = "AXG-S400";
+ amlogic,aux-devs = <&tdmin_a>, <&tdmin_b>, <&tdmin_c>,
+ <&tdmin_lb>, <&tdmout_c>;
+ amlogic,widgets = "Line", "Lineout",
+ "Line", "Linein",
+ "Speaker", "Speaker1 Left",
+ "Speaker", "Speaker1 Right";
+ amlogic,routing = "TDMOUT_C IN 0", "FRDDR_A OUT 2",
+ "SPDIFOUT IN 0", "FRDDR_A OUT 3",
+ "TDMOUT_C IN 1", "FRDDR_B OUT 2",
+ "SPDIFOUT IN 1", "FRDDR_B OUT 3",
+ "TDMOUT_C IN 2", "FRDDR_C OUT 2",
+ "SPDIFOUT IN 2", "FRDDR_C OUT 3",
+ "TDM_C Playback", "TDMOUT_C OUT",
+ "TDMIN_A IN 2", "TDM_C Capture",
+ "TDMIN_A IN 5", "TDM_C Loopback",
+ "TDMIN_B IN 2", "TDM_C Capture",
+ "TDMIN_B IN 5", "TDM_C Loopback",
+ "TDMIN_C IN 2", "TDM_C Capture",
+ "TDMIN_C IN 5", "TDM_C Loopback",
+ "TDMIN_LB IN 2", "TDM_C Loopback",
+ "TDMIN_LB IN 5", "TDM_C Capture",
+ "TODDR_A IN 0", "TDMIN_A OUT",
+ "TODDR_B IN 0", "TDMIN_A OUT",
+ "TODDR_C IN 0", "TDMIN_A OUT",
+ "TODDR_A IN 1", "TDMIN_B OUT",
+ "TODDR_B IN 1", "TDMIN_B OUT",
+ "TODDR_C IN 1", "TDMIN_B OUT",
+ "TODDR_A IN 2", "TDMIN_C OUT",
+ "TODDR_B IN 2", "TDMIN_C OUT",
+ "TODDR_C IN 2", "TDMIN_C OUT",
+ "TODDR_A IN 6", "TDMIN_LB OUT",
+ "TODDR_B IN 6", "TDMIN_LB OUT",
+ "TODDR_C IN 6", "TDMIN_LB OUT",
+ "Lineout", "Lineout AOUTL",
+ "Lineout", "Lineout AOUTR",
+ "Speaker1 Left", "SPK1 OUT_A",
+ "Speaker1 Left", "SPK1 OUT_B",
+ "Speaker1 Right", "SPK1 OUT_C",
+ "Speaker1 Right", "SPK1 OUT_D",
+ "Linein AINL", "Linein",
+ "Linein AINR", "Linein";
+ assigned-clocks = <&clkc CLKID_HIFI_PLL>,
+ <&clkc CLKID_MPLL0>,
+ <&clkc CLKID_MPLL1>;
+ assigned-clock-parents = <0>, <0>, <0>;
+ assigned-clock-rates = <589824000>,
+ <270950400>,
+
[PATCH 06/14] arm64: dts: meson-axg: add spdifout
Add the SPDIF output device of the axg audio subsystem
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
index a20189844d92..c56016a48cc4 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-axg.dtsi
@@ -263,6 +263,17 @@
#reset-cells = <1>;
clocks = <&clkc_audio AUD_CLKID_DDR_ARB>;
};
+
+ spdifout: audio-controller@480 {
+ compatible = "amlogic,axg-spdifout";
+ reg = <0x0 0x480 0x0 0x50>;
+ #sound-dai-cells = <0>;
+ sound-name-prefix = "SPDIFOUT";
+ clocks = <&clkc_audio AUD_CLKID_SPDIFOUT>,
+<&clkc_audio AUD_CLKID_SPDIFOUT_CLK>;
+ clock-names = "pclk", "mclk";
+ status = "disabled";
+ };
};
cbus: bus@ffd0 {
--
2.17.1
[PATCH 12/14] arm64: dts: meson-axg: add spdif-dit codec
Add the SPDIF playback codec to the axg s400 board
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index d318647c86a7..d5c01427a5ca 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -197,6 +197,13 @@
status = "okay";
sound-name-prefix = "Lineout";
};
+
+ spdif_dit: audio-codec@2 {
+ #sound-dai-cells = <0>;
+ compatible = "linux,spdif-dit";
+ status = "okay";
+ sound-name-prefix = "DIT";
+ };
};
ðmac {
--
2.17.1
[PATCH 02/14] arm64: dts: meson-axg: add vcc 5v regulator on the s400
This regulator is controlled by a GPIO and supplies various devices
on the board, such as the lineout codec, the usb supply or the lcd
controller.
Signed-off-by: Jerome Brunet
---
arch/arm64/boot/dts/amlogic/meson-axg-s400.dts | 11 +++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
index 09c7909a78ea..5937d8c3a6ed 100644
--- a/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-axg-s400.dts
@@ -104,6 +104,17 @@
regulator-always-on;
};
+ vcc_5v: regulator-vcc_5v {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC5V";
+ regulator-min-microvolt = <500>;
+ regulator-max-microvolt = <500>;
+ vin-supply = <&main_12v>;
+
+ gpio = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+ };
+
emmc_pwrseq: emmc-pwrseq {
compatible = "mmc-pwrseq-emmc";
reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;
--
2.17.1
[PATCH 00/14] arm64: dts: meson-axg: add audio support
The main purpose of this patchset is to add the audio devices on amlogic's AXG SoCs. Some codecs require some power supplies. This is why the 3 first patches deal with the S400 power supplies, even if some are not related to audio. In term of dependency, apart from the clock bindings you have already pulled for your second PR to arm-soc, this patchset requires the ARB reset bindings [0] for patch 5. I don't know if Philip can make it available somewhere ? Of course, if the dependencies make this patchset too complicated to merge in this cycle, I'll resubmit once the next rc1 is out. Jerome Brunet (14): arm64: dts: meson-axg: improve power supplies description arm64: dts: meson-axg: add vcc 5v regulator on the s400 arm64: dts: meson-axg: add usb power regulator arm64: dts: meson-axg: add audio arb reset controller arm64: dts: meson-axg: add audio fifos arm64: dts: meson-axg: add spdifout arm64: dts: meson-axg: add tdmin formatters arm64: dts: meson-axg: add tdmout formatters arm64: dts: meson-axg: add tdm interfaces arm64: dts: meson-axg: add linein codec arm64: dts: meson-axg: add lineout codec arm64: dts: meson-axg: add spdif-dit codec arm64: dts: meson-axg: s400: enable audio devices arm64: dts: meson-axg: add s400 sound card .../arm64/boot/dts/amlogic/meson-axg-s400.dts | 237 ++ arch/arm64/boot/dts/amlogic/meson-axg.dtsi| 216 2 files changed, 453 insertions(+) -- 2.17.1
