Hi Peppe and Lars,
On 23-11-2016 10:59, Giuseppe CAVALLARO wrote:
> Hello Joao, Lars.
>
> On 11/22/2016 3:16 PM, Joao Pinto wrote:
>>> Ok, it makes sense.
>>> > Just for curiosity the target setup is the following:
>>> > https://www.youtube.com/watc
Hi Lars and Peppe,
On 21-11-2016 16:11, Joao Pinto wrote:
> On 21-11-2016 15:43, Lars Persson wrote:
>>
>>
>>> 21 nov. 2016 kl. 16:06 skrev Joao Pinto <joao.pi...@synopsys.com>:
>>>
>>>> On 21-11-2016 14:25, Giuseppe CAVALLARO wro
Hi Lars and Peppe,
On 21-11-2016 16:11, Joao Pinto wrote:
> On 21-11-2016 15:43, Lars Persson wrote:
>>
>>
>>> 21 nov. 2016 kl. 16:06 skrev Joao Pinto :
>>>
>>>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>>>> On 11/21/2016 2:28 PM
On 21-11-2016 15:43, Lars Persson wrote:
>
>
>> 21 nov. 2016 kl. 16:06 skrev Joao Pinto <joao.pi...@synopsys.com>:
>>
>>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>>> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>>>
>>>>
On 21-11-2016 15:43, Lars Persson wrote:
>
>
>> 21 nov. 2016 kl. 16:06 skrev Joao Pinto :
>>
>>> On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
>>>> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>>>
>>>>
>>>>
On 21-11-2016 15:03, Giuseppe CAVALLARO wrote:
> On 11/21/2016 4:00 PM, Joao Pinto wrote:
>> On 21-11-2016 14:36, Giuseppe CAVALLARO wrote:
>>> Hello Joao
>>>
>>> On 11/21/2016 2:48 PM, Joao Pinto wrote:
>>>> Synopsys QoS IP is a separated ha
On 21-11-2016 15:03, Giuseppe CAVALLARO wrote:
> On 11/21/2016 4:00 PM, Joao Pinto wrote:
>> On 21-11-2016 14:36, Giuseppe CAVALLARO wrote:
>>> Hello Joao
>>>
>>> On 11/21/2016 2:48 PM, Joao Pinto wrote:
>>>> Synopsys QoS IP is a separated ha
On 21-11-2016 14:36, Giuseppe CAVALLARO wrote:
> Hello Joao
>
> On 11/21/2016 2:48 PM, Joao Pinto wrote:
>> Synopsys QoS IP is a separated hardware component, so it should be reusable
>> by
>> all implementations using it and so have its own "core driver&quo
On 21-11-2016 14:36, Giuseppe CAVALLARO wrote:
> Hello Joao
>
> On 11/21/2016 2:48 PM, Joao Pinto wrote:
>> Synopsys QoS IP is a separated hardware component, so it should be reusable
>> by
>> all implementations using it and so have its own "core driver&quo
On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>
>>
>>> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO <peppe.cavall...@st.com>:
>>>
>>> Hello Joao
>>>
>>>> On 11/21/2016 1:32 PM, J
On 21-11-2016 14:25, Giuseppe CAVALLARO wrote:
> On 11/21/2016 2:28 PM, Lars Persson wrote:
>>
>>
>>> 21 nov. 2016 kl. 13:53 skrev Giuseppe CAVALLARO :
>>>
>>> Hello Joao
>>>
>>>> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>&
Hello Peppe,
On 21-11-2016 12:52, Giuseppe CAVALLARO wrote:
> Hello Joao
>
> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>> Hello,
>>
>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
>>> On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent <ra...@rab.in> wrot
Hello Peppe,
On 21-11-2016 12:52, Giuseppe CAVALLARO wrote:
> Hello Joao
>
> On 11/21/2016 1:32 PM, Joao Pinto wrote:
>> Hello,
>>
>> On 21-11-2016 05:29, Rayagond Kokatanur wrote:
>>> On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent wrote:
>>>>
Hello,
On 21-11-2016 05:29, Rayagond Kokatanur wrote:
> On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent <ra...@rab.in> wrote:
>> On Fri, Nov 18, 2016 at 02:20:27PM +0000, Joao Pinto wrote:
>>> For now we are interesting in improving the synopsys QoS driver under
>
Hello,
On 21-11-2016 05:29, Rayagond Kokatanur wrote:
> On Sat, Nov 19, 2016 at 7:26 PM, Rabin Vincent wrote:
>> On Fri, Nov 18, 2016 at 02:20:27PM +0000, Joao Pinto wrote:
>>> For now we are interesting in improving the synopsys QoS driver under
>>> /nect/ethernet/s
On 18-11-2016 16:35, Florian Fainelli wrote:
>
>
> On 11/18/2016 08:31 AM, Joao Pinto wrote:
>> Hi Florian,
>>
>> On 18-11-2016 14:53, Florian Fainelli wrote:
>>> On November 18, 2016 4:28:30 AM PST, Joao Pinto <joao.pi...@synopsys.com>
>>>
On 18-11-2016 16:35, Florian Fainelli wrote:
>
>
> On 11/18/2016 08:31 AM, Joao Pinto wrote:
>> Hi Florian,
>>
>> On 18-11-2016 14:53, Florian Fainelli wrote:
>>> On November 18, 2016 4:28:30 AM PST, Joao Pinto
>>> wrote:
>>>>
sn
Hi Florian,
On 18-11-2016 14:53, Florian Fainelli wrote:
> On November 18, 2016 4:28:30 AM PST, Joao Pinto <joao.pi...@synopsys.com>
> wrote:
>>
>> Dear all,
>>
>> My name is Joao Pinto and I work at Synopsys.
>> I am a kernel developer with specia
Hi Florian,
On 18-11-2016 14:53, Florian Fainelli wrote:
> On November 18, 2016 4:28:30 AM PST, Joao Pinto
> wrote:
>>
>> Dear all,
>>
>> My name is Joao Pinto and I work at Synopsys.
>> I am a kernel developer with special focus in mainline collaboratio
that we have available internally
Thanks,
Joao
>
> Regards,
>
> Ozgur Karatas
>
> 2016-11-18 15:28 GMT+03:00 Joao Pinto <joao.pi...@synopsys.com>:
>
>>
>> Dear all,
>>
>> My name is Joao Pinto and I work at Synopsys.
>> I am a kernel develop
that we have available internally
Thanks,
Joao
>
> Regards,
>
> Ozgur Karatas
>
> 2016-11-18 15:28 GMT+03:00 Joao Pinto :
>
>>
>> Dear all,
>>
>> My name is Joao Pinto and I work at Synopsys.
>> I am a kernel developer with special focus in mainline col
[The previous e-mail had an error, please consider this one. Thank you.]
Dear all,
My name is Joao Pinto and I work at Synopsys.
I am a kernel developer with special focus in mainline collaboration, both Linux
and Buildroot. I was recently named one of the maintainers of the PCIe
Designware core
[The previous e-mail had an error, please consider this one. Thank you.]
Dear all,
My name is Joao Pinto and I work at Synopsys.
I am a kernel developer with special focus in mainline collaboration, both Linux
and Buildroot. I was recently named one of the maintainers of the PCIe
Designware core
Dear all,
My name is Joao Pinto and I work at Synopsys.
I am a kernel developer with special focus in mainline collaboration, both Linux
and Buildroot. I was recently named one of the maintainers of the PCIe
Designware core driver and I was the author of the Designware UFS driver stack.
I am
Dear all,
My name is Joao Pinto and I work at Synopsys.
I am a kernel developer with special focus in mainline collaboration, both Linux
and Buildroot. I was recently named one of the maintainers of the PCIe
Designware core driver and I was the author of the Designware UFS driver stack.
I am
On 16-11-2016 22:18, Bjorn Helgaas wrote:
> On Tue, Nov 15, 2016 at 04:10:46PM +0000, Joao Pinto wrote:
>> I accepted the invitation from Pratyush to replace him in the
>> pcie-designware maintenance. This patch makes the maintainer replacement
>> and symplifies a bi
On 16-11-2016 22:18, Bjorn Helgaas wrote:
> On Tue, Nov 15, 2016 at 04:10:46PM +0000, Joao Pinto wrote:
>> I accepted the invitation from Pratyush to replace him in the
>> pcie-designware maintenance. This patch makes the maintainer replacement
>> and symplifies a bi
I returned to Synopsys and so I am sending this patch to update the email
address of the pcie-designware-plat author.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
drivers/pci/host/pcie-designware-plat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pc
I accepted the invitation from Pratyush to replace him in the
pcie-designware maintenance. This patch makes the maintainer replacement
and symplifies a bit the pcie-designware* maintenance structure.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
Cc: Pratyush Anand <pratyush.an...@gmai
I returned to Synopsys and so I am sending this patch to update the email
address of the pcie-designware-plat author.
Signed-off-by: Joao Pinto
---
drivers/pci/host/pcie-designware-plat.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-designware-plat.c
I accepted the invitation from Pratyush to replace him in the
pcie-designware maintenance. This patch makes the maintainer replacement
and symplifies a bit the pcie-designware* maintenance structure.
Signed-off-by: Joao Pinto
Cc: Pratyush Anand
Cc: Jose Abreu
---
MAINTAINERS | 10
Thank you Bjorn!
On 10/21/2016 3:57 PM, Bjorn Helgaas wrote:
> On Fri, Oct 21, 2016 at 10:31:48AM +0100, Joao Pinto wrote:
>> Although I am leaving Synopsys, I would like to keep working with the
>> linux kernel community and help in what you might find useful. For that
Thank you Bjorn!
On 10/21/2016 3:57 PM, Bjorn Helgaas wrote:
> On Fri, Oct 21, 2016 at 10:31:48AM +0100, Joao Pinto wrote:
>> Although I am leaving Synopsys, I would like to keep working with the
>> linux kernel community and help in what you might find useful. For that
Although I am leaving Synopsys, I would like to keep working with the
linux kernel community and help in what you might find useful. For that
I am sending this patch to change my contact e-mail.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
drivers/pci/host/pcie-designware-plat
Although I am leaving Synopsys, I would like to keep working with the
linux kernel community and help in what you might find useful. For that
I am sending this patch to change my contact e-mail.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
drivers/scsi/ufs/tc-dwc-g210-pci.c
Although I am leaving Synopsys, I would like to keep working with the
linux kernel community and help in what you might find useful. For that
I am sending this patch to change my contact e-mail.
Signed-off-by: Joao Pinto
---
drivers/pci/host/pcie-designware-plat.c | 2 +-
1 file changed, 1
Although I am leaving Synopsys, I would like to keep working with the
linux kernel community and help in what you might find useful. For that
I am sending this patch to change my contact e-mail.
Signed-off-by: Joao Pinto
---
drivers/scsi/ufs/tc-dwc-g210-pci.c| 4 ++--
drivers/scsi/ufs/tc
t; + /* get iATU unroll support */
> + pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
> + dev_dbg(pp->dev, "iATU unroll: %s\n",
> + pp->iatu_unroll_enabled ? "enabled" : "disabled");
> +
> /* set the number of lanes */
> val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
> val &= ~PORT_LINK_MODE_MASK;
>
Acked-by: Joao Pinto <jpi...@synopsys.com>
Thanks
Joao
iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
> + dev_dbg(pp->dev, "iATU unroll: %s\n",
> + pp->iatu_unroll_enabled ? "enabled" : "disabled");
> +
> /* set the number of lanes */
> val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
> val &= ~PORT_LINK_MODE_MASK;
>
Acked-by: Joao Pinto
Thanks
Joao
On 10/14/2016 4:24 PM, Niklas Cassel wrote:
> On 10/14/2016 03:02 PM, Joao Pinto wrote:
>> Hi Niklas,
>>
>>
>> On 10/14/2016 1:41 PM, Niklas Cassel wrote:
>>> Hello
>>>
(snip)
> }
> }
>
> -
On 10/14/2016 4:24 PM, Niklas Cassel wrote:
> On 10/14/2016 03:02 PM, Joao Pinto wrote:
>> Hi Niklas,
>>
>>
>> On 10/14/2016 1:41 PM, Niklas Cassel wrote:
>>> Hello
>>>
(snip)
> }
> }
>
> -
I am going to leave Synopsys and so this patch changes the Maintainer
for PCIe Designware Platform driver to my colleague Jose Abreu.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINT
I am going to leave Synopsys and so this patch changes the Maintainer
for PCIe Designware Platform driver to my colleague Jose Abreu.
Signed-off-by: Joao Pinto
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 01bff8e..5ac91d8a
I am going to leave Synopsys and so this patch changes the Maintainer
for UFS Synopsys' specific drivers to my colleagues Manjunath and Prabu.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAI
I am going to leave Synopsys and so this patch changes the Maintainer
for UFS Synopsys' specific drivers to my colleagues Manjunath and Prabu.
Signed-off-by: Joao Pinto
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ac91d8a
Hi Niklas,
On 10/14/2016 1:41 PM, Niklas Cassel wrote:
> Hello
>
> Because of recent changes to drivers/pci/host/pcie-artpec6.c,
> I was going to try out Bjorn's tag pci-v4.9-changes-2,
> however I was greeted by an imprecise external abort:
>
>
> [0.613082] Trying to unpack rootfs image
Hi Niklas,
On 10/14/2016 1:41 PM, Niklas Cassel wrote:
> Hello
>
> Because of recent changes to drivers/pci/host/pcie-artpec6.c,
> I was going to try out Bjorn's tag pci-v4.9-changes-2,
> however I was greeted by an imprecise external abort:
>
>
> [0.613082] Trying to unpack rootfs image
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ac91d8a..d9855b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12084,7 +12084,8 @@ F: Documentation/scsi/ufs.
Signed-off-by: Joao Pinto
---
MAINTAINERS | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5ac91d8a..d9855b5 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -12084,7 +12084,8 @@ F: Documentation/scsi/ufs.txt
F: drivers/scsi/ufs
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 01bff8e..5ac91d8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9052,7 +9052,7 @@ S:Maintained
F: drivers/pc
Signed-off-by: Joao Pinto
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 01bff8e..5ac91d8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -9052,7 +9052,7 @@ S:Maintained
F: drivers/pci/host/*designware*
PCI
gt; port
> it! Thanks!
>
>
> On 9/28/2016 10:06 AM, Joao Pinto wrote:
>>
>> Hi Subhash,
>>
>> On 9/28/2016 12:05 AM, subha...@codeaurora.org wrote:
>>> Hi Joao,
>>>
>>>
>>> On 2016-09-26 18:10, Kiwoong Kim wrote:
>>>> Hi.
gt; port
> it! Thanks!
>
>
> On 9/28/2016 10:06 AM, Joao Pinto wrote:
>>
>> Hi Subhash,
>>
>> On 9/28/2016 12:05 AM, subha...@codeaurora.org wrote:
>>> Hi Joao,
>>>
>>>
>>> On 2016-09-26 18:10, Kiwoong Kim wrote:
>>>> Hi.
you please send me the
patch and kernel version to apply?
Thanks,
Joao
>
> Regards,
> Subhash
>
>
>>
>> Regards.
>>
>>> -Original Message-
>>> From: linux-scsi-ow...@vger.kernel.org [mailto:linux-scsi-
>>> ow...@vger.kernel.org]
you please send me the
patch and kernel version to apply?
Thanks,
Joao
>
> Regards,
> Subhash
>
>
>>
>> Regards.
>>
>>> -Original Message-
>>> From: linux-scsi-ow...@vger.kernel.org [mailto:linux-scsi-
>>> ow...@vger.kernel.org]
Hi again!
Could you also send me an example of how you are using the IOCTL from your user
app (send/receive data)? I already have my implemented but you use a different
mechanism (I have checked your structures in uapi/scsi/ufs/) and I have to port
it! Thanks!
On 9/28/2016 10:06 AM, Joao Pinto
Hi again!
Could you also send me an example of how you are using the IOCTL from your user
app (send/receive data)? I already have my implemented but you use a different
mechanism (I have checked your structures in uapi/scsi/ufs/) and I have to port
it! Thanks!
On 9/28/2016 10:06 AM, Joao Pinto
Hi!
I am designing an application that has the goal to be an utility for Unipro and
UFS testing purposes. This application is going to run on top of a recent Linux
Kernel containing the new UFS stack (including the new DWC drivers).
I am considering doing the following:
a) Create a new config
Hi!
I am designing an application that has the goal to be an utility for Unipro and
UFS testing purposes. This application is going to run on top of a recent Linux
Kernel containing the new UFS stack (including the new DWC drivers).
I am considering doing the following:
a) Create a new config
On 9/6/2016 4:57 PM, Bjorn Helgaas wrote:
> On Tue, Aug 09, 2016 at 04:49:37PM +0100, Joao Pinto wrote:
>> To fix this, this patch adds ARC as a PCI_MSI_IRQ_DOMAIN supportive
>> platform and adds the generation of msi.h in the ARC arch.
>>
>> Signed-off-by: Joao Pinto &
On 9/6/2016 4:57 PM, Bjorn Helgaas wrote:
> On Tue, Aug 09, 2016 at 04:49:37PM +0100, Joao Pinto wrote:
>> To fix this, this patch adds ARC as a PCI_MSI_IRQ_DOMAIN supportive
>> platform and adds the generation of msi.h in the ARC arch.
>>
>> Signed-off-by: Joao Pinto
Hi Bjorn,
Did you have the chance to check this patch?
Thanks.
On 8/10/2016 6:55 PM, Vineet Gupta wrote:
> On 08/09/2016 08:51 AM, Joao Pinto wrote:
>> Due to the added dependency on PCI_MSI_IRQ_DOMAIN for all PCIe RC
>> drivers, we were unable to build a RC solution for
Hi Bjorn,
Did you have the chance to check this patch?
Thanks.
On 8/10/2016 6:55 PM, Vineet Gupta wrote:
> On 08/09/2016 08:51 AM, Joao Pinto wrote:
>> Due to the added dependency on PCI_MSI_IRQ_DOMAIN for all PCIe RC
>> drivers, we were unable to build a RC solution for
This patch is to fix a building error in branch pci/host-designware.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
drivers/pci/host/pcie-designware.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/hos
This patch is to fix a building error in branch pci/host-designware.
Signed-off-by: Joao Pinto
---
drivers/pci/host/pcie-designware.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designware.c
index be70f28
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
CC: Jisheng Zhang <jszh...@marvell.com>
---
changes v3->v5:
- Just to keep up with the patch version
changes v2->
ry support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pci: move definitions from header to pcie-designware.c
pci: add iATU Unroll mechanism
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 -
driver
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto
CC: Jisheng Zhang
---
changes v3->v5:
- Just to keep up with the patch version
changes v2->v3 (Bjorn Helgaas):
- Separated from the new iATU unroll mec
ry support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pci: move definitions from header to pcie-designware.c
pci: add iATU Unroll mechanism
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 -
driver
Hi Bjorn,
On 8/9/2016 5:54 PM, Bjorn Helgaas wrote:
> Hi Joao,
>
> On Tue, Aug 09, 2016 at 05:35:34PM +0100, Joao Pinto wrote:
>> Simple fix typo.
>
> This patch actually does more than fix a typo. Not sure if you
> intended to split this into separate patches, or to wr
Hi Bjorn,
On 8/9/2016 5:54 PM, Bjorn Helgaas wrote:
> Hi Joao,
>
> On Tue, Aug 09, 2016 at 05:35:34PM +0100, Joao Pinto wrote:
>> Simple fix typo.
>
> This patch actually does more than fix a typo. Not sure if you
> intended to split this into separate patches, or to wr
Simple fix typo.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
changes v4->v5:
- v4 patch was not done properly
changes v1->v4:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Simple fix typo.
Signed-off-by: Joao Pinto
---
changes v4->v5:
- v4 patch was not done properly
changes v1->v4:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/hos
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
changes v4->v5:
- v4 patch was not done properly
changes v3->v4:
- Unroll Mode is now ob
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto
---
changes v4->v5:
- v4 patch was not done properly
changes v3->v4:
- Unroll Mode is now obtained before the host initialization
-
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
changes v3->v4:
- Unroll Mode is now obtained before the host initialization
- The iATU enable check lo
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto
---
changes v3->v4:
- Unroll Mode is now obtained before the host initialization
- The iATU enable check loop is now returning in
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
CC: Jisheng Zhang <jszh...@marvell.com>
---
changes v3->v4:
- Just to keep up with the patch version
changes v2->
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto
CC: Jisheng Zhang
---
changes v3->v4:
- Just to keep up with the patch version
changes v2->v3 (Bjorn Helgaas):
- Separated from the new iATU unroll mec
Simple fix typo.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
changes v1->v4:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c
Simple fix typo.
Signed-off-by: Joao Pinto
---
changes v1->v4:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/p
ry support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pci: move definitions from header to pcie-designware.c
pci: add iATU Unroll mechanism
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 -
driver
ry support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pci: move definitions from header to pcie-designware.c
pci: add iATU Unroll mechanism
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 -
driver
To fix this, this patch adds ARC as a PCI_MSI_IRQ_DOMAIN supportive
platform and adds the generation of msi.h in the ARC arch.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
arch/arc/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 de
To fix this, this patch adds ARC as a PCI_MSI_IRQ_DOMAIN supportive
platform and adds the generation of msi.h in the ARC arch.
Signed-off-by: Joao Pinto
---
arch/arc/include/asm/Kbuild | 1 +
drivers/pci/Kconfig | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch
Hi Kishon,
On 8/3/2016 7:03 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> The PCIe controller present in TI's DRA7 SoC is capable of operating either in
> Root Complex mode or Endpoint mode. (It uses Synopsys Designware Core). I'd
> assume most of the PCIe controllers on other platforms that use
Hi Kishon,
On 8/3/2016 7:03 AM, Kishon Vijay Abraham I wrote:
> Hi,
>
> The PCIe controller present in TI's DRA7 SoC is capable of operating either in
> Root Complex mode or Endpoint mode. (It uses Synopsys Designware Core). I'd
> assume most of the PCIe controllers on other platforms that use
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
changes v2->v3 (Bjorn Helgaas):
- Unused *CTRL3 and *UPPR iATU Unroll registers were removed
- Inbound
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
Signed-off-by: Joao Pinto
---
changes v2->v3 (Bjorn Helgaas):
- Unused *CTRL3 and *UPPR iATU Unroll registers were removed
- Inbound addr builder macr
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
CC: Jisheng Zhang <jszh...@marvell.com>
---
changes v2->v3 (Bjorn Helgaas):
- Separated from the new iATU unroll mechanism
Simple fix typo.
Signed-off-by: Joao Pinto <jpi...@synopsys.com>
---
changes v1->v3:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/dr
ry support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pcie-designware: move definitions
pcie-designware: add iATU Unroll feature
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 -
drivers/pci
This patch moves the sleep definitions to the *.c file like suggested
by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto
CC: Jisheng Zhang
---
changes v2->v3 (Bjorn Helgaas):
- Separated from the new iATU unroll mechanism patch
drivers/pci/host/pcie-designware.c
Simple fix typo.
Signed-off-by: Joao Pinto
---
changes v1->v3:
- Nothing changed. Just to keep up patch set version.
drivers/pci/host/pcie-designware.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/host/pcie-designware.c
b/drivers/pci/host/pcie-designwar
ry support for the mechanism and makes
some minor improvements to the existent one.
Joao Pinto (3):
pcie-designware: move definitions
pcie-designware: add iATU Unroll feature
pcie-designware: fix typo
drivers/pci/host/pcie-designware.c | 138 -
drivers/pci
On 8/2/2016 1:53 PM, Bjorn Helgaas wrote:
> On Tue, Aug 02, 2016 at 11:27:45AM +0100, Joao Pinto wrote:
>> On 7/25/2016 9:44 PM, Bjorn Helgaas wrote:
>>> On Fri, Jul 22, 2016 at 02:29:38PM +0100, Joao Pinto wrote:
>>>> This patch adds the support to the new iA
On 8/2/2016 1:53 PM, Bjorn Helgaas wrote:
> On Tue, Aug 02, 2016 at 11:27:45AM +0100, Joao Pinto wrote:
>> On 7/25/2016 9:44 PM, Bjorn Helgaas wrote:
>>> On Fri, Jul 22, 2016 at 02:29:38PM +0100, Joao Pinto wrote:
>>>> This patch adds the support to the new iA
On 7/25/2016 9:44 PM, Bjorn Helgaas wrote:
> On Fri, Jul 22, 2016 at 02:29:38PM +0100, Joao Pinto wrote:
>> This patch adds the support to the new iATU mechanism that will be used
>> from Core version 4.80, which is called iATU Unroll.
>> The new Cores can support the i
On 7/25/2016 9:44 PM, Bjorn Helgaas wrote:
> On Fri, Jul 22, 2016 at 02:29:38PM +0100, Joao Pinto wrote:
>> This patch adds the support to the new iATU mechanism that will be used
>> from Core version 4.80, which is called iATU Unroll.
>> The new Cores can support the i
In order to make sure that the iATU is really enabled a for loop was
introduced in dw_pcie_prog_outbound_atu() to improve reliability.
This patch also moves the sleep definitions to the *.c file like
suggested by Jisheng Zhang in a previous patch.
Signed-off-by: Joao Pinto <jpi...@synopsys.com
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