-by: Axel Linaxel@ingics.com
for both of these feel free to add ...
Acked-by: John Crispin blo...@openwrt.org
Thanks,
John
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On 11/10/12 16:00, Linus Walleij wrote:
On Wed, Oct 10, 2012 at 2:59 PM, Wei Yongjunweiyj...@gmail.com wrote:
From: Wei Yongjunyongjun_...@trendmicro.com.cn
Remove duplicated include.
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei
On 17/08/12 11:09, Takashi Iwai wrote:
At Fri, 17 Aug 2012 16:43:32 +0800,
Huacai Chen wrote:
Lemote A1004(Laptop) and A1205(All-In-One) use Conexant's hda codec,
this patch modify patch_conexant.c to add Lemote specific code.
Both A1004 and A1205 use the same pin configurations, but
Add gpio driver for Ralink SoC. This driver makes the gpio core on
RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
Signed-off-by: John Crispin blo...@openwrt.org
---
.../devicetree/bindings/gpio/gpio-ralink.txt | 33
arch/mips/Kconfig
Add gpio driver for Ralink SoC. This driver makes the gpio core on
RT2880, RT305x, rt3352, rt3662, rt3883, rt5350 and mt7620 work.
Signed-off-by: John Crispin blo...@openwrt.org
---
Changes in V2
* devm_ioremap_resource() return code was not handled properly
.../devicetree/bindings/gpio/gpio
and CONFIG_RALINK_RT...X to their SOC_* equivalents queued
for inclusion in v3.9-rcX. Is that correct?
Yes, that should be everything. John Crispin, anything missing from that?
Jonas
Hi,
I will look into this later this week.
John
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On 05/02/13 15:46, Linus Walleij wrote:
On Fri, Feb 1, 2013 at 1:04 PM, John Crispinblo...@openwrt.org wrote:
While converting the boards inside OpenWrt to OF I noticed that the we are
missing a pinconf parameter to set a pin to output.
Signed-off-by: John Crispinblo...@openwrt.org
OK, I
On 05/02/13 15:59, Linus Walleij wrote:
Can I just move all these fixes over to the devel
branch?
Hi,
I don't consider any of this as rc material.
sorry I should have put that in a cover letter.
John
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While converting all the boards supported by OpenWrt to OF I noticed that this
feature is missing. Adding it makes the devicetrees more readable.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-lantiq.c | 54 --
drivers/pinctrl
While converting the boards inside OpenWrt to OF I noticed that the we are
missing a pinconf parameter to set a pin to output.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-lantiq.h |1 +
drivers/pinctrl/pinctrl-xway.c | 14 ++
2 files changed, 15
The Falcon driver only defined the pinconf parameters but did not pass them
properly to the underlying api.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-falcon.c |2 ++
1 file changed, 2 insertions(+)
diff
The current code only has a stub for falcon_pinconf_dbg_show. This patch adds
proper functionality.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-falcon.c | 31 +++
1 file changed, 31
When setting the OpenDrain bit we should really honour the argument passed
inside the devicetree.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-xway.c |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers
The clock needs to be activated for the check to work. In order to be compatible
with future silicon make sure that at least 1 pin is available before probing
the pad controller.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers
On the Falcon SoC the bootleds are located on pins 9-14.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-falcon.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl
The mapping logic inside ltq_pmx_gpio_request_enable() was broken. This only
effected Falcon SoC.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-lantiq.c |2 +-
1 file changed, 1 insertion(+), 1 deletion
The template falcon.dtsi lists all 6 pad controllers that can be loaded. Only
probe those that have status = okay; inside the dts file.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-falcon.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pinctrl
The logic of the OD bit was inverted when calling the pinconf get methode.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-xway.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
The XWAY pinctrl driver invalidly uses the port and not the pin number to work
out the registeres and bits to be set for the opendrain and pullup/down
resistors.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-xway.c | 28 ++--
1 file changed
On 25/01/13 01:15, 陈华才 wrote:
ok, I'll prepare v9 of this seris in these days.
Please dont send v9
read my mail and compile / runtime test the tree please
only patch 3 needs to be reworked and an update for the MIPS: Loongson
3: Add HT-linked PCI support. needs to e made
John
Hi,
ok, i dropped the series for now from my tree
John
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Please read the FAQ at
Huacai Chen(13):
MIPS: Loongson: Add basic Loongson-3 definition.
MIPS: Loongson: Add basic Loongson-3 CPU support.
MIPS: Loongson: Introduce and use cpu_has_coherent_cache feature.
MIPS: Loongson 3: Add Lemote-3A machtypes definition.
MIPS: Loongson: Add UEFI-like firmware interface
On 13/09/12 01:15, richard -rw- weinberger wrote:
On Thu, Sep 13, 2012 at 12:50 AM, Tracey Denttdent48...@gmail.com wrote:
Makefile.rej should not be there. That was introduced
in commit 3fa68afc3d774bab1e91cbb3a3cdd1e36068ee95 .
Linus' tree does not contain such a commit id.
Hi,
my bad
On 28/07/12 01:23, Linus Walleij wrote:
On Tue, Jul 24, 2012 at 8:50 AM, John Crispin blo...@openwrt.org wrote:
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.
Signed-off-by: John Crispin blo...@openwrt.org
Signed-off-by: Thomas Langer
Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
up to 32 pads. The GPIO blocks have a per pin IRQs.
Signed-off-by: John Crispin blo...@openwrt.org
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Cc: linux-kernel@vger.kernel.org
---
Changes in V2
* fix typo
On 23/08/12 04:16, David Miller wrote:
From: David Daney ddaney.c...@gmail.com
Date: Tue, 21 Aug 2012 11:45:04 -0700
From: David Daney david.da...@cavium.com
Recent additions to the OCTEON SoC family have included enhancements
to the MIX (octeon_mgmt) Ethernet hardware. These include:
o
driver that was
located in the arch/ folder.
Signed-off-by: John Crispin blo...@openwrt.org
Acked-by: Linus Walleij linus.wall...@linaro.org
Cc: devicetree-disc...@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
---
Previously ack'ed in V2
-- http://www.linux-mips.org/archives/linux-mips/2012-05
Signed-off-by: John Crispin blo...@openwrt.org
Cc: Linus Walleij linus.wall...@linaro.org
Cc: devicetree-disc...@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
---
.../bindings/pinctrl/lantiq,xway-pinumx.txt| 97
1 files changed, 97 insertions(+), 0 deletions
Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
up to 32 pads. The GPIO blocks have a per pin IRQs.
Signed-off-by: John Crispin blo...@openwrt.org
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Cc: linux-kernel@vger.kernel.org
---
arch/mips/include/asm/mach
Signed-off-by: John Crispin blo...@openwrt.org
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: devicetree-disc...@lists.ozlabs.org
Cc: linux-kernel@vger.kernel.org
---
.../bindings/pinctrl/lantiq,falcon-pinumx.txt | 83
-by: John Crispin blo...@openwrt.org
Cc: linux-kernel@vger.kernel.org
---
drivers/gpio/gpio-stp-xway.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
index e35096b..8bead0b 100644
--- a/drivers/gpio/gpio-stp-xway.c
Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
of up to 32 pins.
Signed-off-by: John Crispin blo...@openwrt.org
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Cc: Linus Walleij linus.wall...@linaro.org
Cc: devicetree-disc...@lists.ozlabs.org
Cc: linux-kernel
On 24/07/12 10:09, Langer Thomas (LQDE RD ST PON SW) wrote:
Hello John,
John Crispin wrote on 2012-07-24:
Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5
banks of up to 32 pads. The GPIO blocks have a per pin IRQs.
Signed-off-by: John Crispin blo...@openwrt.org
Signed
Add driver for GPIO blocks found on Lantiq FALCON SoC. The SoC has 5 banks of
up to 32 pads. The GPIO blocks have a per pin IRQs.
Signed-off-by: John Crispin blo...@openwrt.org
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Cc: linux-kernel@vger.kernel.org
---
Changes in V2
* fix typo
On 16/08/13 15:16, Linus Walleij wrote:
I guess you will merge both patches through the MIPS arch
tree?
Hi Linus,
sure, we can take them via the MIPS tree
John
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On 17/09/13 01:09, Rob Herring wrote:
From: Rob Herringrob.herr...@calxeda.com
Convert mips to use the common of_flat_dt_get_machine_name function.
Signed-off-by: Rob Herringrob.herr...@calxeda.com
Cc: Ralf Baechler...@linux-mips.org
Cc: linux-m...@linux-mips.org
---
Acked-by: John Crispin
---
Acked-by: John Crispin blo...@openwrt.org
Thanks for this series ...
arch/mips/include/asm/prom.h | 3 ---
arch/mips/kernel/prom.c | 39 +++
2 files changed, 3 insertions(+), 39 deletions(-)
diff --git a/arch/mips/include/asm/prom.h b/arch/mips
Hi Wolfgang,
should we take 1/7 and 6/7 via the mips tree ?
John
On 14/01/2014 12:58, Wolfram Sang wrote:
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sang w...@the-dreams.de
Acked-by: John Crispin blo
On 16/05/13 13:15, Wolfram Sang wrote:
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sangw...@the-dreams.de
Acked-by: John Crispin blo...@openwrt.org
---
arch/mips/lantiq/xway/gptu.c |4
1 file
On 17/05/13 08:21, Libo Chen wrote:
when gptu_r32 fail, we should put clk before return
Signed-off-by: Libo Chenlibo.c...@huawei.com
Acked-by: John Crispin blo...@openwrt.org
---
arch/mips/lantiq/xway/gptu.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git
On 10/05/13 10:17, Wolfram Sang wrote:
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sangw...@the-dreams.de
Acked-by: John Crispin blo...@openwrt.org
---
arch/mips/lantiq/xway/gptu.c |7 +--
1 file
On 14/05/13 17:00, Laurent Pinchart wrote:
When creating mappings from DT both pin config and group config mappings
are allocated. Free them both when destroying the mappings.
Signed-off-by: Laurent Pinchartlaurent.pinchart+rene...@ideasonboard.com
Acked-by: John Crispin blo...@openwrt.org
On 23/07/13 20:01, Wolfram Sang wrote:
devm_ioremap_resource does sanity checks on the given resource. No need to
duplicate this in the driver.
Signed-off-by: Wolfram Sangw...@the-dreams.de
Acked-by: John Crispin blo...@openwrt.org
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that there is a whole series of commits in today's mips tree
that were committed by John Crispin but have no Signed-off-by from him ...
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From: Thomas Langer thomas.lan...@lantiq.com
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Acked-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-falcon.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-falcon.c b
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-xway.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index e92132c..86c8cf8 100644
--- a/drivers
From: Thomas Langer thomas.lan...@lantiq.com
The pps pin definition is missing in the current code.
Signed-off-by: Thomas Langer thomas.lan...@lantiq.com
Acked-by: John Crispin blo...@openwrt.org
---
Sorry i just noticed that i sent the 2 wrong files yesterday
drivers/pinctrl/pinctrl-falcon.c
We found out how to set the gphy led pinmuxing.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/pinctrl-xway.c | 30 --
1 file changed, 24 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
Drivers need to protect their reset api calls with #ifdef to avoid compile
errors. This patch adds dummy wrappers in the same way that linux/of.h does
it. This results in the nasty ifdefs no longer being needed.
Cc: linux-kernel@vger.kernel.org
Cc: Philipp Zabel p.za...@pengutronix.de
Cc: Gabor
-m...@linux-mips.org Cc: devicet...@vger.kernel.org Cc: John
Crispin blo...@openwrt.org Cc: Mark Rutland
mark.rutl...@arm.com
Acked-by: John Crispin blo...@openwrt.org?
Thanks for the cleanup
--- arch/mips/lantiq/dts/easy50712.dts|1 +
arch/mips/ralink/dts/mt7620a_eval.dts
Hi Eubong,
one small question inline ...
On 22/10/2014 08:39, Eunbong Song wrote:
Currently, arch_trigger_all_cpu_backtrace() is defined in only x86
and sparc which has nmi interrupt. But in case of softlockup not a
hardlockup, it could be possible to dump backtrace of all cpus. and
this
On 22/10/2014 08:54, Eunbong Song wrote:
Hi Eubong,
one small question inline ...
+void arch_trigger_all_cpu_backtrace(bool); +#define
arch_trigger_all_cpu_backtrace arch_trigger_all_cpu_backtrace
What is the purpose of this define ? is this maybe a leftover from
some
Hi Andrew,
On 30/08/2014 00:14, Andrew Bresticker wrote:
Based on 3.17-rc2 and boot tested on Danube (+ out of tree patches) and
Malta.
Lantiq makes a mips soc called danube. is this the same family or is
this just a name collision between 2 chip vendors ?
John
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Hi,
for the lantiq/ralink part ...
Acked-by: John Crispin blo...@openwrt.org
now we just need to merge jonas's appended DTB patch and I can finally
drop the ugly hack i am currently using inside openwrt.
Thanks,
John
On 15/09/2014 19:53, Andrew Bresticker wrote:
To be consistent
Before we had a pinctrl driver we used a custom OF api. This patch converts the
soc specific pinmux data to a new set of structs. We also add some new pinmux
setings.
Signed-off-by: John Crispin blo...@openwrt.org
---
arch/mips/include/asm/mach-ralink/mt7620.h | 41 +--
arch/mips/include
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each
pin individually, these socs have mux groups that when set will effect 1-N pins.
Pin groups have a 2, 4 or 8 different muxes.
Signed-off-by: John Crispin blo...@openwrt.org
---
drivers/pinctrl/Kconfig |5
Signed-off-by: John Crispin blo...@openwrt.org
---
arch/mips/Kconfig |2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 574c430..2d255e8 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -451,6 +451,8 @@ config RALINK
select
Signed-off-by: John Crispin blo...@openwrt.org
---
.../bindings/pinctrl/ralink,rt2880-pinmux.txt | 74
1 file changed, 74 insertions(+)
create mode 100644
Documentation/devicetree/bindings/pinctrl/ralink,rt2880-pinmux.txt
diff --git a/Documentation/devicetree
This series adds a pinctrl driver for ralink SoC. as it touches both arch and
pinctrl files i would prefer to have this go via the mips tree with the other
ralink pathes that i have sent.
John Crispin (4):
MIPS: ralink: cleanup the soc specific pinmux data
pinctrl: ralink: add a pinctrl
-lyon.org
Signed-off-by: Evan Broder e...@ebroder.net
Reviewed-by: David Herrmann dh.herrm...@gmail.com
Tested-by: Pavel Machek pa...@ucw.cz
Acked-by: Peter Korsgaard jac...@sunsite.dk
Signed-off-by: John Crispin blo...@openwrt.org
I am not sure why my SoB was added. I originally sent
On 04/02/2015 11:13, Paul Bolle wrote:
messages. Since I haven't received replies on other, more serious
issues in over three months I assume John has disappeared.)
into thin air, *pooff*
Is SOC_MT7621 still being worked on?
yes we dropped the series as it collided with the gic rework that
On 04/02/2015 12:04, Paul Bolle wrote:
On Wed, 2015-02-04 at 11:19 +0100, John Crispin wrote:
On 04/02/2015 11:13, Paul Bolle wrote:
Is SOC_MT7621 still being worked on?
yes we dropped the series as it collided with the gic rework that
chromiun.org was working on. i hope to push it during
On 04/02/2015 14:59, Guenter Roeck wrote:
On 02/04/2015 04:22 AM, Paul Bolle wrote:
John Crispin schreef op wo 04-02-2015 om 12:10 [+0100]:
i think wim should just drop it and we leave it in openwrt with the
other 1/2 million patches that we have. i prefer to upstream the stuff
without
Hi
there is a cross dependency between the modules. xhci-mtk.ko requires
xhci.ko to be loaded. however this will look for xhci_mtk_add_ep_quirk()
which is part of xhci-mtk. the modules will build but are not run time
loadable.
John
On 08/07/2015 11:41, Chunfeng Yun wrote:
MTK xhci host
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets the power and host/device mode.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
.../devicetree/bindings/phy/ralink-usb-phy.txt | 17 ++
drivers/phy/K
Hi Paul,
--> http://www.linux-mips.org/archives/linux-mips/2015-09/msg00057.html
John
On 10/09/2015 20:03, Paul Burton wrote:
> Ralf: is there a reason you've only applied patch 1 of this series?
>
> v4.2 is broken because these didn't get in (despite being submitted well
> before the
Add a driver to setup the USB phy on Mediatek/Ralink SoCs.
The driver is trivial and only sets up power and host mode.
Signed-off-by: John Crispin <blo...@openwrt.org>
---
Changes in V2
* remove refcounting
* drop empty functions
* dont use static globals
* use explicit compatible s
During stress testing, after reducing the threshold value, we have seen
TX timeouts that were caused by the watchdog_timeo value being too low.
Increase the value to 5 * HZ which is a value commonly used by many other
drivers.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drive
The lookup of the tx_buffer in the error path inside mtk_tx_map() uses the
wrong descriptor pointer. This looks like a copy & paste error. Change the
code to use the correct pointer.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2
The current code only disables those IRQs that we will later use. To
ensure that we have a predefined state, we really want to disable all IRQs.
Change the code to disable all IRQs to achieve this.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth
There are two places inside mtk_poll_rx where rx_dropped is not being
incremented properly. Fix this by adding the missing code to increment
the counter.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2 ++
1 file changed, 2 inse
The QDMA engine can fail to update the register pointing to the next TX
descriptor if this bit does not get set in the QDMA configuration register.
Not setting this bit can result in invalid values inside the TX rings
registers which will causes TX stalls.
Signed-off-by: John Crispin &l
housekeeping again. There is no rush in enqueuing the next packet, it
needs to wait for all the others in the queue to be dispatched first
anyway.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |7 ++-
1 file changed, 2 insertions
The current code unconditionally wakes up the queue at the end of each
tx_poll action. Change the code to only wake up the queues if any of
them have actually been stopped before.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c
The TX ring setup has an off by one error causing it to not utilise all
descriptors. This has the side effect that we need to reset the next
pointer at runtime to make it work. Fix the off by one and remove the
code fixing the ring at runtime.
Signed-off-by: John Crispin <j...@phrozen.
On 06/06/2016 14:21, Andrew Lunn wrote:
>> Hi Andrew,
>>
>> it is waiting for the watchdog to trigger :-) TBH the 1s seems to be too
>> short to for the dma ring length to be flushed and i had to pick some
>> value and 5 is used most places.
>>
>> it really depends on the amount of packets in
The code fails to check if the scratch memory was properly allocated. Add
this check and return with an error if the allocation failed.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/d
The TX ring setup has an off by one error causing it to not utilise all
descriptors. This has the side effect that we need to reset the next
pointer at runtime to make it work. Fix the off by one and remove the
code fixing the ring at runtime.
Signed-off-by: John Crispin <j...@phrozen.
The lookup of the tx_buffer in the error path inside mtk_tx_map() uses the
wrong descriptor pointer. This looks like a copy & paste error. Change the
code to use the correct pointer.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2
During stress testing, after reducing the threshold value, we have seen
TX timeouts that were caused by the watchdog_timeo value being too low.
Increase the value to 5 * HZ which is a value commonly used by many other
drivers.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drive
housekeeping again. There is no rush in enqueuing the next packet, it
needs to wait for all the others in the queue to be dispatched first
anyway.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |7 ++-
1 file changed, 2 insertions
.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index 93af4e3..8b289e1 100644
--- a/d
Scratch memory gets allocated in mtk_init_fq_dma() but the corresponding
code to free it is missing inside mtk_dma_free() causing a memory leak.
With this patch applied, we can run ifconfig up/down several thousand
times without any problems.
Signed-off-by: John Crispin <j...@phrozen.
The QDMA engine can fail to update the register pointing to the next TX
descriptor if this bit does not get set in the QDMA configuration register.
Not setting this bit can result in invalid values inside the TX rings
registers which will causes TX stalls.
Signed-off-by: John Crispin &l
The current code unconditionally wakes up the queue at the end of each
tx_poll action. Change the code to only wake up the queues if any of
them have actually been stopped before.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c
The current code only disables those IRQs that we will later use. To
ensure that we have a predefined state, we really want to disable all IRQs.
Change the code to disable all IRQs to achieve this.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth
On 10/06/2016 13:27, John Crispin wrote:
> This series contains various small fixes that we stumbled across while
> doing thorough testing and code level reviewing of the driver. The only
> patch that sticks out is the first one, which addresses a DQL related
> issue. The rest ar
the list until a better solution is found
John Crispin (11):
net: mediatek: add missing return code check
net: mediatek: fix missing free of scratch memory
net: mediatek: invalid buffer lookup in mtk_tx_map()
net: mediatek: dropped rx packets are not being counted properly
net: mediatek: add
On 10/06/2016 19:46, David Miller wrote:
> From: John Crispin <j...@phrozen.org>
> Date: Fri, 10 Jun 2016 13:30:15 +0200
>
>>
>>
>> On 10/06/2016 13:27, John Crispin wrote:
>>> This series contains various small fixes that we stumbled across while
driver needs to be adapted to handle all 3 rgmii-*id modes
in the same way as normal rgmii when setting up the MAC.
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed,
Lunn <and...@lunn.ch>
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index b0652f6..23
The current code will not setup the PHYs advertisement features correctly.
Fix this and properly advertise Gigabit features and properly handle
asymmetric pause frames.
Signed-off-by: Sean Wang <keyha...@gmail.com>
Signed-off-by: John Crispin <j...@phrozen.org>
---
Changes
The driver currently uses kfree() to clear the mii_bus. This is not the
correct way to clear the memory and mdiobus_free() should be used instead.
This patch fixes the two instances where this happens in the driver.
Reviewed-by: Andrew Lunn <and...@lunn.ch>
Signed-off-by: John Cris
The current driver did not handle the RGMII delay modes and asymmetric flow
control properly. The mii_bus is not freed properly. Also add support for
fixed-phy allowing the driver to work on SoCs that have an internal gigabit
switch.
John Crispin (4):
net-next: mediatek: use mdiobus_free
There are two places inside mtk_poll_rx where rx_dropped is not being
incremented properly. Fix this by adding the missing code to increment
the counter.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |2 ++
1 file changed, 2 inse
-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c |4
1 file changed, 4 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
index ebfca7d..b3032f4 100644
--- a/drivers/net/ethernet/me
handler.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 156 +--
drivers/net/ethernet/mediatek/mtk_eth_soc.h | 15 ++-
2 files changed, 111 insertions(+), 60 deletions(-)
diff --git a/drivers/net/ethernet/me
allows us to use different IRQs for TX and RX. By doing so we can
use affinity to let the SoC handle the IRQs on different cores.
John Crispin (4):
net-next: mediatek: remove superfluous register reads
net-next: mediatek: don't use intermediate variables to store IRQ
masks
net-next
remove the intermediate variables.
Signed-off-by: John Crispin <j...@phrozen.org>
---
drivers/net/ethernet/mediatek/mtk_eth_soc.c | 22 ++
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
b/drivers/net/et
The code that enables and disables IRQs is missing proper locking. After
adding the IRQ grouping patch and routing the RX and TX IRQs to different
cores we experienced IRQ stalls. Fix this by adding proper locking.
We use a dedicated lock to reduce the latency if the IRQ code.
Signed-off-by: John
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