Re: [PATCH] drm/msm/dsi: support CPHY mode for 7nm pll/phy
On 3/5/21 5:45 PM, Dmitry Baryshkov wrote:
On 15/02/2021 19:27, Jonathan Marek wrote:
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
Other that few comments bellow:
Reviewed-by: Dmitry Baryshkov
---
.../devicetree/bindings/display/msm/dsi.txt | 1 +
drivers/gpu/drm/msm/dsi/dsi.c | 12 +--
drivers/gpu/drm/msm/dsi/dsi.h | 6 +-
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 34 +--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 49 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 89 ++-
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 4 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 5 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 71 +--
11 files changed, 210 insertions(+), 66 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
b/Documentation/devicetree/bindings/display/msm/dsi.txt
index b9a64d3ff184..7ffc86a9816b 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -124,6 +124,7 @@ Required properties:
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the
LDO mode PHY
regulator is wanted.
+- qcom,dsi-phy-cphy-mode: Boolean value indicating if CPHY mode is
wanted.
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time
for command mode
panels in microseconds. Driver uses this number
to adjust
the clock rate according to the expected
transfer time.
This should go in a separate patch, shan't it?
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c
b/drivers/gpu/drm/msm/dsi/dsi.c
index 627048851d99..68d8547f7264 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -13,7 +13,7 @@ struct drm_encoder *msm_dsi_get_encoder(struct
msm_dsi *msm_dsi)
return msm_dsi->encoder;
}
-static int dsi_get_phy(struct msm_dsi *msm_dsi)
+static int dsi_get_phy(struct msm_dsi *msm_dsi, bool *cphy_mode)
I see no need to pass the 'cphy_mode' through the bool pointer and back
to msm_dsi_host_init. What about just putting it into struct msm_dsi?
Because it doesn't need to be stored in msm_dsi (need it in msm_dsi_host
which doesn't have access to msm_dsi). But I suppose it doesn't hurt to
also have it in msm_dsi and make things a bit cleaner.
{
struct platform_device *pdev = msm_dsi->pdev;
struct platform_device *phy_pdev;
@@ -29,6 +29,7 @@ static int dsi_get_phy(struct msm_dsi *msm_dsi)
if (phy_pdev)
msm_dsi->phy = platform_get_drvdata(phy_pdev);
+ *cphy_mode = of_property_read_bool(phy_node,
"qcom,dsi-phy-cphy-mode");
of_node_put(phy_node);
if (!phy_pdev || !msm_dsi->phy) {
@@ -65,6 +66,7 @@ static void dsi_destroy(struct msm_dsi *msm_dsi)
static struct msm_dsi *dsi_init(struct platform_device *pdev)
{
struct msm_dsi *msm_dsi;
+ bool cphy_mode;
int ret;
if (!pdev)
@@ -79,13 +81,13 @@ static struct msm_dsi *dsi_init(struct
platform_device *pdev)
msm_dsi->pdev = pdev;
platform_set_drvdata(pdev, msm_dsi);
- /* Init dsi host */
- ret = msm_dsi_host_init(msm_dsi);
+ /* GET dsi PHY */
+ ret = dsi_get_phy(msm_dsi, _mode);
if (ret)
goto destroy_dsi;
- /* GET dsi PHY */
- ret = dsi_get_phy(msm_dsi);
+ /* Init dsi host */
+ ret = msm_dsi_host_init(msm_dsi, cphy_mode);
if (ret)
goto destroy_dsi;
Re: [PATCH] drm/msm/dsi: support CPHY mode for 7nm pll/phy
On 3/5/21 4:48 PM, Rob Herring wrote: On Mon, Feb 15, 2021 at 11:27:44AM -0500, Jonathan Marek wrote: Add the required changes to support 7nm pll/phy in CPHY mode. This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable the CPHY mode. Signed-off-by: Jonathan Marek --- .../devicetree/bindings/display/msm/dsi.txt | 1 + drivers/gpu/drm/msm/dsi/dsi.c | 12 +-- drivers/gpu/drm/msm/dsi/dsi.h | 6 +- drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 + drivers/gpu/drm/msm/dsi/dsi_host.c| 34 +-- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 49 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 89 ++- drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 4 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 5 +- drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 71 +-- 11 files changed, 210 insertions(+), 66 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt b/Documentation/devicetree/bindings/display/msm/dsi.txt index b9a64d3ff184..7ffc86a9816b 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi.txt +++ b/Documentation/devicetree/bindings/display/msm/dsi.txt @@ -124,6 +124,7 @@ Required properties: Optional properties: - qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY regulator is wanted. +- qcom,dsi-phy-cphy-mode: Boolean value indicating if CPHY mode is wanted. This is board or SoC dependent? The latter should be implied by an SoC specific compatible. It is board specific, 7nm dsi phy can operate in either D-PHY or C-PHY mode.
[PATCH] ASoC: codecs: lpass-wsa-macro: fix RX MIX input controls
Attempting to use the RX MIX path at 48kHz plays at 96kHz, because these
controls are incorrectly toggling the first bit of the register, which
is part of the FS_RATE field.
Fix the problem by using the same method used by the "WSA RX_MIX EC0_MUX"
control, which is to use SND_SOC_NOPM as the register and use an enum in
the shift field instead.
Fixes: 2c4066e5d428 ("ASoC: codecs: lpass-wsa-macro: add dapm widgets and
route")
Signed-off-by: Jonathan Marek
---
sound/soc/codecs/lpass-wsa-macro.c | 20 +++-
1 file changed, 11 insertions(+), 9 deletions(-)
diff --git a/sound/soc/codecs/lpass-wsa-macro.c
b/sound/soc/codecs/lpass-wsa-macro.c
index f399f4dff5511..bd2561f9fb9fa 100644
--- a/sound/soc/codecs/lpass-wsa-macro.c
+++ b/sound/soc/codecs/lpass-wsa-macro.c
@@ -1211,14 +1211,16 @@ static int wsa_macro_enable_mix_path(struct
snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_component *component =
snd_soc_dapm_to_component(w->dapm);
- u16 gain_reg;
+ u16 path_reg, gain_reg;
int val;
- switch (w->reg) {
- case CDC_WSA_RX0_RX_PATH_MIX_CTL:
+ switch (w->shift) {
+ case WSA_MACRO_RX_MIX0:
+ path_reg = CDC_WSA_RX0_RX_PATH_MIX_CTL;
gain_reg = CDC_WSA_RX0_RX_VOL_MIX_CTL;
break;
- case CDC_WSA_RX1_RX_PATH_MIX_CTL:
+ case WSA_MACRO_RX_MIX1:
+ path_reg = CDC_WSA_RX1_RX_PATH_MIX_CTL;
gain_reg = CDC_WSA_RX1_RX_VOL_MIX_CTL;
break;
default:
@@ -1231,7 +1233,7 @@ static int wsa_macro_enable_mix_path(struct
snd_soc_dapm_widget *w,
snd_soc_component_write(component, gain_reg, val);
break;
case SND_SOC_DAPM_POST_PMD:
- snd_soc_component_update_bits(component, w->reg,
+ snd_soc_component_update_bits(component, path_reg,
CDC_WSA_RX_PATH_MIX_CLK_EN_MASK,
CDC_WSA_RX_PATH_MIX_CLK_DISABLE);
break;
@@ -2068,14 +2070,14 @@ static const struct snd_soc_dapm_widget
wsa_macro_dapm_widgets[] = {
SND_SOC_DAPM_MUX("WSA_RX0 INP0", SND_SOC_NOPM, 0, 0,
_prim_inp0_mux),
SND_SOC_DAPM_MUX("WSA_RX0 INP1", SND_SOC_NOPM, 0, 0,
_prim_inp1_mux),
SND_SOC_DAPM_MUX("WSA_RX0 INP2", SND_SOC_NOPM, 0, 0,
_prim_inp2_mux),
- SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", CDC_WSA_RX0_RX_PATH_MIX_CTL,
- 0, 0, _mix_mux, wsa_macro_enable_mix_path,
+ SND_SOC_DAPM_MUX_E("WSA_RX0 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX0,
+ 0, _mix_mux, wsa_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("WSA_RX1 INP0", SND_SOC_NOPM, 0, 0,
_prim_inp0_mux),
SND_SOC_DAPM_MUX("WSA_RX1 INP1", SND_SOC_NOPM, 0, 0,
_prim_inp1_mux),
SND_SOC_DAPM_MUX("WSA_RX1 INP2", SND_SOC_NOPM, 0, 0,
_prim_inp2_mux),
- SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", CDC_WSA_RX1_RX_PATH_MIX_CTL,
- 0, 0, _mix_mux, wsa_macro_enable_mix_path,
+ SND_SOC_DAPM_MUX_E("WSA_RX1 MIX INP", SND_SOC_NOPM, WSA_MACRO_RX_MIX1,
+ 0, _mix_mux, wsa_macro_enable_mix_path,
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MIXER_E("WSA_RX INT0 MIX", SND_SOC_NOPM, 0, 0, NULL, 0,
--
2.26.1
Re: [PATCH] pinctrl: qcom: lpass lpi: use default pullup/strength values
On 3/4/21 7:05 PM, Bjorn Andersson wrote:
On Thu 04 Mar 13:48 CST 2021, Jonathan Marek wrote:
If these fields are not set in dts, the driver will use these variables
uninitialized to set the fields. Not only will it set garbage values for
these fields, but it can overflow into other fields and break those.
In the current sm8250 dts, the dmic01 entries do not have a pullup setting,
and might not work without this change.
Perhaps you didn't see it, but Dan reported this a few days back. So
unless you object I would suggest that we include:
I did not see it. But feel free to add tags.
Reported-by: kernel test robot
Reported-by: Dan Carpenter
Reviewed-by: Bjorn Andersson
Regards,
Bjorn
Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Signed-off-by: Jonathan Marek
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 369ee20a7ea95..2f19ab4db7208 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -392,7 +392,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *configs, unsigned int nconfs)
{
struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
- unsigned int param, arg, pullup, strength;
+ unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
bool value, output_enabled = false;
const struct lpi_pingroup *g;
unsigned long sval;
--
2.26.1
[PATCH] ASoC: codecs: lpass-va-macro: mute/unmute all active decimators
An interface can have multiple decimators enabled, so loop over all active
decimators. Otherwise only one channel will be unmuted, and other channels
will be zero. This fixes recording from dual DMIC as a single two channel
stream.
Also remove the now unused "active_decimator" field.
Fixes: 908e6b1df26e ("ASoC: codecs: lpass-va-macro: Add support to VA Macro")
Signed-off-by: Jonathan Marek
---
sound/soc/codecs/lpass-va-macro.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git a/sound/soc/codecs/lpass-va-macro.c
b/sound/soc/codecs/lpass-va-macro.c
index 91e6890d6efcb..3d6976a3d9e42 100644
--- a/sound/soc/codecs/lpass-va-macro.c
+++ b/sound/soc/codecs/lpass-va-macro.c
@@ -189,7 +189,6 @@ struct va_macro {
struct device *dev;
unsigned long active_ch_mask[VA_MACRO_MAX_DAIS];
unsigned long active_ch_cnt[VA_MACRO_MAX_DAIS];
- unsigned long active_decimator[VA_MACRO_MAX_DAIS];
u16 dmic_clk_div;
int dec_mode[VA_MACRO_NUM_DECIMATORS];
@@ -549,11 +548,9 @@ static int va_macro_tx_mixer_put(struct snd_kcontrol
*kcontrol,
if (enable) {
set_bit(dec_id, >active_ch_mask[dai_id]);
va->active_ch_cnt[dai_id]++;
- va->active_decimator[dai_id] = dec_id;
} else {
clear_bit(dec_id, >active_ch_mask[dai_id]);
va->active_ch_cnt[dai_id]--;
- va->active_decimator[dai_id] = -1;
}
snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update);
@@ -880,18 +877,19 @@ static int va_macro_digital_mute(struct snd_soc_dai *dai,
int mute, int stream)
struct va_macro *va = snd_soc_component_get_drvdata(component);
u16 tx_vol_ctl_reg, decimator;
- decimator = va->active_decimator[dai->id];
-
- tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
- VA_MACRO_TX_PATH_OFFSET * decimator;
- if (mute)
- snd_soc_component_update_bits(component, tx_vol_ctl_reg,
- CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
- CDC_VA_TX_PATH_PGA_MUTE_EN);
- else
- snd_soc_component_update_bits(component, tx_vol_ctl_reg,
- CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
- CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
+ for_each_set_bit(decimator, >active_ch_mask[dai->id],
+VA_MACRO_DEC_MAX) {
+ tx_vol_ctl_reg = CDC_VA_TX0_TX_PATH_CTL +
+ VA_MACRO_TX_PATH_OFFSET * decimator;
+ if (mute)
+ snd_soc_component_update_bits(component, tx_vol_ctl_reg,
+ CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
+ CDC_VA_TX_PATH_PGA_MUTE_EN);
+ else
+ snd_soc_component_update_bits(component, tx_vol_ctl_reg,
+ CDC_VA_TX_PATH_PGA_MUTE_EN_MASK,
+ CDC_VA_TX_PATH_PGA_MUTE_DISABLE);
+ }
return 0;
}
--
2.26.1
[PATCH] pinctrl: qcom: lpass lpi: use default pullup/strength values
If these fields are not set in dts, the driver will use these variables
uninitialized to set the fields. Not only will it set garbage values for
these fields, but it can overflow into other fields and break those.
In the current sm8250 dts, the dmic01 entries do not have a pullup setting,
and might not work without this change.
Fixes: 6e261d1090d6 ("pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver")
Signed-off-by: Jonathan Marek
---
drivers/pinctrl/qcom/pinctrl-lpass-lpi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
index 369ee20a7ea95..2f19ab4db7208 100644
--- a/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
+++ b/drivers/pinctrl/qcom/pinctrl-lpass-lpi.c
@@ -392,7 +392,7 @@ static int lpi_config_set(struct pinctrl_dev *pctldev,
unsigned int group,
unsigned long *configs, unsigned int nconfs)
{
struct lpi_pinctrl *pctrl = dev_get_drvdata(pctldev->dev);
- unsigned int param, arg, pullup, strength;
+ unsigned int param, arg, pullup = LPI_GPIO_BIAS_DISABLE, strength = 2;
bool value, output_enabled = false;
const struct lpi_pingroup *g;
unsigned long sval;
--
2.26.1
Re: [PATCH 3/3] fastrpc: remove redundant fastrpc_map_create() call
On 2/22/21 7:37 AM, Srinivas Kandagatla wrote:
On 18/02/2021 03:20, Jonathan Marek wrote:
fastrpc_internal_invoke() will call fastrpc_map_create, so there is no
point in having it called here. This does change the behavior somewhat as
fastrpc_internal_invoke() will release the map afterwards, but that's
what
we want to happen in this case.
This will crash the DSP as you will be freeing the init process memory
while it is actively using it!
The shell/init process is created as part of user process and it should
be valid until the user process is valid! We can not free it when the
invoke is finished/acked as we normally do for other invoke context!
In some firmwares the shell process is statically built into the DSP
firmware which might work! But other normal cases are totally broken by
this patch!
--srini
I am not using the static guest process, I am using the
FASTRPC_IOCTL_INIT_CREATE to load a fastrpc shell process. It doesn't crash.
AFAIK the DSP does not need the process memory after the process
creation - this would allow userspace to modify the executable after the
DSP verifies the hash/signature. So the DSP absolutely needs to make a
copy of it before verifying it (otherwise this would be a pretty serious
and obvious security flaw in qcom's fastrpc system. but I wouldn't be
surprised!).
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 170352b43ab6..ccad9f5f5e2f 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -1013,7 +1013,6 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
struct fastrpc_init_create init;
struct fastrpc_invoke_args *args;
struct fastrpc_phy_page pages[1];
- struct fastrpc_map *map = NULL;
struct fastrpc_buf *imem = NULL;
int memlen;
int err;
@@ -1049,18 +1048,12 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
inbuf.siglen = init.siglen;
fl->pd = USER_PD;
- if (init.filelen && init.filefd) {
- err = fastrpc_map_create(fl, init.filefd, init.filelen, );
- if (err)
- goto err;
- }
- > memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4),
1024 * 1024);
err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen,
);
if (err)
- goto err_alloc;
+ goto err;
fl->init_mem = imem;
args[0].ptr = (u64)(uintptr_t)
@@ -1106,9 +1099,6 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
err_invoke:
fl->init_mem = NULL;
fastrpc_buf_free(imem);
-err_alloc:
- if (map)
- fastrpc_map_put(map);
err:
kfree(args);
[PATCH 3/3] fastrpc: remove redundant fastrpc_map_create() call
fastrpc_internal_invoke() will call fastrpc_map_create, so there is no
point in having it called here. This does change the behavior somewhat as
fastrpc_internal_invoke() will release the map afterwards, but that's what
we want to happen in this case.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 12 +---
1 file changed, 1 insertion(+), 11 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 170352b43ab6..ccad9f5f5e2f 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -1013,7 +1013,6 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
struct fastrpc_init_create init;
struct fastrpc_invoke_args *args;
struct fastrpc_phy_page pages[1];
- struct fastrpc_map *map = NULL;
struct fastrpc_buf *imem = NULL;
int memlen;
int err;
@@ -1049,18 +1048,12 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
inbuf.siglen = init.siglen;
fl->pd = USER_PD;
- if (init.filelen && init.filefd) {
- err = fastrpc_map_create(fl, init.filefd, init.filelen, );
- if (err)
- goto err;
- }
-
memlen = ALIGN(max(INIT_FILELEN_MAX, (int)init.filelen * 4),
1024 * 1024);
err = fastrpc_buf_alloc(fl, fl->sctx->dev, memlen,
);
if (err)
- goto err_alloc;
+ goto err;
fl->init_mem = imem;
args[0].ptr = (u64)(uintptr_t)
@@ -1106,9 +1099,6 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
err_invoke:
fl->init_mem = NULL;
fastrpc_buf_free(imem);
-err_alloc:
- if (map)
- fastrpc_map_put(map);
err:
kfree(args);
--
2.26.1
[PATCH 2/3] fastrpc: move fl->maps list removal into fastrpc_free_map
This fixes the incredibly broken behavior of fastrpc_context_free(),
which calls fastrpc_map_put() but does not remove the map from the list
when it is free'd, causing use-after-free errors.
fl->lock needs to be held not just for list_del(), but also kref_put, to
avoid a race condition with fastrpc_map_find() logic.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 4fabea0c1551..170352b43ab6 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -245,19 +245,21 @@ static void fastrpc_free_map(struct kref *ref)
dma_buf_put(map->buf);
}
+ list_del(>node);
+
kfree(map);
}
static void fastrpc_map_put(struct fastrpc_map *map)
{
- if (map)
- kref_put(>refcount, fastrpc_free_map);
+ spin_lock(>fl->lock);
+ kref_put(>refcount, fastrpc_free_map);
+ spin_unlock(>fl->lock);
}
static void fastrpc_map_get(struct fastrpc_map *map)
{
- if (map)
- kref_get(>refcount);
+ kref_get(>refcount);
}
static int fastrpc_map_find(struct fastrpc_user *fl, int fd,
@@ -351,8 +353,10 @@ static void fastrpc_context_free(struct kref *ref)
ctx = container_of(ref, struct fastrpc_invoke_ctx, refcount);
cctx = ctx->cctx;
- for (i = 0; i < ctx->nscalars; i++)
- fastrpc_map_put(ctx->maps[i]);
+ for (i = 0; i < ctx->nscalars; i++) {
+ if (ctx->maps[i])
+ fastrpc_map_put(ctx->maps[i]);
+ }
if (ctx->buf)
fastrpc_buf_free(ctx->buf);
@@ -1103,12 +1107,8 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
fl->init_mem = NULL;
fastrpc_buf_free(imem);
err_alloc:
- if (map) {
- spin_lock(>lock);
- list_del(>node);
- spin_unlock(>lock);
+ if (map)
fastrpc_map_put(map);
- }
err:
kfree(args);
@@ -1185,10 +1185,9 @@ static int fastrpc_device_release(struct inode *inode,
struct file *file)
fastrpc_context_put(ctx);
}
- list_for_each_entry_safe(map, m, >maps, node) {
- list_del(>node);
+ list_for_each_entry_safe(map, m, >maps, node)
fastrpc_map_put(map);
- }
+ WARN_ON(!list_empty(>maps));
list_for_each_entry_safe(buf, b, >mmaps, node) {
list_del(>node);
--
2.26.1
[PATCH 0/3] fastrpc: fix dmabuf arguments
dmabuf arguments are completely broken, these patches make it possible to actually use dmabuf arguments (in particular, the second patch). Jonathan Marek (3): fastrpc: always use fl->lock and remove fl->mutex fastrpc: move fl->maps list removal into fastrpc_free_map fastrpc: remove redundant fastrpc_map_create() call drivers/misc/fastrpc.c | 48 ++ 1 file changed, 16 insertions(+), 32 deletions(-) -- 2.26.1
[PATCH 1/3] fastrpc: always use fl->lock and remove fl->mutex
Fix the broken behavior of having a separate mutex for locking at this
place, and use the same spinlock that is used to add/remove from the list.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index f12e909034ac..4fabea0c1551 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -230,8 +230,6 @@ struct fastrpc_user {
int pd;
/* Lock for lists */
spinlock_t lock;
- /* lock for allocations */
- struct mutex mutex;
};
static void fastrpc_free_map(struct kref *ref)
@@ -267,16 +265,16 @@ static int fastrpc_map_find(struct fastrpc_user *fl, int
fd,
{
struct fastrpc_map *map = NULL;
- mutex_lock(>mutex);
+ spin_lock(>lock);
list_for_each_entry(map, >maps, node) {
if (map->fd == fd) {
fastrpc_map_get(map);
*ppmap = map;
- mutex_unlock(>mutex);
+ spin_unlock(>lock);
return 0;
}
}
- mutex_unlock(>mutex);
+ spin_unlock(>lock);
return -ENOENT;
}
@@ -1200,7 +1198,6 @@ static int fastrpc_device_release(struct inode *inode,
struct file *file)
fastrpc_session_free(cctx, fl->sctx);
fastrpc_channel_ctx_put(cctx);
- mutex_destroy(>mutex);
kfree(fl);
file->private_data = NULL;
@@ -1222,7 +1219,6 @@ static int fastrpc_device_open(struct inode *inode,
struct file *filp)
filp->private_data = fl;
spin_lock_init(>lock);
- mutex_init(>mutex);
INIT_LIST_HEAD(>pending);
INIT_LIST_HEAD(>maps);
INIT_LIST_HEAD(>mmaps);
@@ -1233,7 +1229,6 @@ static int fastrpc_device_open(struct inode *inode,
struct file *filp)
fl->sctx = fastrpc_session_alloc(cctx);
if (!fl->sctx) {
dev_err(>rpdev->dev, "No session available\n");
- mutex_destroy(>mutex);
kfree(fl);
return -EBUSY;
--
2.26.1
Re: [PATCH] drm/msm/a6xx: fix for kernels without CONFIG_NVMEM
On 2/17/21 3:18 PM, Rob Clark wrote:
On Wed, Feb 17, 2021 at 11:08 AM Jordan Crouse wrote:
On Wed, Feb 17, 2021 at 07:14:16PM +0530, Akhil P Oommen wrote:
On 2/17/2021 8:36 AM, Rob Clark wrote:
On Tue, Feb 16, 2021 at 12:10 PM Jonathan Marek wrote:
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ba8e9d3cf0fe..7fe5d97606aa 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1356,10 +1356,10 @@ static int a6xx_set_supported_hw(struct device *dev,
struct a6xx_gpu *a6xx_gpu,
cell = nvmem_cell_get(dev, "speed_bin");
/*
-* -ENOENT means that the platform doesn't support speedbin which is
-* fine
+* -ENOENT means no speed bin in device tree,
+* -EOPNOTSUPP means kernel was built without CONFIG_NVMEM
very minor nit, it would be nice to at least preserve the gist of the
"which is fine" (ie. some variation of "this is an optional thing and
things won't catch fire without it" ;-))
(which is, I believe, is true, hopefully Akhil could confirm.. if not
we should have a harder dependency on CONFIG_NVMEM..)
IIRC, if the gpu opp table in the DT uses the 'opp-supported-hw' property,
we will see some error during boot up if we don't call
dev_pm_opp_set_supported_hw(). So calling "nvmem_cell_get(dev, "speed_bin")"
is a way to test this.
If there is no other harm, we can put a hard dependency on CONFIG_NVMEM.
I'm not sure if we want to go this far given the squishiness about module
dependencies. As far as I know we are the only driver that uses this seriously
on QCOM SoCs and this is only needed for certain targets. I don't know if we
want to force every target to build NVMEM and QFPROM on our behalf. But maybe
I'm just saying that because Kconfig dependencies tend to break my brain (and
then Arnd has to send a patch to fix it).
Hmm, good point.. looks like CONFIG_NVMEM itself doesn't have any
other dependencies, so I suppose it wouldn't be the end of the world
to select that.. but I guess we don't want to require QFPROM
I guess at the end of the day, what is the failure mode if you have a
speed-bin device, but your kernel config misses QFPROM (and possibly
NVMEM)? If the result is just not having the highest clk rate(s)
available, that isn't the end of the world. But if it makes things
not-work, that is sub-optimal. Generally, especially on ARM, kconfig
seems to be way harder than it should be to build a kernel that works,
if we could somehow not add to that problem (for both people with a6xx
and older gens) that would be nice ;-)
There is a "imply" kconfig option which solves exactly this problem.
(you would "imply NVMEM" instead of "select NVMEM". then it would be
possible to disable NVMEM but it would get enabled by default)
BR,
-R
Re: [PATCH] opp: fix dev_pm_opp_set_rate for different frequency at the same opp level
On 2/16/21 11:53 PM, Viresh Kumar wrote:
On 16-02-21, 15:10, Jonathan Marek wrote:
There is not "nothing to do" when the opp is the same. The frequency can
be different from opp->rate.
I am sorry but I am not sure what are you trying to fix here and what exactly is
broken here. Can you provide a usecase for your platform where this doesn't work
like it used to ?
The specific case is this opp table:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/qcom/sm8250.dtsi#n439
It does not define every possible clock frequency, it only defines the
rates at which a higher rpmhpd level must be used. Which is the intended
use of opp.
Your change broke this completely: the clock rate change can be silently
ignored because the opp level is the same. In particular it breaks
bluetooth for this platform.
Fixes: 81c4d8a3c414 ("opp: Keep track of currently programmed OPP")
Signed-off-by: Jonathan Marek
---
drivers/opp/core.c | 7 +--
drivers/opp/opp.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
[PATCH] drm/msm/a6xx: fix for kernels without CONFIG_NVMEM
Ignore nvmem_cell_get() EOPNOTSUPP error in the same way as a ENOENT error,
to fix the case where the kernel was compiled without CONFIG_NVMEM.
Fixes: fe7952c629da ("drm/msm: Add speed-bin support to a618 gpu")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index ba8e9d3cf0fe..7fe5d97606aa 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1356,10 +1356,10 @@ static int a6xx_set_supported_hw(struct device *dev,
struct a6xx_gpu *a6xx_gpu,
cell = nvmem_cell_get(dev, "speed_bin");
/*
-* -ENOENT means that the platform doesn't support speedbin which is
-* fine
+* -ENOENT means no speed bin in device tree,
+* -EOPNOTSUPP means kernel was built without CONFIG_NVMEM
*/
- if (PTR_ERR(cell) == -ENOENT)
+ if (PTR_ERR(cell) == -ENOENT || PTR_ERR(cell) == -EOPNOTSUPP)
return 0;
else if (IS_ERR(cell)) {
DRM_DEV_ERROR(dev,
--
2.26.1
[PATCH] opp: fix dev_pm_opp_set_rate for different frequency at the same opp level
There is not "nothing to do" when the opp is the same. The frequency can
be different from opp->rate.
Fixes: 81c4d8a3c414 ("opp: Keep track of currently programmed OPP")
Signed-off-by: Jonathan Marek
---
drivers/opp/core.c | 7 +--
drivers/opp/opp.h | 1 +
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/opp/core.c b/drivers/opp/core.c
index c3f3d9249cc5..f82cf72f433e 100644
--- a/drivers/opp/core.c
+++ b/drivers/opp/core.c
@@ -986,6 +986,7 @@ static int _set_opp(struct device *dev, struct opp_table
*opp_table,
struct dev_pm_opp *opp, unsigned long freq)
{
struct dev_pm_opp *old_opp;
+ unsigned long old_freq;
int scaling_down, ret;
if (unlikely(!opp))
@@ -996,15 +997,16 @@ static int _set_opp(struct device *dev, struct opp_table
*opp_table,
_find_current_opp(dev, opp_table);
old_opp = opp_table->current_opp;
+ old_freq = opp_table->current_freq;
/* Return early if nothing to do */
- if (opp_table->enabled && old_opp == opp) {
+ if (opp_table->enabled && old_opp == opp && old_freq == freq) {
dev_dbg(dev, "%s: OPPs are same, nothing to do\n", __func__);
return 0;
}
dev_dbg(dev, "%s: switching OPP: Freq %lu -> %lu Hz, Level %u -> %u, Bw
%u -> %u\n",
- __func__, old_opp->rate, freq, old_opp->level, opp->level,
+ __func__, old_freq, freq, old_opp->level, opp->level,
old_opp->bandwidth ? old_opp->bandwidth[0].peak : 0,
opp->bandwidth ? opp->bandwidth[0].peak : 0);
@@ -1061,6 +1063,7 @@ static int _set_opp(struct device *dev, struct opp_table
*opp_table,
/* Make sure current_opp doesn't get freed */
dev_pm_opp_get(opp);
opp_table->current_opp = opp;
+ opp_table->current_freq = freq;
return ret;
}
diff --git a/drivers/opp/opp.h b/drivers/opp/opp.h
index 9b9daf83b074..9f1d9c877380 100644
--- a/drivers/opp/opp.h
+++ b/drivers/opp/opp.h
@@ -186,6 +186,7 @@ struct opp_table {
enum opp_table_access shared_opp;
struct dev_pm_opp *current_opp;
struct dev_pm_opp *suspend_opp;
+ unsigned long current_freq;
struct mutex genpd_virt_dev_lock;
struct device **genpd_virt_devs;
--
2.26.1
Re: [PATCH v2 1/2] drm/msm: add compatibles for sm8150/sm8250 display
On 2/16/21 11:54 AM, Dmitry Baryshkov wrote:
On Mon, 15 Feb 2021 at 19:25, Jonathan Marek wrote:
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/msm_drv.c | 6 +++---
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 551ae26f60da..5763f43200a0 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
MDSS:
Required properties:
-- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
+- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sm8150-mdss",
"qcom,sm8250-mdss"
- reg: physical base address and length of contoller's registers.
- reg-names: register region names. The following region is required:
* "mdss"
@@ -41,7 +41,7 @@ Optional properties:
MDP:
Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sm8150-dpu",
"qcom,sm8250-dpu"
- reg: physical base address and length of controller's registers.
- reg-names : register region names. The following region is required:
* "mdp"
These two chunks should probably go to the separate patch 'dt-bindings:...'.
In this case I think its better to have this change in the same patch,
but maybe one of the Robs will disagree.
Also, could you please pinpoint the reason for adding more
compatibility strings, while they map to the same internal data?
I think we might want instead to use some generic name for the dpu
block, like "qcom,dpu" or "qcom,mdp-dpu" instead of specifying the
platform name.
sdm845 and sc7180 aren't using generic compatibles, this is just being
consistent with that.
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5a8e3e1fc48c..fff12a4c8bfc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1219,6 +1219,8 @@ static const struct dev_pm_ops dpu_pm_ops = {
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sdm845-dpu", },
{ .compatible = "qcom,sc7180-dpu", },
+ { .compatible = "qcom,sm8150-dpu", },
+ { .compatible = "qcom,sm8250-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 94525ac76d4e..928f13d4bfbc 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1185,9 +1185,7 @@ static int add_display_components(struct device *dev,
* Populate the children devices, find the MDP5/DPU node, and then add
* the interfaces to our components list.
*/
- if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
+ if (!of_device_is_compatible(dev->of_node, "qcom,mdp4")) {
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
DRM_DEV_ERROR(dev, "failed to populate children
devices\n");
@@ -1320,6 +1318,8 @@ static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.26.1
[PATCH] drm/msm/dsi: support CPHY mode for 7nm pll/phy
Add the required changes to support 7nm pll/phy in CPHY mode.
This adds a "qcom,dsi-phy-cphy-mode" property for the PHY node to enable
the CPHY mode.
Signed-off-by: Jonathan Marek
---
.../devicetree/bindings/display/msm/dsi.txt | 1 +
drivers/gpu/drm/msm/dsi/dsi.c | 12 +--
drivers/gpu/drm/msm/dsi/dsi.h | 6 +-
drivers/gpu/drm/msm/dsi/dsi.xml.h | 2 +
drivers/gpu/drm/msm/dsi/dsi_host.c| 34 +--
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 49 +-
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 89 ++-
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 4 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 5 +-
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 71 +--
11 files changed, 210 insertions(+), 66 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
b/Documentation/devicetree/bindings/display/msm/dsi.txt
index b9a64d3ff184..7ffc86a9816b 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -124,6 +124,7 @@ Required properties:
Optional properties:
- qcom,dsi-phy-regulator-ldo-mode: Boolean value indicating if the LDO mode PHY
regulator is wanted.
+- qcom,dsi-phy-cphy-mode: Boolean value indicating if CPHY mode is wanted.
- qcom,mdss-mdp-transfer-time-us: Specifies the dsi transfer time for
command mode
panels in microseconds. Driver uses
this number to adjust
the clock rate according to the
expected transfer time.
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 627048851d99..68d8547f7264 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -13,7 +13,7 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi
*msm_dsi)
return msm_dsi->encoder;
}
-static int dsi_get_phy(struct msm_dsi *msm_dsi)
+static int dsi_get_phy(struct msm_dsi *msm_dsi, bool *cphy_mode)
{
struct platform_device *pdev = msm_dsi->pdev;
struct platform_device *phy_pdev;
@@ -29,6 +29,7 @@ static int dsi_get_phy(struct msm_dsi *msm_dsi)
if (phy_pdev)
msm_dsi->phy = platform_get_drvdata(phy_pdev);
+ *cphy_mode = of_property_read_bool(phy_node, "qcom,dsi-phy-cphy-mode");
of_node_put(phy_node);
if (!phy_pdev || !msm_dsi->phy) {
@@ -65,6 +66,7 @@ static void dsi_destroy(struct msm_dsi *msm_dsi)
static struct msm_dsi *dsi_init(struct platform_device *pdev)
{
struct msm_dsi *msm_dsi;
+ bool cphy_mode;
int ret;
if (!pdev)
@@ -79,13 +81,13 @@ static struct msm_dsi *dsi_init(struct platform_device
*pdev)
msm_dsi->pdev = pdev;
platform_set_drvdata(pdev, msm_dsi);
- /* Init dsi host */
- ret = msm_dsi_host_init(msm_dsi);
+ /* GET dsi PHY */
+ ret = dsi_get_phy(msm_dsi, _mode);
if (ret)
goto destroy_dsi;
- /* GET dsi PHY */
- ret = dsi_get_phy(msm_dsi);
+ /* Init dsi host */
+ ret = msm_dsi_host_init(msm_dsi, cphy_mode);
if (ret)
goto destroy_dsi;
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 78ef5d4ed922..8db4edc286ee 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -108,7 +108,7 @@ struct drm_encoder *msm_dsi_get_encoder(struct msm_dsi
*msm_dsi);
struct msm_dsi_pll;
#ifdef CONFIG_DRM_MSM_DSI_PLL
struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device *pdev,
- enum msm_dsi_phy_type type, int dsi_id);
+ enum msm_dsi_phy_type type, bool cphy_mode, int id);
void msm_dsi_pll_destroy(struct msm_dsi_pll *pll);
int msm_dsi_pll_get_clk_provider(struct msm_dsi_pll *pll,
struct clk **byte_clk_provider, struct clk **pixel_clk_provider);
@@ -118,7 +118,7 @@ int msm_dsi_pll_set_usecase(struct msm_dsi_pll *pll,
enum msm_dsi_phy_usecase uc);
#else
static inline struct msm_dsi_pll *msm_dsi_pll_init(struct platform_device
*pdev,
-enum msm_dsi_phy_type type, int id) {
+enum msm_dsi_phy_type type, bool cphy_mode, int id) {
return ERR_PTR(-ENODEV);
}
static inline void msm_dsi_pll_destroy(struct msm_dsi_pll *pll)
@@ -177,7 +177,7 @@ void msm_dsi_host_get_phy_clk_req(struct mipi_dsi_host
*host,
void msm_dsi_host_destroy(struct mipi_dsi_host *host);
int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
struct drm_device *dev);
-int msm_dsi_host_init(struct msm_dsi *msm_dsi);
+int msm_dsi_host_init(struct msm_dsi *msm_dsi, bool cphy_mode);
int msm_dsi_runtime_suspend(struct device *dev);
int msm_dsi_runti
Re: [PATCH 2/2] arm64: dts: qcom: sm8250: fix display nodes
On 2/11/21 3:05 PM, Dmitry Baryshkov wrote:
On Thu, 11 Feb 2021 at 21:11, Jonathan Marek wrote:
Apply these fixes to the newly added sm8250 display ndoes
- Use sm8250 compatibles instead of sdm845 compatibles
- Remove "notused" interconnect (which apparently was blindly copied from
my old patches)
- Use dispcc node example from dt-bindings, removing clocks which aren't
documented or used by the driver and fixing the region size.
Note: also removed the mmcx-supply for dispcc which wasn't documented when
it was added. I would have left it there but it is also breaking my
use-case (setting a lower power level than what the bootloader sets?).
In our use case dispcc does not work w/o mmcx-supply. Compare this
with the downstream kernel, which actively uses MMCX domain.
I sent a v2/v3 leaving the mmcx-supply untouched (I can fix my problem
by using rpmhpd_opp_nom in the mmcx-supply instead, so its not a problem
with adding it to dispcc). But mmcx-supply still needs to be added to
documentation.
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..20a3ff30e924 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@a80 {
};
mdss: mdss@ae0 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
- interconnects = <_noc MASTER_AMPSS_M0 _noc
SLAVE_DISPLAY_CFG>,
- <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
+ interconnects = <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
<_noc MASTER_MDP_PORT1 _virt
SLAVE_EBI_CH0>;
- interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+ interconnect-names = "mdp0-mem", "mdp1-mem";
power-domains = < MDSS_GDSC>;
@@ -2356,7 +2355,7 @@ mdss: mdss@ae0 {
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2580,36 +2579,21 @@ opp-35800 {
dispcc: clock-controller@af0 {
compatible = "qcom,sm8250-dispcc";
- reg = <0 0x0af0 0 0x2>;
- mmcx-supply = <_reg>;
+ reg = <0 0x0af0 0 0x1>;
clocks = < RPMH_CXO_CLK>,
<_phy 0>,
<_phy 1>,
<_phy 0>,
<_phy 1>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<_clk>;
+<_phy 0>,
+<_phy 1>;
There is no dp_phy on sm8250 yet.
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
- "dp_link_clk_divsel_ten",
- "dp_vco_divided_clk_src_mux",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
- "dptx2_phy_pll_link_clk",
- "dptx2_phy_pll_vco_div_clk",
- "edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk",
- "sleep_clk";
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
[PATCH v3 2/2] arm64: dts: qcom: sm8250: fix display nodes
Apply these fixes to the newly added sm8250 display ndoes
- Use sm8250 compatibles instead of sdm845 compatibles
- Remove "notused" interconnect (which apparently was blindly copied from
my old patches)
- Use dispcc node example from dt-bindings, removing clocks which aren't
documented or used by the driver and fixing the region size.
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 31 +++-
1 file changed, 8 insertions(+), 23 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..693ac533f9b6 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@a80 {
};
mdss: mdss@ae0 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
- interconnects = <_noc MASTER_AMPSS_M0 _noc
SLAVE_DISPLAY_CFG>,
- <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
+ interconnects = <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
<_noc MASTER_MDP_PORT1 _virt
SLAVE_EBI_CH0>;
- interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+ interconnect-names = "mdp0-mem", "mdp1-mem";
power-domains = < MDSS_GDSC>;
@@ -2356,7 +2355,7 @@ mdss: mdss@ae0 {
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2580,7 +2579,7 @@ opp-35800 {
dispcc: clock-controller@af0 {
compatible = "qcom,sm8250-dispcc";
- reg = <0 0x0af0 0 0x2>;
+ reg = <0 0x0af0 0 0x1>;
mmcx-supply = <_reg>;
clocks = < RPMH_CXO_CLK>,
<_phy 0>,
@@ -2588,28 +2587,14 @@ dispcc: clock-controller@af0 {
<_phy 0>,
<_phy 1>,
<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<_clk>;
+<0>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
- "dp_link_clk_divsel_ten",
- "dp_vco_divided_clk_src_mux",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
- "dptx2_phy_pll_link_clk",
- "dptx2_phy_pll_vco_div_clk",
- "edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk",
- "sleep_clk";
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.26.1
[PATCH v3 1/2] drm/msm: add compatibles for sm8150/sm8250 display
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/msm_drv.c | 6 +++---
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 551ae26f60da..5763f43200a0 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
MDSS:
Required properties:
-- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
+- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sm8150-mdss",
"qcom,sm8250-mdss"
- reg: physical base address and length of contoller's registers.
- reg-names: register region names. The following region is required:
* "mdss"
@@ -41,7 +41,7 @@ Optional properties:
MDP:
Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sm8150-dpu",
"qcom,sm8250-dpu"
- reg: physical base address and length of controller's registers.
- reg-names : register region names. The following region is required:
* "mdp"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5a8e3e1fc48c..fff12a4c8bfc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1219,6 +1219,8 @@ static const struct dev_pm_ops dpu_pm_ops = {
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sdm845-dpu", },
{ .compatible = "qcom,sc7180-dpu", },
+ { .compatible = "qcom,sm8150-dpu", },
+ { .compatible = "qcom,sm8250-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 94525ac76d4e..928f13d4bfbc 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1185,9 +1185,7 @@ static int add_display_components(struct device *dev,
* Populate the children devices, find the MDP5/DPU node, and then add
* the interfaces to our components list.
*/
- if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
+ if (!of_device_is_compatible(dev->of_node, "qcom,mdp4")) {
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
DRM_DEV_ERROR(dev, "failed to populate children
devices\n");
@@ -1320,6 +1318,8 @@ static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.26.1
[PATCH v3 0/2] arm64: dts: qcom: sm8250: fix display nodes
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250 display nodes. v2: do not remove mmcx-supply from dispcc node v3: remove references to dp_phy (missed this in v2, sorry for the spam) Jonathan Marek (2): drm/msm: add compatibles for sm8150/sm8250 display arm64: dts: qcom: sm8250: fix display nodes .../devicetree/bindings/display/msm/dpu.txt | 4 +-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 31 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++ drivers/gpu/drm/msm/msm_drv.c | 6 ++-- 4 files changed, 15 insertions(+), 28 deletions(-) -- 2.26.1
[PATCH v2 2/2] arm64: dts: qcom: sm8250: fix display nodes
Apply these fixes to the newly added sm8250 display ndoes
- Use sm8250 compatibles instead of sdm845 compatibles
- Remove "notused" interconnect (which apparently was blindly copied from
my old patches)
- Use dispcc node example from dt-bindings, removing clocks which aren't
documented or used by the driver and fixing the region size.
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 33
1 file changed, 9 insertions(+), 24 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..35f45f5e1c76 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@a80 {
};
mdss: mdss@ae0 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
- interconnects = <_noc MASTER_AMPSS_M0 _noc
SLAVE_DISPLAY_CFG>,
- <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
+ interconnects = <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
<_noc MASTER_MDP_PORT1 _virt
SLAVE_EBI_CH0>;
- interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+ interconnect-names = "mdp0-mem", "mdp1-mem";
power-domains = < MDSS_GDSC>;
@@ -2356,7 +2355,7 @@ mdss: mdss@ae0 {
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2580,36 +2579,22 @@ opp-35800 {
dispcc: clock-controller@af0 {
compatible = "qcom,sm8250-dispcc";
- reg = <0 0x0af0 0 0x2>;
+ reg = <0 0x0af0 0 0x1>;
mmcx-supply = <_reg>;
clocks = < RPMH_CXO_CLK>,
<_phy 0>,
<_phy 1>,
<_phy 0>,
<_phy 1>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<_clk>;
+<_phy 0>,
+<_phy 1>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
- "dp_link_clk_divsel_ten",
- "dp_vco_divided_clk_src_mux",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
- "dptx2_phy_pll_link_clk",
- "dptx2_phy_pll_vco_div_clk",
- "edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk",
- "sleep_clk";
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.26.1
[PATCH v2 1/2] drm/msm: add compatibles for sm8150/sm8250 display
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/msm_drv.c | 6 +++---
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 551ae26f60da..5763f43200a0 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
MDSS:
Required properties:
-- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
+- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sm8150-mdss",
"qcom,sm8250-mdss"
- reg: physical base address and length of contoller's registers.
- reg-names: register region names. The following region is required:
* "mdss"
@@ -41,7 +41,7 @@ Optional properties:
MDP:
Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sm8150-dpu",
"qcom,sm8250-dpu"
- reg: physical base address and length of controller's registers.
- reg-names : register region names. The following region is required:
* "mdp"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5a8e3e1fc48c..fff12a4c8bfc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1219,6 +1219,8 @@ static const struct dev_pm_ops dpu_pm_ops = {
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sdm845-dpu", },
{ .compatible = "qcom,sc7180-dpu", },
+ { .compatible = "qcom,sm8150-dpu", },
+ { .compatible = "qcom,sm8250-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 94525ac76d4e..928f13d4bfbc 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1185,9 +1185,7 @@ static int add_display_components(struct device *dev,
* Populate the children devices, find the MDP5/DPU node, and then add
* the interfaces to our components list.
*/
- if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
+ if (!of_device_is_compatible(dev->of_node, "qcom,mdp4")) {
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
DRM_DEV_ERROR(dev, "failed to populate children
devices\n");
@@ -1320,6 +1318,8 @@ static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.26.1
[PATCH v2 0/2] arm64: dts: qcom: sm8250: fix display nodes
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250 display nodes. v2: do not remove mmcx-supply from dispcc node Jonathan Marek (2): drm/msm: add compatibles for sm8150/sm8250 display arm64: dts: qcom: sm8250: fix display nodes .../devicetree/bindings/display/msm/dpu.txt | 4 +-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 33 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++ drivers/gpu/drm/msm/msm_drv.c | 6 ++-- 4 files changed, 16 insertions(+), 29 deletions(-) -- 2.26.1
[PATCH 1/2] drm/msm: add compatibles for sm8150/sm8250 display
The driver already has support for sm8150/sm8250, but the compatibles were
never added.
Also inverse the non-mdp4 condition in add_display_components() to avoid
having to check every new compatible in the condition.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/display/msm/dpu.txt | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/msm_drv.c | 6 +++---
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/msm/dpu.txt
b/Documentation/devicetree/bindings/display/msm/dpu.txt
index 551ae26f60da..5763f43200a0 100644
--- a/Documentation/devicetree/bindings/display/msm/dpu.txt
+++ b/Documentation/devicetree/bindings/display/msm/dpu.txt
@@ -8,7 +8,7 @@ The DPU display controller is found in SDM845 SoC.
MDSS:
Required properties:
-- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss"
+- compatible: "qcom,sdm845-mdss", "qcom,sc7180-mdss", "qcom,sm8150-mdss",
"qcom,sm8250-mdss"
- reg: physical base address and length of contoller's registers.
- reg-names: register region names. The following region is required:
* "mdss"
@@ -41,7 +41,7 @@ Optional properties:
MDP:
Required properties:
-- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu"
+- compatible: "qcom,sdm845-dpu", "qcom,sc7180-dpu", "qcom,sm8150-dpu",
"qcom,sm8250-dpu"
- reg: physical base address and length of controller's registers.
- reg-names : register region names. The following region is required:
* "mdp"
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 5a8e3e1fc48c..fff12a4c8bfc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -1219,6 +1219,8 @@ static const struct dev_pm_ops dpu_pm_ops = {
static const struct of_device_id dpu_dt_match[] = {
{ .compatible = "qcom,sdm845-dpu", },
{ .compatible = "qcom,sc7180-dpu", },
+ { .compatible = "qcom,sm8150-dpu", },
+ { .compatible = "qcom,sm8250-dpu", },
{}
};
MODULE_DEVICE_TABLE(of, dpu_dt_match);
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 94525ac76d4e..928f13d4bfbc 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1185,9 +1185,7 @@ static int add_display_components(struct device *dev,
* Populate the children devices, find the MDP5/DPU node, and then add
* the interfaces to our components list.
*/
- if (of_device_is_compatible(dev->of_node, "qcom,mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sdm845-mdss") ||
- of_device_is_compatible(dev->of_node, "qcom,sc7180-mdss")) {
+ if (!of_device_is_compatible(dev->of_node, "qcom,mdp4")) {
ret = of_platform_populate(dev->of_node, NULL, NULL, dev);
if (ret) {
DRM_DEV_ERROR(dev, "failed to populate children
devices\n");
@@ -1320,6 +1318,8 @@ static const struct of_device_id dt_match[] = {
{ .compatible = "qcom,mdss", .data = (void *)KMS_MDP5 },
{ .compatible = "qcom,sdm845-mdss", .data = (void *)KMS_DPU },
{ .compatible = "qcom,sc7180-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8150-mdss", .data = (void *)KMS_DPU },
+ { .compatible = "qcom,sm8250-mdss", .data = (void *)KMS_DPU },
{}
};
MODULE_DEVICE_TABLE(of, dt_match);
--
2.26.1
[PATCH 0/2] arm64: dts: qcom: sm8250: fix display nodes
Add sm8150/sm8250 compatibles to drm/msm and fix the sm8250 display nodes. Jonathan Marek (2): drm/msm: add compatibles for sm8150/sm8250 display arm64: dts: qcom: sm8250: fix display nodes .../devicetree/bindings/display/msm/dpu.txt | 4 +-- arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++ drivers/gpu/drm/msm/msm_drv.c | 6 ++-- 4 files changed, 16 insertions(+), 30 deletions(-) -- 2.26.1
[PATCH 2/2] arm64: dts: qcom: sm8250: fix display nodes
Apply these fixes to the newly added sm8250 display ndoes
- Use sm8250 compatibles instead of sdm845 compatibles
- Remove "notused" interconnect (which apparently was blindly copied from
my old patches)
- Use dispcc node example from dt-bindings, removing clocks which aren't
documented or used by the driver and fixing the region size.
Note: also removed the mmcx-supply for dispcc which wasn't documented when
it was added. I would have left it there but it is also breaking my
use-case (setting a lower power level than what the bootloader sets?).
Fixes: 7c1dffd471b1 ("arm64: dts: qcom: sm8250.dtsi: add display system nodes")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34
1 file changed, 9 insertions(+), 25 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 947e1accae3a..20a3ff30e924 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -2323,14 +2323,13 @@ usb_2_dwc3: dwc3@a80 {
};
mdss: mdss@ae0 {
- compatible = "qcom,sdm845-mdss";
+ compatible = "qcom,sm8250-mdss";
reg = <0 0x0ae0 0 0x1000>;
reg-names = "mdss";
- interconnects = <_noc MASTER_AMPSS_M0 _noc
SLAVE_DISPLAY_CFG>,
- <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
+ interconnects = <_noc MASTER_MDP_PORT0 _virt
SLAVE_EBI_CH0>,
<_noc MASTER_MDP_PORT1 _virt
SLAVE_EBI_CH0>;
- interconnect-names = "notused", "mdp0-mem", "mdp1-mem";
+ interconnect-names = "mdp0-mem", "mdp1-mem";
power-domains = < MDSS_GDSC>;
@@ -2356,7 +2355,7 @@ mdss: mdss@ae0 {
ranges;
mdss_mdp: mdp@ae01000 {
- compatible = "qcom,sdm845-dpu";
+ compatible = "qcom,sm8250-dpu";
reg = <0 0x0ae01000 0 0x8f000>,
<0 0x0aeb 0 0x2008>;
reg-names = "mdp", "vbif";
@@ -2580,36 +2579,21 @@ opp-35800 {
dispcc: clock-controller@af0 {
compatible = "qcom,sm8250-dispcc";
- reg = <0 0x0af0 0 0x2>;
- mmcx-supply = <_reg>;
+ reg = <0 0x0af0 0 0x1>;
clocks = < RPMH_CXO_CLK>,
<_phy 0>,
<_phy 1>,
<_phy 0>,
<_phy 1>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<0>,
-<_clk>;
+<_phy 0>,
+<_phy 1>;
clock-names = "bi_tcxo",
"dsi0_phy_pll_out_byteclk",
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
- "dp_link_clk_divsel_ten",
- "dp_vco_divided_clk_src_mux",
- "dptx1_phy_pll_link_clk",
- "dptx1_phy_pll_vco_div_clk",
- "dptx2_phy_pll_link_clk",
- "dptx2_phy_pll_vco_div_clk",
- "edp_phy_pll_link_clk",
- "edp_phy_pll_vco_div_clk",
- "sleep_clk";
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.26.1
[PATCH] regulator: qcom-rpmh: fix pm8009 ldo7
Use the correct name to avoid ldo7 commands being sent to ldo6's address.
Fixes: 06369bcc15a1 ("regulator: qcom-rpmh: Add support for SM8150")
Signed-off-by: Jonathan Marek
---
drivers/regulator/qcom-rpmh-regulator.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/regulator/qcom-rpmh-regulator.c
b/drivers/regulator/qcom-rpmh-regulator.c
index 05f1b4e150f4..043dc2fd39eb 100644
--- a/drivers/regulator/qcom-rpmh-regulator.c
+++ b/drivers/regulator/qcom-rpmh-regulator.c
@@ -937,7 +937,7 @@ static const struct rpmh_vreg_init_data pm8009_vreg_data[]
= {
RPMH_VREG("ldo4", "ldo%s4", _nldo, "vdd-l4"),
RPMH_VREG("ldo5", "ldo%s5", _pldo, "vdd-l5-l6"),
RPMH_VREG("ldo6", "ldo%s6", _pldo, "vdd-l5-l6"),
- RPMH_VREG("ldo7", "ldo%s6", _pldo_lv, "vdd-l7"),
+ RPMH_VREG("ldo7", "ldo%s7", _pldo_lv, "vdd-l7"),
{},
};
--
2.26.1
[PATCH] misc: fastrpc: fix incorrect usage of dma_map_sgtable
dma_map_sgtable() returns 0 on success, which is the opposite of what this
code was doing.
Fixes: 7cd7edb89437 ("misc: fastrpc: fix common struct sg_table related issues")
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 70eb5ed942d0..f12e909034ac 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -520,12 +520,13 @@ fastrpc_map_dma_buf(struct dma_buf_attachment *attachment,
{
struct fastrpc_dma_buf_attachment *a = attachment->priv;
struct sg_table *table;
+ int ret;
table = >sgt;
- if (!dma_map_sgtable(attachment->dev, table, dir, 0))
- return ERR_PTR(-ENOMEM);
-
+ ret = dma_map_sgtable(attachment->dev, table, dir, 0);
+ if (ret)
+ table = ERR_PTR(ret);
return table;
}
--
2.26.1
[PATCH] drm/msm: fix a6xx_gmu_clear_oob
The cleanup patch broke a6xx_gmu_clear_oob, fix it by adding the missing
bitshift operation.
Fixes: 555c50a4a19b ("drm/msm: Clean up GMU OOB set/clear handling")
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 71c917f909af..91cf46f84025 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -339,7 +339,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum
a6xx_gmu_oob_state state)
else
bit = a6xx_gmu_oob_bits[state].ack_new;
- gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, bit);
+ gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
}
/* Enable CPU control of SPTP power power collapse */
--
2.26.1
[PATCH] arm64: dts: qcom: sort sm8150 usb_2 node
Fix an error introduced resolving conflicts with camnoc_virt node.
Fixes: 0c9dde0d2015 ("arm64: dts: qcom: sm8150: Add secondary USB and PHY
nodes")
---
arch/arm64/boot/dts/qcom/sm8150.dtsi | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index bcfb06f5bebe..743228ba148f 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -976,13 +976,6 @@ usb_1_dwc3: dwc3@a60 {
};
};
- camnoc_virt: interconnect@ac0 {
- compatible = "qcom,sm8150-camnoc-virt";
- reg = <0 0x0ac0 0 0x1000>;
- #interconnect-cells = <1>;
- qcom,bcm-voters = <_bcm_voter>;
- };
-
usb_2: usb@a8f8800 {
compatible = "qcom,sm8150-dwc3", "qcom,dwc3";
reg = <0 0x0a8f8800 0 0x400>;
@@ -1028,6 +1021,13 @@ usb_2_dwc3: dwc3@a80 {
};
};
+ camnoc_virt: interconnect@ac0 {
+ compatible = "qcom,sm8150-camnoc-virt";
+ reg = <0 0x0ac0 0 0x1000>;
+ #interconnect-cells = <1>;
+ qcom,bcm-voters = <_bcm_voter>;
+ };
+
aoss_qmp: power-controller@c30 {
compatible = "qcom,sm8150-aoss-qmp";
reg = <0x0 0x0c30 0x0 0x10>;
--
2.26.1
[PATCH] arm64: dts: qcom: fix indentation error in sm8250 cpu nodes
Use tabs instead of 6 spaces.
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 34 ++--
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 468ba1d18751..e43a362f5e59 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -93,10 +93,10 @@ CPU0: cpu@0 {
qcom,freq-domain = <_hw 0>;
#cooling-cells = <2>;
L2_0: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
L3_0: l3-cache {
- compatible = "cache";
+ compatible = "cache";
};
};
};
@@ -110,8 +110,8 @@ CPU1: cpu@100 {
qcom,freq-domain = <_hw 0>;
#cooling-cells = <2>;
L2_100: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
@@ -124,8 +124,8 @@ CPU2: cpu@200 {
qcom,freq-domain = <_hw 0>;
#cooling-cells = <2>;
L2_200: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
@@ -138,8 +138,8 @@ CPU3: cpu@300 {
qcom,freq-domain = <_hw 0>;
#cooling-cells = <2>;
L2_300: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
@@ -152,8 +152,8 @@ CPU4: cpu@400 {
qcom,freq-domain = <_hw 1>;
#cooling-cells = <2>;
L2_400: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
@@ -166,8 +166,8 @@ CPU5: cpu@500 {
qcom,freq-domain = <_hw 1>;
#cooling-cells = <2>;
L2_500: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
@@ -181,8 +181,8 @@ CPU6: cpu@600 {
qcom,freq-domain = <_hw 1>;
#cooling-cells = <2>;
L2_600: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
@@ -195,8 +195,8 @@ CPU7: cpu@700 {
qcom,freq-domain = <_hw 2>;
#cooling-cells = <2>;
L2_700: l2-cache {
- compatible = "cache";
- next-level-cache = <_0>;
+ compatible = "cache";
+ next-level-cache = <_0>;
};
};
};
--
2.26.1
[PATCH] arm64: dts: qcom: update usb qmp phy clock-cells property
The top-level node doesn't provide any clocks, the subnode provides a
single clock with of_clk_hw_simple_get.
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sc7180.dtsi | 1 -
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8150.dtsi | 4 ++--
arch/arm64/boot/dts/qcom/sm8250.dtsi | 4 ++--
4 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi
b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6678f1e8e395..0189cbfad521 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -2608,7 +2608,6 @@ usb_1_qmpphy: phy-wrapper@88e9000 {
<0 0x088e8000 0 0x38>;
reg-names = "reg-base", "dp_com";
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 40e8c11f23ab..4a353c432a83 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3482,7 +3482,6 @@ usb_1_qmpphy: phy@88e9000 {
<0 0x088e8000 0 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -3504,6 +3503,7 @@ usb_1_ssphy: lanes@88e9200 {
<0 0x088e9600 0 0x128>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clocks = < GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
@@ -3515,7 +3515,6 @@ usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sdm845-qmp-usb3-uni-phy";
reg = <0 0x088eb000 0 0x18c>;
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -3535,6 +3534,7 @@ usb_2_ssphy: lane@88eb200 {
<0 0x088eb400 0 0x1fc>,
<0 0x088eb800 0 0x218>,
<0 0x088eb600 0 0x70>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clocks = < GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
diff --git a/arch/arm64/boot/dts/qcom/sm8150.dtsi
b/arch/arm64/boot/dts/qcom/sm8150.dtsi
index dab852833a65..bcfb06f5bebe 100644
--- a/arch/arm64/boot/dts/qcom/sm8150.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8150.dtsi
@@ -857,7 +857,6 @@ usb_1_qmpphy: phy@88e9000 {
<0 0x088e8000 0 0x10>;
reg-names = "reg-base", "dp_com";
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -879,6 +878,7 @@ usb_1_ssphy: lanes@88e9200 {
<0 0x088e9600 0 0x200>,
<0 0x088e9800 0 0x200>,
<0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
#phy-cells = <0>;
clocks = < GCC_USB3_PRIM_PHY_PIPE_CLK>;
clock-names = "pipe0";
@@ -904,7 +904,6 @@ usb_2_qmpphy: phy@88eb000 {
compatible = "qcom,sm8150-qmp-usb3-uni-phy";
reg = <0 0x088eb000 0 0x200>;
status = "disabled";
- #clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
@@ -924,6 +923,7 @@ usb_2_ssphy: lane@88eb200 {
<0 0x088eb400 0 0x200>,
<0 0x088eb800 0 0x800>,
<0 0x088eb600 0 0x200>;
+ #clock-cells = &
[PATCH] arm64: dts: qcom: fix serial output for sm8250-hdk
The uart2 node has been renamed, apply the change to sm8250-hdk dts too so
that serial output works.
Fixes: 91ed0e90fc49 ("arm64: dts: qcom: add sm8250 hdk dts")
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sm8250-hdk.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
index b5026e422aa6..c3a2c5aa6fe9 100644
--- a/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
+++ b/arch/arm64/boot/dts/qcom/sm8250-hdk.dts
@@ -17,7 +17,7 @@ / {
compatible = "qcom,sm8250-hdk", "qcom,sm8250";
aliases {
- serial0 =
+ serial0 =
};
chosen {
@@ -387,7 +387,7 @@ {
gpio-reserved-ranges = <28 4>, <40 4>;
};
- {
+ {
status = "okay";
};
--
2.26.1
Re: [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
On 11/16/20 12:50 PM, Rob Clark wrote: On Mon, Nov 16, 2020 at 9:33 AM Christoph Hellwig wrote: On Sat, Nov 14, 2020 at 03:07:20PM -0500, Jonathan Marek wrote: qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like dma_sync_single_for_cpu() does deal in some way with the partial cache line case, although I'm not sure that means we can have a nonCoherentAtomSize=1. No, it doesn't. You need to ensure ownership is managed at dma_get_cache_alignment() granularity. my guess is nonCoherentAtomSize=1 only works in the case of cache coherent buffers nonCoherentAtomSize doesn't apply to coherent memory (as the name implies), I guess qcom's driver is just wrong about having nonCoherentAtomSize=1. Jordan just mentioned there is at least one conformance test for this, I wonder if it just doesn't test it well enough, or just doesn't test the non-coherent memory type?
Re: [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
On 11/14/20 2:39 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 10:58 AM Jonathan Marek wrote:
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+ struct device *dev = msm_obj->base.dev->dev;
+
+ /* exit early if get_pages() hasn't been called yet */
+ if (!msm_obj->pages)
+ return;
+
+ /* TODO: sync only the specified range */
+
+ if (flags & MSM_GEM_SYNC_FOR_DEVICE) {
+ dma_sync_sg_for_device(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_TO_DEVICE);
+ }
+
+ if (flags & MSM_GEM_SYNC_FOR_CPU) {
+ dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_FROM_DEVICE);
+ }
Splitting this helper from the only caller is rather strange, epecially
with the two unused arguments. And I think the way this is specified
to take a range, but ignoring it is actively dangerous. User space will
rely on it syncing everything sooner or later and then you are stuck.
So just define a sync all primitive for now, and if you really need a
range sync and have actually implemented it add a new ioctl for that.
We do already have a split of ioctl "layer" which enforces valid ioctl
params, etc, and gem (or other) module code which is called by the
ioctl func. So I think it is fine to keep this split here. (Also, I
think at some point there will be a uring type of ioctl alternative
which would re-use the same gem func.)
But I do agree that the range should be respected or added later..
drm_ioctl() dispatch is well prepared for extending ioctls.
And I assume there should be some validation that the range is aligned
to cache-line? Or can we flush a partial cache line?
The range is intended to be "sync at least this range", so that
userspace doesn't have to worry about details like that.
I don't think userspace can *not* worry about details like that.
Consider a case where the cpu and gpu are simultaneously accessing
different parts of a buffer (for ex, sub-allocation). There needs to
be cache-line separation between the two.
Right.. and it also seems like we can't get away with just
flushing/invalidating the whole thing.
qcom's vulkan driver has nonCoherentAtomSize=1, and it looks like
dma_sync_single_for_cpu() does deal in some way with the partial cache
line case, although I'm not sure that means we can have a
nonCoherentAtomSize=1.
BR,
-R
Re: [RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
On 11/14/20 1:46 PM, Rob Clark wrote:
On Sat, Nov 14, 2020 at 8:24 AM Christoph Hellwig wrote:
On Sat, Nov 14, 2020 at 10:17:12AM -0500, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+ struct device *dev = msm_obj->base.dev->dev;
+
+ /* exit early if get_pages() hasn't been called yet */
+ if (!msm_obj->pages)
+ return;
+
+ /* TODO: sync only the specified range */
+
+ if (flags & MSM_GEM_SYNC_FOR_DEVICE) {
+ dma_sync_sg_for_device(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_TO_DEVICE);
+ }
+
+ if (flags & MSM_GEM_SYNC_FOR_CPU) {
+ dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_FROM_DEVICE);
+ }
Splitting this helper from the only caller is rather strange, epecially
with the two unused arguments. And I think the way this is specified
to take a range, but ignoring it is actively dangerous. User space will
rely on it syncing everything sooner or later and then you are stuck.
So just define a sync all primitive for now, and if you really need a
range sync and have actually implemented it add a new ioctl for that.
We do already have a split of ioctl "layer" which enforces valid ioctl
params, etc, and gem (or other) module code which is called by the
ioctl func. So I think it is fine to keep this split here. (Also, I
think at some point there will be a uring type of ioctl alternative
which would re-use the same gem func.)
But I do agree that the range should be respected or added later..
drm_ioctl() dispatch is well prepared for extending ioctls.
And I assume there should be some validation that the range is aligned
to cache-line? Or can we flush a partial cache line?
The range is intended to be "sync at least this range", so that
userspace doesn't have to worry about details like that.
BR,
-R
[RESEND PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/drm/msm/msm_drv.h | 2 ++
drivers/gpu/drm/msm/msm_gem.c | 23 +++
include/uapi/drm/msm_drm.h| 20
4 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index bae48afca82e..3f17acdf6594 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -959,6 +959,26 @@ static int msm_ioctl_submitqueue_close(struct drm_device
*dev, void *data,
return msm_submitqueue_remove(file->driver_priv, id);
}
+static int msm_ioctl_gem_sync_cache(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_msm_gem_sync_cache *args = data;
+ struct drm_gem_object *obj;
+
+ if (args->flags & ~MSM_GEM_SYNC_CACHE_FLAGS)
+ return -EINVAL;
+
+ obj = drm_gem_object_lookup(file, args->handle);
+ if (!obj)
+ return -ENOENT;
+
+ msm_gem_sync_cache(obj, args->flags, args->offset, args->end);
+
+ drm_gem_object_put(obj);
+
+ return 0;
+}
+
static const struct drm_ioctl_desc msm_ioctls[] = {
DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,msm_ioctl_get_param,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new,
DRM_RENDER_ALLOW),
@@ -971,6 +991,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(MSM_GEM_SYNC_CACHE,msm_ioctl_gem_sync_cache,
DRM_RENDER_ALLOW),
};
static const struct vm_operations_struct vm_ops = {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 22ebecb28349..f170f843010e 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -318,6 +318,8 @@ void msm_gem_active_get(struct drm_gem_object *obj, struct
msm_gpu *gpu);
void msm_gem_active_put(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t
*timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
uint32_t size, uint32_t flags, uint32_t *handle, char *name);
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 3d8254b5de16..039738696f9a 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -797,6 +797,29 @@ int msm_gem_cpu_fini(struct drm_gem_object *obj)
return 0;
}
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+ struct device *dev = msm_obj->base.dev->dev;
+
+ /* exit early if get_pages() hasn't been called yet */
+ if (!msm_obj->pages)
+ return;
+
+ /* TODO: sync only the specified range */
+
+ if (flags & MSM_GEM_SYNC_FOR_DEVICE) {
+ dma_sync_sg_for_device(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_TO_DEVICE);
+ }
+
+ if (flags & MSM_GEM_SYNC_FOR_CPU) {
+ dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_FROM_DEVICE);
+ }
+}
+
#ifdef CONFIG_DEBUG_FS
static void describe_fence(struct dma_fence *fence, const char *type,
struct seq_file *m)
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 474497e8743a..c8288f328528 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -319,6 +319,24 @@ struct drm_msm_submitqueue_query {
__u32 pad;
};
+/*
+ * Host cache maintenance (relevant for MSM_BO_CACHED)
+ * driver may both clean/invalidate (flush) for clean
+ */
+
+#define MSM_GEM_SYNC_FOR_DEVICE0x1
+#define MSM_GEM_SYNC_FOR_CPU 0x2
+
+#define MSM_GEM_SYNC_CACHE_FLAGS (MSM_GEM_SYNC_FOR_DEVICE | \
+MSM_GEM_SYNC_FOR_CPU)
+
+struct drm_msm_gem_sync_cache {
+ __u32 handle;
+ __u32 flags;
+ __u64 offset;
+ __u64 end; /* offset + size */
+};
+
#define DRM_MSM_GET_PARAM 0x00
/* placeholder:
#define
[RESEND PATCH v2 3/5] drm/msm: call dma_direct_bypass()
Always use direct dma ops and no swiotlb. Note: arm-smmu-qcom already avoids creating iommu dma ops, but not everything uses arm-smmu-qcom and this also sets the dma mask. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/msm_drv.c | 8 +--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index e5816b498494..07c50405970a 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -20,6 +20,7 @@ config DRM_MSM select SND_SOC_HDMI_CODEC if SND_SOC select SYNC_FILE select PM_OPP + select DMA_OPS_BYPASS help DRM/KMS driver for MSM/snapdragon. diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 49685571dc0e..bae48afca82e 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -1288,10 +1289,11 @@ static int msm_pdev_probe(struct platform_device *pdev) if (ret) goto fail; - /* on all devices that I am aware of, iommu's which can map -* any address the cpu can see are used: + /* always use direct dma ops and no swiotlb +* note: arm-smmu-qcom already avoids creating iommu dma ops, but +* not everything uses arm-smmu-qcom and this also sets the dma mask */ - ret = dma_set_mask_and_coherent(>dev, ~0); + ret = dma_direct_bypass(>dev); if (ret) goto fail; -- 2.26.1
[RESEND PATCH v2 2/5] dma-direct: add dma_direct_bypass() to force direct ops
Add a function to force direct ops and disable swiotlb for a deivce.
Signed-off-by: Jonathan Marek
---
include/linux/dma-direct.h | 9 +
kernel/dma/direct.c| 23 +++
2 files changed, 32 insertions(+)
diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h
index 18aade195884..41f57e1b7aa5 100644
--- a/include/linux/dma-direct.h
+++ b/include/linux/dma-direct.h
@@ -124,4 +124,13 @@ int dma_direct_supported(struct device *dev, u64 mask);
dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
size_t size, enum dma_data_direction dir, unsigned long attrs);
+#if IS_ENABLED(CONFIG_DMA_OPS_BYPASS) &&
!IS_ENABLED(CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED)
+int dma_direct_bypass(struct device *dev);
+#else
+static inline int dma_direct_bypass(struct device *dev)
+{
+ return -EIO;
+}
+#endif
+
#endif /* _LINUX_DMA_DIRECT_H */
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 06c111544f61..304a5a77cccb 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -548,3 +548,26 @@ int dma_direct_set_offset(struct device *dev, phys_addr_t
cpu_start,
return 0;
}
EXPORT_SYMBOL_GPL(dma_direct_set_offset);
+
+/**
+ * dma_direct_bypass - always use direct mapping path for device
+ * @dev: device pointer
+ *
+ * Note: this also bypasses swiotlb. Not available for arch with
+ * force_dma_unencrypted(), since this doesn't deal with that.
+ */
+#if IS_ENABLED(CONFIG_DMA_OPS_BYPASS) &&
!IS_ENABLED(CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED)
+int dma_direct_bypass(struct device *dev)
+{
+ int ret;
+
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (ret)
+ return ret;
+
+ dev->bus_dma_limit = DMA_BIT_MASK(64);
+ dev->dma_ops_bypass = true;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dma_direct_bypass);
+#endif
--
2.26.1
[RESEND PATCH v2 5/5] drm/msm: bump up the uapi version
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594..7230d3c0eee5 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -39,9 +39,10 @@
* GEM object's debug name
* - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
* - 1.6.0 - Syncobj support
+ * - 1.7.0 - MSM_BO_CACHED_COHERENT and DRM_IOCTL_MSM_GEM_SYNC_CACHE
*/
#define MSM_VERSION_MAJOR 1
-#define MSM_VERSION_MINOR 6
+#define MSM_VERSION_MINOR 7
#define MSM_VERSION_PATCHLEVEL 0
static const struct drm_mode_config_funcs mode_config_funcs = {
--
2.26.1
[RESEND PATCH v2 1/5] drm/msm: add MSM_BO_CACHED_COHERENT
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm/msm_drm.h | 5 ++---
4 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 58e03b20e1c7..21c9bc954f38 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -410,6 +410,7 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
config.rev.minor, config.rev.patchid);
priv->is_a2xx = config.rev.core == 2;
+ priv->has_cached_coherent = config.rev.core >= 6;
gpu = info->init(drm);
if (IS_ERR(gpu)) {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index f33281ac7913..22ebecb28349 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -168,6 +168,7 @@ struct msm_drm_private {
struct msm_file_private *lastctx;
/* gpu is only set on open(), but we need this info earlier */
bool is_a2xx;
+ bool has_cached_coherent;
struct drm_fb_helper *fbdev;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 04be4cf1..3d8254b5de16 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -420,6 +420,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj,
if (msm_obj->flags & MSM_BO_MAP_PRIV)
prot |= IOMMU_PRIV;
+ if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
+ prot |= IOMMU_CACHE;
+
WARN_ON(!mutex_is_locked(_obj->lock));
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -1004,6 +1007,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
uint32_t size, uint32_t flags,
struct drm_gem_object **obj)
{
+ struct msm_drm_private *priv = dev->dev_private;
struct msm_gem_object *msm_obj;
switch (flags & MSM_BO_CACHE_MASK) {
@@ -1011,6 +1015,10 @@ static int msm_gem_new_impl(struct drm_device *dev,
case MSM_BO_CACHED:
case MSM_BO_WC:
break;
+ case MSM_BO_CACHED_COHERENT:
+ if (priv->has_cached_coherent)
+ break;
+ /* fallthrough */
default:
DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
(flags & MSM_BO_CACHE_MASK));
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index a6c1f3eb2623..474497e8743a 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -94,12 +94,11 @@ struct drm_msm_param {
#define MSM_BO_CACHED0x0001
#define MSM_BO_WC0x0002
#define MSM_BO_UNCACHED 0x0004
+#define MSM_BO_CACHED_COHERENT 0x08
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
MSM_BO_GPU_READONLY | \
- MSM_BO_CACHED | \
- MSM_BO_WC | \
- MSM_BO_UNCACHED)
+ MSM_BO_CACHE_MASK)
struct drm_msm_gem_new {
__u64 size; /* in */
--
2.26.1
[RESEND PATCH v2 0/5] drm/msm: support for host-cached BOs
v2: - added patches 2/3 to enable using dma_ops_bypass - changed DRM_MSM_GEM_SYNC_CACHE patch to use dma_sync_sg_for_device() and dma_sync_sg_for_cpu(), and renamed sync flags. Not sure I did the right thing with for the dma_ops_bypass part, this is what I came up with reading the emails. Jonathan Marek (5): drm/msm: add MSM_BO_CACHED_COHERENT dma-direct: add dma_direct_bypass() to force direct ops drm/msm: call dma_direct_bypass() drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance drm/msm: bump up the uapi version drivers/gpu/drm/msm/Kconfig| 1 + drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 32 +++--- drivers/gpu/drm/msm/msm_drv.h | 3 ++ drivers/gpu/drm/msm/msm_gem.c | 31 + include/linux/dma-direct.h | 9 ++ include/uapi/drm/msm_drm.h | 25 +++-- kernel/dma/direct.c| 23 8 files changed, 118 insertions(+), 7 deletions(-) -- 2.26.1
[PATCH v2 5/5] drm/msm: bump up the uapi version
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3f17acdf6594..7230d3c0eee5 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -39,9 +39,10 @@
* GEM object's debug name
* - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
* - 1.6.0 - Syncobj support
+ * - 1.7.0 - MSM_BO_CACHED_COHERENT and DRM_IOCTL_MSM_GEM_SYNC_CACHE
*/
#define MSM_VERSION_MAJOR 1
-#define MSM_VERSION_MINOR 6
+#define MSM_VERSION_MINOR 7
#define MSM_VERSION_PATCHLEVEL 0
static const struct drm_mode_config_funcs mode_config_funcs = {
--
2.26.1
[PATCH v2 1/5] drm/msm: add MSM_BO_CACHED_COHERENT
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
Reviewed-by: Jordan Crouse
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm/msm_drm.h | 5 ++---
4 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 58e03b20e1c7..21c9bc954f38 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -410,6 +410,7 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
config.rev.minor, config.rev.patchid);
priv->is_a2xx = config.rev.core == 2;
+ priv->has_cached_coherent = config.rev.core >= 6;
gpu = info->init(drm);
if (IS_ERR(gpu)) {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index f33281ac7913..22ebecb28349 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -168,6 +168,7 @@ struct msm_drm_private {
struct msm_file_private *lastctx;
/* gpu is only set on open(), but we need this info earlier */
bool is_a2xx;
+ bool has_cached_coherent;
struct drm_fb_helper *fbdev;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 04be4cf1..3d8254b5de16 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -420,6 +420,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj,
if (msm_obj->flags & MSM_BO_MAP_PRIV)
prot |= IOMMU_PRIV;
+ if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
+ prot |= IOMMU_CACHE;
+
WARN_ON(!mutex_is_locked(_obj->lock));
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -1004,6 +1007,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
uint32_t size, uint32_t flags,
struct drm_gem_object **obj)
{
+ struct msm_drm_private *priv = dev->dev_private;
struct msm_gem_object *msm_obj;
switch (flags & MSM_BO_CACHE_MASK) {
@@ -1011,6 +1015,10 @@ static int msm_gem_new_impl(struct drm_device *dev,
case MSM_BO_CACHED:
case MSM_BO_WC:
break;
+ case MSM_BO_CACHED_COHERENT:
+ if (priv->has_cached_coherent)
+ break;
+ /* fallthrough */
default:
DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
(flags & MSM_BO_CACHE_MASK));
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index a6c1f3eb2623..474497e8743a 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -94,12 +94,11 @@ struct drm_msm_param {
#define MSM_BO_CACHED0x0001
#define MSM_BO_WC0x0002
#define MSM_BO_UNCACHED 0x0004
+#define MSM_BO_CACHED_COHERENT 0x08
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
MSM_BO_GPU_READONLY | \
- MSM_BO_CACHED | \
- MSM_BO_WC | \
- MSM_BO_UNCACHED)
+ MSM_BO_CACHE_MASK)
struct drm_msm_gem_new {
__u64 size; /* in */
--
2.26.1
[PATCH v2 3/5] drm/msm: call dma_direct_bypass()
Always use direct dma ops and no swiotlb. Note: arm-smmu-qcom already avoids creating iommu dma ops, but not everything uses arm-smmu-qcom and this also sets the dma mask. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/Kconfig | 1 + drivers/gpu/drm/msm/msm_drv.c | 8 +--- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index e5816b498494..07c50405970a 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -20,6 +20,7 @@ config DRM_MSM select SND_SOC_HDMI_CODEC if SND_SOC select SYNC_FILE select PM_OPP + select DMA_OPS_BYPASS help DRM/KMS driver for MSM/snapdragon. diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 49685571dc0e..bae48afca82e 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -6,6 +6,7 @@ */ #include +#include #include #include #include @@ -1288,10 +1289,11 @@ static int msm_pdev_probe(struct platform_device *pdev) if (ret) goto fail; - /* on all devices that I am aware of, iommu's which can map -* any address the cpu can see are used: + /* always use direct dma ops and no swiotlb +* note: arm-smmu-qcom already avoids creating iommu dma ops, but +* not everything uses arm-smmu-qcom and this also sets the dma mask */ - ret = dma_set_mask_and_coherent(>dev, ~0); + ret = dma_direct_bypass(>dev); if (ret) goto fail; -- 2.26.1
[PATCH v2 0/5] drm/msm: support for host-cached BOs
This is to support cached and cached-coherent memory types in vulkan. v2: - added patches 2/3 to enable using dma_ops_bypass - changed DRM_MSM_GEM_SYNC_CACHE patch to use dma_sync_sg_for_device() and dma_sync_sg_for_cpu(), and renamed sync flags. Not sure I did the right thing with for the dma_ops_bypass part, this is what I came up with reading the emails. Jonathan Marek (5): drm/msm: add MSM_BO_CACHED_COHERENT dma-direct: add dma_direct_bypass() to force direct ops drm/msm: call dma_direct_bypass() drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance drm/msm: bump up the uapi version drivers/gpu/drm/msm/Kconfig| 1 + drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 32 +++--- drivers/gpu/drm/msm/msm_drv.h | 3 ++ drivers/gpu/drm/msm/msm_gem.c | 31 + include/linux/dma-direct.h | 9 ++ include/uapi/drm/msm_drm.h | 25 +++-- kernel/dma/direct.c| 23 8 files changed, 118 insertions(+), 7 deletions(-) -- 2.26.1
[PATCH v2 2/5] dma-direct: add dma_direct_bypass() to force direct ops
Add a function to force direct ops and disable swiotlb for a deivce.
Signed-off-by: Jonathan Marek
---
include/linux/dma-direct.h | 9 +
kernel/dma/direct.c| 23 +++
2 files changed, 32 insertions(+)
diff --git a/include/linux/dma-direct.h b/include/linux/dma-direct.h
index 18aade195884..41f57e1b7aa5 100644
--- a/include/linux/dma-direct.h
+++ b/include/linux/dma-direct.h
@@ -124,4 +124,13 @@ int dma_direct_supported(struct device *dev, u64 mask);
dma_addr_t dma_direct_map_resource(struct device *dev, phys_addr_t paddr,
size_t size, enum dma_data_direction dir, unsigned long attrs);
+#if IS_ENABLED(CONFIG_DMA_OPS_BYPASS) &&
!IS_ENABLED(CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED)
+int dma_direct_bypass(struct device *dev);
+#else
+static inline int dma_direct_bypass(struct device *dev)
+{
+ return -EIO;
+}
+#endif
+
#endif /* _LINUX_DMA_DIRECT_H */
diff --git a/kernel/dma/direct.c b/kernel/dma/direct.c
index 06c111544f61..304a5a77cccb 100644
--- a/kernel/dma/direct.c
+++ b/kernel/dma/direct.c
@@ -548,3 +548,26 @@ int dma_direct_set_offset(struct device *dev, phys_addr_t
cpu_start,
return 0;
}
EXPORT_SYMBOL_GPL(dma_direct_set_offset);
+
+/**
+ * dma_direct_bypass - always use direct mapping path for device
+ * @dev: device pointer
+ *
+ * Note: this also bypasses swiotlb. Not available for arch with
+ * force_dma_unencrypted(), since this doesn't deal with that.
+ */
+#if IS_ENABLED(CONFIG_DMA_OPS_BYPASS) &&
!IS_ENABLED(CONFIG_ARCH_HAS_FORCE_DMA_UNENCRYPTED)
+int dma_direct_bypass(struct device *dev)
+{
+ int ret;
+
+ ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
+ if (ret)
+ return ret;
+
+ dev->bus_dma_limit = DMA_BIT_MASK(64);
+ dev->dma_ops_bypass = true;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(dma_direct_bypass);
+#endif
--
2.26.1
[PATCH v2 4/5] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/drm/msm/msm_drv.h | 2 ++
drivers/gpu/drm/msm/msm_gem.c | 23 +++
include/uapi/drm/msm_drm.h| 20
4 files changed, 66 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index bae48afca82e..3f17acdf6594 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -959,6 +959,26 @@ static int msm_ioctl_submitqueue_close(struct drm_device
*dev, void *data,
return msm_submitqueue_remove(file->driver_priv, id);
}
+static int msm_ioctl_gem_sync_cache(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_msm_gem_sync_cache *args = data;
+ struct drm_gem_object *obj;
+
+ if (args->flags & ~MSM_GEM_SYNC_CACHE_FLAGS)
+ return -EINVAL;
+
+ obj = drm_gem_object_lookup(file, args->handle);
+ if (!obj)
+ return -ENOENT;
+
+ msm_gem_sync_cache(obj, args->flags, args->offset, args->end);
+
+ drm_gem_object_put(obj);
+
+ return 0;
+}
+
static const struct drm_ioctl_desc msm_ioctls[] = {
DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,msm_ioctl_get_param,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new,
DRM_RENDER_ALLOW),
@@ -971,6 +991,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(MSM_GEM_SYNC_CACHE,msm_ioctl_gem_sync_cache,
DRM_RENDER_ALLOW),
};
static const struct vm_operations_struct vm_ops = {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 22ebecb28349..f170f843010e 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -318,6 +318,8 @@ void msm_gem_active_get(struct drm_gem_object *obj, struct
msm_gpu *gpu);
void msm_gem_active_put(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t
*timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
uint32_t size, uint32_t flags, uint32_t *handle, char *name);
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index 3d8254b5de16..039738696f9a 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -797,6 +797,29 @@ int msm_gem_cpu_fini(struct drm_gem_object *obj)
return 0;
}
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+ struct device *dev = msm_obj->base.dev->dev;
+
+ /* exit early if get_pages() hasn't been called yet */
+ if (!msm_obj->pages)
+ return;
+
+ /* TODO: sync only the specified range */
+
+ if (flags & MSM_GEM_SYNC_FOR_DEVICE) {
+ dma_sync_sg_for_device(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_TO_DEVICE);
+ }
+
+ if (flags & MSM_GEM_SYNC_FOR_CPU) {
+ dma_sync_sg_for_cpu(dev, msm_obj->sgt->sgl,
+ msm_obj->sgt->nents, DMA_FROM_DEVICE);
+ }
+}
+
#ifdef CONFIG_DEBUG_FS
static void describe_fence(struct dma_fence *fence, const char *type,
struct seq_file *m)
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 474497e8743a..c8288f328528 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -319,6 +319,24 @@ struct drm_msm_submitqueue_query {
__u32 pad;
};
+/*
+ * Host cache maintenance (relevant for MSM_BO_CACHED)
+ * driver may both clean/invalidate (flush) for clean
+ */
+
+#define MSM_GEM_SYNC_FOR_DEVICE0x1
+#define MSM_GEM_SYNC_FOR_CPU 0x2
+
+#define MSM_GEM_SYNC_CACHE_FLAGS (MSM_GEM_SYNC_FOR_DEVICE | \
+MSM_GEM_SYNC_FOR_CPU)
+
+struct drm_msm_gem_sync_cache {
+ __u32 handle;
+ __u32 flags;
+ __u64 offset;
+ __u64 end; /* offset + size */
+};
+
#define DRM_MSM_GET_PARAM 0x00
/* placeholder:
#define
Re: [PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
On 10/6/20 3:23 AM, Christoph Hellwig wrote:
On Mon, Oct 05, 2020 at 10:35:43AM -0400, Jonathan Marek wrote:
The cache synchronization doesn't have anything to do with IOMMU (for
example: cache synchronization would be useful in cases where drm/msm
doesn't use IOMMU).
It has to do with doing DMA. And we have two frameworks for doing DMA:
either the DMA API which is for general driver use, and which as part of
the design includes cache maintainance hidden behind the concept of
ownership transfers. And we have the much more bare bones IOMMU API.
If people want to use the "raw" IOMMU API with not cache coherent
devices we'll need a cache maintainance API that goes along with it.
It could either be formally part of the IOMMU API or be separate.
What is needed is to call arch_sync_dma_for_{cpu,device} (which is what I
went with initially, but then decided to re-use drm/msm's
sync_for_{cpu,device}). But you are also saying those functions aren't for
driver use, and I doubt IOMMU maintainers will want to add wrappers for
these functions just to satisfy this "not for driver use" requirement.
arch_sync_dma_for_{cpu,device} are low-level helpers (and not very
great ones at that). The definitively should not be used by drivers.
They would be very useful buildblocks for a IOMMU cache maintainance
API.
Of course the best outcome would be if we could find a way for the MSM
drm driver to just use DMA API and not deal with the lower level
abstractions. Do you remember why the driver went for use of the IOMMU
API?
One example why drm/msm can't use DMA API is multiple page table support
(that is landing in 5.10), which is something that definitely couldn't
work with DMA API.
Another one is being able to choose the address for mappings, which
AFAIK DMA API can't do (somewhat related to this: qcom hardware often
has ranges of allowed addresses, which the dma_mask mechanism fails to
represent, what I see is drivers using dma_mask as a "maximum address",
and since addresses are allocated from the top it generally works)
But let us imagine drm/msm switches to using DMA API. a2xx GPUs have
their own very basic MMU (implemented by msm_gpummu.c), that will need
to implement dma_map_ops, which will have to call
arch_sync_dma_for_{cpu,device}. So drm/msm still needs to call
arch_sync_dma_for_{cpu,device} in that scenario.
Re: [PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
On 10/5/20 4:29 AM, Christoph Hellwig wrote:
On Fri, Oct 02, 2020 at 08:46:35AM -0400, Jonathan Marek wrote:
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+
+ /* TODO: sync only the required range, and don't invalidate on clean */
+
+ if (flags & MSM_GEM_SYNC_CACHE_CLEAN)
+ sync_for_device(msm_obj);
+
+ if (flags & MSM_GEM_SYNC_CACHE_INVALIDATE)
+ sync_for_cpu(msm_obj);
And make to these ones as well. They are complete abuses of the DMA
API, and while we had to live with that for now to not cause regressions
they absoutely must not be exposed in a userspace ABI like this.
How do you propose that cached non-coherent memory be implemented? It is a
useful feature for userspace.
If the driver is using the DMA API you need to use dma_alloc_noncoherent
and friends as of 5.10 (see the iommu list for the discussion).
If you use the raw IOMMU API (which I think the msm drm driver does) you
need to work with the maintainers to implement a cache synchronization
API that is not tied to the DMA API.
The cache synchronization doesn't have anything to do with IOMMU (for
example: cache synchronization would be useful in cases where drm/msm
doesn't use IOMMU).
What is needed is to call arch_sync_dma_for_{cpu,device} (which is what
I went with initially, but then decided to re-use drm/msm's
sync_for_{cpu,device}). But you are also saying those functions aren't
for driver use, and I doubt IOMMU maintainers will want to add wrappers
for these functions just to satisfy this "not for driver use" requirement.
Re: [PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
On 10/2/20 3:53 AM, Christoph Hellwig wrote:
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
NAK, dma-noncoherent.h is not for driver use. And will in fact go
away in 5.10.
Not actually used, so can be removed.
#include
@@ -808,6 +809,20 @@ int msm_gem_cpu_fini(struct drm_gem_object *obj)
return 0;
}
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+
+ /* TODO: sync only the required range, and don't invalidate on clean */
+
+ if (flags & MSM_GEM_SYNC_CACHE_CLEAN)
+ sync_for_device(msm_obj);
+
+ if (flags & MSM_GEM_SYNC_CACHE_INVALIDATE)
+ sync_for_cpu(msm_obj);
And make to these ones as well. They are complete abuses of the DMA
API, and while we had to live with that for now to not cause regressions
they absoutely must not be exposed in a userspace ABI like this.
How do you propose that cached non-coherent memory be implemented? It is
a useful feature for userspace.
[PATCH 2/3] drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance
This makes it possible to use the non-coherent cached MSM_BO_CACHED mode,
which otherwise doesn't provide any method for cleaning/invalidating the
cache to sync with the device.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 21 +
drivers/gpu/drm/msm/msm_drv.h | 2 ++
drivers/gpu/drm/msm/msm_gem.c | 15 +++
include/uapi/drm/msm_drm.h| 20
4 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 9716210495fc..305db1db1064 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -964,6 +964,26 @@ static int msm_ioctl_submitqueue_close(struct drm_device
*dev, void *data,
return msm_submitqueue_remove(file->driver_priv, id);
}
+static int msm_ioctl_gem_sync_cache(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ struct drm_msm_gem_sync_cache *args = data;
+ struct drm_gem_object *obj;
+
+ if (args->flags & ~MSM_GEM_SYNC_CACHE_FLAGS)
+ return -EINVAL;
+
+ obj = drm_gem_object_lookup(file, args->handle);
+ if (!obj)
+ return -ENOENT;
+
+ msm_gem_sync_cache(obj, args->flags, args->offset, args->end);
+
+ drm_gem_object_put(obj);
+
+ return 0;
+}
+
static const struct drm_ioctl_desc msm_ioctls[] = {
DRM_IOCTL_DEF_DRV(MSM_GET_PARAM,msm_ioctl_get_param,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new,
DRM_RENDER_ALLOW),
@@ -976,6 +996,7 @@ static const struct drm_ioctl_desc msm_ioctls[] = {
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_NEW, msm_ioctl_submitqueue_new,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_CLOSE, msm_ioctl_submitqueue_close,
DRM_RENDER_ALLOW),
DRM_IOCTL_DEF_DRV(MSM_SUBMITQUEUE_QUERY, msm_ioctl_submitqueue_query,
DRM_RENDER_ALLOW),
+ DRM_IOCTL_DEF_DRV(MSM_GEM_SYNC_CACHE,msm_ioctl_gem_sync_cache,
DRM_RENDER_ALLOW),
};
static const struct vm_operations_struct vm_ops = {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 6384844b1696..5e932dae453f 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -314,6 +314,8 @@ void msm_gem_move_to_active(struct drm_gem_object *obj,
void msm_gem_move_to_inactive(struct drm_gem_object *obj);
int msm_gem_cpu_prep(struct drm_gem_object *obj, uint32_t op, ktime_t
*timeout);
int msm_gem_cpu_fini(struct drm_gem_object *obj);
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end);
void msm_gem_free_object(struct drm_gem_object *obj);
int msm_gem_new_handle(struct drm_device *dev, struct drm_file *file,
uint32_t size, uint32_t flags, uint32_t *handle, char *name);
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index ad9a627493ae..93da88b3fc50 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -8,6 +8,7 @@
#include
#include
#include
+#include
#include
@@ -808,6 +809,20 @@ int msm_gem_cpu_fini(struct drm_gem_object *obj)
return 0;
}
+void msm_gem_sync_cache(struct drm_gem_object *obj, uint32_t flags,
+ size_t range_start, size_t range_end)
+{
+ struct msm_gem_object *msm_obj = to_msm_bo(obj);
+
+ /* TODO: sync only the required range, and don't invalidate on clean */
+
+ if (flags & MSM_GEM_SYNC_CACHE_CLEAN)
+ sync_for_device(msm_obj);
+
+ if (flags & MSM_GEM_SYNC_CACHE_INVALIDATE)
+ sync_for_cpu(msm_obj);
+}
+
#ifdef CONFIG_DEBUG_FS
static void describe_fence(struct dma_fence *fence, const char *type,
struct seq_file *m)
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index 474497e8743a..1dfafa71fc94 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -319,6 +319,24 @@ struct drm_msm_submitqueue_query {
__u32 pad;
};
+/*
+ * Host cache maintenance (relevant for MSM_BO_CACHED)
+ * driver may both clean/invalidate (flush) for clean
+ */
+
+#define MSM_GEM_SYNC_CACHE_CLEAN 0x1
+#define MSM_GEM_SYNC_CACHE_INVALIDATE 0x2
+
+#define MSM_GEM_SYNC_CACHE_FLAGS (MSM_GEM_SYNC_CACHE_CLEAN | \
+MSM_GEM_SYNC_CACHE_INVALIDATE)
+
+struct drm_msm_gem_sync_cache {
+ __u32 handle;
+ __u32 flags;
+ __u64 offset;
+ __u64 end; /* offset + size */
+};
+
#define DRM_MSM_GET_PARAM 0x00
/* placeholder:
#define DRM_MSM_SET_PARAM 0x01
@@ -336,6 +354,7 @@ struct drm_msm_submitqueue_query {
#define DRM_MSM_SUBMITQUEUE_NEW0x0A
#define DRM_MSM_SUBMITQUEUE_CLOSE 0x0B
#define DRM_MSM_SUBMITQUEUE_QUERY 0x0C
+#define DRM_MSM_GEM_SYNC_CACHE 0x0D
#define DRM_IOCTL_MSM_GET_PARAM
[PATCH 0/3] drm/msm: support for host-cached BOs
This is to support cached and cached-coherent memory types in vulkan. I made a corresponding WIP merge request [1] which shows usage of this. [1] https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6949 Jonathan Marek (3): drm/msm: add MSM_BO_CACHED_COHERENT drm/msm: add DRM_MSM_GEM_SYNC_CACHE for non-coherent cache maintenance drm/msm: bump up the uapi version drivers/gpu/drm/msm/adreno/adreno_device.c | 1 + drivers/gpu/drm/msm/msm_drv.c | 24 - drivers/gpu/drm/msm/msm_drv.h | 3 +++ drivers/gpu/drm/msm/msm_gem.c | 23 include/uapi/drm/msm_drm.h | 25 +++--- 5 files changed, 72 insertions(+), 4 deletions(-) -- 2.26.1
[PATCH 1/3] drm/msm: add MSM_BO_CACHED_COHERENT
Add a new cache mode for creating coherent host-cached BOs.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/adreno_device.c | 1 +
drivers/gpu/drm/msm/msm_drv.h | 1 +
drivers/gpu/drm/msm/msm_gem.c | 8
include/uapi/drm/msm_drm.h | 5 ++---
4 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c
b/drivers/gpu/drm/msm/adreno/adreno_device.c
index 9eeb46bf2a5d..2aa707546254 100644
--- a/drivers/gpu/drm/msm/adreno/adreno_device.c
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -410,6 +410,7 @@ static int adreno_bind(struct device *dev, struct device
*master, void *data)
config.rev.minor, config.rev.patchid);
priv->is_a2xx = config.rev.core == 2;
+ priv->has_cached_coherent = config.rev.core >= 6;
gpu = info->init(drm);
if (IS_ERR(gpu)) {
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 2c3225bc1794..6384844b1696 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -167,6 +167,7 @@ struct msm_drm_private {
struct msm_file_private *lastctx;
/* gpu is only set on open(), but we need this info earlier */
bool is_a2xx;
+ bool has_cached_coherent;
struct drm_fb_helper *fbdev;
diff --git a/drivers/gpu/drm/msm/msm_gem.c b/drivers/gpu/drm/msm/msm_gem.c
index b2f49152b4d4..ad9a627493ae 100644
--- a/drivers/gpu/drm/msm/msm_gem.c
+++ b/drivers/gpu/drm/msm/msm_gem.c
@@ -431,6 +431,9 @@ static int msm_gem_pin_iova(struct drm_gem_object *obj,
if (msm_obj->flags & MSM_BO_MAP_PRIV)
prot |= IOMMU_PRIV;
+ if (msm_obj->flags & MSM_BO_CACHED_COHERENT)
+ prot |= IOMMU_CACHE;
+
WARN_ON(!mutex_is_locked(_obj->lock));
if (WARN_ON(msm_obj->madv != MSM_MADV_WILLNEED))
@@ -998,6 +1001,7 @@ static int msm_gem_new_impl(struct drm_device *dev,
uint32_t size, uint32_t flags,
struct drm_gem_object **obj)
{
+ struct msm_drm_private *priv = dev->dev_private;
struct msm_gem_object *msm_obj;
switch (flags & MSM_BO_CACHE_MASK) {
@@ -1005,6 +1009,10 @@ static int msm_gem_new_impl(struct drm_device *dev,
case MSM_BO_CACHED:
case MSM_BO_WC:
break;
+ case MSM_BO_CACHED_COHERENT:
+ if (priv->has_cached_coherent)
+ break;
+ /* fallthrough */
default:
DRM_DEV_ERROR(dev->dev, "invalid cache flag: %x\n",
(flags & MSM_BO_CACHE_MASK));
diff --git a/include/uapi/drm/msm_drm.h b/include/uapi/drm/msm_drm.h
index a6c1f3eb2623..474497e8743a 100644
--- a/include/uapi/drm/msm_drm.h
+++ b/include/uapi/drm/msm_drm.h
@@ -94,12 +94,11 @@ struct drm_msm_param {
#define MSM_BO_CACHED0x0001
#define MSM_BO_WC0x0002
#define MSM_BO_UNCACHED 0x0004
+#define MSM_BO_CACHED_COHERENT 0x08
#define MSM_BO_FLAGS (MSM_BO_SCANOUT | \
MSM_BO_GPU_READONLY | \
- MSM_BO_CACHED | \
- MSM_BO_WC | \
- MSM_BO_UNCACHED)
+ MSM_BO_CACHE_MASK)
struct drm_msm_gem_new {
__u64 size; /* in */
--
2.26.1
[PATCH 3/3] drm/msm: bump up the uapi version
Increase the minor version to indicate the presence of new features.
Signed-off-by: Jonathan Marek
---
drivers/gpu/drm/msm/msm_drv.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 305db1db1064..502aafe7d1e6 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -38,9 +38,10 @@
* GEM object's debug name
* - 1.5.0 - Add SUBMITQUERY_QUERY ioctl
* - 1.6.0 - Syncobj support
+ * - 1.7.0 - MSM_BO_CACHED_COHERENT and DRM_IOCTL_MSM_GEM_SYNC_CACHE
*/
#define MSM_VERSION_MAJOR 1
-#define MSM_VERSION_MINOR 6
+#define MSM_VERSION_MINOR 7
#define MSM_VERSION_PATCHLEVEL 0
static const struct drm_mode_config_funcs mode_config_funcs = {
--
2.26.1
Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
On 9/24/20 2:16 AM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-23 09:10:04)
On 9/22/20 3:00 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:07)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
[...]
+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+ { .fw_name = "bi_tcxo" },
+ { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+ { .fw_name = "dsi1_phy_pll_out_dsiclk" },
Can we remove clk postfix on these clk names?
This is consistent with the names used in both sdm845 and sc7180
drivers. If this should change then those should be changed too?
If DT isn't using it already then it sounds OK to change the other
SoCs. Otherwise fix it just for this one.
Both sdm845 and sc7180 DT are using these names. I kept these names in
the V4 I just sent, keeping things consistent is a lot more beneficial
than dropping 3 extra characters from the DT names.
The sc7180 dispcc driver is recent and has all of these:
- dp_phy_pll_link_clk
- dp_phy_pll_vco_div_clk
- dsi0_phy_pll_out_byteclk
- dsi0_phy_pll_out_dsiclk
So I just can't imagine dropping the clk postfix is actually important.
[PATCH v4 2/2] clk: qcom: Add display clock controller driver for SM8150 and SM8250
Add support for the display clock controller found on SM8150 and SM8250.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1 +
drivers/clk/qcom/dispcc-sm8250.c | 1107 ++
3 files changed, 1117 insertions(+)
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 058327310c25..c4f1c5c4c442 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -413,6 +413,15 @@ config SDM_LPASSCC_845
Say Y if you want to use the LPASS branch clocks of the LPASS clock
controller to reset the LPASS subsystem.
+config SM_DISPCC_8250
+ tristate "SM8150 and SM8250 Display Clock Controller"
+ depends on SM_GCC_8150 || SM_GCC_8250
+ help
+ Support for the display clock controller on Qualcomm Technologies, Inc
+ SM8150 and SM8250 devices.
+ Say Y if you want to support display devices and functionality such as
+ splash screen.
+
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9677e769e7e9..d3c72354cb27 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
+obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..07a98d3f882d
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1107 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_CORE_BI_PLL_TEST_SE,
+ P_DISP_CC_PLL0_OUT_MAIN,
+ P_DISP_CC_PLL1_OUT_EVEN,
+ P_DISP_CC_PLL1_OUT_MAIN,
+ P_DP_PHY_PLL_LINK_CLK,
+ P_DP_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX1_PHY_PLL_LINK_CLK,
+ P_DPTX1_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX2_PHY_PLL_LINK_CLK,
+ P_DPTX2_PHY_PLL_VCO_DIV_CLK,
+ P_DSI0_PHY_PLL_OUT_BYTECLK,
+ P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_DSI1_PHY_PLL_OUT_BYTECLK,
+ P_DSI1_PHY_PLL_OUT_DSICLK,
+ P_EDP_PHY_PLL_LINK_CLK,
+ P_EDP_PHY_PLL_VCO_DIV_CLK,
+};
+
+static struct pll_vco vco_table[] = {
+ { 24960, 20, 0 },
+};
+
+static struct alpha_pll_config disp_cc_pll0_config = {
+ .l = 0x47,
+ .alpha = 0xE000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_init_data disp_cc_pll0_init = {
+ .name = "disp_cc_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+};
+
+static struct clk_alpha_pll disp_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = vco_table,
+ .num_vco = ARRAY_SIZE(vco_table),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = _cc_pll0_init
+};
+
+static struct alpha_pll_config disp_cc_pll1_config = {
+ .l = 0x1F,
+ .alpha = 0x4000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_init_data disp_cc_pll1_init = {
+ .name = "disp_cc_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+};
+
+static struct clk_alpha_pll disp_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = vco_table,
+ .num_vco = ARRAY_SIZE(vco_table),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr.hw.init = _cc_pll1_init
+};
+
+static const struct parent_map disp_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_DP_PHY_PLL_LINK_CLK, 1 },
+ { P_DP_PHY_PLL_VCO
[PATCH v4 0/2] SM8150 and SM8250 dispcc drivers
Add display clock drivers required to get DSI and DP displays working on SM8150 and SM8250 SoCs. Derived from downstream drivers. Notable changes compared to downstream: - EDP clks removed (nothing uses these even in downstream it seems) - freq_tbl values for dp_link clk is in Hz and not kHz v2: - updated dts example to reflect the change (first patch) - updated config_ctl_hi1_val in sm8250 dispcc to latest downstream v3: - combined dt-binding: "gcc_disp_gpll0_clk_src" is needed by sc7180 too - use the right order in drivers/clk/qcom/Kconfig v4: - Dropped combining yaml with sdm845/sc7180 dispcc - Combined drivers into one (sm8250 driver + patched pll config for sm8150) - Dropped uses of CLK_GET_RATE_NOCACHE (which was copied from downstream) - Dropped CLK_SET_RATE_PARENT from some DP clocks (upstream phy design) Jonathan Marek (2): dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings clk: qcom: Add display clock controller driver for SM8150 and SM8250 .../bindings/clock/qcom,dispcc-sm8x50.yaml| 93 ++ drivers/clk/qcom/Kconfig |9 + drivers/clk/qcom/Makefile |1 + drivers/clk/qcom/dispcc-sm8250.c | 1107 + .../dt-bindings/clock/qcom,dispcc-sm8150.h|1 + .../dt-bindings/clock/qcom,dispcc-sm8250.h| 66 + 6 files changed, 1277 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml create mode 100644 drivers/clk/qcom/dispcc-sm8250.c create mode 12 include/dt-bindings/clock/qcom,dispcc-sm8150.h create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h -- 2.26.1
[PATCH v4 1/2] dt-bindings: clock: add QCOM SM8150 and SM8250 display clock bindings
Add device tree bindings for display clock controller for
Qualcomm Technology Inc's SM8150 and SM8250 SoCs.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../bindings/clock/qcom,dispcc-sm8x50.yaml| 93 +++
.../dt-bindings/clock/qcom,dispcc-sm8150.h| 1 +
.../dt-bindings/clock/qcom,dispcc-sm8250.h| 66 +
3 files changed, 160 insertions(+)
create mode 100644
Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
create mode 12 include/dt-bindings/clock/qcom,dispcc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
new file mode 100644
index ..0cdf53f41f84
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm8x50.yaml
@@ -0,0 +1,93 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,dispcc-sm8x50.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Display Clock & Reset Controller Binding for SM8150/SM8250
+
+maintainers:
+ - Jonathan Marek
+
+description: |
+ Qualcomm display clock control module which supports the clocks, resets and
+ power domains on SM8150 and SM8250.
+
+ See also:
+dt-bindings/clock/qcom,dispcc-sm8150.h
+dt-bindings/clock/qcom,dispcc-sm8250.h
+
+properties:
+ compatible:
+enum:
+ - qcom,sm8150-dispcc
+ - qcom,sm8250-dispcc
+
+ clocks:
+items:
+ - description: Board XO source
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY
+ - description: VCO DIV clock from DP PHY
+
+ clock-names:
+items:
+ - const: bi_tcxo
+ - const: dsi0_phy_pll_out_byteclk
+ - const: dsi0_phy_pll_out_dsiclk
+ - const: dsi1_phy_pll_out_byteclk
+ - const: dsi1_phy_pll_out_dsiclk
+ - const: dp_phy_pll_link_clk
+ - const: dp_phy_pll_vco_div_clk
+
+ '#clock-cells':
+const: 1
+
+ '#reset-cells':
+const: 1
+
+ '#power-domain-cells':
+const: 1
+
+ reg:
+maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+#include
+clock-controller@af0 {
+ compatible = "qcom,sm8250-dispcc";
+ reg = <0x0af0 0x1>;
+ clocks = < RPMH_CXO_CLK>,
+ <_phy 0>,
+ <_phy 1>,
+ <_phy 0>,
+ <_phy 1>,
+ <_phy 0>,
+ <_phy 1>;
+ clock-names = "bi_tcxo",
+"dsi0_phy_pll_out_byteclk",
+"dsi0_phy_pll_out_dsiclk",
+"dsi1_phy_pll_out_byteclk",
+"dsi1_phy_pll_out_dsiclk",
+"dp_phy_pll_link_clk",
+"dp_phy_pll_vco_div_clk";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+};
+...
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h
b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
new file mode 12
index ..0312b4544acb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h
@@ -0,0 +1 @@
+qcom,dispcc-sm8250.h
\ No newline at end of file
diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h
b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
new file mode 100644
index ..fdaca6ad5c85
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H
+
+/* DISP_CC clock registers */
+#define DISP_CC_MDSS_AHB_CLK 0
+#define DISP_CC_MDSS_AHB_CLK_SRC 1
+#define DISP_CC_MDSS_BYTE0_CLK 2
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 3
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4
+#define DISP_CC_MDSS_BYTE0_INTF_CLK5
+#define DISP_CC_MDSS_BYTE1_CLK 6
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 7
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8
+#define DISP_CC_MDSS_BYTE1_INTF_CLK9
+#define DISP_CC_MDSS_DP_AUX1_CLK 10
+#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11
+#define DISP_CC_MDSS_DP_AUX_CLK12
+#define DISP_CC_MDSS_DP_AUX_CLK_SRC13
+#define DISP_CC_MDSS_DP_LINK1_CLK 14
+#define DI
Re: [PATCH v2 5/5] clk: qcom: add video clock controller driver for SM8250
On 9/23/20 7:30 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-23 09:07:16)
On 9/22/20 2:46 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-03 20:09:54)
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0_clk = {
+ .halt_reg = 0xd34,
+ .halt_check = BRANCH_HALT_SKIP, /* TODO: hw gated ? */
Is this resolved?
Downstream has this clock as BRANCH_HALT_VOTED, but with the upstream
venus driver (with patches to enable sm8250), that results in a
"video_cc_mvs0_clk status stuck at 'off" error. AFAIK venus
enables/disables this clock on its own (venus still works without
touching this clock), but I didn't want to remove this in case it might
be needed. I removed these clocks in the v3 I just sent.
Hmm. Does downstream use these clks? There have been some clk stuck
problems with venus recently that were attributed to improperly enabling
clks before enabling interconnects and power domains. Maybe it's the
same problem.
Yes, downstream uses these clks.
The "stuck" problem still happens if GSDCS/interconnects are always on,
and like I mentioned, venus works even with these clocks completely
removed.
I think venus controls these clocks (and downstream just happens to try
enabling it at a point where venus has already enabled it?). I'm not too
sure about this, it might have something to do with the GDSC having the
HW_CTRL flag too..
Re: [PATCH v3 6/7] clk: qcom: Add display clock controller driver for SM8150
On 9/22/20 3:04 PM, Stephen Boyd wrote: Quoting Jonathan Marek (2020-09-11 08:34:06) Add support for the display clock controller found on SM8150 based devices. This would allow display drivers to probe and control their clocks. Signed-off-by: Jonathan Marek --- drivers/clk/qcom/Kconfig |9 + drivers/clk/qcom/Makefile|1 + drivers/clk/qcom/dispcc-sm8150.c | 1152 ++ 3 files changed, 1162 insertions(+) create mode 100644 drivers/clk/qcom/dispcc-sm8150.c If the bindings are the same for these two drivers I wonder if there is anything different between the two. Maybe the two drivers can be one driver? Possibly, the biggest difference seems to be the plls (trion vs lucid, different config), which could be resolved in the probe() function. If you think combining the drivers is the right thing to do then I can do that.
Re: [PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
On 9/22/20 3:00 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-11 08:34:07)
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
[...]
+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+ { .fw_name = "bi_tcxo" },
+ { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+ { .fw_name = "dsi1_phy_pll_out_dsiclk" },
Can we remove clk postfix on these clk names?
This is consistent with the names used in both sdm845 and sc7180
drivers. If this should change then those should be changed too?
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
+ F(1920, P_BI_TCXO, 1, 0, 0),
+ F(3750, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
+ F(7500, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
+ .cmd_rcgr = 0x22bc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_3,
+ .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_ahb_clk_src",
+ .parent_data = disp_cc_parent_data_3,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_shared_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
+ F(1920, P_BI_TCXO, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+ .cmd_rcgr = 0x2110,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_byte0_clk_src",
+ .parent_data = disp_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
Why do we need CLK_GET_RATE_NOCACHE? Please remove it.
+ .ops = _byte2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+ .cmd_rcgr = 0x212c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_2,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_byte1_clk_src",
+ .parent_data = disp_cc_parent_data_2,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .ops = _byte2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
+ .cmd_rcgr = 0x2240,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_1,
+ .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_dp_aux1_clk_src",
+ .parent_data = disp_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
+ .cmd_rcgr = 0x21dc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_1,
+ .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_dp_aux_clk_src",
+ .parent_data = disp_cc_parent_data_1,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_ops,
+ },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
+ F(16200, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(27000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(54000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ F(81000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
+ .cmd_rcgr = 0x220c,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = disp_cc_parent_map_0,
+ .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "disp_cc_mdss_dp_link1_clk_src",
+ .parent_data = disp_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+ .ops = _rcg2_ops,
+ },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
+
Re: [PATCH v2 5/5] clk: qcom: add video clock controller driver for SM8250
On 9/22/20 2:46 PM, Stephen Boyd wrote:
Quoting Jonathan Marek (2020-09-03 20:09:54)
Add support for the video clock controller found on SM8250 based devices.
Derived from the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8250.c | 518 ++
3 files changed, 528 insertions(+)
create mode 100644 drivers/clk/qcom/videocc-sm8250.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 40d7ee9886c9..95efa38211d5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -453,6 +453,15 @@ config SM_VIDEOCC_8150
Say Y if you want to support video devices and functionality such as
video encode and decode.
+config SM_VIDEOCC_8250
+ tristate "SM8250 Video Clock Controller"
+ select SDM_GCC_8250
+ select QCOM_GDSC
+ help
+ Support for the video clock controller on SM8250 devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode and decode.
+
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6f4c580d2728..55fb20800b66 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
+obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/videocc-sm8250.c
b/drivers/clk/qcom/videocc-sm8250.c
new file mode 100644
index ..a814d10945c4
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sm8250.c
@@ -0,0 +1,518 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
[...]
+static struct clk_rcg2 video_cc_ahb_clk_src = {
+ .cmd_rcgr = 0xbd4,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_0,
+ .freq_tbl = ftbl_video_cc_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "video_cc_ahb_clk_src",
+ .parent_data = video_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_shared_ops,
+ },
+};
+
+static struct clk_rcg2 video_cc_xo_clk_src = {
+ .cmd_rcgr = 0xecc,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_0,
+ .freq_tbl = ftbl_video_cc_ahb_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "video_cc_xo_clk_src",
+ .parent_data = video_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
Similar critical clk comment, see below.
+ .ops = _rcg2_ops,
+ },
+};
+
+static struct clk_branch video_cc_ahb_clk = {
+ .halt_reg = 0xe58,
+ .halt_check = BRANCH_HALT,
+ .clkr = {
+ .enable_reg = 0xe58,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_ahb_clk",
+ .parent_data = &(const struct clk_parent_data){
+ .hw = _cc_ahb_clk_src.clkr.hw,
+ },
+ .num_parents = 1,
+ .flags = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
Similar critical clk comment, see below.
+ .ops = _branch2_ops,
+ },
+ },
+};
+
+static struct clk_branch video_cc_mvs0_clk = {
+ .halt_reg = 0xd34,
+ .halt_check = BRANCH_HALT_SKIP, /* TODO: hw gated ? */
Is this resolved?
Downstream has this clock as BRANCH_HALT_VOTED, but with the upstream
venus driver (with patches to enable sm8250), that results in a
"video_cc_mvs0_clk status stuck at 'off" error. AFAIK venus
enables/disables this clock on its own (venus still works without
touching this clock), but I didn't want to remove this in case it might
be needed. I removed these clocks in the v3 I just sent.
+ .clkr = {
+ .enable_reg = 0xd34,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "video_cc_mvs0_clk",
+ .parent_data = &(con
[PATCH v3 3/5] dt-bindings: clock: add SM8250 QCOM video clock bindings
Add device tree bindings for video clock controller for SM8250 SoCs. Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring --- .../bindings/clock/qcom,videocc.yaml | 4 ++- .../dt-bindings/clock/qcom,videocc-sm8250.h | 34 +++ 2 files changed, 37 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8250.h diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index bb1c1a841b68..567202942b88 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -11,12 +11,13 @@ maintainers: description: | Qualcomm video clock control module which supports the clocks, resets and - power domains on SDM845/SC7180/SM8150. + power domains on SDM845/SC7180/SM8150/SM8250. See also: dt-bindings/clock/qcom,videocc-sc7180.h dt-bindings/clock/qcom,videocc-sdm845.h dt-bindings/clock/qcom,videocc-sm8150.h +dt-bindings/clock/qcom,videocc-sm8250.h properties: compatible: @@ -24,6 +25,7 @@ properties: - qcom,sc7180-videocc - qcom,sdm845-videocc - qcom,sm8150-videocc + - qcom,sm8250-videocc clocks: items: diff --git a/include/dt-bindings/clock/qcom,videocc-sm8250.h b/include/dt-bindings/clock/qcom,videocc-sm8250.h new file mode 100644 index ..2b2b3867af25 --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8250.h @@ -0,0 +1,34 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8250_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_MVS0_CLK_SRC 0 +#define VIDEO_CC_MVS0C_CLK 1 +#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC2 +#define VIDEO_CC_MVS1_CLK_SRC 3 +#define VIDEO_CC_MVS1_DIV2_CLK 4 +#define VIDEO_CC_MVS1C_CLK 5 +#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC6 +#define VIDEO_CC_PLL0 7 +#define VIDEO_CC_PLL1 8 + +/* VIDEO_CC resets */ +#define VIDEO_CC_CVP_INTERFACE_BCR 0 +#define VIDEO_CC_CVP_MVS0_BCR 1 +#define VIDEO_CC_MVS0C_CLK_ARES2 +#define VIDEO_CC_CVP_MVS0C_BCR 3 +#define VIDEO_CC_CVP_MVS1_BCR 4 +#define VIDEO_CC_MVS1C_CLK_ARES5 +#define VIDEO_CC_CVP_MVS1C_BCR 6 + +#define MVS0C_GDSC 0 +#define MVS1C_GDSC 1 +#define MVS0_GDSC 2 +#define MVS1_GDSC 3 + +#endif -- 2.26.1
[PATCH v3 4/5] clk: qcom: add video clock controller driver for SM8150
Add support for the video clock controller found on SM8150 based devices.
Derived from the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8150.c | 276 ++
3 files changed, 286 insertions(+)
create mode 100644 drivers/clk/qcom/videocc-sm8150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 058327310c25..40d7ee9886c9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -444,6 +444,15 @@ config SM_GPUCC_8250
Say Y if you want to support graphics controller devices and
functionality such as 3D graphics.
+config SM_VIDEOCC_8150
+ tristate "SM8150 Video Clock Controller"
+ select SDM_GCC_8150
+ select QCOM_GDSC
+ help
+ Support for the video clock controller on SM8150 devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode and decode.
+
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9677e769e7e9..6f4c580d2728 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -68,6 +68,7 @@ obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
+obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/videocc-sm8150.c
b/drivers/clk/qcom/videocc-sm8150.c
new file mode 100644
index ..3087e2ec8fd4
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sm8150.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "common.h"
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "reset.h"
+#include "gdsc.h"
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_CORE_BI_PLL_TEST_SE,
+ P_VIDEO_PLL0_OUT_EVEN,
+ P_VIDEO_PLL0_OUT_MAIN,
+ P_VIDEO_PLL0_OUT_ODD,
+};
+
+static struct pll_vco trion_vco[] = {
+ { 24960, 20, 0 },
+};
+
+static struct alpha_pll_config video_pll0_config = {
+ .l = 0x14,
+ .alpha = 0xD555,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2267,
+ .config_ctl_hi1_val = 0x0024,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x00D0,
+};
+
+static struct clk_alpha_pll video_pll0 = {
+ .offset = 0x42c,
+ .vco_table = trion_vco,
+ .num_vco = ARRAY_SIZE(trion_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "video_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_trion_ops,
+ },
+ },
+};
+
+static const struct parent_map video_cc_parent_map_0[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_PLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_0[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = _pll0.clkr.hw },
+};
+
+static const struct freq_tbl ftbl_video_cc_iris_clk_src[] = {
+ F(1920, P_BI_TCXO, 1, 0, 0),
+ F(2, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(24000, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(33800, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(36500, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(44400, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ F(53300, P_VIDEO_PLL0_OUT_MAIN, 2, 0, 0),
+ { }
+};
+
+static struct clk_rcg2 video_cc_iris_clk_src = {
+ .cmd_rcgr = 0x7f0,
+ .mnd_width = 0,
+ .hid_width = 5,
+ .parent_map = video_cc_parent_map_0,
+ .freq_tbl = ftbl_video_cc_iris_clk_src,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "video_cc_iris_clk_src",
+ .parent_data = video_cc_parent_data_0,
+ .num_parents = ARRAY_SIZE(video_cc_parent_data_0),
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = _rcg2_shared_ops,
+ },
+};
+
+static struct clk_branch video_cc_iris_ahb_clk = {
+ .halt_reg = 0x8f4,
+ .halt_check = BRANCH_VOTED,
+
[PATCH v3 5/5] clk: qcom: add video clock controller driver for SM8250
Add support for the video clock controller found on SM8250 based devices.
Derived from the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig | 9 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/videocc-sm8250.c | 369 ++
3 files changed, 379 insertions(+)
create mode 100644 drivers/clk/qcom/videocc-sm8250.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 40d7ee9886c9..95efa38211d5 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -453,6 +453,15 @@ config SM_VIDEOCC_8150
Say Y if you want to support video devices and functionality such as
video encode and decode.
+config SM_VIDEOCC_8250
+ tristate "SM8250 Video Clock Controller"
+ select SDM_GCC_8250
+ select QCOM_GDSC
+ help
+ Support for the video clock controller on SM8250 devices.
+ Say Y if you want to support video devices and functionality such as
+ video encode and decode.
+
config SPMI_PMIC_CLKDIV
tristate "SPMI PMIC clkdiv Support"
depends on SPMI || COMPILE_TEST
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 6f4c580d2728..55fb20800b66 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -69,6 +69,7 @@ obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
obj-$(CONFIG_SM_GPUCC_8250) += gpucc-sm8250.o
obj-$(CONFIG_SM_VIDEOCC_8150) += videocc-sm8150.o
+obj-$(CONFIG_SM_VIDEOCC_8250) += videocc-sm8250.o
obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
diff --git a/drivers/clk/qcom/videocc-sm8250.c
b/drivers/clk/qcom/videocc-sm8250.c
new file mode 100644
index ..2797c61f5938
--- /dev/null
+++ b/drivers/clk/qcom/videocc-sm8250.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "reset.h"
+#include "gdsc.h"
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_CORE_BI_PLL_TEST_SE,
+ P_VIDEO_PLL0_OUT_MAIN,
+ P_VIDEO_PLL1_OUT_MAIN,
+};
+
+static struct pll_vco lucid_vco[] = {
+ { 24960, 20, 0 },
+};
+
+static const struct alpha_pll_config video_pll0_config = {
+ .l = 0x25,
+ .alpha = 0x8000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_alpha_pll video_pll0 = {
+ .offset = 0x42c,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "video_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config video_pll1_config = {
+ .l = 0x2B,
+ .alpha = 0xC000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_alpha_pll video_pll1 = {
+ .offset = 0x7d0,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "video_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct parent_map video_cc_parent_map_1[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_PLL0_OUT_MAIN, 1 },
+};
+
+static const struct clk_parent_data video_cc_parent_data_1[] = {
+ { .fw_name = "bi_tcxo" },
+ { .hw = _pll0.clkr.hw },
+};
+
+static const struct parent_map video_cc_parent_map_2[] = {
+ { P_BI_TCXO, 0 },
+ { P_VIDEO_PLL1_OUT_MAIN, 1 },
[PATCH v3 0/5] SM8150 and SM8250 videocc drivers
Add videocc drivers for SM8150/SM8250 required to boot and use venus.
v2:
- fixed dt_binding_check/checkpatch warnings in SM8250 bindings
- added 19.2Mhz in SM8250 freq tbls for consistency with other videocc
v3:
- sorted sc7180 to come before sdm845 in combined yaml
- deleted some SM8250 clocks (hardware controlled and always on)
Jonathan Marek (5):
dt-bindings: clock: combine qcom,sdm845-videocc and
qcom,sc7180-videocc
dt-bindings: clock: add SM8150 QCOM video clock bindings
dt-bindings: clock: add SM8250 QCOM video clock bindings
clk: qcom: add video clock controller driver for SM8150
clk: qcom: add video clock controller driver for SM8250
.../bindings/clock/qcom,sc7180-videocc.yaml | 65 ---
...,sdm845-videocc.yaml => qcom,videocc.yaml} | 18 +-
drivers/clk/qcom/Kconfig | 18 +
drivers/clk/qcom/Makefile | 2 +
drivers/clk/qcom/videocc-sm8150.c | 276 +
drivers/clk/qcom/videocc-sm8250.c | 369 ++
.../dt-bindings/clock/qcom,videocc-sm8150.h | 25 ++
.../dt-bindings/clock/qcom,videocc-sm8250.h | 34 ++
8 files changed, 737 insertions(+), 70 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-videocc.yaml =>
qcom,videocc.yaml} (68%)
create mode 100644 drivers/clk/qcom/videocc-sm8150.c
create mode 100644 drivers/clk/qcom/videocc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8250.h
--
2.26.1
[PATCH v3 2/5] dt-bindings: clock: add SM8150 QCOM video clock bindings
Add device tree bindings for video clock controller for SM8150 SoCs. Signed-off-by: Jonathan Marek Reviewed-by: Rob Herring --- .../bindings/clock/qcom,videocc.yaml | 4 ++- .../dt-bindings/clock/qcom,videocc-sm8150.h | 25 +++ 2 files changed, 28 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,videocc-sm8150.h diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml index 874be03c33f5..bb1c1a841b68 100644 --- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml @@ -11,17 +11,19 @@ maintainers: description: | Qualcomm video clock control module which supports the clocks, resets and - power domains on SDM845/SC7180. + power domains on SDM845/SC7180/SM8150. See also: dt-bindings/clock/qcom,videocc-sc7180.h dt-bindings/clock/qcom,videocc-sdm845.h +dt-bindings/clock/qcom,videocc-sm8150.h properties: compatible: enum: - qcom,sc7180-videocc - qcom,sdm845-videocc + - qcom,sm8150-videocc clocks: items: diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h new file mode 100644 index ..e24ee840cfdb --- /dev/null +++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H + +/* VIDEO_CC clocks */ +#define VIDEO_CC_IRIS_AHB_CLK 0 +#define VIDEO_CC_IRIS_CLK_SRC 1 +#define VIDEO_CC_MVS0_CORE_CLK 2 +#define VIDEO_CC_MVS1_CORE_CLK 3 +#define VIDEO_CC_MVSC_CORE_CLK 4 +#define VIDEO_CC_PLL0 5 + +/* VIDEO_CC Resets */ +#define VIDEO_CC_MVSC_CORE_CLK_BCR 0 + +/* VIDEO_CC GDSCRs */ +#define VENUS_GDSC 0 +#define VCODEC0_GDSC 1 +#define VCODEC1_GDSC 2 + +#endif -- 2.26.1
[PATCH v3 1/5] dt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 videocc bindings.
Signed-off-by: Jonathan Marek
Reviewed-by: Rob Herring
---
.../bindings/clock/qcom,sc7180-videocc.yaml | 65 ---
...,sdm845-videocc.yaml => qcom,videocc.yaml} | 14 ++--
2 files changed, 9 insertions(+), 70 deletions(-)
delete mode 100644
Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-videocc.yaml =>
qcom,videocc.yaml} (76%)
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
b/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
deleted file mode 100644
index 2feea2b91aa9..
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-videocc.yaml
+++ /dev/null
@@ -1,65 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-videocc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Video Clock & Reset Controller Binding for SC7180
-
-maintainers:
- - Taniya Das
-
-description: |
- Qualcomm video clock control module which supports the clocks, resets and
- power domains on SC7180.
-
- See also dt-bindings/clock/qcom,videocc-sc7180.h.
-
-properties:
- compatible:
-const: qcom,sc7180-videocc
-
- clocks:
-items:
- - description: Board XO source
-
- clock-names:
-items:
- - const: bi_tcxo
-
- '#clock-cells':
-const: 1
-
- '#reset-cells':
-const: 1
-
- '#power-domain-cells':
-const: 1
-
- reg:
-maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
-#include
-clock-controller@ab0 {
- compatible = "qcom,sc7180-videocc";
- reg = <0x0ab0 0x1>;
- clocks = < RPMH_CXO_CLK>;
- clock-names = "bi_tcxo";
- #clock-cells = <1>;
- #reset-cells = <1>;
- #power-domain-cells = <1>;
-};
-...
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
similarity index 76%
rename from Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
rename to Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index f7a0cf53d5f0..874be03c33f5 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -1,23 +1,27 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-videocc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,videocc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Video Clock & Reset Controller Binding for SDM845
+title: Qualcomm Video Clock & Reset Controller Binding
maintainers:
- Taniya Das
description: |
Qualcomm video clock control module which supports the clocks, resets and
- power domains on SDM845.
+ power domains on SDM845/SC7180.
- See also dt-bindings/clock/qcom,videocc-sdm845.h.
+ See also:
+dt-bindings/clock/qcom,videocc-sc7180.h
+dt-bindings/clock/qcom,videocc-sdm845.h
properties:
compatible:
-const: qcom,sdm845-videocc
+enum:
+ - qcom,sc7180-videocc
+ - qcom,sdm845-videocc
clocks:
items:
--
2.26.1
Re: [Freedreno] [PATCH] drm/msm: Fix the a650 hw_apriv check
On 9/15/20 11:56 AM, Jordan Crouse wrote:
Commit 604234f33658 ("drm/msm: Enable expanded apriv support for a650")
was checking the result of adreno_is_a650() before the gpu revision
got probed in adreno_gpu_init() so it was always coming across as
false. Snoop into the revision ID ahead of time to correctly set the
hw_apriv flag so that it can be used by msm_gpu to properly setup
global buffers.
Fixes: 604234f33658 ("drm/msm: Enable expanded apriv support for a650")
Signed-off-by: Jordan Crouse
Tested-by: Jonathan Marek
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 74bc27eb4203..f3b6d93c207c 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1048,6 +1048,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
{
struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev;
+ struct adreno_platform_config *config = pdev->dev.platform_data;
+ const struct adreno_info *info;
struct device_node *node;
struct a6xx_gpu *a6xx_gpu;
struct adreno_gpu *adreno_gpu;
@@ -1064,7 +1066,14 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
adreno_gpu->registers = NULL;
adreno_gpu->reg_offsets = a6xx_register_offsets;
- if (adreno_is_a650(adreno_gpu))
+ /*
+* We need to know the platform type before calling into adreno_gpu_init
+* so that the hw_apriv flag can be correctly set. Snoop into the info
+* and grab the revision number
+*/
+ info = adreno_info(config->rev);
+
+ if (info && info->revn == 650)
adreno_gpu->base.hw_apriv = true;
ret = adreno_gpu_init(dev, pdev, adreno_gpu, , 1);
Re: [PATCH v2 0/7] SM8150 and SM8250 dispcc drivers
On 9/14/20 7:57 PM, Stephen Boyd wrote: Quoting Dmitry Baryshkov (2020-09-07 07:25:45) On 04/09/2020 01:26, Jonathan Marek wrote: Add display clock drivers required to get DSI and DP displays working on SM8150 and SM8250 SoCs. Derived from downstream drivers. Notable changes compared to downstream: - EDP clks removed (nothing uses these even in downstream it seems) - freq_tbl values for dp_link clk is in Hz and not kHz On SM8250: Tested-by: Dmitry Baryshkov Can this be carried to v3? I already included the tag in the last commit which adds the SM8250 dispcc driver (probably should've included it in the SM8250 dt-bindings patch too though).
[PATCH v2 1/3] drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timing
The clk_pre/clk_post values in shared_timings are used instead, and these
are unused.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
index ef8672d7b123..886a9e3b44b5 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
@@ -50,8 +50,6 @@ extern const struct msm_dsi_phy_cfg dsi_phy_10nm_cfgs;
extern const struct msm_dsi_phy_cfg dsi_phy_10nm_8998_cfgs;
struct msm_dsi_dphy_timing {
- u32 clk_pre;
- u32 clk_post;
u32 clk_zero;
u32 clk_trail;
u32 clk_prepare;
--
2.26.1
[PATCH v2 0/3] Add support for SM8150 and SM8250 DSI.
Note I haven't tested SM8150 recently, but DSI is almost identical to SM8250. v2: - added workaround for 5GHz max_rate overflowing in 32-bit builds (based on robclark's suggestion) - Updated Kconfig option to mention SM8250 and not just SM8150 Jonathan Marek (3): drm/msm/dsi: remove unused clk_pre/clk_post in msm_dsi_dphy_timing drm/msm/dsi: add DSI config for sm8150 and sm8250 drm/msm/dsi: add support for 7nm DSI PHY/PLL .../devicetree/bindings/display/msm/dsi.txt | 6 +- drivers/gpu/drm/msm/Kconfig | 8 + drivers/gpu/drm/msm/Makefile | 2 + drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi.xml.h | 423 drivers/gpu/drm/msm/dsi/dsi_cfg.c | 5 +- drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 102 ++ drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 6 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 255 + drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 4 + drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 10 + drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 904 ++ 13 files changed, 1724 insertions(+), 5 deletions(-) create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c -- 2.26.1
[PATCH v2 3/3] drm/msm/dsi: add support for 7nm DSI PHY/PLL
This adds support for the 7nm ("V4") DSI PHY/PLL for sm8150 and sm8250.
Implementation is based on 10nm driver, but updated based on the downstream
7nm driver.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
.../devicetree/bindings/display/msm/dsi.txt | 6 +-
drivers/gpu/drm/msm/Kconfig | 8 +
drivers/gpu/drm/msm/Makefile | 2 +
drivers/gpu/drm/msm/dsi/dsi.h | 2 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 423
drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 102 ++
drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 4 +
drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 255 +
drivers/gpu/drm/msm/dsi/pll/dsi_pll.c | 4 +
drivers/gpu/drm/msm/dsi/pll/dsi_pll.h | 10 +
drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c | 904 ++
11 files changed, 1718 insertions(+), 2 deletions(-)
create mode 100644 drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
create mode 100644 drivers/gpu/drm/msm/dsi/pll/dsi_pll_7nm.c
diff --git a/Documentation/devicetree/bindings/display/msm/dsi.txt
b/Documentation/devicetree/bindings/display/msm/dsi.txt
index 7884fd7a85c1..b9a64d3ff184 100644
--- a/Documentation/devicetree/bindings/display/msm/dsi.txt
+++ b/Documentation/devicetree/bindings/display/msm/dsi.txt
@@ -90,6 +90,8 @@ Required properties:
* "qcom,dsi-phy-14nm-660"
* "qcom,dsi-phy-10nm"
* "qcom,dsi-phy-10nm-8998"
+ * "qcom,dsi-phy-7nm"
+ * "qcom,dsi-phy-7nm-8150"
- reg: Physical base address and length of the registers of PLL, PHY. Some
revisions require the PHY regulator base address, whereas others require the
PHY lane base address. See below for each PHY revision.
@@ -98,7 +100,7 @@ Required properties:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_regulator"
- For DSI 14nm and 10nm PHYs:
+ For DSI 14nm, 10nm and 7nm PHYs:
* "dsi_pll"
* "dsi_phy"
* "dsi_phy_lane"
@@ -116,7 +118,7 @@ Required properties:
- vcca-supply: phandle to vcca regulator device node
For 14nm PHY:
- vcca-supply: phandle to vcca regulator device node
- For 10nm PHY:
+ For 10nm and 7nm PHY:
- vdds-supply: phandle to vdds regulator device node
Optional properties:
diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
index 6deaa7d01654..5c55cd0ce9f9 100644
--- a/drivers/gpu/drm/msm/Kconfig
+++ b/drivers/gpu/drm/msm/Kconfig
@@ -110,3 +110,11 @@ config DRM_MSM_DSI_10NM_PHY
default y
help
Choose this option if DSI PHY on SDM845 is used on the platform.
+
+config DRM_MSM_DSI_7NM_PHY
+ bool "Enable DSI 7nm PHY driver in MSM DRM (used by SM8150/SM8250)"
+ depends on DRM_MSM_DSI
+ default y
+ help
+ Choose this option if DSI PHY on SM8150/SM8250 is used on the
+ platform.
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 42f8aae28b31..c65cdd6397a3 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -119,6 +119,7 @@ msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o
msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o
msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o
+msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/phy/dsi_phy_7nm.o
ifeq ($(CONFIG_DRM_MSM_DSI_PLL),y)
msm-y += dsi/pll/dsi_pll.o
@@ -126,6 +127,7 @@ msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/pll/dsi_pll_28nm.o
msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/pll/dsi_pll_28nm_8960.o
msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/pll/dsi_pll_14nm.o
msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/pll/dsi_pll_10nm.o
+msm-$(CONFIG_DRM_MSM_DSI_7NM_PHY) += dsi/pll/dsi_pll_7nm.o
endif
obj-$(CONFIG_DRM_MSM) += msm.o
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 4de771d6f0be..78ef5d4ed922 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -30,6 +30,8 @@ enum msm_dsi_phy_type {
MSM_DSI_PHY_28NM_8960,
MSM_DSI_PHY_14NM,
MSM_DSI_PHY_10NM,
+ MSM_DSI_PHY_7NM,
+ MSM_DSI_PHY_7NM_V4_1,
MSM_DSI_PHY_MAX
};
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h
b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 8e536e060070..50eb4d1b8fdd 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -1886,5 +1886,428 @@ static inline uint32_t
REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x
#define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x01a0
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID0 0x
+
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID1 0x0004
+
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID2 0x0008
+
+#define REG_DSI_7nm_PHY_CMN_REVISION_ID3
[PATCH v2 2/3] drm/msm/dsi: add DSI config for sm8150 and sm8250
This allows DSI driver to work with sm8150 and sm8250. The sdm845 config
is re-used as the config is the same.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov (SM8250)
---
drivers/gpu/drm/msm/dsi/dsi_cfg.c | 5 -
drivers/gpu/drm/msm/dsi/dsi_cfg.h | 2 ++
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
index f892f2cbe8bb..b2ff68a15791 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c
@@ -265,9 +265,12 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[]
= {
_dsi_cfg, _dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_2_1,
_dsi_cfg, _dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_3_0,
+ _dsi_cfg, _dsi_6g_v2_host_ops},
+ {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_0,
+ _dsi_cfg, _dsi_6g_v2_host_ops},
{MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_4_1,
_dsi_cfg, _dsi_6g_v2_host_ops},
-
};
const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
index efd469d1db45..ade9b609c7d9 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h
+++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h
@@ -21,6 +21,8 @@
#define MSM_DSI_6G_VER_MINOR_V2_1_00x2001
#define MSM_DSI_6G_VER_MINOR_V2_2_00x2000
#define MSM_DSI_6G_VER_MINOR_V2_2_10x20020001
+#define MSM_DSI_6G_VER_MINOR_V2_3_00x2003
+#define MSM_DSI_6G_VER_MINOR_V2_4_00x2004
#define MSM_DSI_6G_VER_MINOR_V2_4_10x20040001
#define MSM_DSI_V2_VER_MINOR_8064 0x0
--
2.26.1
[PATCH v3 2/7] arm64: dts: qcom: sdm845-dispcc: same name for dp_phy clocks as sc7180
This makes it easier to combine dt bindings for sdm845/sc7180 dispcc.
Note: nothing upstream provides these clocks and the sdm845 dispcc driver
hasn't switched to using .fw_name for these clocks (these properties are
ignored), so changing this shouldn't be a problem.
Signed-off-by: Jonathan Marek
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2884577dcb77..8184d6204b33 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -4139,8 +4139,8 @@ dispcc: clock-controller@af0 {
"dsi0_phy_pll_out_dsiclk",
"dsi1_phy_pll_out_byteclk",
"dsi1_phy_pll_out_dsiclk",
- "dp_link_clk_divsel_ten",
- "dp_vco_divided_clk_src_mux";
+ "dp_phy_pll_link_clk",
+ "dp_phy_pll_vco_div_clk";
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
--
2.26.1
[PATCH v3 1/7] dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as sc7180
This makes it easier to combine dt bindings for sdm845/sc7180 dispcc. Note: nothing upstream provides these clocks and the sdm845 dispcc driver hasn't switched to using .fw_name for these clocks (these properties are ignored), so changing this shouldn't be a problem. Signed-off-by: Jonathan Marek --- .../devicetree/bindings/clock/qcom,sdm845-dispcc.yaml | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml index 4a3be733d042..ead44705333b 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml @@ -43,8 +43,8 @@ properties: - const: dsi0_phy_pll_out_dsiclk - const: dsi1_phy_pll_out_byteclk - const: dsi1_phy_pll_out_dsiclk - - const: dp_link_clk_divsel_ten - - const: dp_vco_divided_clk_src_mux + - const: dp_phy_pll_link_clk + - const: dp_phy_pll_vco_div_clk '#clock-cells': const: 1 @@ -92,8 +92,8 @@ examples: "dsi0_phy_pll_out_dsiclk", "dsi1_phy_pll_out_byteclk", "dsi1_phy_pll_out_dsiclk", -"dp_link_clk_divsel_ten", -"dp_vco_divided_clk_src_mux"; +"dp_phy_pll_link_clk", +"dp_phy_pll_vco_div_clk"; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; -- 2.26.1
[PATCH v3 5/7] dt-bindings: clock: Introduce QCOM SM8250 display clock bindings
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8250 SoCs. Signed-off-by: Jonathan Marek --- .../bindings/clock/qcom,dispcc.yaml | 4 +- .../dt-bindings/clock/qcom,dispcc-sm8250.h| 66 +++ 2 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml index 9702066cda38..ca4c4e944c6c 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml @@ -11,12 +11,13 @@ maintainers: description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SDM845/SC7180/SM8150. + power domains on SDM845/SC7180/SM8150/SM8250. See also: dt-bindings/clock/qcom,dispcc-sdm845.h dt-bindings/clock/qcom,dispcc-sc7180.h dt-bindings/clock/qcom,dispcc-sm8150.h +dt-bindings/clock/qcom,dispcc-sm8250.h properties: compatible: @@ -24,6 +25,7 @@ properties: - qcom,sdm845-dispcc - qcom,sc7180-dispcc - qcom,sm8150-dispcc + - qcom,sm8250-dispcc # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. # The code had to use hardcoded mechanisms to find the input clocks. diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h new file mode 100644 index ..fdaca6ad5c85 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h @@ -0,0 +1,66 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8250_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AHB_CLK_SRC 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK5 +#define DISP_CC_MDSS_BYTE1_CLK 6 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 +#define DISP_CC_MDSS_BYTE1_INTF_CLK9 +#define DISP_CC_MDSS_DP_AUX1_CLK 10 +#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 +#define DISP_CC_MDSS_DP_AUX_CLK12 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC13 +#define DISP_CC_MDSS_DP_LINK1_CLK 14 +#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 15 +#define DISP_CC_MDSS_DP_LINK1_DIV_CLK_SRC 16 +#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 17 +#define DISP_CC_MDSS_DP_LINK_CLK 18 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 19 +#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 20 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 21 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 22 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 23 +#define DISP_CC_MDSS_DP_PIXEL2_CLK 24 +#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 25 +#define DISP_CC_MDSS_DP_PIXEL_CLK 26 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 27 +#define DISP_CC_MDSS_ESC0_CLK 28 +#define DISP_CC_MDSS_ESC0_CLK_SRC 29 +#define DISP_CC_MDSS_ESC1_CLK 30 +#define DISP_CC_MDSS_ESC1_CLK_SRC 31 +#define DISP_CC_MDSS_MDP_CLK 32 +#define DISP_CC_MDSS_MDP_CLK_SRC 33 +#define DISP_CC_MDSS_MDP_LUT_CLK 34 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 35 +#define DISP_CC_MDSS_PCLK0_CLK 36 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 37 +#define DISP_CC_MDSS_PCLK1_CLK 38 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 39 +#define DISP_CC_MDSS_ROT_CLK 40 +#define DISP_CC_MDSS_ROT_CLK_SRC 41 +#define DISP_CC_MDSS_RSCC_AHB_CLK 42 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK43 +#define DISP_CC_MDSS_VSYNC_CLK 44 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 45 +#define DISP_CC_PLL0 46 +#define DISP_CC_PLL1 47 + +/* DISP_CC Reset */ +#define DISP_CC_MDSS_CORE_BCR 0 +#define DISP_CC_MDSS_RSCC_BCR 1 + +/* DISP_CC GDSCR */ +#define MDSS_GDSC 0 + +#endif -- 2.26.1
[PATCH v3 4/7] dt-bindings: clock: Introduce QCOM SM8150 display clock bindings
Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 SoCs. Signed-off-by: Jonathan Marek --- .../bindings/clock/qcom,dispcc.yaml | 10 +-- .../dt-bindings/clock/qcom,dispcc-sm8150.h| 69 +++ 2 files changed, 75 insertions(+), 4 deletions(-) create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml index 7d5b25dfe0b1..9702066cda38 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml @@ -11,26 +11,28 @@ maintainers: description: | Qualcomm display clock control module which supports the clocks, resets and - power domains on SDM845/SC7180. + power domains on SDM845/SC7180/SM8150. See also: dt-bindings/clock/qcom,dispcc-sdm845.h dt-bindings/clock/qcom,dispcc-sc7180.h +dt-bindings/clock/qcom,dispcc-sm8150.h properties: compatible: enum: - qcom,sdm845-dispcc - qcom,sc7180-dispcc + - qcom,sm8150-dispcc # NOTE: sdm845.dtsi existed for quite some time and specified no clocks. # The code had to use hardcoded mechanisms to find the input clocks. # New dts files should have these clocks. clocks: -minItems: 8 +minItems: 7 items: - description: Board XO source - - description: GPLL0 source from GCC + - description: GPLL0 source from GCC (sdm845/sc7180 only) - description: GPLL0 div source from GCC (sdm845 only) - description: Byte clock from DSI PHY0 - description: Pixel clock from DSI PHY0 @@ -40,7 +42,7 @@ properties: - description: VCO DIV clock from DP PHY clock-names: -minItems: 8 +minItems: 7 items: - const: bi_tcxo - const: gcc_disp_gpll0_clk_src diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8150.h b/include/dt-bindings/clock/qcom,dispcc-sm8150.h new file mode 100644 index ..2b96b0b4fe97 --- /dev/null +++ b/include/dt-bindings/clock/qcom,dispcc-sm8150.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8150_H + +/* DISP_CC clock registers */ +#define DISP_CC_MDSS_AHB_CLK 0 +#define DISP_CC_MDSS_AHB_CLK_SRC 1 +#define DISP_CC_MDSS_BYTE0_CLK 2 +#define DISP_CC_MDSS_BYTE0_CLK_SRC 3 +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 4 +#define DISP_CC_MDSS_BYTE0_INTF_CLK5 +#define DISP_CC_MDSS_BYTE1_CLK 6 +#define DISP_CC_MDSS_BYTE1_CLK_SRC 7 +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 8 +#define DISP_CC_MDSS_BYTE1_INTF_CLK9 +#define DISP_CC_MDSS_DP_AUX1_CLK 10 +#define DISP_CC_MDSS_DP_AUX1_CLK_SRC 11 +#define DISP_CC_MDSS_DP_AUX_CLK12 +#define DISP_CC_MDSS_DP_AUX_CLK_SRC13 +#define DISP_CC_MDSS_DP_CRYPTO1_CLK14 +#define DISP_CC_MDSS_DP_CRYPTO1_CLK_SRC15 +#define DISP_CC_MDSS_DP_CRYPTO_CLK 16 +#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 17 +#define DISP_CC_MDSS_DP_LINK1_CLK 18 +#define DISP_CC_MDSS_DP_LINK1_CLK_SRC 19 +#define DISP_CC_MDSS_DP_LINK1_INTF_CLK 20 +#define DISP_CC_MDSS_DP_LINK_CLK 21 +#define DISP_CC_MDSS_DP_LINK_CLK_SRC 22 +#define DISP_CC_MDSS_DP_LINK_INTF_CLK 23 +#define DISP_CC_MDSS_DP_PIXEL1_CLK 24 +#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC 25 +#define DISP_CC_MDSS_DP_PIXEL2_CLK 26 +#define DISP_CC_MDSS_DP_PIXEL2_CLK_SRC 27 +#define DISP_CC_MDSS_DP_PIXEL_CLK 28 +#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 29 +#define DISP_CC_MDSS_ESC0_CLK 30 +#define DISP_CC_MDSS_ESC0_CLK_SRC 31 +#define DISP_CC_MDSS_ESC1_CLK 32 +#define DISP_CC_MDSS_ESC1_CLK_SRC 33 +#define DISP_CC_MDSS_MDP_CLK 34 +#define DISP_CC_MDSS_MDP_CLK_SRC 35 +#define DISP_CC_MDSS_MDP_LUT_CLK 36 +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 37 +#define DISP_CC_MDSS_PCLK0_CLK 38 +#define DISP_CC_MDSS_PCLK0_CLK_SRC 39 +#define DISP_CC_MDSS_PCLK1_CLK 40 +#define DISP_CC_MDSS_PCLK1_CLK_SRC 41 +#define DISP_CC_MDSS_ROT_CLK 42 +#define DISP_CC_MDSS_ROT_CLK_SRC 43 +#define DISP_CC_MDSS_RSCC_AHB_CLK 44 +#define DISP_CC_MDSS_RSCC_VSYNC_CLK45 +#define DISP_CC_MDSS_VSYNC_CLK 46 +#define DISP_CC_MDSS_VSYNC_CLK_SRC 47 +#define DISP_CC_PLL0 48 +#define DISP_CC_PLL1 49 + +/* DISP_CC Reset
[PATCH v3 7/7] clk: qcom: Add display clock controller driver for SM8250
Add support for the display clock controller found on SM8250
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Jonathan Marek
Tested-by: Dmitry Baryshkov
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1 +
drivers/clk/qcom/dispcc-sm8250.c | 1100 ++
3 files changed, 1110 insertions(+)
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index c15907842cb3..c81eae64b809 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -422,6 +422,15 @@ config SM_DISPCC_8150
Say Y if you want to support display devices and functionality such as
splash screen.
+config SM_DISPCC_8250
+ tristate "SM8250 Display Clock Controller"
+ select SM_GCC_8250
+ help
+ Support for the display clock controller on Qualcomm Technologies, Inc
+ SM8250 devices.
+ Say Y if you want to support display devices and functionality such as
+ splash screen.
+
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index edea87f1c7e6..8eb395d02a32 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -65,6 +65,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o
+obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
new file mode 100644
index ..7c0f384a3a42
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_CHIP_SLEEP_CLK,
+ P_CORE_BI_PLL_TEST_SE,
+ P_DISP_CC_PLL0_OUT_MAIN,
+ P_DISP_CC_PLL1_OUT_EVEN,
+ P_DISP_CC_PLL1_OUT_MAIN,
+ P_DP_PHY_PLL_LINK_CLK,
+ P_DP_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX1_PHY_PLL_LINK_CLK,
+ P_DPTX1_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX2_PHY_PLL_LINK_CLK,
+ P_DPTX2_PHY_PLL_VCO_DIV_CLK,
+ P_DSI0_PHY_PLL_OUT_BYTECLK,
+ P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_DSI1_PHY_PLL_OUT_BYTECLK,
+ P_DSI1_PHY_PLL_OUT_DSICLK,
+ P_EDP_PHY_PLL_LINK_CLK,
+ P_EDP_PHY_PLL_VCO_DIV_CLK,
+};
+
+static struct pll_vco lucid_vco[] = {
+ { 24960, 20, 0 },
+};
+
+static const struct alpha_pll_config disp_cc_pll0_config = {
+ .l = 0x47,
+ .alpha = 0xE000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_alpha_pll disp_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "disp_cc_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_lucid_ops,
+ },
+ },
+};
+
+static const struct alpha_pll_config disp_cc_pll1_config = {
+ .l = 0x1F,
+ .alpha = 0x4000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2261,
+ .config_ctl_hi1_val = 0x329A699C,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x,
+};
+
+static struct clk_alpha_pll disp_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = lucid_vco,
+ .num_vco = ARRAY_SIZE(lucid_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "disp_cc_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents
[PATCH v3 6/7] clk: qcom: Add display clock controller driver for SM8150
Add support for the display clock controller found on SM8150
based devices. This would allow display drivers to probe and
control their clocks.
Signed-off-by: Jonathan Marek
---
drivers/clk/qcom/Kconfig |9 +
drivers/clk/qcom/Makefile|1 +
drivers/clk/qcom/dispcc-sm8150.c | 1152 ++
3 files changed, 1162 insertions(+)
create mode 100644 drivers/clk/qcom/dispcc-sm8150.c
diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 058327310c25..c15907842cb3 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -413,6 +413,15 @@ config SDM_LPASSCC_845
Say Y if you want to use the LPASS branch clocks of the LPASS clock
controller to reset the LPASS subsystem.
+config SM_DISPCC_8150
+ tristate "SM8150 Display Clock Controller"
+ select SM_GCC_8150
+ help
+ Support for the display clock controller on Qualcomm Technologies, Inc
+ SM8150 devices.
+ Say Y if you want to support display devices and functionality such as
+ splash screen.
+
config SM_GCC_8150
tristate "SM8150 Global Clock Controller"
help
diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
index 9677e769e7e9..edea87f1c7e6 100644
--- a/drivers/clk/qcom/Makefile
+++ b/drivers/clk/qcom/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
+obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o
obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o
diff --git a/drivers/clk/qcom/dispcc-sm8150.c b/drivers/clk/qcom/dispcc-sm8150.c
new file mode 100644
index ..0e4178df678f
--- /dev/null
+++ b/drivers/clk/qcom/dispcc-sm8150.c
@@ -0,0 +1,1152 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include
+#include
+#include
+#include
+#include
+
+#include
+
+#include "clk-alpha-pll.h"
+#include "clk-branch.h"
+#include "clk-rcg.h"
+#include "clk-regmap-divider.h"
+#include "common.h"
+#include "gdsc.h"
+#include "reset.h"
+
+enum {
+ P_BI_TCXO,
+ P_CORE_BI_PLL_TEST_SE,
+ P_DISP_CC_PLL0_OUT_MAIN,
+ P_DISP_CC_PLL1_OUT_EVEN,
+ P_DISP_CC_PLL1_OUT_MAIN,
+ P_DP_PHY_PLL_LINK_CLK,
+ P_DP_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX1_PHY_PLL_LINK_CLK,
+ P_DPTX1_PHY_PLL_VCO_DIV_CLK,
+ P_DPTX2_PHY_PLL_LINK_CLK,
+ P_DPTX2_PHY_PLL_VCO_DIV_CLK,
+ P_DSI0_PHY_PLL_OUT_BYTECLK,
+ P_DSI0_PHY_PLL_OUT_DSICLK,
+ P_DSI1_PHY_PLL_OUT_BYTECLK,
+ P_DSI1_PHY_PLL_OUT_DSICLK,
+ P_EDP_PHY_PLL_LINK_CLK,
+ P_EDP_PHY_PLL_VCO_DIV_CLK,
+};
+
+static struct pll_vco trion_vco[] = {
+ { 24960, 20, 0 },
+};
+
+static struct alpha_pll_config disp_cc_pll0_config = {
+ .l = 0x47,
+ .alpha = 0xE000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2267,
+ .config_ctl_hi1_val = 0x0024,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x00D0,
+};
+
+static struct clk_alpha_pll disp_cc_pll0 = {
+ .offset = 0x0,
+ .vco_table = trion_vco,
+ .num_vco = ARRAY_SIZE(trion_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "disp_cc_pll0",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_trion_ops,
+ },
+ },
+};
+
+static struct alpha_pll_config disp_cc_pll1_config = {
+ .l = 0x1F,
+ .alpha = 0x4000,
+ .config_ctl_val = 0x20485699,
+ .config_ctl_hi_val = 0x2267,
+ .config_ctl_hi1_val = 0x0024,
+ .user_ctl_val = 0x,
+ .user_ctl_hi_val = 0x0805,
+ .user_ctl_hi1_val = 0x00D0,
+};
+
+static struct clk_alpha_pll disp_cc_pll1 = {
+ .offset = 0x1000,
+ .vco_table = trion_vco,
+ .num_vco = ARRAY_SIZE(trion_vco),
+ .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TRION],
+ .clkr = {
+ .hw.init = &(struct clk_init_data){
+ .name = "disp_cc_pll1",
+ .parent_data = &(const struct clk_parent_data){
+ .fw_name = "bi_tcxo",
+ },
+ .num_parents = 1,
+ .ops = _alpha_pll_trion_ops,
+
[PATCH v3 3/7] dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc
These two bindings are almost identical, so combine them into one. This
will make it easier to add the sm8150 and sm8250 dispcc bindings.
Signed-off-by: Jonathan Marek
---
...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 18 ++--
.../bindings/clock/qcom,sc7180-dispcc.yaml| 86 ---
2 files changed, 12 insertions(+), 92 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml =>
qcom,dispcc.yaml} (86%)
delete mode 100644
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
similarity index 86%
rename from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
rename to Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index ead44705333b..7d5b25dfe0b1 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
@@ -1,32 +1,37 @@
# SPDX-License-Identifier: GPL-2.0-only
%YAML 1.2
---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Display Clock & Reset Controller Binding for SDM845
+title: Qualcomm Display Clock & Reset Controller Binding
maintainers:
- Taniya Das
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains on SDM845.
+ power domains on SDM845/SC7180.
- See also dt-bindings/clock/qcom,dispcc-sdm845.h.
+ See also:
+dt-bindings/clock/qcom,dispcc-sdm845.h
+dt-bindings/clock/qcom,dispcc-sc7180.h
properties:
compatible:
-const: qcom,sdm845-dispcc
+enum:
+ - qcom,sdm845-dispcc
+ - qcom,sc7180-dispcc
# NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
# The code had to use hardcoded mechanisms to find the input clocks.
# New dts files should have these clocks.
clocks:
+minItems: 8
items:
- description: Board XO source
- description: GPLL0 source from GCC
- - description: GPLL0 div source from GCC
+ - description: GPLL0 div source from GCC (sdm845 only)
- description: Byte clock from DSI PHY0
- description: Pixel clock from DSI PHY0
- description: Byte clock from DSI PHY1
@@ -35,6 +40,7 @@ properties:
- description: VCO DIV clock from DP PHY
clock-names:
+minItems: 8
items:
- const: bi_tcxo
- const: gcc_disp_gpll0_clk_src
diff --git a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
b/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
deleted file mode 100644
index e94847f92770..
--- a/Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
+++ /dev/null
@@ -1,86 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-%YAML 1.2
-$id: http://devicetree.org/schemas/clock/qcom,sc7180-dispcc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Qualcomm Display Clock & Reset Controller Binding for SC7180
-
-maintainers:
- - Taniya Das
-
-description: |
- Qualcomm display clock control module which supports the clocks, resets and
- power domains on SC7180.
-
- See also dt-bindings/clock/qcom,dispcc-sc7180.h.
-
-properties:
- compatible:
-const: qcom,sc7180-dispcc
-
- clocks:
-items:
- - description: Board XO source
- - description: GPLL0 source from GCC
- - description: Byte clock from DSI PHY
- - description: Pixel clock from DSI PHY
- - description: Link clock from DP PHY
- - description: VCO DIV clock from DP PHY
-
- clock-names:
-items:
- - const: bi_tcxo
- - const: gcc_disp_gpll0_clk_src
- - const: dsi0_phy_pll_out_byteclk
- - const: dsi0_phy_pll_out_dsiclk
- - const: dp_phy_pll_link_clk
- - const: dp_phy_pll_vco_div_clk
-
- '#clock-cells':
-const: 1
-
- '#reset-cells':
-const: 1
-
- '#power-domain-cells':
-const: 1
-
- reg:
-maxItems: 1
-
-required:
- - compatible
- - reg
- - clocks
- - clock-names
- - '#clock-cells'
- - '#reset-cells'
- - '#power-domain-cells'
-
-additionalProperties: false
-
-examples:
- - |
-#include
-#include
-clock-controller@af0 {
- compatible = "qcom,sc7180-dispcc";
- reg = <0x0af0 0x20>;
- clocks = < RPMH_CXO_CLK>,
- < GCC_DISP_GPLL0_CLK_SRC>,
- <_phy 0>,
- <_phy 1>,
- <_phy 0>,
- <_phy 1>;
- clock-names = "bi_tcxo",
-"gcc_disp_gpll0_clk_src",
-"dsi0_phy_pll_out_byteclk",
-"dsi0_phy_pll_out_dsiclk",
-"dp_phy_pll_link_clk",
-
[PATCH v3 0/7] SM8150 and SM8250 dispcc drivers
Add display clock drivers required to get DSI and DP displays working on
SM8150 and SM8250 SoCs.
Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz
v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream
v3:
- combined dt-binding: "gcc_disp_gpll0_clk_src" is needed by sc7180 too
- use the right order in drivers/clk/qcom/Kconfig
Jonathan Marek (7):
dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as
sc7180
arm64: dts: qcom: sdm845-dispcc: same name for dp_phy clocks as sc7180
dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc
dt-bindings: clock: Introduce QCOM SM8150 display clock bindings
dt-bindings: clock: Introduce QCOM SM8250 display clock bindings
clk: qcom: Add display clock controller driver for SM8150
clk: qcom: Add display clock controller driver for SM8250
...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 32 +-
.../bindings/clock/qcom,sc7180-dispcc.yaml| 86 --
arch/arm64/boot/dts/qcom/sdm845.dtsi |4 +-
drivers/clk/qcom/Kconfig | 18 +
drivers/clk/qcom/Makefile |2 +
drivers/clk/qcom/dispcc-sm8150.c | 1152 +
drivers/clk/qcom/dispcc-sm8250.c | 1100
.../dt-bindings/clock/qcom,dispcc-sm8150.h| 69 +
.../dt-bindings/clock/qcom,dispcc-sm8250.h| 66 +
9 files changed, 2430 insertions(+), 99 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml =>
qcom,dispcc.yaml} (74%)
delete mode 100644
Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
create mode 100644 drivers/clk/qcom/dispcc-sm8150.c
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h
--
2.26.1
[PATCH v2 2/3] misc: fastrpc: define names for protection domain ids
Define SENSORS_PD for the next patch, to void using magic values for these.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 7939c55daceb..07b381c042cd 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -73,6 +73,11 @@
#define FASTRPC_RMID_INIT_CREATE_ATTR 7
#define FASTRPC_RMID_INIT_CREATE_STATIC8
+/* Protection Domain(PD) ids */
+#define AUDIO_PD (0) /* also GUEST_OS PD? */
+#define USER_PD(1)
+#define SENSORS_PD (2)
+
#define miscdev_to_cctx(d) container_of(d, struct fastrpc_channel_ctx, miscdev)
static const char *domains[FASTRPC_DEV_MAX] = { "adsp", "mdsp",
@@ -1037,7 +1042,7 @@ static int fastrpc_init_create_process(struct
fastrpc_user *fl,
inbuf.pageslen = 1;
inbuf.attrs = init.attrs;
inbuf.siglen = init.siglen;
- fl->pd = 1;
+ fl->pd = USER_PD;
if (init.filelen && init.filefd) {
err = fastrpc_map_create(fl, init.filefd, init.filelen, );
@@ -1287,7 +1292,7 @@ static int fastrpc_init_attach(struct fastrpc_user *fl)
args[0].fd = -1;
args[0].reserved = 0;
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0);
- fl->pd = 0;
+ fl->pd = AUDIO_PD;
return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE,
sc, [0]);
--
2.26.1
[PATCH v2 0/3] misc: fastrpc: add ioctl for attaching to sensors pd
Initializing sensors requires attaching to pd 2. Add an ioctl for that. This corresponds to FASTRPC_INIT_ATTACH_SENSORS in the downstream driver. v2: - define names of PD values in a separate patch - split out identation fix in a separate patch Jonathan Marek (3): misc: fastrpc: fix indentation error in uapi header misc: fastrpc: define names for protection domain ids misc: fastrpc: add ioctl for attaching to sensors pd drivers/misc/fastrpc.c | 16 include/uapi/misc/fastrpc.h | 5 +++-- 2 files changed, 15 insertions(+), 6 deletions(-) -- 2.26.1
[PATCH v2 1/3] misc: fastrpc: fix indentation error in uapi header
Use tabs instead of spaces.
Fixes: 2419e55e532d ("misc: fastrpc: add mmap/unmap support")
Signed-off-by: Jonathan Marek
---
include/uapi/misc/fastrpc.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/uapi/misc/fastrpc.h b/include/uapi/misc/fastrpc.h
index 07de2b7aac85..de31f0bd4779 100644
--- a/include/uapi/misc/fastrpc.h
+++ b/include/uapi/misc/fastrpc.h
@@ -10,8 +10,8 @@
#define FASTRPC_IOCTL_INVOKE _IOWR('R', 3, struct fastrpc_invoke)
#define FASTRPC_IOCTL_INIT_ATTACH _IO('R', 4)
#define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct
fastrpc_init_create)
-#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
-#define FASTRPC_IOCTL_MUNMAP_IOWR('R', 7, struct
fastrpc_req_munmap)
+#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
+#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap)
struct fastrpc_invoke_args {
__u64 ptr;
--
2.26.1
Re: [PATCH v2 3/4] soundwire: qcom: add support for mmio soundwire master devices
On 9/8/20 9:56 AM, Pierre-Louis Bossart wrote:
@@ -764,8 +786,11 @@ static int qcom_swrm_probe(struct platform_device
*pdev)
if (!ctrl->regmap)
return -EINVAL;
} else {
- /* Only WCD based SoundWire controller is supported */
- return -ENOTSUPP;
+ ctrl->reg_read = qcom_swrm_cpu_reg_read;
+ ctrl->reg_write = qcom_swrm_cpu_reg_write;
+ ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ctrl->mmio))
+ return PTR_ERR(ctrl->mmio);
Shouldn't this be conditional on SLIMBUS being enabled, as done in your
patch2?
No, the case above is the SLIMBUS case. This patch is adding support for
the non-SLIMBUS case.
}
ctrl->irq = of_irq_get(dev->of_node, 0);
[PATCH v2] arm64: dts: qcom: add sm8250 fastrpc nodes
Add fastrpc nodes for sDSP, cDSP, and aDSP.
Signed-off-by: Jonathan Marek
---
v2: rebase without audio dts nodes, changed "dsps" to "sdsp"
arch/arm64/boot/dts/qcom/sm8250.dtsi | 115 ++-
1 file changed, 113 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi
b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index d223a2a14f2d..8ca544b47190 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -1282,8 +1282,35 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
mboxes = < IPCC_CLIENT_SLPI
IPCC_MPROC_SIGNAL_GLINK_QMP>;
- label = "lpass";
+ label = "slpi";
qcom,remote-pid = <3>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels =
"fastrpcglink-apps-dsp";
+ label = "sdsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <_smmu 0x0541
0x0>;
+ };
+
+ compute-cb@2 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <_smmu 0x0542
0x0>;
+ };
+
+ compute-cb@3 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <_smmu 0x0543
0x0>;
+ /* note: shared-cb = <4> in
downstream */
+ };
+ };
};
};
@@ -1320,8 +1347,66 @@ IPCC_MPROC_SIGNAL_GLINK_QMP
mboxes = < IPCC_CLIENT_CDSP
IPCC_MPROC_SIGNAL_GLINK_QMP>;
- label = "lpass";
+ label = "cdsp";
qcom,remote-pid = <5>;
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ qcom,glink-channels =
"fastrpcglink-apps-dsp";
+ label = "cdsp";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compute-cb@1 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <_smmu 0x1001
0x0460>;
+ };
+
+ compute-cb@2 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <_smmu 0x1002
0x0460>;
+ };
+
+ compute-cb@3 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <_smmu 0x1003
0x0460>;
+ };
+
+ compute-cb@4 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <_smmu 0x1004
0x0460>;
+ };
+
+ compute-cb@5 {
+ compatible =
"qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus
[PATCH] soundwire: qcom: fix SLIBMUS/SLIMBUS typo
Fix slimbus case being broken thanks to a typo.
Fixes: 5bd773242f75 ("soundwire: qcom: avoid dependency on CONFIG_SLIMBUS")
Signed-off-by: Jonathan Marek
---
This should be squashed into the problematic patch if possible,
but I'm not sure if that's possible since its already in linux-next?
drivers/soundwire/qcom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 100af93a5eab..c406a079d237 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -780,7 +780,7 @@ static int qcom_swrm_probe(struct platform_device *pdev)
if (!ctrl)
return -ENOMEM;
-#if IS_ENABLED(CONFIG_SLIBMUS)
+#if IS_ENABLED(CONFIG_SLIMBUS)
if (dev->parent->bus == _bus) {
#else
if (false) {
--
2.26.1
[PATCH v2 3/3] misc: fastrpc: add ioctl for attaching to sensors pd
Initializing sensors requires attaching to pd 2. Add an ioctl for that.
This corresponds to FASTRPC_INIT_ATTACH_SENSORS in the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 9 ++---
include/uapi/misc/fastrpc.h | 1 +
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 07b381c042cd..f05f4b5934bd 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -1281,7 +1281,7 @@ static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl,
char __user *argp)
return 0;
}
-static int fastrpc_init_attach(struct fastrpc_user *fl)
+static int fastrpc_init_attach(struct fastrpc_user *fl, int pd)
{
struct fastrpc_invoke_args args[1];
int tgid = fl->tgid;
@@ -1292,7 +1292,7 @@ static int fastrpc_init_attach(struct fastrpc_user *fl)
args[0].fd = -1;
args[0].reserved = 0;
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0);
- fl->pd = AUDIO_PD;
+ fl->pd = pd;
return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE,
sc, [0]);
@@ -1482,7 +1482,10 @@ static long fastrpc_device_ioctl(struct file *file,
unsigned int cmd,
err = fastrpc_invoke(fl, argp);
break;
case FASTRPC_IOCTL_INIT_ATTACH:
- err = fastrpc_init_attach(fl);
+ err = fastrpc_init_attach(fl, AUDIO_PD);
+ break;
+ case FASTRPC_IOCTL_INIT_ATTACH_SNS:
+ err = fastrpc_init_attach(fl, SENSORS_PD);
break;
case FASTRPC_IOCTL_INIT_CREATE:
err = fastrpc_init_create_process(fl, argp);
diff --git a/include/uapi/misc/fastrpc.h b/include/uapi/misc/fastrpc.h
index de31f0bd4779..0a89f95463f6 100644
--- a/include/uapi/misc/fastrpc.h
+++ b/include/uapi/misc/fastrpc.h
@@ -12,6 +12,7 @@
#define FASTRPC_IOCTL_INIT_CREATE _IOWR('R', 5, struct
fastrpc_init_create)
#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct fastrpc_req_munmap)
+#define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8)
struct fastrpc_invoke_args {
__u64 ptr;
--
2.26.1
Re: [PATCH] misc: fastrpc: add ioctl for attaching to sensors pd
On 9/7/20 8:33 AM, Greg Kroah-Hartman wrote:
On Mon, Aug 31, 2020 at 08:32:59PM -0400, Jonathan Marek wrote:
Initializing sensors requires attaching to pd 2. Add an ioctl for that.
This corresponds to FASTRPC_INIT_ATTACH_SENSORS in the downstream driver.
Signed-off-by: Jonathan Marek
---
drivers/misc/fastrpc.c | 9 ++---
include/uapi/misc/fastrpc.h | 5 +++--
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/fastrpc.c b/drivers/misc/fastrpc.c
index 7939c55daceb..ea5e9ca0d705 100644
--- a/drivers/misc/fastrpc.c
+++ b/drivers/misc/fastrpc.c
@@ -1276,7 +1276,7 @@ static int fastrpc_dmabuf_alloc(struct fastrpc_user *fl,
char __user *argp)
return 0;
}
-static int fastrpc_init_attach(struct fastrpc_user *fl)
+static int fastrpc_init_attach(struct fastrpc_user *fl, int pd)
{
struct fastrpc_invoke_args args[1];
int tgid = fl->tgid;
@@ -1287,7 +1287,7 @@ static int fastrpc_init_attach(struct fastrpc_user *fl)
args[0].fd = -1;
args[0].reserved = 0;
sc = FASTRPC_SCALARS(FASTRPC_RMID_INIT_ATTACH, 1, 0);
- fl->pd = 0;
+ fl->pd = pd;
return fastrpc_internal_invoke(fl, true, FASTRPC_INIT_HANDLE,
sc, [0]);
@@ -1477,7 +1477,10 @@ static long fastrpc_device_ioctl(struct file *file,
unsigned int cmd,
err = fastrpc_invoke(fl, argp);
break;
case FASTRPC_IOCTL_INIT_ATTACH:
- err = fastrpc_init_attach(fl);
+ err = fastrpc_init_attach(fl, 0);
+ break;
+ case FASTRPC_IOCTL_INIT_ATTACH_SNS:
+ err = fastrpc_init_attach(fl, 2);
Shouldn't you have #defines for those magic numbers somewhere? What
does 0 and 2 mean?
This is based off a downstream driver which also uses magic numbers,
although I can make an educated guess about the meaning.
Srini do you have any suggestions for how to name these values?
thanks,
greg k-h
Re: [PATCH] misc: fastrpc: add ioctl for attaching to sensors pd
On 9/7/20 9:58 AM, Srinivas Kandagatla wrote: On 07/09/2020 14:51, Jonathan Marek wrote: @@ -1477,7 +1477,10 @@ static long fastrpc_device_ioctl(struct file *file, unsigned int cmd, err = fastrpc_invoke(fl, argp); break; case FASTRPC_IOCTL_INIT_ATTACH: - err = fastrpc_init_attach(fl); + err = fastrpc_init_attach(fl, 0); + break; + case FASTRPC_IOCTL_INIT_ATTACH_SNS: + err = fastrpc_init_attach(fl, 2); Shouldn't you have #defines for those magic numbers somewhere? What does 0 and 2 mean? This is based off a downstream driver which also uses magic numbers, although I can make an educated guess about the meaning. Srini do you have any suggestions for how to name these values? These are domain id corresponding to each core. you can use SDSP_DOMAIN_ID in here! these are already defined in the file as: #define ADSP_DOMAIN_ID (0) #define MDSP_DOMAIN_ID (1) #define SDSP_DOMAIN_ID (2) #define CDSP_DOMAIN_ID (3) I don't think this is right: FASTRPC_IOCTL_INIT_ATTACH uses pd = 0 FASTRPC_IOCTL_INIT_CREATE uses pd = 1 And these two ioctl are used with all DSP cores. So it wouldn't make sense for the pd value to correspond to the domain id. --srini
Re: [PATCH] misc: fastrpc: add ioctl for attaching to sensors pd
On 9/7/20 10:01 AM, Srinivas Kandagatla wrote:
On 07/09/2020 14:47, Jonathan Marek wrote:
On 9/7/20 8:36 AM, Srinivas Kandagatla wrote:
On 01/09/2020 01:32, Jonathan Marek wrote:
-#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct
fastrpc_req_mmap)
-#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct
fastrpc_req_munmap)
+#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct
fastrpc_req_mmap)
+#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct
fastrpc_req_munmap)
Looks like changes that do not belong to this patch!
I wanted to try this patch on SM8250.
How do you test attaching fastrpc to sensor core?, I mean which
userspace lib/tool do you use?
--srini
I pushed my sdsprpcd implementation to github, which is responsible
for initializing the sensors, and uses this ioctl:
https://github.com/flto/fastrpc
Thanks!, I can take a look and see if I can try it out with linaro
fastrpc library!
You don't need linaro fastrpc library to try it, everything you need is
in that repo.
Note: it uses my own WIP fastrpc "library" instead of the one from
linaro, I also have other related code, like a sensor client, and
cDSP/aDSP compute examples, but need to confirm that I can share them
Also, the corresponding dts patch I sent has a problem, the label =
"dsps"; should be label = "sdsp"; (copied the "dsps" from downstream,
but upstream expects "sdsp"), will send a v2 later today.
Also the dts patch will fail to apply as it is, as it seems me that you
have based the patch after adding audio dts patch!
Thanks for pointing it out, will make sure the v2 applies cleanly
without audio dts patches applied.
--srini
+#define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8)
Re: [PATCH] misc: fastrpc: add ioctl for attaching to sensors pd
On 9/7/20 8:36 AM, Srinivas Kandagatla wrote:
On 01/09/2020 01:32, Jonathan Marek wrote:
-#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct
fastrpc_req_mmap)
-#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct
fastrpc_req_munmap)
+#define FASTRPC_IOCTL_MMAP _IOWR('R', 6, struct fastrpc_req_mmap)
+#define FASTRPC_IOCTL_MUNMAP _IOWR('R', 7, struct
fastrpc_req_munmap)
Looks like changes that do not belong to this patch!
I wanted to try this patch on SM8250.
How do you test attaching fastrpc to sensor core?, I mean which
userspace lib/tool do you use?
--srini
I pushed my sdsprpcd implementation to github, which is responsible for
initializing the sensors, and uses this ioctl:
https://github.com/flto/fastrpc
Note: it uses my own WIP fastrpc "library" instead of the one from
linaro, I also have other related code, like a sensor client, and
cDSP/aDSP compute examples, but need to confirm that I can share them
Also, the corresponding dts patch I sent has a problem, the label =
"dsps"; should be label = "sdsp"; (copied the "dsps" from downstream,
but upstream expects "sdsp"), will send a v2 later today.
+#define FASTRPC_IOCTL_INIT_ATTACH_SNS _IO('R', 8)
[PATCH v2 1/4] soundwire: qcom: fix abh/ahb typo
The function name qcom_swrm_abh_reg_read should say ahb, fix that.
Signed-off-by: Jonathan Marek
Reviewed-by: Srinivas Kandagatla
---
drivers/soundwire/qcom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 915c2cf0c274..d1e33ef1afac 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -114,7 +114,7 @@ struct qcom_swrm_ctrl {
#define to_qcom_sdw(b) container_of(b, struct qcom_swrm_ctrl, bus)
-static int qcom_swrm_abh_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
+static int qcom_swrm_ahb_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
u32 *val)
{
struct regmap *wcd_regmap = ctrl->regmap;
@@ -754,7 +754,7 @@ static int qcom_swrm_probe(struct platform_device *pdev)
return -ENOMEM;
if (dev->parent->bus == _bus) {
- ctrl->reg_read = qcom_swrm_abh_reg_read;
+ ctrl->reg_read = qcom_swrm_ahb_reg_read;
ctrl->reg_write = qcom_swrm_ahb_reg_write;
ctrl->regmap = dev_get_regmap(dev->parent, NULL);
if (!ctrl->regmap)
--
2.26.1
[PATCH v2 0/4] soundwire: qcom: add support for mmio soundwire master
This adds initial support for soundwire device on sm8250. Tested with the "wsa" sdw device, which is simpler than the others. v2 addresses some feedback, but I kept this series as simple as possible. In particular, I didn't implement CMD_NACKED from FIFO_STATUS, because the downstream driver doesn't define this bit, so I can't implement it. Soundwire works without it and It shouldn't be difficult to implement later. Jonathan Marek (4): soundwire: qcom: fix abh/ahb typo soundwire: qcom: avoid dependency on CONFIG_SLIMBUS soundwire: qcom: add support for mmio soundwire master devices soundwire: qcom: add v1.5.1 compatible .../bindings/soundwire/qcom,sdw.txt | 1 + drivers/soundwire/Kconfig | 2 +- drivers/soundwire/qcom.c | 38 +-- 3 files changed, 36 insertions(+), 5 deletions(-) -- 2.26.1
[PATCH v2 4/4] soundwire: qcom: add v1.5.1 compatible
Add a compatible string for HW version v1.5.1 on sm8250 SoCs.
Signed-off-by: Jonathan Marek
---
Documentation/devicetree/bindings/soundwire/qcom,sdw.txt | 1 +
drivers/soundwire/qcom.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
index 436547f3b155..b104be131235 100644
--- a/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
+++ b/Documentation/devicetree/bindings/soundwire/qcom,sdw.txt
@@ -11,6 +11,7 @@ board specific bus parameters.
Example:
"qcom,soundwire-v1.3.0"
"qcom,soundwire-v1.5.0"
+ "qcom,soundwire-v1.5.1"
"qcom,soundwire-v1.6.0"
- reg:
Usage: required
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index ff28794868ca..41dda3b85413 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -888,6 +888,7 @@ static int qcom_swrm_remove(struct platform_device *pdev)
static const struct of_device_id qcom_swrm_of_match[] = {
{ .compatible = "qcom,soundwire-v1.3.0", },
+ { .compatible = "qcom,soundwire-v1.5.1", },
{/* sentinel */},
};
--
2.26.1
[PATCH v2 2/4] soundwire: qcom: avoid dependency on CONFIG_SLIMBUS
The driver may be used without slimbus, so don't depend on slimbus.
Signed-off-by: Jonathan Marek
---
drivers/soundwire/Kconfig | 2 +-
drivers/soundwire/qcom.c | 4
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/soundwire/Kconfig b/drivers/soundwire/Kconfig
index fa2b4ab92ed9..f83d02c9c60a 100644
--- a/drivers/soundwire/Kconfig
+++ b/drivers/soundwire/Kconfig
@@ -33,7 +33,7 @@ config SOUNDWIRE_INTEL
config SOUNDWIRE_QCOM
tristate "Qualcomm SoundWire Master driver"
- depends on SLIMBUS
+ imply SLIMBUS
depends on SND_SOC
help
SoundWire Qualcomm Master driver.
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index d1e33ef1afac..6401ad451eee 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -753,7 +753,11 @@ static int qcom_swrm_probe(struct platform_device *pdev)
if (!ctrl)
return -ENOMEM;
+#if IS_ENABLED(CONFIG_SLIBMUS)
if (dev->parent->bus == _bus) {
+#else
+ if (false) {
+#endif
ctrl->reg_read = qcom_swrm_ahb_reg_read;
ctrl->reg_write = qcom_swrm_ahb_reg_write;
ctrl->regmap = dev_get_regmap(dev->parent, NULL);
--
2.26.1
[PATCH v2 3/4] soundwire: qcom: add support for mmio soundwire master devices
Adds support for qcom soundwire devices with memory mapped IO registers.
Signed-off-by: Jonathan Marek
---
drivers/soundwire/qcom.c | 29 +++--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/drivers/soundwire/qcom.c b/drivers/soundwire/qcom.c
index 6401ad451eee..ff28794868ca 100644
--- a/drivers/soundwire/qcom.c
+++ b/drivers/soundwire/qcom.c
@@ -34,6 +34,7 @@
#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED BIT(10)
#define SWRM_INTERRUPT_MASK_ADDR 0x204
#define SWRM_INTERRUPT_CLEAR 0x208
+#define SWRM_INTERRUPT_CPU_EN 0x210
#define SWRM_CMD_FIFO_WR_CMD 0x300
#define SWRM_CMD_FIFO_RD_CMD 0x304
#define SWRM_CMD_FIFO_CMD 0x308
@@ -90,6 +91,7 @@ struct qcom_swrm_ctrl {
struct sdw_bus bus;
struct device *dev;
struct regmap *regmap;
+ void __iomem *mmio;
struct completion *comp;
struct work_struct slave_work;
/* read/write lock */
@@ -154,6 +156,20 @@ static int qcom_swrm_ahb_reg_write(struct qcom_swrm_ctrl
*ctrl,
return SDW_CMD_OK;
}
+static int qcom_swrm_cpu_reg_read(struct qcom_swrm_ctrl *ctrl, int reg,
+ u32 *val)
+{
+ *val = readl(ctrl->mmio + reg);
+ return SDW_CMD_OK;
+}
+
+static int qcom_swrm_cpu_reg_write(struct qcom_swrm_ctrl *ctrl, int reg,
+ int val)
+{
+ writel(val, ctrl->mmio + reg);
+ return SDW_CMD_OK;
+}
+
static int qcom_swrm_cmd_fifo_wr_cmd(struct qcom_swrm_ctrl *ctrl, u8 cmd_data,
u8 dev_addr, u16 reg_addr)
{
@@ -310,6 +326,12 @@ static int qcom_swrm_init(struct qcom_swrm_ctrl *ctrl)
ctrl->reg_write(ctrl, SWRM_COMP_CFG_ADDR,
SWRM_COMP_CFG_IRQ_LEVEL_OR_PULSE_MSK |
SWRM_COMP_CFG_ENABLE_MSK);
+
+ /* enable CPU IRQs */
+ if (ctrl->mmio) {
+ ctrl->reg_write(ctrl, SWRM_INTERRUPT_CPU_EN,
+ SWRM_INTERRUPT_STATUS_RMSK);
+ }
return 0;
}
@@ -764,8 +786,11 @@ static int qcom_swrm_probe(struct platform_device *pdev)
if (!ctrl->regmap)
return -EINVAL;
} else {
- /* Only WCD based SoundWire controller is supported */
- return -ENOTSUPP;
+ ctrl->reg_read = qcom_swrm_cpu_reg_read;
+ ctrl->reg_write = qcom_swrm_cpu_reg_write;
+ ctrl->mmio = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(ctrl->mmio))
+ return PTR_ERR(ctrl->mmio);
}
ctrl->irq = of_irq_get(dev->of_node, 0);
--
2.26.1
