On 2/2/19 2:08 AM, Dmitry Osipenko wrote:
01.02.2019 18:37, Joseph Lo пишет:
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11, Dmitry Osipenko wrote:
01.02.2019 16:06, Dmitry Osipenko пишет:
01.02.2019 6
On 2/2/19 9:30 PM, Dmitry Osipenko wrote:
01.02.2019 18:37, Joseph Lo пишет:
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11, Dmitry Osipenko wrote:
01.02.2019 16:06, Dmitry Osipenko пишет:
01.02.2019 6
On 2/2/19 9:38 PM, Dmitry Osipenko wrote:
02.02.2019 2:53, Joseph Lo пишет:
On 2/2/19 2:08 AM, Dmitry Osipenko wrote:
01.02.2019 18:37, Joseph Lo пишет:
On 2/1/19 11:13 PM, Dmitry Osipenko wrote:
01.02.2019 17:13, Joseph Lo пишет:
On 2/1/19 9:54 PM, Jon Hunter wrote:
On 01/02/2019 13:11
CPU suspends in power down state.
Based on the work of Antti P Miettinen
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Joseph Lo
---
drivers/clocksource/Kconfig | 3 +
drivers/clocksource/Makefile | 1 +
drivers/clocksource/timer
,
or watchdog interrupts.
Cc: Daniel Lezcano
Cc: Thomas Gleixner
Cc: linux-kernel@vger.kernel.org
Cc: devicet...@vger.kernel.org
Signed-off-by: Joseph Lo
---
.../bindings/timer/nvidia,tegra210-timer.txt | 25 +++
1 file changed, 25 insertions(+)
create mode 100644
Documentation
Hi,
On 10/13/2014 03:37 PM, Jingchang Lu wrote:
This patch fixes commit 2dea53bf57783f243c892e99c10c6921e956aa7e,
"serial: of-serial: add PM suspend/resume support", which disables
the uart clock on suspend, but also causes a hardware hang on register
access if no_console_suspend command line
ine option is used.
Also, not every of_serial device is an 8250 port, so the serial8250
suspend/resume functions should only be applied to a real 8250 port.
Signed-off-by: Jingchang Lu
If you can make sure this patch can build without include
, then this patch
Tested-by: Joseph Lo
On 10/15/2014 02:32 PM, Jingchang Lu wrote:
-Original Message-
From: Joseph Lo [mailto:jose...@nvidia.com]
Sent: Wednesday, October 15, 2014 9:01 AM
To: Lu Jingchang-B35083; gre...@linuxfoundation.org
Cc: pe...@hurleysoftware.com; a...@arndb.de; linux-kernel@vger.kernel.org;
linux-ser
On 10/15/2014 02:41 PM, Joseph Lo wrote:
On 10/15/2014 02:32 PM, Jingchang Lu wrote:
-Original Message-
From: Joseph Lo [mailto:jose...@nvidia.com]
Sent: Wednesday, October 15, 2014 9:01 AM
To: Lu Jingchang-B35083; gre...@linuxfoundation.org
Cc: pe...@hurleysoftware.com; a...@arndb.de
al_suspend/resume.
changes in v3:
fix up point reference and deference.
changes in v2:
add switch selection on uart type.
Hi Jingchang,
Thanks for the fix. This patch
Tested-by: Joseph Lo
drivers/tty/serial/of_serial.c | 53 --
1 file changed, 46
Hi,
This patch might have a potential issue that cause system hard hung
immediately when it accesses to registers with no clock. This could
happen on many chips that mainline kernel supporting with the setting
"no_console_suspend=1" during suspend time.
On 09/23/2014 04:34 PM, Jingchang Lu
appropriate to flush the entire cache at
this stage.
Therefore, ensure that r0 is set to TEGRA_FLUSH_CACHE_ALL when calling
tegra_disable_clean_inv_dcache() from tegra20_sleep_core_finish() and
tegra30_sleep_core_finish().
Signed-off-by: Jon Hunter
---
Thanks for the fix.
Reviewed-by: Joseph Lo
On 07/20/2016 09:22 AM, Rob Herring wrote:
On Tue, Jul 19, 2016 at 05:17:23PM +0800, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU
On 07/14/2016 03:41 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
Hi Rob,
Thanks for your reviewing.
On 07/12/2016 12:05 AM, Stephen Warren wrote:
On 07/11/2016 08:22 AM, Rob Herring wrote:
On Tue, Jul 05, 2016 at 05:04:24PM +0800, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading
On 07/08/2016 05:10 AM, Sivaram Nair wrote:
On Tue, Jul 05, 2016 at 05:04:23PM +0800, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC) for remote processors currently. The
HSP HW modules support some different features
On 07/08/2016 05:33 AM, Sivaram Nair wrote:
On Thu, Jul 07, 2016 at 02:37:27PM +0800, Joseph Lo wrote:
On 07/06/2016 08:23 PM, Alexandre Courbot wrote:
On Wed, Jul 6, 2016 at 6:06 PM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph
On 07/19/2016 07:13 AM, Stephen Warren wrote:
On 07/11/2016 10:08 AM, Stephen Warren wrote:
On 07/11/2016 08:14 AM, Rob Herring wrote:
On Thu, Jul 07, 2016 at 12:35:02PM -0600, Stephen Warren wrote:
On 07/07/2016 12:13 PM, Sivaram Nair wrote:
On Tue, Jul 05, 2016 at 05:04:22PM +0800, Joseph
the interprocessor communication (IPC) between the CPU
and BPMP.
Signed-off-by: Joseph Lo
---
Changes in V3:
- s/mmio-ram/mmio-sram/
- revise the file path of the reference binding documents and header files
for more generic viem in different SW projects
Changes in V2:
- update the message
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo
---
Sorry. Please allow me just update the binding patches of this series.
Want to make sure the binding is acceptable first.
Thanks.
Changes in V3:
- use two cells
On 07/01/2016 12:02 AM, Stephen Warren wrote:
On 06/30/2016 03:25 AM, Joseph Lo wrote:
On 06/29/2016 11:28 PM, Stephen Warren wrote:
On 06/28/2016 11:56 PM, Joseph Lo wrote:
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo
---
Changes in V2:
- revise the compatible string, interrupt-names, interrupts, and #mbox-cells
properties
- remove "nvidia,hsp-function" property
- fix
to represent the binding update
Joseph Lo (10):
Documentation: dt-bindings: mailbox: tegra: Add binding for HSP
mailbox
mailbox: tegra-hsp: Add HSP(Hardware Synchronization Primitives)
driver
Documentation: dt-bindings: firmware: tegra: add bindings of the BPMP
firmware: tegra: add
the interprocessor communication (IPC) between the CPU
and BPMP.
Signed-off-by: Joseph Lo
---
Changes in V2:
- update the message that the BPMP is clock and reset control provider
- add tegra186-clock.h and tegra186-reset.h header files
- revise the description of the required properties
Add NVIDIA Tegra186 P3310 main board support, which is a chip module
with DRAM, nonvolatile storage, WiFi, ethernet and PMIC chips on it. It
also needs an IO board and hooks on it to represent as an application
platform.
Signed-off-by: Joseph Lo
---
Changes in V2:
- update according
Add NVIDIA Tegra186 P2771 board support, which is a reference
development board with P2597 I/O board and P3310 chip module on it.
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts
This adds the initial support of Tegra186 SoC, which can help to bring
up the debug console and initrd for further developing.
Signed-off-by: Joseph Lo
---
Changes in V2:
- update the file according the HSP and BPMP binding fix in V2
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 77
. And there are multiple HSP HW instances on the chip. So the
driver is extendable to support more features for different IPC
requirement.
The driver of remote processor can use it as a mailbox client and deal
with the IPC protocol to synchronize the data communications.
Signed-off-by: Joseph Lo
---
Changes in V2
and payloads. So the
clients can use it to send/receive messages to/from remote ones.
We introduce it as a library for the firmware drivers, which can use it
for IPC.
Based-on-the-work-by:
Peter Newman
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
drivers/firmware/Kconfig| 1
Enable Tegra186 SoC.
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index e69051098435..64d767ec142c 100644
--- a/arch/arm64/configs/defconfig
.
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
drivers/soc/tegra/Kconfig | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 03089ad2fc65..88a71dfd466c 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra
needs two things to initiate IPC between BPMP. Get the
service from the bpmp_ops structure and maintain the message format as
the BPMP ABI defined.
Based-on-the-work-by:
Sivaram Nair
Signed-off-by: Joseph Lo
---
Changes in V2:
- None
---
drivers/firmware/tegra/Kconfig | 12 +
drivers/firmware
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC) for remote processors currently. The
HSP HW modules support some different features
On 07/07/2016 01:02 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives
On 07/06/2016 07:42 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU
On 07/07/2016 01:03 AM, Stephen Warren wrote:
On 07/05/2016 03:04 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management, clock
management, and reset control tasks from the CPU. The binding document
On 07/06/2016 08:23 PM, Alexandre Courbot wrote:
On Wed, Jul 6, 2016 at 6:06 PM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor
On 07/07/2016 12:50 AM, Stephen Warren wrote:
On 07/06/2016 03:06 AM, Joseph Lo wrote:
On 07/06/2016 03:05 PM, Alexandre Courbot wrote:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra HSP mailbox driver implements the signaling doorbell-based
interprocessor communication (IPC
On 07/06/2016 07:39 PM, Alexandre Courbot wrote:
Sorry, I will probably need to do several passes on this one to
understand everything, but here is what I can say after a first look:
On Tue, Jul 5, 2016 at 6:04 PM, Joseph Lo wrote:
The Tegra BPMP (Boot and Power Management Processor
and payloads. So the
clients can use it to send/receive messages to/from remote ones.
We introduce it as a library for the firmware drivers, which can use it
for IPC.
Based-on-the-work-by:
Peter Newman
Signed-off-by: Joseph Lo
---
drivers/firmware/Kconfig| 1 +
drivers/firmware
. And there are multiple HSP HW instances on the chip. So the
driver is extendable to support more features for different IPC
requirement.
The driver of remote processor can use it as a mailbox client and deal
with the IPC protocol to synchronize the data communications.
Signed-off-by: Joseph Lo
---
drivers
supports debug console and initrd for initial bring up currently. More drivers
and functions can be supported based on this later.
Thanks,
Joseph
Joseph Lo (10):
Documentation: dt-bindings: mailbox: tegra: Add binding for HSP
mailbox
mailbox: tegra-hsp: Add HSP(Hardware Synchronization
use hardware synchronization primitive, when operating
between two processors not in an SMP relationship.
Signed-off-by: Joseph Lo
---
.../bindings/mailbox/nvidia,tegra186-hsp.txt | 42 ++
include/dt-bindings/mailbox/tegra-hsp.h| 20 +++
2 files
) between the CPU and BPMP.
Signed-off-by: Joseph Lo
---
.../bindings/firmware/nvidia,tegra186-bpmp.txt | 61 ++
1 file changed, 61 insertions(+)
create mode 100644
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt
diff --git
a/Documentation/devicetree
Add NVIDIA Tegra186 P2771 board support, which is a reference
development board with P2597 I/O board and P3310 chip module on it.
Signed-off-by: Joseph Lo
---
arch/arm64/boot/dts/nvidia/Makefile| 1 +
arch/arm64/boot/dts/nvidia/tegra186-p2771-.dts | 8
2 files
This adds the initial support of Tegra186 SoC, which can help to bring
up the debug console and initrd for further developing.
Signed-off-by: Joseph Lo
---
arch/arm64/boot/dts/nvidia/tegra186.dtsi | 77
1 file changed, 77 insertions(+)
create mode 100644 arch
Add NVIDIA Tegra186 P3310 main board support, which is a chip module
with DRAM, nonvolatile storage, WiFi, ethernet and PMIC chips on it. It
also needs an IO board and hooks on it to represent as an application
platform.
Signed-off-by: Joseph Lo
---
arch/arm64/boot/dts/nvidia/tegra186-p3310
Enable Tegra186 SoC.
Signed-off-by: Joseph Lo
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index f267eea101a7..033d9cb1e983 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs
needs two things to initiate IPC between BPMP. Get the
service from the bpmp_ops structure and maintain the message format as
the BPMP ABI defined.
Based-on-the-work-by:
Sivaram Nair
Signed-off-by: Joseph Lo
---
drivers/firmware/tegra/Kconfig | 12 +
drivers/firmware/tegra/Makefile |1
.
Signed-off-by: Joseph Lo
---
drivers/soc/tegra/Kconfig | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig
index 03089ad2fc65..88a71dfd466c 100644
--- a/drivers/soc/tegra/Kconfig
+++ b/drivers/soc/tegra/Kconfig
@@ -61,6 +61,20
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
Add DT binding for the Hardware Synchronization Primitives (HSP). The
HSP is designed for the processors to share resources and communicate
together. It provides a set of hardware synchronization primitives
On 06/28/2016 12:08 AM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
The BPMP is a specific processor in Tegra chip, which is designed for
booting process handling and offloading the power management tasks
from the CPU. The binding document defines the resources that would
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
snip.
Currently the usage of HSP HW in the downstream kernel is something like
the model below.
remote_processor_A
On 06/29/2016 11:28 PM, Stephen Warren wrote:
On 06/28/2016 11:56 PM, Joseph Lo wrote:
On 06/29/2016 03:08 AM, Stephen Warren wrote:
On 06/28/2016 03:15 AM, Joseph Lo wrote:
On 06/27/2016 11:55 PM, Stephen Warren wrote:
On 06/27/2016 03:02 AM, Joseph Lo wrote:
snip.
Currently the usage
On Sat, 2013-08-24 at 03:45 +0800, Colin Cross wrote:
> Joseph Lo reported a lockup on Tegra3 caused
> by a race condition in coupled cpuidle. When two or more cpus
Actually this issue can be reproduced on both Tegra20/30 platforms. And
I suggest using Tegra20 to replace Tegra3 here, w
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