On Wed, Aug 1, 2012 at 8:31 PM, Fan Du f...@windriver.com wrote:
show_backtrace must have an valid task when calling unwind_stack,
so fix it by checking first.
[...]
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -151,6 +151,10 @@ static void show_backtrace(struct
(cpu, cpu_callin_map)
- (system_state == SYSTEM_RUNNING ||
-system_state == SYSTEM_BOOTING))
+ if (!cpu_online(cpu) !cpu_isset(cpu, cpu_callin_map))
play_dead();
This fix works for me.
Acked-by: Kevin Cernekee cerne
.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Eric Dumazet eric.duma...@gmail.com
Cc: Patrick McHardy ka...@trash.net
---
Baseline: git://1984.lsi.us.es/nf-next
v3-v4 changes:
Fix patch context and APIs to match the current Linux tree. These
changes are from OpenWRT (Gabor
On Sun, Dec 16, 2012 at 4:44 PM, Pablo Neira Ayuso pa...@netfilter.org wrote:
What happened to this? OpenWRT is still carrying it, and it broke in
3.7. Here's a completely untested update...
I requested Kevin to resend a new version based on the current kernel
tree while spinning on old
On Mon, May 6, 2013 at 10:25 PM, H. Peter Anvin h...@zytor.com wrote:
Hello,
The touchpad on Lenovo Yoga 13 seems to have broken some time between 3.4
and the current kernel. The dmesg is full of spewage:
[ 256.246481] atkbd serio0: Use 'setkeycodes e03e keycode' to make it
known.
[
On Wed, Jul 16, 2014 at 11:08 AM, Alan Stern st...@rowland.harvard.edu wrote:
I am not so much concerned about userspace, but about reusing of as
much of existing PM framework in the drivers. Right now it is very
hard to correctly track dependencies between general open/close,
system
the __raw_ accessors directly, so it
is a reasonably common requirement.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/Kconfig | 3 +++
include/linux/irq.h | 13 +
2 files changed, 16 insertions(+)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
- Update the documentation
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7120-l2-intc.txt | 26 ++--
drivers/irqchip/irq-bcm7120-l2.c | 146 ++---
2 files changed, 114 insertions(+), 58 deletions(-)
diff --git
This change was just made on bcm7120-l2, so let's keep things consistent
between the two drivers.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-brcmstb-l2.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/irqchip/irq
Some chips, such as BCM6328, only require the former driver. Some
BCM7xxx STB configurations only require the latter driver. Treat them
as two separate entities, and update the mach-bcm dependencies to
reflect the change.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/arm/mach-bcm
The cached value already incorporates irq_fwd_mask, and was saved the
last time an IRQ was enabled/disabled.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 11 +++
1 file changed, 3 insertions(+), 8 deletions(-)
diff --git a/drivers/irqchip/irq
This mask should have been 0x_, not 0x0fff_.
The change should not have an effect on current users (STB) because bits
31:27 are unused.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This can compile for MIPS (or anything else) now.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 6f0e80b..6a03c65 100644
--- a/drivers/irqchip/Kconfig
+++ b
This keeps things consistent between the core bcm7120-l2 driver and the
helpers in generic-chip.c.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/irqchip/irq-bcm7120-l2.c
by brcmstb-l2, the bcm7120-l2 controller
does not latch the IRQ status. Bits can change if the inputs to the
controller change. Also, do_bad_IRQ() is an ARM-specific macro.
So let's just nuke it.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 9
The irq-brcmstb-l2 driver has a single dependency on the ARM code, the
do_bad_IRQ macro. Expand this macro in-place so that the driver can be
built on non-ARM platforms.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-brcmstb-l2.c | 7 ---
1 file changed, 4
A couple of accesses to IRQEN (base+0x00) just used base directly, so
they would break if IRQEN ever became nonzero. Make sure that all
reads/writes specify the register offset constant.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 6 +++---
1 file
On Wed, Oct 29, 2014 at 12:43 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 28 October 2014 20:58:48 Kevin Cernekee wrote:
+#ifdef CONFIG_RAW_IRQ_ACCESSORS
+
+#ifndef irq_reg_writel
+# define irq_reg_writel(val, addr) __raw_writel(val, addr)
+#endif
+#ifndef irq_reg_readl
On Wed, Oct 29, 2014 at 12:14 PM, Arnd Bergmann a...@arndb.de wrote:
The host CPU is connected to the peripheral/register interface using a
32-bit wide data bus. A simple 32-bit store originating from the host
CPU, targeted to an onchip SoC peripheral, will never need endian
swapping. i.e.
On Wed, Oct 29, 2014 at 2:13 PM, Arnd Bergmann a...@arndb.de wrote:
On Wednesday 29 October 2014 13:09:47 Kevin Cernekee wrote:
On Wed, Oct 29, 2014 at 12:14 PM, Arnd Bergmann a...@arndb.de wrote:
The host CPU is connected to the peripheral/register interface using a
32-bit wide data bus
On Wed, Oct 29, 2014 at 12:53 AM, Arnd Bergmann a...@arndb.de wrote:
On Tuesday 28 October 2014 20:58:57 Kevin Cernekee wrote:
Most implementations of the bcm7120-l2 controller only have a single
32-bit enable word + 32-bit status word. But some instances have added
more enable/status pairs
?
Kevin Cernekee (15):
irqchip: Replace irq_reg_{readl,writel} with {readl,writel}
sh: Eliminate unused irq_reg_{readl,writel} accessors
genirq: Generic chip: Move irq_reg_{readl,writel} accessors into
generic-chip.c
genirq: Generic chip: Change irq_reg_{readl,writel} arguments
Allow the compiler to inline an LE MMIO access if the configuration only
supports LE registers, or a BE MMIO access if the configuration only
supports BE registers. If the configuration supports both (possibly
a multiplatform kernel) then make the decision at runtime.
Signed-off-by: Kevin
A couple of accesses to IRQEN (base+0x00) just used base directly, so
they would break if IRQEN ever became nonzero. Make sure that all
reads/writes specify the register offset constant.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers
enable/status register pair per instance.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7120-l2-intc.txt | 26 ++--
drivers/irqchip/irq-bcm7120-l2.c | 146 ++---
2 files changed, 114 insertions(+), 58 deletions(-)
diff
On all supported SoCs, the kernel will be built with CONFIG_CPU_BIG_ENDIAN
iff the CPU is running in BE mode. Leverage this fact to autodetect
the MMIO byte ordering to use in generic-chip.c.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/Kconfig | 2 ++
drivers
Instead of taking a raw register virtual address, we will take an
irq_chip_generic struct and a register offset. This makes it possible to
implement different behavior on different irqchips.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
kernel/irq/generic-chip.c | 30
Some chips, such as BCM6328, only require the former driver. Some
BCM7xxx STB configurations only require the latter driver. Treat them
as two separate entities, and update the mach-bcm dependencies to
reflect the change.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann
The cached value already incorporates irq_fwd_mask, and was saved the
last time an IRQ was enabled/disabled.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 11 +++
1 file changed, 3 insertions(+), 8
This mask should have been 0x_, not 0x0fff_.
The change should not have an effect on current users (STB) because bits
31:27 are unused.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers
This can compile for MIPS (or anything else) now.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers/irqchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b
by brcmstb-l2, the bcm7120-l2 controller
does not latch the IRQ status. Bits can change if the inputs to the
controller change. Also, do_bad_IRQ() is an ARM-specific macro.
So let's just nuke it.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Florian Fainelli f.faine...@gmail.com
The irq-brcmstb-l2 driver has a single dependency on the ARM code, the
do_bad_IRQ macro. Expand this macro in-place so that the driver can be
built on non-ARM platforms.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Florian Fainelli f.faine
This allows us to implement per-irqchip behavior when necessary, instead
of hardcoding the behavior for all irqchip drivers at compile time.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
include/linux/irq.h | 7 ---
kernel/irq/generic-chip.c | 10 ++
2 files changed, 10
Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating
the irqchip.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 15 +--
2 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/include
Defining these macros way down in arch/sh/.../irq.c doesn't cause
kernel/irq/generic-chip.c to use them. As far as I can tell this code
has no effect.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/sh/boards/mach-se/7343/irq.c | 3 ---
arch/sh/boards/mach-se/7722/irq.c | 3 ---
2
Nobody is overriding these definitions anyway, so get rid of the wrappers.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-atmel-aic.c | 40 -
drivers/irqchip/irq-atmel-aic5.c | 65 +++-
drivers/irqchip/irq
On Thu, Oct 30, 2014 at 3:48 AM, Arnd Bergmann a...@arndb.de wrote:
On Thursday 30 October 2014 11:43:00 Thomas Gleixner wrote:
On Thu, 30 Oct 2014, Arnd Bergmann wrote:
On Wednesday 29 October 2014 19:17:55 Kevin Cernekee wrote:
Defining these macros way down in arch/sh/.../irq.c doesn't
On Thu, Oct 30, 2014 at 2:58 AM, Arnd Bergmann a...@arndb.de wrote:
On the MIPS BCM7xxx chips, LE/BE support was a design requirement. So:
- The chips include a strap pin for LE/BE so it can be configured
through board jumpers. This is the only supported method of switching
endianness.
On Thu, Oct 30, 2014 at 4:09 AM, Sergei Shtylyov wrote:
diff --git a/drivers/irqchip/irq-bcm7120-l2.c
b/drivers/irqchip/irq-bcm7120-l2.c
index b9f4fb8..49d8f3d 100644
--- a/drivers/irqchip/irq-bcm7120-l2.c
+++ b/drivers/irqchip/irq-bcm7120-l2.c
[...]
@@ -51,19 +49,12 @@ static void
On Thu, Oct 30, 2014 at 12:52 PM, Arnd Bergmann a...@arndb.de wrote:
Ah, I think I understand what you mean now. So this strapping is done
for legacy operating systems that are not endian-aware and hardwired
to one or the other.
Hmm, maybe, but this wasn't done for legacy reasons. The
On Wed, Nov 19, 2014 at 7:04 PM, Brian Norris
computersforpe...@gmail.com wrote:
On Sat, Nov 15, 2014 at 04:17:24PM -0800, Kevin Cernekee wrote:
The lack of a reboot handler is annoying; syscon-reboot probably won't work
on STB (because it requires two writes).
Can't you reuse drivers/power
On Thu, Nov 20, 2014 at 10:09 AM, Florian Fainelli f.faine...@gmail.com wrote:
Slightly unrelated, did you also try to use drivers/bus/brcmstb_gisb.c
on these MIPS platforms?
Its usefulness is probably lower on MIPS since we typically get accurate
bus errors to be decoded by the CPU and
an interrupt as soon as they call
request_irq(). (This is technically already the correct development
practice, but some drivers probably expect not to receive interrupts
until they have performed some I/O.)
Signed-off-by: Brian Norris computersforpe...@gmail.com
Signed-off-by: Kevin Cernekee cerne
MIPS_L1_CACHE_SHIFT_x option is selected,
Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index
Some machines only have one bus type to register (e.g. simple-bus).
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/kernel/prom.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 452d4350ce42
at
https://github.com/Broadcom/aeolus . The other chips use legacy non-DT
bootloaders, so they will need to select an appropriate builtin DTB at
compile time until the bootloader is updated.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../devicetree/bindings/mips/brcm/bmips.txt| 8
From: Dmitry Torokhov d...@chromium.org
Return value of irq_of_parse_and_map() is unsigned int, with 0
indicating failure, so testing for negative result never works.
Signed-off-by: Dmitry Torokhov d...@chromium.org
Acked-by: Florian Fainelli f.faine...@gmail.com
Tested-by: Kevin Cernekee cerne
, retain the current behavior.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7120-l2-intc.txt | 5 +-
drivers/irqchip/irq-bcm7120-l2.c | 76 +-
2 files changed, 63 insertions(+), 18 deletions(-)
diff --git
exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7038-l1-intc.txt | 52
drivers/irqchip/Kconfig
.
This patch changes the plumbing but doesn't yet provide a way for users
to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 41 +++-
1 file changed, 28
If the machine doesn't set its own _machine_restart callback, call the
common do_kernel_restart() instead. This allows arch-independent reset
drivers from drivers/power/reset/ to be used to reboot the machine.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/kernel/reset.c | 2
. This will allow for eliminating my dma.c.
Brian Norris (1):
irqchip: brcmstb-l2: don't clear wakeable interrupts at init time
Dmitry Torokhov (2):
irqchip: brcmstb-l2: fix error handling of irq_of_parse_and_map
irqchip: bcm7120-l2: fix error handling of irq_of_parse_and_map
Kevin Cernekee
From: Dmitry Torokhov d...@chromium.org
Return value of irq_of_parse_and_map() is unsigned int, with 0
indicating failure, so testing for negative result never works.
Signed-off-by: Dmitry Torokhov d...@chromium.org
Acked-by: Florian Fainelli f.faine...@gmail.com
Tested-by: Kevin Cernekee cerne
Several drivers now use this API, including the ARM GIC driver, so remove
the outdated comment.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
Documentation/IRQ-domain.txt | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/IRQ-domain.txt b/Documentation/IRQ
On Mon, Nov 24, 2014 at 11:29 AM, Andrew Bresticker abres...@google.com wrote:
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
+void __init plat_time_init(void)
+{
+ struct device_node *np;
+ u32 freq;
+
+ np = of_find_node_by_name(NULL, cpus);
+ if
On Mon, Nov 24, 2014 at 6:00 AM, Arnd Bergmann a...@arndb.de wrote:
It mihgt be good to split this into multiple patches
OK. For V4 I could submit the arch/mips/bmips code changes in one
patch, and then add the DTS files in the next patch?
--- /dev/null
+++ b/arch/mips/bmips/Kconfig
@@ -0,0
Update link to point to Steve's current tree on git.samba.org. Remove
link to the old patchwork instance which shows no new patches since 2010.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
MAINTAINERS | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/MAINTAINERS b
, 1000) * 100;
Introduce a temporary u64 abs_t variable to fix this.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
fs/cifs/netmisc.c | 12 +++-
1 file changed, 7 insertions(+), 5 deletions(-)
Note: this is compile-tested only (on a 32-bit build).
diff --git a/fs/cifs/netmisc.c b/fs
On Mon, Nov 10, 2014 at 2:00 PM, Kevin Hilman khil...@kernel.org wrote:
Kevin Cernekee cerne...@gmail.com writes:
Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating
the irqchip.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
I bisected a couple ARM boot failures
On Tue, Dec 23, 2014 at 8:07 AM, Florian Fainelli f.faine...@gmail.com wrote:
2014-12-22 15:27 GMT-08:00 Andrew Bresticker abres...@chromium.org:
Move the MIPS device-trees into the appropriate vendor sub-directories.
Signed-off-by: Andrew Bresticker abres...@chromium.org
---
patches in the series:
Tested-by: Kevin Cernekee cerne...@gmail.com
--
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Please read the FAQ at http
-directories
MIPS: Add dtbs_install target
Brian Norris (1):
irqchip: brcmstb-l2: don't clear wakeable interrupts at init time
Kevin Cernekee (22):
MIPS: bcm3384: Fix outdated use of mips_cpu_intc_init()
MIPS: Create a common asm/mach-generic/war.h
MIPS: bcm3384: Rename bcm3384 target to bmips
dedicated L1 lines
- one enable/status pair (32 bits only)
Much of the driver code can be shared with BCM3380-style controllers, but
in order to do this cleanly, let's split out the BCM7xxx-specific logic
first.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7120
Most of the supported chips use legacy (non-DT) bootloaders, so they will
need to select an appropriate builtin DTB at compile time until the
bootloader is updated. Provide suitable DTS files, and a means to compile
one of them into the kernel image.
Signed-off-by: Kevin Cernekee cerne
The DT bindings for this platform have changed as the bootloader and
product requirements evolved. In particular, there are both
Linux-on-Zephyr and Linux-on-Viper configurations.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/boot/dts/brcm/bcm3384.dtsi| 109
This is a more standardized way of handling DMA remapping, and it is
suitable for the memory map found on BCM3384.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/bmips/dma.c | 100 ++
1 file changed, 68 insertions(+), 32 deletions
MIPS_L1_CACHE_SHIFT_x option is selected,
Kconfig sets CONFIG_MIPS_L1_CACHE_SHIFT to the highest value.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/Kconfig | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 31bbec0
These controllers support multiple enable/status pairs (64+ IRQs),
can put the enable/status words at different offsets, and do not
support multiple parent IRQs.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm3380-l2-intc.txt | 41
drivers
BCM3384/BCM63xx can use the common drivers/irqchip/irq-bcm7120-l2.c for
this purpose; BCM7xxx will use drivers/irqchip/irq-bcm7038-l1.c. We no
longer need this code under arch/mips.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../devicetree/bindings/mips/brcm/bcm3384-intc.txt | 37
.
This patch changes the plumbing but doesn't yet provide a way for users
to instantiate a controller with arbitrary IRQEN/IRQSTAT offsets.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 41 +++-
1 file changed, 28
This function was renamed to mips_cpu_irq_of_init(), so fix it to avoid
a compile error.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/bcm3384/irq.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/bcm3384/irq.c b/arch/mips/bcm3384/irq.c
index
Several drivers now use this API, including the ARM GIC driver, so remove
the outdated comment.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
Documentation/IRQ-domain.txt | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/Documentation/IRQ-domain.txt b/Documentation/IRQ
an interrupt as soon as they call
request_irq(). (This is technically already the correct development
practice, but some drivers probably expect not to receive interrupts
until they have performed some I/O.)
Signed-off-by: Brian Norris computersforpe...@gmail.com
Signed-off-by: Kevin Cernekee cerne
Add an entry for each supported Broadcom SoC.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Signed-off-by: Jaedon Shin jaedon.s...@gmail.com
---
Documentation/devicetree/bindings/mips/brcm/cm-dsl.txt | 11 ---
Documentation/devicetree/bindings/mips/brcm/soc.txt| 12
2
This platform is configured primarily through device tree, and we can
reuse the same code to support a bunch of other chips. Change the name
to reflect this.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/Kbuild.platforms | 2 +-
arch/mips
Also, add an LE defconfig for set-top box (BCM7xxx). This will allow the
BMIPS kernel to run on several non-BCM3384 platforms.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Signed-off-by: Jaedon Shin jaedon.s...@gmail.com
---
arch/mips/Kconfig | 18 +--
arch/mips
A couple of chips require special handling in order to make SMP secondary
boot and/or exception vectors work correctly. Take care of these in
setup.c.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/bmips/setup.c | 101 +++-
1 file
This will be required to support BMIPS3300 platforms.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/include/asm/mach-bmips/spaces.h | 18 ++
1 file changed, 18 insertions(+)
create mode 100644 arch/mips/include/asm/mach-bmips/spaces.h
diff --git a/arch/mips
11 platforms require at least one of these workarounds to be enabled; 22
platforms do not. In the latter case we can fall back to a generic version.
Note that this also deletes an orphaned reference to RM9000_CDEX_SMP_WAR.
Suggested-by: Arnd Bergmann a...@arndb.de
Signed-off-by: Kevin Cernekee
There is no bcm3384 bus so let's just remove it to avoid confusion.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/bmips/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/bmips/setup.c b/arch/mips/bmips/setup.c
index 5099109..ac402ed 100644
From: Andrew Bresticker abres...@chromium.org
Add the dtbs_install Makefile target to install the dtb files into
$INSTALL_DTBS_PATH.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Tested-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/Makefile | 5 +
1 file changed, 5 insertions
Add a new section covering the Generic BMIPS machine type.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
Documentation/devicetree/booting-without-of.txt | 28 +
1 file changed, 28 insertions(+)
diff --git a/Documentation/devicetree/booting-without-of.txt
b
From: Andrew Bresticker abres...@chromium.org
Move the MIPS device-trees into the appropriate vendor sub-directories.
Signed-off-by: Andrew Bresticker abres...@chromium.org
Tested-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/Makefile | 2 +-
arch/mips
-by: Kevin Cernekee cerne...@gmail.com
Signed-off-by: Jaedon Shin jaedon.s...@gmail.com
---
arch/mips/mm/dma-default.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index af5f046..38ee47a 100644
--- a/arch/mips/mm/dma-default.c
If the machine doesn't set its own _machine_restart callback, call the
common do_kernel_restart() instead. This allows arch-independent reset
drivers from drivers/power/reset/ to be used to reboot the machine.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/kernel/reset.c | 2
Some machines only have one bus type to register (e.g. simple-bus).
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/mips/kernel/prom.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/mips/kernel/prom.c b/arch/mips/kernel/prom.c
index 452d435..e303cb1 100644
exists on the ARM BCM7xxx chips, but typically the ARM GIC
is used instead. So this driver is primarily intended for MIPS STB chips.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7038-l1-intc.txt | 52
drivers/irqchip/Kconfig
Defining these macros way down in arch/sh/.../irq.c doesn't cause
kernel/irq/generic-chip.c to use them. As far as I can tell this code
has no effect.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
arch/sh/boards/mach-se/7343/irq.c | 3 ---
arch/sh/boards/mach-se/7722/irq.c | 3 ---
2
Currently, these I/O accessors always assume little endian 32-bit
registers (readl/writel). On some systems the IRQ registers need to be
accessed in BE mode or using 16-bit loads/stores, so we will provide a
way to override the default behavior.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Some chips, such as BCM6328, only require bcm7120-l2. Some BCM7xxx STB
configurations only require brcmstb-l2. Treat them as two separate
entities, and update the mach-bcm dependencies to reflect the change.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann a...@arndb.de
. But that
operation never needs endian swapping, so it's probably not a big deal.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-brcmstb-l2.c | 34 ++
1 file changed, 22 insertions(+), 12 deletions(-)
diff --git a/drivers/irqchip/irq
This mask should have been 0x_, not 0x0fff_.
The change should not have an effect on current users (STB) because bits
31:27 are unused.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers
by brcmstb-l2, the bcm7120-l2 controller
does not latch the IRQ status. Bits can change if the inputs to the
controller change. Also, do_bad_IRQ() is an ARM-specific macro.
So let's just nuke it.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Florian Fainelli f.faine...@gmail.com
enable/status register pair per instance.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
.../interrupt-controller/brcm,bcm7120-l2-intc.txt | 26 ++--
drivers/irqchip/irq-bcm7120-l2.c | 144 ++---
2 files changed, 113 insertions(+), 57 deletions(-)
diff
mode but runs a BE kernel, but currently none
of the supported ARM platforms are ever expected to run BE.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 24 ++--
1 file changed, 14 insertions(+), 10 deletions(-)
diff --git a/drivers
A couple of accesses to IRQEN (base+0x00) just used base directly, so
they would break if IRQEN ever became nonzero. Make sure that all
reads/writes specify the register offset constant.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers
The cached value already incorporates irq_fwd_mask, and was saved the
last time an IRQ was enabled/disabled.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers/irqchip/irq-bcm7120-l2.c | 11 +++
1 file changed, 3 insertions(+), 8
This can compile for MIPS (or anything else) now.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
Acked-by: Arnd Bergmann a...@arndb.de
Acked-by: Florian Fainelli f.faine...@gmail.com
---
drivers/irqchip/Kconfig | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/irqchip/Kconfig b
Use io{read,write}32be if the caller specified IRQ_GC_BE_IO when creating
the irqchip.
Signed-off-by: Kevin Cernekee cerne...@gmail.com
---
include/linux/irq.h | 1 +
kernel/irq/generic-chip.c | 16
2 files changed, 17 insertions(+)
diff --git a/include/linux/irq.h b
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