Re: [PATCH] omap: twl-common: Fix musb-hdrc device name.
Hi,
On Tuesday 03 December 2013 02:03 PM, Marek Belisko wrote:
Without this change when booting omap3 device (gta04) with board file
leads to follwing errors:
[1.203308] musb-hdrc musb-hdrc.0.auto: unable to find phy
[1.209075] HS USB OTG: no transceiver configured
[1.214019] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with
status -517
and usb isn't working.
This is probably regression caused by commit: 6c27f939
I think a better fix would be to have this merged..
https://lkml.org/lkml/2013/7/26/91
Signed-off-by: Marek Belisko marek.beli...@open-nandra.com
---
arch/arm/mach-omap2/twl-common.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/twl-common.c
b/arch/arm/mach-omap2/twl-common.c
index b0d54da..3640ce0 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -92,7 +92,7 @@ void __init omap_pmic_late_init(void)
#if defined(CONFIG_ARCH_OMAP3)
struct phy_consumer consumers[] = {
- PHY_CONSUMER(musb-hdrc.0, usb),
+ PHY_CONSUMER(musb-hdrc.0.auto, usb),
the index '0' might vary for some boards leading it to again break musb.
Thanks
Kishon
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Re: [PATCH] omap: twl-common: Fix musb-hdrc device name.
Hi,
On Tuesday 03 December 2013 02:38 PM, Belisko Marek wrote:
Hi,
On Tue, Dec 3, 2013 at 9:58 AM, Kishon Vijay Abraham I kis...@ti.com wrote:
Hi,
On Tuesday 03 December 2013 02:03 PM, Marek Belisko wrote:
Without this change when booting omap3 device (gta04) with board file
leads to follwing errors:
[1.203308] musb-hdrc musb-hdrc.0.auto: unable to find phy
[1.209075] HS USB OTG: no transceiver configured
[1.214019] musb-hdrc musb-hdrc.0.auto: musb_init_controller failed with
status -517
and usb isn't working.
This is probably regression caused by commit: 6c27f939
I think a better fix would be to have this merged..
https://lkml.org/lkml/2013/7/26/91
Yes I see but how this could help with current situation? Ho you then
specify device number?
With this we can for sure know the device numbering (of MUSB) starts from '0'.
If we use PLATFORM_DEVID_AUTO, we won't know what dev number has been assigned
to us. In your case you get musb-hdrc.0.auto because no one else is creating
a device using PLATFORM_DEVID_AUTO (before your device is created).
This patch is fixing 3.13-rcx regression.
Signed-off-by: Marek Belisko marek.beli...@open-nandra.com
---
arch/arm/mach-omap2/twl-common.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-omap2/twl-common.c
b/arch/arm/mach-omap2/twl-common.c
index b0d54da..3640ce0 100644
--- a/arch/arm/mach-omap2/twl-common.c
+++ b/arch/arm/mach-omap2/twl-common.c
@@ -92,7 +92,7 @@ void __init omap_pmic_late_init(void)
#if defined(CONFIG_ARCH_OMAP3)
struct phy_consumer consumers[] = {
- PHY_CONSUMER(musb-hdrc.0, usb),
+ PHY_CONSUMER(musb-hdrc.0.auto, usb),
the index '0' might vary for some boards leading it to again break musb.
If you run grep for musb-hdrc :
arch/arm/mach-omap2/board-3430sdp.c: usb_bind_phy(musb-hdrc.0.auto,
0, twl4030_usb);
arch/arm/mach-omap2/board-devkit8000.c:
usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb);
arch/arm/mach-omap2/board-overo.c: usb_bind_phy(musb-hdrc.0.auto, 0,
twl4030_usb);
arch/arm/mach-omap2/board-omap3beagle.c:
usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb);
arch/arm/mach-omap2/board-omap3touchbook.c:
usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb);
arch/arm/mach-omap2/board-cm-t35.c: usb_bind_phy(musb-hdrc.0.auto,
0, twl4030_usb);
arch/arm/mach-omap2/board-omap3stalker.c:
usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb);
arch/arm/mach-omap2/board-omap3logic.c:
usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb);
arch/arm/mach-omap2/board-2430sdp.c: usb_bind_phy(musb-hdrc.0.auto,
0, twl4030_usb);
arch/arm/mach-omap2/board-ldp.c: usb_bind_phy(musb-hdrc.0.auto, 0,
twl4030_usb);
arch/arm/mach-omap2/board-rx51.c: usb_bind_phy(musb-hdrc.0.auto, 0,
twl4030_usb);
arch/arm/mach-omap2/board-omap3pandora.c:
usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb);
hmm.. that patch was in a series that fixes this too
https://lkml.org/lkml/2013/7/26/88
Thanks
Kishon
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Re: [PATCH v2 1/7] usb: dwc3: get usb_phy only if the platform indicates the presence of PHY's
Hi,
On Tuesday 26 November 2013 03:02 AM, Felipe Balbi wrote:
Hi,
On Mon, Nov 11, 2013 at 08:06:12PM +0530, Kishon Vijay Abraham I wrote:
diff --git a/drivers/usb/dwc3/platform_data.h
b/drivers/usb/dwc3/platform_data.h
index 7db34f0..49ffa6d 100644
--- a/drivers/usb/dwc3/platform_data.h
+++ b/drivers/usb/dwc3/platform_data.h
@@ -24,4 +24,6 @@ struct dwc3_platform_data {
enum usb_device_speed maximum_speed;
enum usb_dr_mode dr_mode;
bool tx_fifo_resize;
+ bool usb2_phy;
+ bool usb3_phy;
This would look better as a quirks flag, then we could:
unsigned long quirks;
#define DWC3_QUIRK_NO_USB3_PHY BIT(0)
#define DWC3_QUIRK_NO_USB2_PHY BIT(1)
Should this quirk be used for dt also? Currently we find if it has usb3 phy
or
usb2 phy from the dt data only. But if we add a quirk, we'll have to add a
property to populate the quirk no?
either we use the quirk, or use the fact that no usb2_phy phandle is
defined, would work both ways, no ?
In my v3, I've made both to use quirks since we don't want to have separate
mechanism for dt and non-dt stuff to know the presence of a particular PHY.
Thanks
Kishon
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[PATCH v2] phy: kconfig: add depends on USB_PHY to OMAP_USB2 and TWL4030_USB
Fixes warning: (OMAP_USB2 TWL4030_USB) selects USB_PHY which has unmet direct dependencies (USB_SUPPORT) that shows up while disabling USB_SUPPORT from menuconfig. Reported-by: Russell King li...@arm.linux.org.uk Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Acked-by: Felipe Balbi ba...@ti.com --- Changes from v1: * changed from *depends on USB_SUPPORT* to *depends on USB_PHY and also changed the subject. drivers/phy/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..330ef2d 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -24,8 +24,8 @@ config PHY_EXYNOS_MIPI_VIDEO config OMAP_USB2 tristate OMAP USB2 PHY Driver depends on ARCH_OMAP2PLUS + depends on USB_PHY select GENERIC_PHY - select USB_PHY select OMAP_CONTROL_USB help Enable this to support the transceiver that is part of SOC. This @@ -36,8 +36,8 @@ config OMAP_USB2 config TWL4030_USB tristate TWL4030 USB Transceiver Driver depends on TWL4030_CORE REGULATOR_TWL4030 USB_MUSB_OMAP2PLUS + depends on USB_PHY select GENERIC_PHY - select USB_PHY help Enable this to support the USB OTG transceiver on TWL4030 family chips (including the TWL5030 and TPS659x0 devices). -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v2 2/7] usb: dwc3: adapt dwc3 core to use Generic PHY Framework
Hi,
On Tuesday 03 December 2013 05:29 PM, Heikki Krogerus wrote:
Hi Kishon,
On Wed, Oct 16, 2013 at 01:24:12AM +0530, Kishon Vijay Abraham I wrote:
+count = of_property_match_string(node, phy-names, usb2-phy);
+if (count = 0 || (pdata pdata-usb2_generic_phy)) {
+dwc-usb2_generic_phy = devm_phy_get(dev, usb2-phy);
+if (IS_ERR(dwc-usb2_generic_phy)) {
+dev_err(dev, no usb2 phy configured yet);
+return PTR_ERR(dwc-usb2_generic_phy);
+}
+dwc-usb2_phy = NULL;
+}
+
+count = of_property_match_string(node, phy-names, usb3-phy);
+if (count = 0 || (pdata pdata-usb3_generic_phy)) {
+dwc-usb3_generic_phy = devm_phy_get(dev, usb3-phy);
+if (IS_ERR(dwc-usb3_generic_phy)) {
+dev_err(dev, no usb3 phy configured yet);
+return PTR_ERR(dwc-usb3_generic_phy);
+}
+dwc-usb3_phy = NULL;
+}
Is there some specific reason for these checks? The driver should not
need to care about the platform (DT, ACPI, platform based).
yeah just wanted to throw an error if a platform needs PHY but wasn't able to
get it. Btw this has changed after my v3 of this patch series which I sent
sometime back [1] where we use quirks to know if a PHY is needed for that
platform or not.
http://www.spinics.net/lists/linux-usb/msg98077.html
Thanks
Kishon
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Re: [PATCH RFC 1/4] phy: Add new Exynos5 USB 3.0 PHY driver
Hi Vivek, On Wednesday 20 November 2013 09:14 PM, Kishon Vijay Abraham I wrote: Hi, On Wednesday 20 November 2013 03:02 PM, Vivek Gautam wrote: On Wed, Nov 20, 2013 at 2:34 PM, Kishon Vijay Abraham I kis...@ti.com wrote: On Wednesday 20 November 2013 02:27 PM, Vivek Gautam wrote: Hi Kishon, On Mon, Nov 11, 2013 at 4:41 PM, Kishon Vijay Abraham I kis...@ti.com wrote: Hi, sorry for the delayed response. On Wednesday 06 November 2013 05:37 AM, Jingoo Han wrote: On Wednesday, November 06, 2013 2:58 AM, Vivek Gautam wrote: On Tue, Nov 5, 2013 at 5:33 PM, Jingoo Han jg1@samsung.com wrote: [.] USB3.0 PHY consists of two blocks such as 3.0 block and 2.0 block. This USB3.0 PHY can support UTMI+ and PIPE3 interface for 3.0 block and 2.0 block, respectively. Conclusion: 1) USB2.0 PHY: USB2.0 HOST, USB2.0 Device Base address: 0x1213 2) USB3.0 PHY: USB3.0 DRD (3.0 HOST 3.0 Device) Base address: 0x1210 2.0 block(UTMI+) 3.0 block(PIPE3) And this is of course the PHY used by DWC3 controller, which works at both High speed as well as Super Speed. Right ? Right. While 3.0 block(PIPE3) can be used for Super Speed, 2.0 block(UTMI+) can be used for High speed. It should then come under *single IP muliple PHY* category similar to what Sylwester has done. Do you mean that i should be including PHY IDs for UTMI+ phy and PIPE3 phy present in this PHY block ? AFAICS the two phys (UTMI+ and PIPE3) do not really have separate registers to program, and that's the reason we program the entire PHY in a shot. you mean you program the same set of bits for UTMI+ and PIPE3? No, looking closely into PHY datasheet as well as Exynos5250 manual, i can see that UTMI+ and PIPE3 phys have separate bit settings. So i think we should be able to segregate the two PHYs (UTMI+ and PIPE3). Pardon me for my earlier observations. no problem.. Let me clarify more with our h/w team also on this and then i will confirm with this. Did you get more information on this? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v3 04/10] usb: dwc3: use quirks to know if a particualr platform doesn't have PHY
Hi, On Wednesday 04 December 2013 08:10 PM, Heikki Krogerus wrote: Hi guys, Kishon, sorry I did not see this v3 set. On Mon, Nov 25, 2013 at 03:31:24PM +0530, Kishon Vijay Abraham I wrote: There can be systems which does not have an external phy, so get phy only if no quirks are added that indicates the PHY is not present. Introduced two quirk flags to indicate the *absence* of usb2 phy and usb3 phy. Also remove checking if return value is -ENXIO since it's now changed to always enable usb_phy layer. Can you guys explain why is something like this needed? Like with clocks and gpios, the device drivers shouldn't need to care any more if the platform has the phys or not. -ENODEV tells you your platform Shouldn't we report if a particular platform needs a PHY and not able to get it. How will a user know if a particular controller is not working because it's not able to get and initialize the PHYs? Don't you think in such cases it's better to fail (and return from probe) because the controller will not work anyway without the PHY? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v4 0/9] phy: Add new Exynos USB 2.0 PHY driver
Hi, On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote: Hi, This is the fourth version of the patchset adding the new Exynos USB 2.0 PHY driver. The driver uses the Generic PHY Framework. A month has passed since the last version. I have addressed numerous comments that appeared on the mailing list in this patch. I would like to specially thank Kishon, Tomasz, Matt and Vivek for their comments. This patch contains two necessary patches to the phy core. It is very useful to be able to get phy using a device tree node. In addition this patch depends on: [PATCH V11 1/3] ARM: dts: Add pmu sysreg node to exynos5250 and exynos5420 dtsi files [1]. Best wishes, Kamil Debski The last four patches are missing [1] [1] - https://lkml.org/lkml/2013/12/5/166 Thanks Kishon [1] - http://www.spinics.net/lists/linux-samsung-soc/msg24528.html Changes from v3: - using PMU and system registers indirectly via syscon - change labelling - change Kconfig name - fixed typos/stray whitespace - move of_phy_provider_register() to the end of probe - add a regular error return code to the rate_to_clk functions - cleanup code and remove unused code - change struct names to avoid collisions - add mechanism to support multiple phys by the ehci driver Changes from v2: - rebase all patches to the usb-next branch - fixes in the documentation file - remove wrong entries in the phy node (ranges, and #address- #size-cells) - add clocks and clock-names as required properites - rephrase a few sentences - fixes in the ehci-exynos.c file - move phy_name variable next to phy in exynos_ehci_hcd - remove otg from exynos_ehci_hcd as it was no longer used - move devm_phy_get after the Exynos5440 skip_phy check - fixes in the s3c-hsotg.c file - cosmetic fixes (remove empty line that was wrongfully added) - fixes in the main driver - remove cpu_type in favour for a boolean flag matched with the compatible value - rename files, structures, variables and Kconfig entires - change from simple uphy to usb2_phy - fix multiline comments style - simplify #ifdefs in of_device_id - fix Kconfig description - change dev_info to dev_dbg where reasonable - cosmetic changes (remove wrongful blank lines) - remove unnecessary reference counting Changes from v1: - the changes include minor fixes of the hardware initialization of the PHY module - some other minor fixes were introduced -- Original cover letter: Hi, This patch adds a new drive for USB PHYs for Samsung SoCs. The driver is using the Generic PHY Framework created by Kishon Vijay Abrahan I. It can be found here https://lkml.org/lkml/2013/8/21/29. This patch adds support to Exynos4 family of SoCs. Support for Exynos3 and Exynos5 is planned to be added in the near future. I welcome your comments. -- [1] https://lkml.org/lkml/2013/8/21/29 Kamil Debski (8): phy: core: Change the way of_phy_get is called phy: core: Add devm_of_phy_get to phy-core phy: Add new Exynos USB PHY driver usb: ehci-s5p: Change to use phy provided by the generic phy framework usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver dts: Add usb2phy to Exynos 4 dts: Add usb2phy to Exynos 5250 Mateusz Krawczuk (1): phy: Add support for S5PV210 to the Exynos USB PHY driver .../devicetree/bindings/arm/samsung/pmu.txt|2 + .../devicetree/bindings/phy/samsung-usbphy.txt | 56 +++ .../devicetree/bindings/usb/samsung-hsotg.txt |4 + Documentation/devicetree/bindings/usb/usb-ehci.txt | 35 ++ arch/arm/boot/dts/exynos4.dtsi | 31 ++ arch/arm/boot/dts/exynos4210.dtsi | 17 + arch/arm/boot/dts/exynos4x12.dtsi | 17 + arch/arm/boot/dts/exynos5250.dtsi | 33 +- drivers/phy/Kconfig| 35 ++ drivers/phy/Makefile |5 + drivers/phy/phy-core.c | 43 ++- drivers/phy/phy-exynos4210-usb2.c | 264 ++ drivers/phy/phy-exynos4212-usb2.c | 312 + drivers/phy/phy-exynos5250-usb2.c | 363 drivers/phy/phy-s5pv210-usb2.c | 206 +++ drivers/phy/phy-samsung-usb2.c | 240 + drivers/phy/phy-samsung-usb2.h | 74 drivers/usb/gadget/s3c-hsotg.c | 11 +- drivers/usb/host/ehci-exynos.c | 95 +++-- include/linux/phy/phy.h|3 + 20 files changed, 1789 insertions(+), 57 deletions(-) create mode 100644
Re: [PATCH 1/9] phy: core: Change the way of_phy_get is called
Hi,
On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
Previously the of_phy_get function took a struct device * and
was declared static. It was impossible to call it from
another driver and thus it was impossible to get phy defined
It was never intended to be called from other drivers. What's up with the
wrapper of of_phy_get, phy_get()/devm_phy_get()? Why isn't that enough?
Thanks
Kishon
for a given node.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
drivers/phy/phy-core.c | 12 +---
include/linux/phy/phy.h |1 +
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 03cf8fb..7fb3474 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -250,20 +250,17 @@ EXPORT_SYMBOL_GPL(phy_power_off);
* not yet loaded. This function uses of_xlate call back function provided
* while registering the phy_provider to find the phy instance.
*/
-static struct phy *of_phy_get(struct device *dev, int index)
+struct phy *of_phy_get(struct device_node *np, int index)
{
int ret;
struct phy_provider *phy_provider;
struct phy *phy = NULL;
struct of_phandle_args args;
- ret = of_parse_phandle_with_args(dev-of_node, phys, #phy-cells,
+ ret = of_parse_phandle_with_args(np, phys, #phy-cells,
index, args);
- if (ret) {
- dev_dbg(dev, failed to get phy in %s node\n,
- dev-of_node-full_name);
+ if (ret)
return ERR_PTR(-ENODEV);
- }
mutex_lock(phy_provider_mutex);
phy_provider = of_phy_provider_lookup(args.np);
@@ -281,6 +278,7 @@ err0:
return phy;
}
+EXPORT_SYMBOL_GPL(of_phy_get);
/**
* phy_put() - release the PHY
@@ -370,7 +368,7 @@ struct phy *phy_get(struct device *dev, const char
*string)
if (dev-of_node) {
index = of_property_match_string(dev-of_node, phy-names,
string);
- phy = of_phy_get(dev, index);
+ phy = of_phy_get(dev-of_node, index);
if (IS_ERR(phy)) {
dev_err(dev, unable to find phy\n);
return phy;
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 6d72269..169f572 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -131,6 +131,7 @@ struct phy *phy_get(struct device *dev, const char
*string);
struct phy *devm_phy_get(struct device *dev, const char *string);
void phy_put(struct phy *phy);
void devm_phy_put(struct device *dev, struct phy *phy);
+struct phy *of_phy_get(struct device_node *np, int index);
struct phy *of_phy_simple_xlate(struct device *dev,
struct of_phandle_args *args);
struct phy *phy_create(struct device *dev, const struct phy_ops *ops,
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Re: [PATCH v4 3/9] phy: Add new Exynos USB PHY driver
Hi,
On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/phy/samsung-usbphy.txt | 54
drivers/phy/Kconfig| 20 ++
drivers/phy/Makefile |3 +
drivers/phy/phy-exynos4210-usb2.c | 264 +
drivers/phy/phy-exynos4212-usb2.c | 312
drivers/phy/phy-samsung-usb2.c | 228 ++
drivers/phy/phy-samsung-usb2.h | 72 +
7 files changed, 953 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/samsung-usbphy.txt
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4212-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
new file mode 100644
index 000..cadbf70
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt
use the existing samsung-phy.txt.
@@ -0,0 +1,54 @@
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usb2-phy
+ - samsung,exynos4212-usb2-phy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system
registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clocks is required by the phy module
+ - next for each of the phys a clock has to be assidned, this clock
%s/assidned/assigned/
+ will be used to determine clocking frequency for the phys
+ (the labels are specified in the paragraph below)
+
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos
4210
+and Exynos 4212) it is as follows:
+ 0 - USB device (device),
+ 1 - USB host (host),
+ 2 - HSIC0 (hsic0),
+ 3 - HSIC1 (hsic1),
+
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+usbphy: phy@125B {
use lower case for address here...
+ compatible = samsung,exynos4212-usb2-phy;
+ reg = 0x125B 0x100 0x10020704 0x0c 0x1001021c 0x4;
and here..
+ clocks = clock 305, clock 2, clock 2, clock 2,
+ clock 2;
+ clock-names = phy, device, host, hsic0, hsic1;
+ status = okay;
+ #phy-cells = 1;
+ samsung,sysreg-phandle = sys_reg;
+ samsung,pmureg-phandle = pmu_reg;
+};
+
+Then the PHY can be used in other nodes such as:
+
+phy-consumer@1234 {
+ phys = usbphy 2;
+ phy-names = phy;
+};
+
+Refer to DT bindings documentation of particular PHY consumer devices for
more
+information about required PHYs and the way of specification.
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index a344f3d..b29018f 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -51,4 +51,24 @@ config PHY_EXYNOS_DP_VIDEO
help
Support for Display Port PHY found on Samsung EXYNOS SoCs.
+config PHY_SAMSUNG_USB2
+ tristate Samsung USB 2.0 PHY driver
+ help
+ Enable this to support Samsung USB phy helper driver for Samsung SoCs.
+ This driver provides common interface to interact, for Samsung
+ USB 2.0 PHY driver.
+
+config PHY_EXYNOS4210_USB2
+ bool Support for Exynos 4210
+ depends on PHY_SAMSUNG_USB2
+ depends on CPU_EXYNOS4210
select GENERIC_PHY here?
+ help
+ Enable USB PHY support for Exynos 4210
Add more explanation here and make checkpatch happy.
+
+config PHY_EXYNOS4212_USB2
+ bool Support for Exynos 4212
+ depends on PHY_SAMSUNG_USB2
+ depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412)
select GENERIC_PHY.
+ help
+ Enable USB PHY support for Exynos 4212
more explanation here too..
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index d0caae9..9f4befd 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,3 +7,6 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
Re: [PATCH v4 5/9] usb: s3c-hsotg: Use the new Exynos USB phy driver with the generic phy framework
Hi,
On Thursday 05 December 2013 05:59 PM, Kamil Debski wrote:
Change the used phy driver to the new Exynos USB phy driver that uses the
generic phy framework.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com
---
.../devicetree/bindings/usb/samsung-hsotg.txt |4
drivers/usb/gadget/s3c-hsotg.c | 11 ++-
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
index b83d428..9340d06 100644
--- a/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-hsotg.txt
@@ -24,6 +24,8 @@ Required properties:
- first entry: must be otg
- vusb_d-supply: phandle to voltage regulator of digital section,
- vusb_a-supply: phandle to voltage regulator of analog section.
+- phys: from general PHY binding: phandle to the PHY device
+- phy-names: from general PHY binding: should be usb2-phy
are you sure it's usb2-phy. The example below seems to have a different value.
Thanks
Kishon
Example
-
@@ -36,5 +38,7 @@ Example
clock-names = otg;
vusb_d-supply = vusb_reg;
vusb_a-supply = vusbdac_reg;
+ phys = usb2phy 0;
+ phy-names = device;
};
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index eccb147..db096fd 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -31,6 +31,7 @@
#include linux/regulator/consumer.h
#include linux/of.h
#include linux/of_platform.h
+#include linux/phy/phy.h
#include linux/usb/ch9.h
#include linux/usb/gadget.h
@@ -162,7 +163,7 @@ struct s3c_hsotg_ep {
struct s3c_hsotg {
struct device*dev;
struct usb_gadget_driver *driver;
- struct usb_phy *phy;
+ struct phy *phy;
struct s3c_hsotg_plat*plat;
spinlock_t lock;
@@ -2905,7 +2906,7 @@ static void s3c_hsotg_phy_enable(struct s3c_hsotg
*hsotg)
dev_dbg(hsotg-dev, pdev 0x%p\n, pdev);
if (hsotg-phy)
- usb_phy_init(hsotg-phy);
+ phy_power_on(hsotg-phy);
else if (hsotg-plat-phy_init)
hsotg-plat-phy_init(pdev, hsotg-plat-phy_type);
}
@@ -2922,7 +2923,7 @@ static void s3c_hsotg_phy_disable(struct s3c_hsotg
*hsotg)
struct platform_device *pdev = to_platform_device(hsotg-dev);
if (hsotg-phy)
- usb_phy_shutdown(hsotg-phy);
+ phy_power_off(hsotg-phy);
else if (hsotg-plat-phy_exit)
hsotg-plat-phy_exit(pdev, hsotg-plat-phy_type);
}
@@ -3529,7 +3530,7 @@ static void s3c_hsotg_delete_debug(struct s3c_hsotg
*hsotg)
static int s3c_hsotg_probe(struct platform_device *pdev)
{
struct s3c_hsotg_plat *plat = dev_get_platdata(pdev-dev);
- struct usb_phy *phy;
+ struct phy *phy;
struct device *dev = pdev-dev;
struct s3c_hsotg_ep *eps;
struct s3c_hsotg *hsotg;
@@ -3544,7 +3545,7 @@ static int s3c_hsotg_probe(struct platform_device *pdev)
return -ENOMEM;
}
- phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
+ phy = devm_phy_get(pdev-dev, usb2-phy);
if (IS_ERR(phy)) {
/* Fallback for pdata */
plat = dev_get_platdata(pdev-dev);
--
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Re: [PATCH v4 6/9] phy: Add support for S5PV210 to the Exynos USB PHY driver
Hi, On Friday 06 December 2013 04:01 PM, Kamil Debski wrote: From: Mateusz Krawczuk mat.krawc...@gmail.com Add support for the Samsung's S5PV210 SoC to the Exynos USB PHY driver. Signed-off-by: Mateusz Krawczuk m.krawc...@partner.samsung.com [k.deb...@samsung.com: cleanup and commit description] [k.deb...@samsung.com: make changes accordingly to the mailing list comments] Signed-off-by: Kamil Debski k.deb...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/phy/samsung-usbphy.txt |1 + drivers/phy/Kconfig|7 + drivers/phy/Makefile |1 + drivers/phy/phy-s5pv210-usb2.c | 206 drivers/phy/phy-samsung-usb2.c |6 + drivers/phy/phy-samsung-usb2.h |1 + 6 files changed, 222 insertions(+) create mode 100644 drivers/phy/phy-s5pv210-usb2.c diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt index cadbf70..77a8e9c 100644 --- a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt @@ -3,6 +3,7 @@ Samsung S5P/EXYNOS SoC series USB PHY Required properties: - compatible : should be one of the listed compatibles: + - samsung,s5pv210-usb2-phy - samsung,exynos4210-usb2-phy - samsung,exynos4212-usb2-phy - reg : a list of registers used by phy driver diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index b29018f..2e433cd 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -58,6 +58,13 @@ config PHY_SAMSUNG_USB2 This driver provides common interface to interact, for Samsung USB 2.0 PHY driver. +config PHY_S5PV210_USB2 + bool Support for S5PV210 + depends on PHY_SAMSUNG_USB2 + depends on ARCH_S5PV210 + help + Enable USB PHY support for S5PV210 more description here.. + config PHY_EXYNOS4210_USB2 bool Support for Exynos 4210 depends on PHY_SAMSUNG_USB2 diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 9f4befd..fefc6c2 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -8,5 +8,6 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o obj-$(CONFIG_TWL4030_USB)+= phy-twl4030-usb.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-samsung-usb2.o +obj-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS4210_USB2)+= phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4212_USB2)+= phy-exynos4212-usb2.o diff --git a/drivers/phy/phy-s5pv210-usb2.c b/drivers/phy/phy-s5pv210-usb2.c new file mode 100644 index 000..528a114 --- /dev/null +++ b/drivers/phy/phy-s5pv210-usb2.c @@ -0,0 +1,206 @@ +/* + * Samsung SoC USB 1.1/2.0 PHY driver - S5PV210 support + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Authors: Kamil Debski k.deb...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/spinlock.h I think my comments for the previous patch with a similar driver (phy-exynos4210-usb2.c) is applicable here also. Thanks Kishon +#include phy-samsung-usb2.h + +/* Exynos USB PHY registers */ + +/* PHY power control */ +#define S5PV210_UPHYPWR 0x0 + +#define S5PV210_UPHYPWR_PHY0_SUSPEND (1 0) +#define S5PV210_UPHYPWR_PHY0_PWR (1 3) +#define S5PV210_UPHYPWR_PHY0_OTG_PWR (1 4) +#define S5PV210_UPHYPWR_PHY0 ( \ + S5PV210_UPHYPWR_PHY0_SUSPEND | \ + S5PV210_UPHYPWR_PHY0_PWR | \ + S5PV210_UPHYPWR_PHY0_OTG_PWR) + +#define S5PV210_UPHYPWR_PHY1_SUSPEND (1 6) +#define S5PV210_UPHYPWR_PHY1_PWR (1 7) +#define S5PV210_UPHYPWR_PHY1 ( \ + S5PV210_UPHYPWR_PHY1_SUSPEND | \ + S5PV210_UPHYPWR_PHY1_PWR) + +/* PHY clock control */ +#define S5PV210_UPHYCLK 0x4 + +#define S5PV210_UPHYCLK_PHYFSEL_MASK (0x3 0) +#define S5PV210_UPHYCLK_PHYFSEL_48MHZ(0x0 0) +#define S5PV210_UPHYCLK_PHYFSEL_24MHZ(0x3 0) +#define S5PV210_UPHYCLK_PHYFSEL_12MHZ(0x2 0) + +#define S5PV210_UPHYCLK_PHY0_ID_PULLUP (0x1 2) +#define S5PV210_UPHYCLK_PHY0_COMMON_ON (0x1 4) +#define S5PV210_UPHYCLK_PHY1_COMMON_ON (0x1 7) + +/* PHY reset control */ +#define S5PV210_UPHYRST 0x8 + +#define S5PV210_URSTCON_PHY0
Re: [PATCH v4 7/9] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
On Friday 06 December 2013 04:02 PM, Kamil Debski wrote: Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Signed-off-by: Kamil Debski k.deb...@samsung.com Signed-off-by: Kyungmin Park kyungmin.p...@samsung.com --- .../devicetree/bindings/phy/samsung-usbphy.txt |1 + drivers/phy/Kconfig|8 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5250-usb2.c | 363 drivers/phy/phy-samsung-usb2.c |6 + drivers/phy/phy-samsung-usb2.h |1 + 6 files changed, 380 insertions(+) create mode 100644 drivers/phy/phy-exynos5250-usb2.c diff --git a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt index 77a8e9c..94096fc 100644 --- a/Documentation/devicetree/bindings/phy/samsung-usbphy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-usbphy.txt @@ -6,6 +6,7 @@ Required properties: - samsung,s5pv210-usb2-phy - samsung,exynos4210-usb2-phy - samsung,exynos4212-usb2-phy + - samsung,exynos5250-usb2-phy - reg : a list of registers used by phy driver - first and obligatory is the location of phy modules registers - samsung,sysreg-phandle - handle to syscon used to control the system registers diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 2e433cd..74e9064 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -78,4 +78,12 @@ config PHY_EXYNOS4212_USB2 depends on (SOC_EXYNOS4212 || SOC_EXYNOS4412) help Enable USB PHY support for Exynos 4212 + +config PHY_EXYNOS5250_USB2 + bool Support for Exynos 5250 + depends on PHY_SAMSUNG_USB2 + depends on SOC_EXYNOS5250 + help + Enable USB PHY support for Exynos 5250 My comments for the previous patch is applicable here too.. Thanks Kishon + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index fefc6c2..33c3ac1 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-samsung-usb2.o obj-$(CONFIG_PHY_S5PV210_USB2) += phy-s5pv210-usb2.o obj-$(CONFIG_PHY_EXYNOS4210_USB2)+= phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4212_USB2)+= phy-exynos4212-usb2.o +obj-$(CONFIG_PHY_EXYNOS5250_USB2)+= phy-exynos5250-usb2.o diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c new file mode 100644 index 000..7aeebc8 --- /dev/null +++ b/drivers/phy/phy-exynos5250-usb2.c @@ -0,0 +1,363 @@ +/* + * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Kamil Debski k.deb...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/clk.h +#include linux/delay.h +#include linux/io.h +#include linux/kernel.h +#include linux/module.h +#include linux/of.h +#include linux/of_address.h +#include linux/phy/phy.h +#include linux/platform_device.h +#include linux/regmap.h +#include linux/spinlock.h +#include phy-samsung-usb2.h + +/* Exynos USB PHY registers */ +#define EXYNOS_5250_REFCLKSEL_CRYSTAL0x0 +#define EXYNOS_5250_REFCLKSEL_XO 0x1 +#define EXYNOS_5250_REFCLKSEL_CLKCORE0x2 + +#define EXYNOS_5250_FSEL_9MHZ6 0x0 +#define EXYNOS_5250_FSEL_10MHZ 0x1 +#define EXYNOS_5250_FSEL_12MHZ 0x2 +#define EXYNOS_5250_FSEL_19MHZ2 0x3 +#define EXYNOS_5250_FSEL_20MHZ 0x4 +#define EXYNOS_5250_FSEL_24MHZ 0x5 +#define EXYNOS_5250_FSEL_50MHZ 0x7 + +/* Normal host */ +#define EXYNOS_5250_HOSTPHYCTRL0 0x0 + +#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL (0x1 31) +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19 +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK \ + (0x3 EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT 16 +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \ + (0x7 EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNIN (0x1 11) +#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE (0x1 10) +#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N (0x1 9) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK (0x3 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL (0x0 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST(0x2 7) +#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ (0x1 6)
[PATCH v2 0/2] usb: fix controller-PHY binding for OMAP3 platform
After the platform devices are created using PLATFORM_DEVID_AUTO, the device names given in usb_bind_phy (in board file) does not match with the actual device name causing the USB PHY library not to return the PHY reference when the MUSB controller request for the PHY in the non-dt boot case. So removed creating platform devices using PLATFORM_DEVID_AUTO in omap2430.c. Changes from v1: * refreshed to the latested mainline kernel * added musb_put_id from omap2430 remove. Kishon Vijay Abraham I (2): usb: musb: omap: remove using PLATFORM_DEVID_AUTO in omap2430.c arm: omap: remove *.auto* from device names given in usb_bind_phy arch/arm/mach-omap2/board-2430sdp.c|2 +- arch/arm/mach-omap2/board-3430sdp.c|2 +- arch/arm/mach-omap2/board-cm-t35.c |2 +- arch/arm/mach-omap2/board-devkit8000.c |2 +- arch/arm/mach-omap2/board-ldp.c|2 +- arch/arm/mach-omap2/board-omap3beagle.c|2 +- arch/arm/mach-omap2/board-omap3logic.c |2 +- arch/arm/mach-omap2/board-omap3pandora.c |2 +- arch/arm/mach-omap2/board-omap3stalker.c |2 +- arch/arm/mach-omap2/board-omap3touchbook.c |2 +- arch/arm/mach-omap2/board-overo.c |2 +- arch/arm/mach-omap2/board-rx51.c |2 +- drivers/usb/musb/musb_core.c | 31 +++- drivers/usb/musb/musb_core.h |2 ++ drivers/usb/musb/omap2430.c| 19 +++-- 15 files changed, 61 insertions(+), 15 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v2 2/2] arm: omap: remove *.auto* from device names given in usb_bind_phy
Previously MUSB wrapper (OMAP) device used PLATFORM_DEVID_AUTO while creating MUSB core device. So in usb_bind_phy (binds the controller with the PHY), the device name of the controller had *.auto* in it. Since with using PLATFORM_DEVID_AUTO, there is no way to know the exact device name in advance, the data given in usb_bind_phy became obsolete and usb_get_phy was failing. So MUSB wrapper was modified not to use PLATFORM_DEVID_AUTO. Corresponding change is done in board file here. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- arch/arm/mach-omap2/board-2430sdp.c|2 +- arch/arm/mach-omap2/board-3430sdp.c|2 +- arch/arm/mach-omap2/board-cm-t35.c |2 +- arch/arm/mach-omap2/board-devkit8000.c |2 +- arch/arm/mach-omap2/board-ldp.c|2 +- arch/arm/mach-omap2/board-omap3beagle.c|2 +- arch/arm/mach-omap2/board-omap3logic.c |2 +- arch/arm/mach-omap2/board-omap3pandora.c |2 +- arch/arm/mach-omap2/board-omap3stalker.c |2 +- arch/arm/mach-omap2/board-omap3touchbook.c |2 +- arch/arm/mach-omap2/board-overo.c |2 +- arch/arm/mach-omap2/board-rx51.c |2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/arch/arm/mach-omap2/board-2430sdp.c b/arch/arm/mach-omap2/board-2430sdp.c index c711ad6..cc679c6 100644 --- a/arch/arm/mach-omap2/board-2430sdp.c +++ b/arch/arm/mach-omap2/board-2430sdp.c @@ -246,7 +246,7 @@ static void __init omap_2430sdp_init(void) omap_hsmmc_init(mmc); omap_mux_init_signal(usb0hs_stp, OMAP_PULL_ENA | OMAP_PULL_UP); - usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb); + usb_bind_phy(musb-hdrc.0, 0, twl4030_usb); usb_musb_init(NULL); board_smc91x_init(); diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c index d95d0ef..873e463 100644 --- a/arch/arm/mach-omap2/board-3430sdp.c +++ b/arch/arm/mach-omap2/board-3430sdp.c @@ -607,7 +607,7 @@ static void __init omap_3430sdp_init(void) omap_ads7846_init(1, gpio_pendown, 310, NULL); omap_serial_init(); omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL); - usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb); + usb_bind_phy(musb-hdrc.0, 0, twl4030_usb); usb_musb_init(NULL); board_smc91x_init(); board_flash_init(sdp_flash_partitions, chip_sel_3430, 0); diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c index 8dd0ec8..ddcadfa 100644 --- a/arch/arm/mach-omap2/board-cm-t35.c +++ b/arch/arm/mach-omap2/board-cm-t35.c @@ -725,7 +725,7 @@ static void __init cm_t3x_common_init(void) cm_t35_init_display(); omap_twl4030_audio_init(cm-t3x, NULL); - usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb); + usb_bind_phy(musb-hdrc.0, 0, twl4030_usb); usb_musb_init(NULL); cm_t35_init_usbh(); cm_t35_init_camera(); diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c index cdc4fb9..bb589f1 100644 --- a/arch/arm/mach-omap2/board-devkit8000.c +++ b/arch/arm/mach-omap2/board-devkit8000.c @@ -628,7 +628,7 @@ static void __init devkit8000_init(void) omap_ads7846_init(2, OMAP3_DEVKIT_TS_GPIO, 0, NULL); - usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb); + usb_bind_phy(musb-hdrc.0, 0, twl4030_usb); usb_musb_init(NULL); usbhs_init(usbhs_bdata); board_nand_init(devkit8000_nand_partitions, diff --git a/arch/arm/mach-omap2/board-ldp.c b/arch/arm/mach-omap2/board-ldp.c index 4ec8d82..ec9b349 100644 --- a/arch/arm/mach-omap2/board-ldp.c +++ b/arch/arm/mach-omap2/board-ldp.c @@ -402,7 +402,7 @@ static void __init omap_ldp_init(void) omap_ads7846_init(1, 54, 310, NULL); omap_serial_init(); omap_sdrc_init(NULL, NULL); - usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb); + usb_bind_phy(musb-hdrc.0, 0, twl4030_usb); usb_musb_init(NULL); board_nand_init(ldp_nand_partitions, ARRAY_SIZE(ldp_nand_partitions), 0, 0, nand_default_timings); diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c index d6ed819..0cba5eb 100644 --- a/arch/arm/mach-omap2/board-omap3beagle.c +++ b/arch/arm/mach-omap2/board-omap3beagle.c @@ -561,7 +561,7 @@ static void __init omap3_beagle_init(void) omap_sdrc_init(mt46h32m32lf6_sdrc_params, mt46h32m32lf6_sdrc_params); - usb_bind_phy(musb-hdrc.0.auto, 0, twl4030_usb); + usb_bind_phy(musb-hdrc.0, 0, twl4030_usb); usb_musb_init(NULL); usbhs_init(usbhs_bdata); diff --git a/arch/arm/mach-omap2/board-omap3logic.c b/arch/arm/mach-omap2/board-omap3logic.c index bab51e6..d9a6c38 100644 --- a/arch/arm/mach-omap2/board-omap3logic.c +++ b/arch/arm/mach-omap2/board-omap3logic.c @@ -216,7 +216,7 @@ static void __init omap3logic_init(void
[PATCH v2 1/2] usb: musb: omap: remove using PLATFORM_DEVID_AUTO in omap2430.c
After the platform devices are created using PLATFORM_DEVID_AUTO, the
device names given in usb_bind_phy (in board file) does not match with
the actual device name causing the USB PHY library not to return the
PHY reference when the MUSB controller request for the PHY in the non-dt boot
case.
So removed creating platform devices using PLATFORM_DEVID_AUTO in omap2430.c.
This is also needed for the Generic PHY Framework.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/usb/musb/musb_core.c | 31 ++-
drivers/usb/musb/musb_core.h |2 ++
drivers/usb/musb/omap2430.c | 19 +--
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index 0a43329..aaf734c 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -94,6 +94,7 @@
#include linux/sched.h
#include linux/slab.h
#include linux/init.h
+#include linux/idr.h
#include linux/list.h
#include linux/kobject.h
#include linux/prefetch.h
@@ -120,7 +121,7 @@ MODULE_DESCRIPTION(DRIVER_INFO);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_LICENSE(GPL);
MODULE_ALIAS(platform: MUSB_DRIVER_NAME);
-
+static DEFINE_IDA(musb_ida);
/*-*/
@@ -131,6 +132,34 @@ static inline struct musb *dev_to_musb(struct device *dev)
/*-*/
+int musb_get_id(struct device *dev, gfp_t gfp_mask)
+{
+ int ret;
+ int id;
+
+ ret = ida_pre_get(musb_ida, gfp_mask);
+ if (!ret) {
+ dev_err(dev, failed to reserve resource for id\n);
+ return -ENOMEM;
+ }
+
+ ret = ida_get_new(musb_ida, id);
+ if (ret 0) {
+ dev_err(dev, failed to allocate a new id\n);
+ return ret;
+ }
+
+ return id;
+}
+EXPORT_SYMBOL_GPL(musb_get_id);
+
+void musb_put_id(struct device *dev, int id)
+{
+ dev_dbg(dev, removing id %d\n, id);
+ ida_remove(musb_ida, id);
+}
+EXPORT_SYMBOL_GPL(musb_put_id);
+
#ifndef CONFIG_BLACKFIN
static int musb_ulpi_read(struct usb_phy *phy, u32 offset)
{
diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h
index 29f7cd7..63614283 100644
--- a/drivers/usb/musb/musb_core.h
+++ b/drivers/usb/musb/musb_core.h
@@ -506,6 +506,8 @@ extern const char musb_driver_name[];
extern void musb_stop(struct musb *musb);
extern void musb_start(struct musb *musb);
+int musb_get_id(struct device *dev, gfp_t gfp_mask);
+void musb_put_id(struct device *dev, int id);
extern void musb_write_fifo(struct musb_hw_ep *ep, u16 len, const u8 *src);
extern void musb_read_fifo(struct musb_hw_ep *ep, u16 len, u8 *dst);
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index 2a408cd..14a612c 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -45,6 +45,7 @@
struct omap2430_glue {
struct device *dev;
+ int id;
struct platform_device *musb;
enum omap_musb_vbus_id_status status;
struct work_struct omap_musb_mailbox_work;
@@ -508,6 +509,7 @@ static int omap2430_probe(struct platform_device *pdev)
struct device_node *np = pdev-dev.of_node;
struct musb_hdrc_config *config;
int ret = -ENOMEM;
+ int musbid;
glue = devm_kzalloc(pdev-dev, sizeof(*glue), GFP_KERNEL);
if (!glue) {
@@ -515,10 +517,18 @@ static int omap2430_probe(struct platform_device *pdev)
goto err0;
}
- musb = platform_device_alloc(musb-hdrc, PLATFORM_DEVID_AUTO);
+ /* get the musb id */
+ musbid = musb_get_id(pdev-dev, GFP_KERNEL);
+ if (musbid 0) {
+ dev_err(pdev-dev, failed to allocate musb id\n);
+ ret = -ENOMEM;
+ goto err0;
+ }
+
+ musb = platform_device_alloc(musb-hdrc, musbid);
if (!musb) {
dev_err(pdev-dev, failed to allocate musb device\n);
- goto err0;
+ goto err1;
}
musb-dev.parent= pdev-dev;
@@ -528,6 +538,7 @@ static int omap2430_probe(struct platform_device *pdev)
glue-dev = pdev-dev;
glue-musb = musb;
glue-status= OMAP_MUSB_UNKNOWN;
+ glue-id= musbid;
glue-control_otghs = ERR_PTR(-ENODEV);
if (np) {
@@ -633,6 +644,9 @@ static int omap2430_probe(struct platform_device *pdev)
err2:
platform_device_put(musb);
+err1:
+ musb_put_id(pdev-dev, musbid);
+
err0:
return ret;
}
@@ -643,6 +657,7 @@ static int omap2430_remove(struct platform_device *pdev)
cancel_work_sync(glue-omap_musb_mailbox_work
[PATCH 3/3] phy: kconfig: add depends on USB_PHY to OMAP_USB2 and TWL4030_USB
Fixes warning: (OMAP_USB2 TWL4030_USB) selects USB_PHY which has unmet direct dependencies (USB_SUPPORT) that shows up while disabling USB_SUPPORT from menuconfig. Reported-by: Russell King li...@arm.linux.org.uk Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Acked-by: Felipe Balbi ba...@ti.com --- drivers/phy/Kconfig |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index a344f3d..330ef2d 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -24,8 +24,8 @@ config PHY_EXYNOS_MIPI_VIDEO config OMAP_USB2 tristate OMAP USB2 PHY Driver depends on ARCH_OMAP2PLUS + depends on USB_PHY select GENERIC_PHY - select USB_PHY select OMAP_CONTROL_USB help Enable this to support the transceiver that is part of SOC. This @@ -36,8 +36,8 @@ config OMAP_USB2 config TWL4030_USB tristate TWL4030 USB Transceiver Driver depends on TWL4030_CORE REGULATOR_TWL4030 USB_MUSB_OMAP2PLUS + depends on USB_PHY select GENERIC_PHY - select USB_PHY help Enable this to support the USB OTG transceiver on TWL4030 family chips (including the TWL5030 and TPS659x0 devices). -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 1/3] drivers: phy: Fix memory leak
From: Sachin Kamat sachin.ka...@linaro.org
'phy' was not being freed upon error in one of the cases.
Adjust the 'goto's to fix this.
Signed-off-by: Sachin Kamat sachin.ka...@linaro.org
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-core.c | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 03cf8fb..712b358 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -453,7 +453,7 @@ struct phy *phy_create(struct device *dev, const struct
phy_ops *ops,
if (id 0) {
dev_err(dev, unable to get id\n);
ret = id;
- goto err0;
+ goto err1;
}
device_initialize(phy-dev);
@@ -468,11 +468,11 @@ struct phy *phy_create(struct device *dev, const struct
phy_ops *ops,
ret = dev_set_name(phy-dev, phy-%s.%d, dev_name(dev), id);
if (ret)
- goto err1;
+ goto err2;
ret = device_add(phy-dev);
if (ret)
- goto err1;
+ goto err2;
if (pm_runtime_enabled(dev)) {
pm_runtime_enable(phy-dev);
@@ -481,11 +481,11 @@ struct phy *phy_create(struct device *dev, const struct
phy_ops *ops,
return phy;
-err1:
+err2:
ida_remove(phy_ida, phy-id);
put_device(phy-dev);
+err1:
kfree(phy);
-
err0:
return ERR_PTR(ret);
}
--
1.7.10.4
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[PATCH 2/3] drivers: phy: tweaks to phy_create()
From: Dan Carpenter dan.carpen...@oracle.com
If this was called with a NULL dev then it lead to a NULL dereference
when we called dev_WARN(). I have changed it to WARN_ON() so that we
get a stack dump and can fix the caller.
The rest of this patch is just cleanup like returning directly instead
of having do-nothing gotos. Using descriptive labels instead of
GW-BASIC style err0 and err1. I also flipped the order of
put_device() and ida_remove() so they are a mirror reflection of the
order they were allocated.
Signed-off-by: Dan Carpenter dan.carpen...@oracle.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-core.c | 26 ++
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 712b358..58e0e97 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -437,23 +437,18 @@ struct phy *phy_create(struct device *dev, const struct
phy_ops *ops,
int id;
struct phy *phy;
- if (!dev) {
- dev_WARN(dev, no device provided for PHY\n);
- ret = -EINVAL;
- goto err0;
- }
+ if (WARN_ON(!dev))
+ return ERR_PTR(-EINVAL);
phy = kzalloc(sizeof(*phy), GFP_KERNEL);
- if (!phy) {
- ret = -ENOMEM;
- goto err0;
- }
+ if (!phy)
+ return ERR_PTR(-ENOMEM);
id = ida_simple_get(phy_ida, 0, 0, GFP_KERNEL);
if (id 0) {
dev_err(dev, unable to get id\n);
ret = id;
- goto err1;
+ goto free_phy;
}
device_initialize(phy-dev);
@@ -468,11 +463,11 @@ struct phy *phy_create(struct device *dev, const struct
phy_ops *ops,
ret = dev_set_name(phy-dev, phy-%s.%d, dev_name(dev), id);
if (ret)
- goto err2;
+ goto put_dev;
ret = device_add(phy-dev);
if (ret)
- goto err2;
+ goto put_dev;
if (pm_runtime_enabled(dev)) {
pm_runtime_enable(phy-dev);
@@ -481,12 +476,11 @@ struct phy *phy_create(struct device *dev, const struct
phy_ops *ops,
return phy;
-err2:
- ida_remove(phy_ida, phy-id);
+put_dev:
put_device(phy-dev);
-err1:
+ ida_remove(phy_ida, phy-id);
+free_phy:
kfree(phy);
-err0:
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(phy_create);
--
1.7.10.4
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[PATCH 0/3] PHY: Fixes for 3.13-rc
Hi Greg, We have three patches to be merged in PHY subsystem for this rc cycle and all of them are critical. One fixes a memory leak, the other solves a NULL dereference while calling dev_WARN and the last one fixes a randconfig error. Let me know if I have to change anything. I've also queued these fixes in https://git.kernel.org/cgit/linux/kernel/git/kishon/linux-phy.git/ fixes (contains patches to be merged in other trees too). Dan Carpenter (1): drivers: phy: tweaks to phy_create() Kishon Vijay Abraham I (1): phy: kconfig: add depends on USB_PHY to OMAP_USB2 and TWL4030_USB Sachin Kamat (1): drivers: phy: Fix memory leak drivers/phy/Kconfig|4 ++-- drivers/phy/phy-core.c | 26 ++ 2 files changed, 12 insertions(+), 18 deletions(-) -- 1.7.10.4 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH][next] phy: core: make NULL a valid phy reference if !CONFIG_GENERIC_PHY
Hi Santosh,
On Thursday 13 March 2014 07:07 PM, Santosh Shilimkar wrote:
On Thursday 13 March 2014 07:11 PM, Strashko, Grygorii wrote:
This fixes a regression on Keystone 2 platforms caused by patch
57303488cd37da58263e842de134dc65f7c626d5
usb: dwc3: adapt dwc3 core to use Generic PHY Framework which adds
optional support of generic phy in DWC3 core.
On Keystone 2 platforms the USB is not working now because
CONFIG_GENERIC_PHY isn't set and, as result, Generic PHY APIs stubs
return -ENOSYS always. The log shows:
dwc3 269.dwc3: failed to initialize core
dwc3: probe of 269.dwc3 failed with error -38
Hence, fix it by making NULL a valid phy reference in Generic PHY
APIs stubs in the same way as it was done by the patch
04c2facad8fee66c981a51852806d8923336f362 drivers: phy: Make NULL
a valid phy reference.
CC: Kishon Vijay Abraham I kis...@ti.com
CC: Felipe Balbi ba...@ti.com
CC: Santosh Shilimkar santosh.shilim...@ti.com
Signed-off-by: Grygorii Strashko grygorii.stras...@ti.com
---
This fixes the regression seen in Linux next and patch seems
reasonable to me.
Acked-by: Santosh Shilimkar santosh.shilim...@ti.com
Felipe, Kishon,
Can you guys pick this fix if you are ok by it. Thanks
I've already given a PULL request to Greg for 3.15. Is it ok to take
this in -rc cycle?
-Kishon
include/linux/phy/phy.h |8
1 file changed, 8 insertions(+)
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index e2f5ca9..5a9b193 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -204,21 +204,29 @@ static inline void phy_pm_runtime_forbid(struct phy *phy)
static inline int phy_init(struct phy *phy)
{
+ if (!phy)
+ return 0;
return -ENOSYS;
}
static inline int phy_exit(struct phy *phy)
{
+ if (!phy)
+ return 0;
return -ENOSYS;
}
static inline int phy_power_on(struct phy *phy)
{
+ if (!phy)
+ return 0;
return -ENOSYS;
}
static inline int phy_power_off(struct phy *phy)
{
+ if (!phy)
+ return 0;
return -ENOSYS;
}
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Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes
Hi Roger,
On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 110 ++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 10 ---
2 files changed, 110 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..1e73900 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -811,6 +811,116 @@
clocks = sata_ref_clk;
ti,hwmods = sata;
};
+
+ omap_control_usb2phy1: control-phy@4a002300 {
+ compatible = ti,control-phy-usb2;
+ reg = 0x4a002300 0x4;
+ reg-names = power;
+ };
+
+ omap_control_usb3phy1: control-phy@4a002370 {
+ compatible = ti,control-phy-pipe3;
+ reg = 0x4a002370 0x4;
+ reg-names = power;
+ };
+
+ omap_control_usb2phy2: control-phy@0x4a002e74 {
+ compatible = ti,control-phy-usb2-dra7;
+ reg = 0x4a002e74 0x4;
+ reg-names = power;
+ };
+
+ /* OCP2SCP1 */
+ ocp2scp@4a08 {
+ compatible = ti,omap-ocp2scp;
+ #address-cells = 1;
+ #size-cells = 1;
+ ranges;
+ reg = 0x4a08 0x20;
+ ti,hwmods = ocp2scp1;
+
+ usb2_phy1: phy@4a084000 {
+ compatible = ti,omap-usb2;
+ reg = 0x4a084000 0x400;
+ ctrl-module = omap_control_usb2phy1;
+ clocks = usb_phy1_always_on_clk32k,
+usb_otg_ss1_refclk960m;
+ clock-names = wkupclk,
+ refclk;
+ #phy-cells = 0;
+ };
+
+ usb2_phy2: phy@4a085000 {
+ compatible = ti,omap-usb2;
+ reg = 0x4a085000 0x400;
+ ctrl-module = omap_control_usb2phy2;
+ clocks = usb_phy2_always_on_clk32k,
+usb_otg_ss2_refclk960m;
+ clock-names = wkupclk,
+ refclk;
+ #phy-cells = 0;
+ };
+
+ usb3_phy1: phy@4a084400 {
+ compatible = ti,omap-usb3;
+ reg = 0x4a084400 0x80,
+ 0x4a084800 0x64,
+ 0x4a084c00 0x40;
+ reg-names = phy_rx, phy_tx, pll_ctrl;
+ ctrl-module = omap_control_usb3phy1;
+ clocks = usb_phy3_always_on_clk32k,
+sys_clkin1,
+usb_otg_ss1_refclk960m,
+dpll_core_h13x2_ck;
+ clock-names = wkupclk,
+ sysclk,
+ refclk,
+ optclk;
Do we use this 'optclk' in driver?
-Kishon
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Re: [PATCH 7/8] ARM: dts: dra7: Add USB related nodes
On Friday 14 March 2014 05:41 PM, Roger Quadros wrote:
On 03/14/2014 12:38 PM, Kishon Vijay Abraham I wrote:
Hi Roger,
On Friday 07 March 2014 06:39 PM, Roger Quadros wrote:
Add nodes for the Super Speed USB controllers, omap-control-usb,
USB2 PHY and USB3 PHY devices.
Remove ocp2scp1 address space from hwmod data as it is
now provided via device tree.
Signed-off-by: Roger Quadros rog...@ti.com
---
arch/arm/boot/dts/dra7.dtsi | 110
++
arch/arm/mach-omap2/omap_hwmod_7xx_data.c | 10 ---
2 files changed, 110 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 597979b..1e73900 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -811,6 +811,116 @@
clocks = sata_ref_clk;
ti,hwmods = sata;
};
+
+omap_control_usb2phy1: control-phy@4a002300 {
+compatible = ti,control-phy-usb2;
+reg = 0x4a002300 0x4;
+reg-names = power;
+};
+
+omap_control_usb3phy1: control-phy@4a002370 {
+compatible = ti,control-phy-pipe3;
+reg = 0x4a002370 0x4;
+reg-names = power;
+};
+
+omap_control_usb2phy2: control-phy@0x4a002e74 {
+compatible = ti,control-phy-usb2-dra7;
+reg = 0x4a002e74 0x4;
+reg-names = power;
+};
+
+/* OCP2SCP1 */
+ocp2scp@4a08 {
+compatible = ti,omap-ocp2scp;
+#address-cells = 1;
+#size-cells = 1;
+ranges;
+reg = 0x4a08 0x20;
+ti,hwmods = ocp2scp1;
+
+usb2_phy1: phy@4a084000 {
+compatible = ti,omap-usb2;
+reg = 0x4a084000 0x400;
+ctrl-module = omap_control_usb2phy1;
+clocks = usb_phy1_always_on_clk32k,
+ usb_otg_ss1_refclk960m;
+clock-names =wkupclk,
+refclk;
+#phy-cells = 0;
+};
+
+usb2_phy2: phy@4a085000 {
+compatible = ti,omap-usb2;
+reg = 0x4a085000 0x400;
+ctrl-module = omap_control_usb2phy2;
+clocks = usb_phy2_always_on_clk32k,
+ usb_otg_ss2_refclk960m;
+clock-names =wkupclk,
+refclk;
+#phy-cells = 0;
+};
+
+usb3_phy1: phy@4a084400 {
+compatible = ti,omap-usb3;
+reg = 0x4a084400 0x80,
+ 0x4a084800 0x64,
+ 0x4a084c00 0x40;
+reg-names = phy_rx, phy_tx, pll_ctrl;
+ctrl-module = omap_control_usb3phy1;
+clocks = usb_phy3_always_on_clk32k,
+ sys_clkin1,
+ usb_otg_ss1_refclk960m,
+ dpll_core_h13x2_ck;
+clock-names =wkupclk,
+sysclk,
+refclk,
+optclk;
Do we use this 'optclk' in driver?
No we don't. Still the device seems to work without it.
This is supposed to be USB_LFPS_TX_GFCLK or USB3PHY_REF_CLK.
I think it should be enabled. Did you check the status of this clock in
CM_L3INIT_CLKSTCTRL? Moreover USB_LFPS_TX_GFCLK is an interface clock,
so IIUC setting the module mode will enable it.
Btw how did you tell dpll_core_h13x2_ck enables USB_LFPS_TX_GFCLK?
Cheers
Kishon
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Re: [PATCH 1/2] usb: dwc3: core: continue probing if usb phy library returns -ENODEV/-ENXIO
Hi Roger, On Friday 21 February 2014 05:59 PM, Roger Quadros wrote: On 02/21/2014 02:25 PM, Kishon Vijay Abraham I wrote: Hi Roger, On Wednesday 19 February 2014 06:07 PM, Roger Quadros wrote: Hi, On 02/12/2014 11:46 AM, Kishon Vijay Abraham I wrote: On Wednesday 29 January 2014 08:17 PM, Heikki Krogerus wrote: Hi, On Tue, Jan 28, 2014 at 10:30:36AM -0600, Felipe Balbi wrote: On Tue, Jan 28, 2014 at 05:32:30PM +0200, Heikki Krogerus wrote: On Mon, Jan 27, 2014 at 10:05:20AM -0600, Felipe Balbi wrote: For the controller drivers the PHYs are just a resource like any other. The controller drivers can't have any responsibility of them. They should not care if PHY drivers are available for them or not, or even if the PHY framework is available or not. huh? If memory isn't available you don't continue probing, right ? If your IORESOURCE_MEM is missing, you also don't continue probing, if your IRQ line is missing, you bail too. Those are also nothing but resources to the driver, what you're asking here is to treat PHY as a _different_ resource; which might be fine, but we need to make sure we don't continue probing when a PHY is missing in a platform that certainly needs a PHY. Yes, true. In my head I was comparing the PHY only to resources like gpios, clocks, dma channels, etc. that are often optional to the drivers. But I really want to see the argument against using no-op. As far as I could see, everybody needs a PHY driver one way or another, some platforms just haven't sent any PHY driver upstream and have their own hacked up solution to avoid using the PHY layer. Not true in our case. Platforms using Intel's SoCs and chip sets may or may not have controllable USB PHY. Quite often they don't. The Baytrails have usually ULPI PHY for USB2, but that does not mean they provide any vendor specific functions or any need for a driver in any case. that's different from what I heard. I don't know where you got that impression, but it's not true. The Baytrail SoCs for example don't have internal USB PHYs, which means the manufacturers using it can select what they want. So we have boards where PHY driver(s) is needed and boards where it isn't. alright, that explains it ;-) So you have external USB2 and USB3 PHYs ? You have an external PIPE3 interface ? That's quite an achievement, kudos to your HW designers. Getting timing closure on PIPE3 is a difficult task. No, only the USB2 PHY is external. I'm giving you wrong information, I'm sorry about that. Need to concentrate on what I'm writing. snip This is really good to get. We have some projects where we are dealing with more embedded environments, like IVI, where the kernel should be stripped of everything useless. Since the PHYs are autonomous, we should be able to disable the PHY libraries/frameworks. hmmm, in that case it's a lot easier to treat. We can use ERR_PTR(-ENXIO) as an indication that the framework is disabled, or something like that. The difficult is really reliably supporting e.g. OMAP5 (which won't work without a PHY) and your BayTrail with autonomous PHYs. What can we use as an indication ? OMAP has it's own glue driver, so shouldn't it depend on the PHY layer? right, but the PHY is connected to the dwc3 core and not to the glue. I mean, I need to know that a particular platform depends on a PHY driver before I decide to return -EPROBE_DEFER or just assume the PHY isn't needed ;-) I don't think dwc3 (core) should care about that. The PHY layer needs to tell us that. If the PHY driver that the platform depends is not available yet, the PHY layer returns -EPROBE_DEFER and dwc3 ends up returning -EPROBE_DEFER. I don't think the PHY layer can 'reliably' tell if PHY driver is available or not. Consider when the phy_provider_register fails, there is no way to know if PHY driver is available or not. There are a few cases where PHY layer returns -EPROBE_DEFER but none of them can tell for sure that PHY driver is either available and failed or not available at all. It would be best for us to leave that to the platforms if we want to be sure if the platform needs a PHY or not. Just to summarize this thread on what we need Thanks for summarizing. 1) dwc3 core shouldn't worry about platform specific stuff i.e. PHY needed or not. It should be as generic as possible. 2) dwc3 core should continue probe even if PHY layer is not enabled, as not all platforms need it. 3) dwc3 core should continue probe if PHY device is not available. (-ENODEV?) 4) dwc3 core should error out on any error condition if PHY device is available and caused some error, e.g. init error. 5) dwc3 core should return EPROBE_DEFER if PHY device is available but device driver is not yet loaded. 6) platform glue should do the necessary sanity checks for availability of all resources like PHY device, PHY layer, etc, before populating the dwc3 device. e.g. in OMAP5
Re: [PATCH 1/2] usb: dwc3: core: continue probing if usb phy library returns -ENODEV/-ENXIO
On Friday 21 February 2014 05:59 PM, Roger Quadros wrote: On 02/21/2014 02:25 PM, Kishon Vijay Abraham I wrote: Hi Roger, On Wednesday 19 February 2014 06:07 PM, Roger Quadros wrote: Hi, On 02/12/2014 11:46 AM, Kishon Vijay Abraham I wrote: On Wednesday 29 January 2014 08:17 PM, Heikki Krogerus wrote: Hi, On Tue, Jan 28, 2014 at 10:30:36AM -0600, Felipe Balbi wrote: On Tue, Jan 28, 2014 at 05:32:30PM +0200, Heikki Krogerus wrote: On Mon, Jan 27, 2014 at 10:05:20AM -0600, Felipe Balbi wrote: For the controller drivers the PHYs are just a resource like any other. The controller drivers can't have any responsibility of them. They should not care if PHY drivers are available for them or not, or even if the PHY framework is available or not. huh? If memory isn't available you don't continue probing, right ? If your IORESOURCE_MEM is missing, you also don't continue probing, if your IRQ line is missing, you bail too. Those are also nothing but resources to the driver, what you're asking here is to treat PHY as a _different_ resource; which might be fine, but we need to make sure we don't continue probing when a PHY is missing in a platform that certainly needs a PHY. Yes, true. In my head I was comparing the PHY only to resources like gpios, clocks, dma channels, etc. that are often optional to the drivers. But I really want to see the argument against using no-op. As far as I could see, everybody needs a PHY driver one way or another, some platforms just haven't sent any PHY driver upstream and have their own hacked up solution to avoid using the PHY layer. Not true in our case. Platforms using Intel's SoCs and chip sets may or may not have controllable USB PHY. Quite often they don't. The Baytrails have usually ULPI PHY for USB2, but that does not mean they provide any vendor specific functions or any need for a driver in any case. that's different from what I heard. I don't know where you got that impression, but it's not true. The Baytrail SoCs for example don't have internal USB PHYs, which means the manufacturers using it can select what they want. So we have boards where PHY driver(s) is needed and boards where it isn't. alright, that explains it ;-) So you have external USB2 and USB3 PHYs ? You have an external PIPE3 interface ? That's quite an achievement, kudos to your HW designers. Getting timing closure on PIPE3 is a difficult task. No, only the USB2 PHY is external. I'm giving you wrong information, I'm sorry about that. Need to concentrate on what I'm writing. snip This is really good to get. We have some projects where we are dealing with more embedded environments, like IVI, where the kernel should be stripped of everything useless. Since the PHYs are autonomous, we should be able to disable the PHY libraries/frameworks. hmmm, in that case it's a lot easier to treat. We can use ERR_PTR(-ENXIO) as an indication that the framework is disabled, or something like that. The difficult is really reliably supporting e.g. OMAP5 (which won't work without a PHY) and your BayTrail with autonomous PHYs. What can we use as an indication ? OMAP has it's own glue driver, so shouldn't it depend on the PHY layer? right, but the PHY is connected to the dwc3 core and not to the glue. I mean, I need to know that a particular platform depends on a PHY driver before I decide to return -EPROBE_DEFER or just assume the PHY isn't needed ;-) I don't think dwc3 (core) should care about that. The PHY layer needs to tell us that. If the PHY driver that the platform depends is not available yet, the PHY layer returns -EPROBE_DEFER and dwc3 ends up returning -EPROBE_DEFER. I don't think the PHY layer can 'reliably' tell if PHY driver is available or not. Consider when the phy_provider_register fails, there is no way to know if PHY driver is available or not. There are a few cases where PHY layer returns -EPROBE_DEFER but none of them can tell for sure that PHY driver is either available and failed or not available at all. It would be best for us to leave that to the platforms if we want to be sure if the platform needs a PHY or not. Just to summarize this thread on what we need Thanks for summarizing. 1) dwc3 core shouldn't worry about platform specific stuff i.e. PHY needed or not. It should be as generic as possible. I think this contradicts with Felipe's requirement of dwc3 core bailing out if a particular platform needs a PHY but it's not able to get it. 2) dwc3 core should continue probe even if PHY layer is not enabled, as not all platforms need it. 3) dwc3 core should continue probe if PHY device is not available. (-ENODEV?) 4) dwc3 core should error out on any error condition if PHY device is available and caused some error, e.g. init error. 5) dwc3 core should return EPROBE_DEFER if PHY device is available but device driver is not yet loaded. 6) platform glue should do the necessary
Re: [PATCH V8 1/2] PHY: Exynos: Add Exynos5250 SATA PHY driver
Hi, On Monday 24 February 2014 07:02 PM, Yuvaraj Kumar C D wrote: This patch adds the SATA PHY driver for Exynos5250.Exynos5250 SATA PHY comprises of CMU and TRSV blocks which are of I2C register Map. So this patch also adds a i2c client driver, which is used configure We no longer have i2c client driver here. the CMU and TRSV block of exynos5250 SATA PHY. This patch incorporates the generic PHY framework to deal with SATA PHY. It should be rephrased to have *uses* generic PHY framework. However I feel we can do away with this line. This patch depends on the below patch for the sata functionality [1].ata: ahci_platform: Manage SATA PHY by Roger Quadros rog...@ti.com hasn't this patch merged yet? Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 1/2] usb: dwc3: core: continue probing if usb phy library returns -ENODEV/-ENXIO
Hi, On Monday 24 February 2014 04:35 PM, Roger Quadros wrote: On 02/24/2014 11:51 AM, Kishon Vijay Abraham I wrote: Hi Roger, On Friday 21 February 2014 05:59 PM, Roger Quadros wrote: On 02/21/2014 02:25 PM, Kishon Vijay Abraham I wrote: Hi Roger, On Wednesday 19 February 2014 06:07 PM, Roger Quadros wrote: Hi, On 02/12/2014 11:46 AM, Kishon Vijay Abraham I wrote: On Wednesday 29 January 2014 08:17 PM, Heikki Krogerus wrote: Hi, On Tue, Jan 28, 2014 at 10:30:36AM -0600, Felipe Balbi wrote: On Tue, Jan 28, 2014 at 05:32:30PM +0200, Heikki Krogerus wrote: On Mon, Jan 27, 2014 at 10:05:20AM -0600, Felipe Balbi wrote: For the controller drivers the PHYs are just a resource like any other. The controller drivers can't have any responsibility of them. They should not care if PHY drivers are available for them or not, or even if the PHY framework is available or not. huh? If memory isn't available you don't continue probing, right ? If your IORESOURCE_MEM is missing, you also don't continue probing, if your IRQ line is missing, you bail too. Those are also nothing but resources to the driver, what you're asking here is to treat PHY as a _different_ resource; which might be fine, but we need to make sure we don't continue probing when a PHY is missing in a platform that certainly needs a PHY. Yes, true. In my head I was comparing the PHY only to resources like gpios, clocks, dma channels, etc. that are often optional to the drivers. But I really want to see the argument against using no-op. As far as I could see, everybody needs a PHY driver one way or another, some platforms just haven't sent any PHY driver upstream and have their own hacked up solution to avoid using the PHY layer. Not true in our case. Platforms using Intel's SoCs and chip sets may or may not have controllable USB PHY. Quite often they don't. The Baytrails have usually ULPI PHY for USB2, but that does not mean they provide any vendor specific functions or any need for a driver in any case. that's different from what I heard. I don't know where you got that impression, but it's not true. The Baytrail SoCs for example don't have internal USB PHYs, which means the manufacturers using it can select what they want. So we have boards where PHY driver(s) is needed and boards where it isn't. alright, that explains it ;-) So you have external USB2 and USB3 PHYs ? You have an external PIPE3 interface ? That's quite an achievement, kudos to your HW designers. Getting timing closure on PIPE3 is a difficult task. No, only the USB2 PHY is external. I'm giving you wrong information, I'm sorry about that. Need to concentrate on what I'm writing. snip This is really good to get. We have some projects where we are dealing with more embedded environments, like IVI, where the kernel should be stripped of everything useless. Since the PHYs are autonomous, we should be able to disable the PHY libraries/frameworks. hmmm, in that case it's a lot easier to treat. We can use ERR_PTR(-ENXIO) as an indication that the framework is disabled, or something like that. The difficult is really reliably supporting e.g. OMAP5 (which won't work without a PHY) and your BayTrail with autonomous PHYs. What can we use as an indication ? OMAP has it's own glue driver, so shouldn't it depend on the PHY layer? right, but the PHY is connected to the dwc3 core and not to the glue. I mean, I need to know that a particular platform depends on a PHY driver before I decide to return -EPROBE_DEFER or just assume the PHY isn't needed ;-) I don't think dwc3 (core) should care about that. The PHY layer needs to tell us that. If the PHY driver that the platform depends is not available yet, the PHY layer returns -EPROBE_DEFER and dwc3 ends up returning -EPROBE_DEFER. I don't think the PHY layer can 'reliably' tell if PHY driver is available or not. Consider when the phy_provider_register fails, there is no way to know if PHY driver is available or not. There are a few cases where PHY layer returns -EPROBE_DEFER but none of them can tell for sure that PHY driver is either available and failed or not available at all. It would be best for us to leave that to the platforms if we want to be sure if the platform needs a PHY or not. Just to summarize this thread on what we need Thanks for summarizing. 1) dwc3 core shouldn't worry about platform specific stuff i.e. PHY needed or not. It should be as generic as possible. 2) dwc3 core should continue probe even if PHY layer is not enabled, as not all platforms need it. 3) dwc3 core should continue probe if PHY device is not available. (-ENODEV?) 4) dwc3 core should error out on any error condition if PHY device is available and caused some error, e.g. init error. 5) dwc3 core should return EPROBE_DEFER if PHY device is available but device driver is not yet loaded. 6) platform glue should do the necessary
Re: [PATCH RESEND v10 1/4] PHY: Add function set_speed to generic PHY framework
Hi,
On Tuesday 25 February 2014 11:44 AM, Loc Ho wrote:
This patch adds function set_speed to the generic PHY framework operation
structure. This function can be called to instruct the PHY underlying layer
at specified lane to configure for specified speed in hertz.
Signed-off-by: Loc Ho l...@apm.com
---
drivers/phy/phy-core.c | 21 +
include/linux/phy/phy.h |8
2 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 645c867..44f2f63 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -257,6 +257,27 @@ int phy_power_off(struct phy *phy)
}
EXPORT_SYMBOL_GPL(phy_power_off);
missing function comment :-s
+int phy_set_speed(struct phy *phy, int lane, u64 speed)
+{
Thanks
Kishon
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Re: [PATCH RESEND v10 1/4] PHY: Add function set_speed to generic PHY framework
On Tuesday 25 February 2014 07:15 PM, Tejun Heo wrote: On Tue, Feb 25, 2014 at 05:35:37PM +0530, Kishon Vijay Abraham I wrote: Hi, On Tuesday 25 February 2014 11:44 AM, Loc Ho wrote: This patch adds function set_speed to the generic PHY framework operation structure. This function can be called to instruct the PHY underlying layer at specified lane to configure for specified speed in hertz. Signed-off-by: Loc Ho l...@apm.com --- drivers/phy/phy-core.c | 21 + include/linux/phy/phy.h |8 2 files changed, 29 insertions(+), 0 deletions(-) diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c index 645c867..44f2f63 100644 --- a/drivers/phy/phy-core.c +++ b/drivers/phy/phy-core.c @@ -257,6 +257,27 @@ int phy_power_off(struct phy *phy) } EXPORT_SYMBOL_GPL(phy_power_off); missing function comment :-s Can you please let me know when this series goes in? I'll pull in the phy tree into libata and then apply the ata patches on top. I'll send the final pull request for 3.15 merge window by next weekend to Greg kh. Before that I'd like to have my comments addressed in this patch series. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH RESEND v10 2/4] Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
On Tuesday 25 February 2014 11:44 AM, Loc Ho wrote:
missing commit log..
-Kishon
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
.../devicetree/bindings/phy/apm-xgene-phy.txt | 79
1 files changed, 79 insertions(+), 0 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
new file mode 100644
index 000..5f3a65a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
@@ -0,0 +1,79 @@
+* APM X-Gene 15Gbps Multi-purpose PHY nodes
+
+PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
+PHY (pair of lanes) has its own node.
+
+Required properties:
+- compatible : Shall be apm,xgene-phy.
+- reg: PHY memory resource is the SDS PHY access
resource.
+- #phy-cells : Shall be 1 as it expects one argument for setting
+ the mode of the PHY. Possible values are 0 (SATA),
+ 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
+
+Optional properties:
+- status : Shall be ok if enabled or disabled if disabled.
+ Default is ok.
+- clocks : Reference to the clock entry.
+- apm,tx-eye-tuning : Manual control to fine tune the capture of the serial
+ bit lines from the automatic calibrated position.
+ Two set of 3-tuple setting for each (up to 3)
+ supported link speed on the host. Range from 0 to
+ 127 in unit of one bit period. Default is 10.
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means
sample
+ data earlier than the nominal sampling point. 1 means
+ sample data later than the nominal sampling point.
+ Two set of 3-tuple setting for each (up to 3)
+ supported link speed on the host. Default is 0.
+- apm,tx-boost-gain : Frequency boost AC (LSB 3-bit) and DC (2-bit)
+ gain control. Two set of 3-tuple setting for each
+ (up to 3) supported link speed on the host. Range is
+ between 0 to 31 in unit of dB. Default is 3.
+- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
+ each (up to 3) supported link speed on the host.
+ Range is between 0 to 199500 in unit of uV.
+ Default is 199500 uV.
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
+ 3-tuple setting for each (up to 3) supported link
+ speed on the host. Range is 0 to 273000 in unit of
+ uV. Default is 0.
+- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of
+ 3-tuple setting for each (up to 3) supported link
+ speed on the host. Range is 0 to 127400 in unit uV.
+ Default is 0x0.
+- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is
+ between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for
each
+ supported link speed on the host.
+0 = 1-2Gbps
+1 = 2-4Gbps (1st tuple default)
+2 = 4-8Gbps
+3 = 8-15Gbps (2nd tuple default)
+4 = 2.5-4Gbps
+5 = 4-5Gbps
+6 = 5-6Gbps
+7 = 6-16Gbps (3rd tuple default)
+
+NOTE: PHY override parameters are board specific setting.
+
+Example:
+ phy1: phy@1f21a000 {
+ compatible = apm,xgene-phy;
+ reg = 0x0 0x1f21a000 0x0 0x100;
+ #phy-cells = 1;
+ status = disabled;
+ };
+
+ phy2: phy@1f22a000 {
+ compatible = apm,xgene-phy;
+ reg = 0x0 0x1f22a000 0x0 0x100;
+ #phy-cells = 1;
+ status = ok;
+ };
+
+ phy3: phy@1f23a000 {
+ compatible = apm,xgene-phy;
+ reg = 0x0 0x1f23a000 0x0 0x100;
+ #phy-cells = 1;
+ status = ok;
+ };
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Re: [PATCH RESEND v10 3/4] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
On Tuesday 25 February 2014 11:44 AM, Loc Ho wrote:
This patch adds support for APM X-Gene SoC 15Gbps Multi-purpose PHY.
This is the physical layer interface for the corresponding host
controller. Currently, only external clock and SATA mode
are supported.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/phy/Kconfig |7 +
drivers/phy/Makefile|2 +
drivers/phy/phy-xgene.c | 1826 +++
3 files changed, 1835 insertions(+), 0 deletions(-)
create mode 100644 drivers/phy/phy-xgene.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..229db49 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,11 @@ config BCM_KONA_USB2_PHY
help
Enable this to support the Broadcom Kona USB 2.0 PHY.
+config PHY_XGENE
+ tristate APM X-Gene 15Gbps PHY support
+ depends on ARM64 || COMPILE_TEST
+ select GENERIC_PHY
depends on HAS_IOMEM and CONFIG_OF..
+ help
+ This option enables support for APM X-Gene SoC multi-purpose PHY.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..dee70f4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,5 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) +=
phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+
diff --git a/drivers/phy/phy-xgene.c b/drivers/phy/phy-xgene.c
new file mode 100644
index 000..653868d
--- /dev/null
+++ b/drivers/phy/phy-xgene.c
@@ -0,0 +1,1826 @@
+/*
+ * AppliedMicro X-Gene Multi-purpose PHY driver
+ *
+ * Copyright (c) 2014, Applied Micro Circuits Corporation
+ * Author: Loc Ho l...@apm.com
+ * Tuan Phan tp...@apm.com
+ * Suman Tripathi stripa...@apm.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see http://www.gnu.org/licenses/.
+ *
+ * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
+ * The first PLL clock macro is used for internal reference clock. The second
+ * PLL clock macro is used to generate the clock for the PHY. This driver
+ * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
+ * operate according to the mode of operation. The first PLL CMU is only
+ * required if internal clock is enabled.
+ *
+ * Logical Layer Out Of HW module units:
+ *
+ * -
+ * | Internal ||--|
+ * | Ref PLL CMU || | --
+ * | MUX |-|PHY PLL CMU|| Serdes|
+ * | | | |-
+ * External Clock --| | -
+ * |--|
+ *
+ * The Ref PLL CMU CSR (Configureation System Registers) is accessed
%s/Configureation/Configuration
+ * indirectly from the SDS offset at 0x2000. It is only required for
+ * internal reference clock.
+ * The PHY PLL CMU CSR is accessed indirectly from the SDS offset at 0x.
+ * The Serdes CSR is accessed indirectly from the SDS offset at 0x0400.
+ *
+ * The Ref PLL CMU can be located within the same PHY IP or outside the PHY IP
+ * due to shared Ref PLL CMU. For PHY with Ref PLL CMU shared with another IP,
+ * it is located outside the PHY IP. This is the case for the PHY located
+ * at 0x1f23a000 (SATA Port 4/5). For such PHY, another resource is required
+ * to located the SDS/Ref PLL CMU module and its clock for that IP enabled.
+ *
+ * Currently, this driver only supports SATA mode with external clock.
+ */
+#include linux/module.h
+#include linux/platform_device.h
+#include linux/io.h
+#include linux/delay.h
+#include linux/phy/phy.h
+#include linux/clk.h
+
+/* Max 2 lanes per a PHY unit */
+#define MAX_LANE 2
+
+/* Register offset inside the PHY */
+#define SERDES_PLL_INDIRECT_OFFSET 0x
+#define SERDES_PLL_REF_INDIRECT_OFFSET 0x2000
+#define SERDES_INDIRECT_OFFSET 0x0400
+#define SERDES_LANE_STRIDE 0x0200
+
+/* Some default Serdes parameters */
+#define DEFAULT_SATA_TXBOOST_GAIN { 0x1e, 0x1e, 0x1e }
+#define DEFAULT_SATA_TXEYEDIRECTION{ 0x0, 0x0, 0x0 }
+#define
Re: [PATCH RESEND v10 3/4] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
On Thursday 27 February 2014 02:15 AM, Loc Ho wrote:
Hi,
+config PHY_XGENE
+ tristate APM X-Gene 15Gbps PHY support
+ depends on ARM64 || COMPILE_TEST
+ select GENERIC_PHY
depends on HAS_IOMEM and CONFIG_OF..
I will make it depends as HAS_IOMEM OF (ARM64 || COMPILE_TEST)
+/* PLL Clock Macro Unit (CMU) CSR accessing from SDS indirectly */
+#define CMU_REG0 0x0
+#define CMU_REG0_PLL_REF_SEL_MASK 0x2000
+#define CMU_REG0_PLL_REF_SEL_SET(dst, src)\
+ (((dst) ~0x2000) | (((u32)(src) 0xd) 0x2000))
using decimals for shift value would be better. No strong feeling though.
I will change to integer value.
+/*
+ * For chip earlier than A3 version, enable this flag.
+ * To enable, pass boot argument phy_xgene.preA3Chip=1
+ */
+static int preA3Chip;
+MODULE_PARM_DESC(preA3Chip, Enable pre-A3 chip support (1=enable 0=disable));
+module_param_named(preA3Chip, preA3Chip, int, 0444);
Do we need to have module param for this? I mean we can differentiate between
different chip versions in dt data only.
This is only required for the short term. Once all the pre-A3 system
are replaced, there isn't an need for this. For those who still has an
pre-A3 silicon system, this would provide an short term solution for
them. DT isn't quite correct here. This is an global thing. I guess I
can OR all node. If it is still better to put in the DT, let me know
and I will move it.
+
+static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg,
+ u32 indirect_data_reg, u32 addr, u32 data)
+{
+ u32 val;
+ u32 cmd;
+
+ cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
+ cmd = CFG_IND_ADDR_SET(cmd, addr);
This looks hacky. If 'CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK' should be
set then it should be part of the second argument. From the macro
'CFG_IND_ADDR_SET' the first argument should be more like the current value
present in the register right? I feel the macro (CFG_IND_ADDR_SET) is not used
in the way it is intended to.
The macro XXX_SET is intended to update an field within the register.
The update field is returned. The first assignment lines are setting
another field. Those two lines can be written as:
cmd = 0;
cmd |= CFG_IND_WR_CMD_MASK;== Set the CMD bit
cmd |= CFG_IND_CMD_DONE_MASK;== Set the DONE bit
cmd = CFG_IND_ADDR_SET(cmd, addr);=== Set the field ADDR
#define CFG_IND_ADDR_SET(dst, src) \
(((dst) ~0x0030) | (((u32)(src)4) 0x0030))
From this macro the first argument should be the present value in that
register. Here you reset the address bits and write the new address bits.
IMO the first argument should be the value in 'csr_base +
indirect_cmd_reg'. So it resets the address bits in 'csr_base +
indirect_cmd_reg' and write down the new address bits.
Thanks
Kishon
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Re: [PATCH RESEND v10 3/4] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
On Thursday 27 February 2014 11:55 AM, Loc Ho wrote:
Hi,
+
+static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg,
+ u32 indirect_data_reg, u32 addr, u32 data)
+{
+ u32 val;
+ u32 cmd;
+
+ cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
+ cmd = CFG_IND_ADDR_SET(cmd, addr);
This looks hacky. If 'CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK' should
be set then it should be part of the second argument. From the macro
'CFG_IND_ADDR_SET' the first argument should be more like the current value
present in the register right? I feel the macro (CFG_IND_ADDR_SET) is not
used in the way it is intended to.
The macro XXX_SET is intended to update an field within the register.
The update field is returned. The first assignment lines are setting
another field. Those two lines can be written as:
cmd = 0;
cmd |= CFG_IND_WR_CMD_MASK;== Set the CMD bit
cmd |= CFG_IND_CMD_DONE_MASK;== Set the DONE bit
cmd = CFG_IND_ADDR_SET(cmd, addr);=== Set the field ADDR
#define CFG_IND_ADDR_SET(dst, src) \
(((dst) ~0x0030) | (((u32)(src)4) 0x0030))
From this macro the first argument should be the present value in that
register. Here you reset the address bits and write the new address bits.
Yes.. This is correct. I am clearing x number of bit and then set new value.
IMO the first argument should be the value in 'csr_base + indirect_cmd_reg'.
So it resets the address bits in 'csr_base + indirect_cmd_reg' and write
down the new address bits.
Yes.. The above code does just that. In addition, I am also setting
the bits CFG_IND_WR_CMD_MASK and CFG_IND_CMD_DONE_MASK with the two
previous statement. Think of the code flow as follow:
val = readl(some void * address); /* read the register */
Where are you reading the register in your code (before CFG_IND_ADDR_SET)?
val = _SET(val, 0x1);/* set bit 0 - assuming set
bit 0 only */
If you want to set other bits (other than address) don't use
CFG_IND_ADDR_SET macro. That looks hacky to me.
val = _SET(val, 0x1); /* set bit 1 - assuming set
bit 1 only */
val = _SET(val, 0x5);/* set upper 16 bit of the
register to 0x5 - assuming set field of the upper 16 bits */
Instead writing the above, I am replacing the above 4 lines with these
two lines:
cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
cmd = CFG_IND_ADDR_SET(cmd, addr);
Is there clear?
-Loc
Cheers
Kishon
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Re: [PATCH RESEND v10 3/4] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
On Thursday 27 February 2014 12:04 PM, Kishon Vijay Abraham I wrote:
On Thursday 27 February 2014 11:55 AM, Loc Ho wrote:
Hi,
+
+static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg,
+ u32 indirect_data_reg, u32 addr, u32 data)
+{
+ u32 val;
+ u32 cmd;
+
+ cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
+ cmd = CFG_IND_ADDR_SET(cmd, addr);
This looks hacky. If 'CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK'
should
be set then it should be part of the second argument. From the macro
'CFG_IND_ADDR_SET' the first argument should be more like the
current value
present in the register right? I feel the macro (CFG_IND_ADDR_SET)
is not
used in the way it is intended to.
The macro XXX_SET is intended to update an field within the register.
The update field is returned. The first assignment lines are setting
another field. Those two lines can be written as:
cmd = 0;
cmd |= CFG_IND_WR_CMD_MASK;== Set the CMD bit
cmd |= CFG_IND_CMD_DONE_MASK;== Set the DONE bit
cmd = CFG_IND_ADDR_SET(cmd, addr);=== Set the field ADDR
#define CFG_IND_ADDR_SET(dst, src) \
(((dst) ~0x0030) | (((u32)(src)4)
0x0030))
From this macro the first argument should be the present value in that
register. Here you reset the address bits and write the new address
bits.
Yes.. This is correct. I am clearing x number of bit and then set new
value.
IMO the first argument should be the value in 'csr_base +
indirect_cmd_reg'.
So it resets the address bits in 'csr_base + indirect_cmd_reg' and write
down the new address bits.
Yes.. The above code does just that. In addition, I am also setting
the bits CFG_IND_WR_CMD_MASK and CFG_IND_CMD_DONE_MASK with the two
previous statement. Think of the code flow as follow:
val = readl(some void * address); /* read the register */
Where are you reading the register in your code (before CFG_IND_ADDR_SET)?
val = _SET(val, 0x1);/* set bit 0 - assuming set
bit 0 only */
If you want to set other bits (other than address) don't use
CFG_IND_ADDR_SET macro. That looks hacky to me.
huh.. looked it again and I think only the readl is missing. If you can
add that, it should be fine.
How about something like this
val = readl(csr_base + indirect_cmd_reg);
val = CFG_IND_ADDR_SET(val, addr);
val |= CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
writel(val, csr_base + indirect_cmd_reg);
Cheers
Kishon
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Re: [PATCH RESEND v10 3/4] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
On Thursday 27 February 2014 12:11 PM, Loc Ho wrote:
Hi,
+
+static void sds_wr(void __iomem *csr_base, u32 indirect_cmd_reg,
+ u32 indirect_data_reg, u32 addr, u32 data)
+{
+ u32 val;
+ u32 cmd;
+
+ cmd = CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK;
+ cmd = CFG_IND_ADDR_SET(cmd, addr);
This looks hacky. If 'CFG_IND_WR_CMD_MASK | CFG_IND_CMD_DONE_MASK'
should
be set then it should be part of the second argument. From the macro
'CFG_IND_ADDR_SET' the first argument should be more like the current
value
present in the register right? I feel the macro (CFG_IND_ADDR_SET) is
not
used in the way it is intended to.
The macro XXX_SET is intended to update an field within the register.
The update field is returned. The first assignment lines are setting
another field. Those two lines can be written as:
cmd = 0;
cmd |= CFG_IND_WR_CMD_MASK;== Set the CMD bit
cmd |= CFG_IND_CMD_DONE_MASK;== Set the DONE bit
cmd = CFG_IND_ADDR_SET(cmd, addr);=== Set the field ADDR
#define CFG_IND_ADDR_SET(dst, src) \
(((dst) ~0x0030) | (((u32)(src)4) 0x0030))
From this macro the first argument should be the present value in that
register. Here you reset the address bits and write the new address bits.
Yes.. This is correct. I am clearing x number of bit and then set new
value.
IMO the first argument should be the value in 'csr_base +
indirect_cmd_reg'.
So it resets the address bits in 'csr_base + indirect_cmd_reg' and write
down the new address bits.
Yes.. The above code does just that. In addition, I am also setting
the bits CFG_IND_WR_CMD_MASK and CFG_IND_CMD_DONE_MASK with the two
previous statement. Think of the code flow as follow:
val = readl(some void * address); /* read the register */
Where are you reading the register in your code (before CFG_IND_ADDR_SET)?
I am not reading the register as I will be completely setting them.
Ok. Never-mind then. Sorry for the noise. You code is fine.
Thanks
Kishon
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Re: [PATCH v2 5/5] phy: mvebu-sata: prepare new Dove DT Kconfig variable
On Saturday 01 March 2014 02:03 PM, Sebastian Hesselbarth wrote: DT-enabled Dove will move over from ARCH_DOVE in mach-dove to MACH_DOVE in mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new DT-only MACH_DOVE Kconfig. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com --- Kishon, Mark Brown requested to take the corresponding ASoC patch through his tree. Therefore, I have split the former patch into individual subsystem patches. This patch also received an update, to not break bisectability we add DT-enabled MACH_DOVE and maintain ARCH_DOVE, which is non-DT only after conversion. ARCH_DOVE will be removed, when legacy mach-dove will be removed. Cool.. Should this patch be going through PHY tree? Cheers Kishon Cc: Kishon Vijay Abraham I kis...@ti.com Cc: Jason Cooper ja...@lakedaemon.net Cc: Andrew Lunn and...@lunn.ch Cc: Gregory Clement gregory.clem...@free-electrons.com Cc: linux-arm-ker...@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/phy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index c7a551c2d5f1..e81daff7b5a3 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -24,7 +24,7 @@ config PHY_EXYNOS_MIPI_VIDEO config PHY_MVEBU_SATA def_bool y - depends on ARCH_KIRKWOOD || ARCH_DOVE + depends on ARCH_KIRKWOOD || ARCH_DOVE || MACH_DOVE depends on OF select GENERIC_PHY -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 3/4] ARM: DT: STi: Add DT node for MiPHY365x
Hi,
On Friday 14 February 2014 04:53 PM, Lee Jones wrote:
The MiPHY365x is a Generic PHY which can serve various SATA or PCIe
devices. It has 2 ports which it can use for either; both SATA, both
PCIe or one of each in any configuration.
Cc: devicet...@vger.kernel.org
Cc: Srinivas Kandagatla srinivas.kandaga...@st.com
Signed-off-by: Lee Jones lee.jo...@linaro.org
since this uses 'dt-bindings/phy/phy-miphy365x.h' which is used in phy
driver as well, I need ACK from dt maintainers so that I can queue both
the driver and dt patches myself.
Thanks
Kishon
---
arch/arm/boot/dts/stih416-b2020-revE.dts | 6 +-
arch/arm/boot/dts/stih416-b2020.dts | 6 ++
arch/arm/boot/dts/stih416.dtsi | 13 +
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/stih416-b2020-revE.dts
b/arch/arm/boot/dts/stih416-b2020-revE.dts
index a874570..dbe67fa 100644
--- a/arch/arm/boot/dts/stih416-b2020-revE.dts
+++ b/arch/arm/boot/dts/stih416-b2020-revE.dts
@@ -32,6 +32,10 @@
ethernet1: ethernet@fef08000 {
snps,reset-gpio = PIO0 7;
};
- };
+ miphy365x_phy: miphy365x@0 {
+ st,pcie_tx_pol_inv = 1;
+ st,sata_gen = gen3;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/stih416-b2020.dts
b/arch/arm/boot/dts/stih416-b2020.dts
index 276f28d..fd9cbad 100644
--- a/arch/arm/boot/dts/stih416-b2020.dts
+++ b/arch/arm/boot/dts/stih416-b2020.dts
@@ -13,4 +13,10 @@
model = STiH416 B2020;
compatible = st,stih416, st,stih416-b2020;
+ soc {
+ miphy365x_phy: miphy365x@0 {
+ st,pcie_tx_pol_inv = 1;
+ st,sata_gen = gen3;
+ };
+ };
};
diff --git a/arch/arm/boot/dts/stih416.dtsi b/arch/arm/boot/dts/stih416.dtsi
index 85b8063..9fd8efb 100644
--- a/arch/arm/boot/dts/stih416.dtsi
+++ b/arch/arm/boot/dts/stih416.dtsi
@@ -9,6 +9,8 @@
#include stih41x.dtsi
#include stih416-clock.dtsi
#include stih416-pinctrl.dtsi
+
+#include dt-bindings/phy/phy-miphy365x.h
#include dt-bindings/interrupt-controller/arm-gic.h
#include dt-bindings/reset-controller/stih416-resets.h
/ {
@@ -140,5 +142,16 @@
clocks = CLK_S_ICN_REG_0;
};
+ miphy365x_phy: miphy365x@0 {
+ compatible = st,miphy365x-phy;
+ reg = 0xfe382000 0x100,
+ 0xfe38a000 0x100,
+ 0xfe394000 0x100,
+ 0xfe804000 0x100;
+ reg-names = sata0, sata1, pcie0, pcie1;
+
+ #phy-cells = 2;
+ st,syscfg = syscfg_rear;
+ };
};
};
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[PATCH v5 0/6] Make dwc3 use Generic PHY Framework
Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3
should be programmed. While this can be considered as a temporary fix,
a long term solution would be to add 'nop' PHY for platforms that does
not have programmable PHY.
Adapted DWC3 and USB3 PHY to use Generic PHY framework. Also changed the
name of USB3 PHY driver to PIPE3 PHY driver since the same driver has to
be used for SATA and PCIE too.
Changes from v4: (sending the entire patch series again)
* check the return values of phy_init and phy_power_on
* print errors if power_on or power_off of PHY fails.
Changes from v3: (Sent only adapt dwc3 core to use Generic PHY Framework)
* avoided using quirks and rely on the return values of PHY APIs to find the
presence of PHY.
Changes from v2:
* added a couple of fixes. One is invoking phy_resume after phy_init and the
other is power off phy in error patch
* used quirks to identify if a particular platform does not have PHYs
* removed using separate header for pipe3 driver and also removed all referencs
to SATA and PCIe in pipe3 driver since it's not yet adapted for those drivers.
Changes from v1:
* The logic in which the driver detects the presence of PHYs has changed.
* patch ordering has changed
* udelay is replaced with usleep_range
* A patch to remove set_suspend callback which was deferred from Generic
PHY Framework series has been included.
Kishon Vijay Abraham I (6):
usb: dwc3: core: support optional PHYs
usb: dwc3: adapt dwc3 core to use Generic PHY Framework
drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework
usb: phy: omap-usb2: remove *set_suspend* callback from omap-usb2
phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
arm/dts: added dt properties to adapt to the new phy framwork
Documentation/devicetree/bindings/usb/dwc3.txt |6 +-
arch/arm/boot/dts/omap5.dtsi |5 +-
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
drivers/phy/phy-omap-usb2.c| 27 +--
.../phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} | 240
drivers/usb/dwc3/core.c| 116 +++---
drivers/usb/dwc3/core.h|7 +
drivers/usb/phy/Kconfig| 11 -
drivers/usb/phy/Makefile |1 -
include/linux/{usb = phy}/omap_usb.h |3 -
11 files changed, 264 insertions(+), 164 deletions(-)
rename drivers/{usb/phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} (54%)
rename include/linux/{usb = phy}/omap_usb.h (95%)
--
1.7.9.5
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[PATCH v5 2/6] usb: dwc3: adapt dwc3 core to use Generic PHY Framework
Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
power_on and power_off the following APIs are used phy_init(), phy_exit(),
phy_power_on() and phy_power_off().
However using the old USB phy library wont be removed till the PHYs of all
other SoC's using dwc3 core is adapted to the Generic PHY Framework.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/dwc3.txt |6 +-
drivers/usb/dwc3/core.c| 86 +---
drivers/usb/dwc3/core.h|7 ++
3 files changed, 89 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index e807635..471366d 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -6,11 +6,13 @@ Required properties:
- compatible: must be snps,dwc3
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
+
+Optional properties:
- usb-phy : array of phandle for the PHY device. The first element
in the array is expected to be a handle to the USB2/HS PHY and
the second element is expected to be a handle to the USB3/SS PHY
-
-Optional properties:
+ - phys: from the *Generic PHY* bindings
+ - phy-names: from the *Generic PHY* bindings
- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 225a4d6..497234a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -61,9 +61,10 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
-static void dwc3_core_soft_reset(struct dwc3 *dwc)
+static int dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
+ int ret;
/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc-regs, DWC3_GCTL);
@@ -82,6 +83,15 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc)
usb_phy_init(dwc-usb2_phy);
usb_phy_init(dwc-usb3_phy);
+ ret = phy_init(dwc-usb2_generic_phy);
+ if (ret 0)
+ return ret;
+
+ ret = phy_init(dwc-usb3_generic_phy);
+ if (ret 0) {
+ phy_exit(dwc-usb2_generic_phy);
+ return ret;
+ }
mdelay(100);
/* Clear USB3 PHY reset */
@@ -100,6 +110,8 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc)
reg = dwc3_readl(dwc-regs, DWC3_GCTL);
reg = ~DWC3_GCTL_CORESOFTRESET;
dwc3_writel(dwc-regs, DWC3_GCTL, reg);
+
+ return 0;
}
/**
@@ -381,7 +393,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
cpu_relax();
} while (true);
- dwc3_core_soft_reset(dwc);
+ ret = dwc3_core_soft_reset(dwc);
+ if (ret)
+ goto err0;
reg = dwc3_readl(dwc-regs, DWC3_GCTL);
reg = ~DWC3_GCTL_SCALEDOWN_MASK;
@@ -446,6 +460,8 @@ err2:
err1:
usb_phy_shutdown(dwc-usb2_phy);
usb_phy_shutdown(dwc-usb3_phy);
+ phy_exit(dwc-usb2_generic_phy);
+ phy_exit(dwc-usb3_generic_phy);
err0:
return ret;
@@ -453,14 +469,12 @@ err0:
static void dwc3_core_exit(struct dwc3 *dwc)
{
- if (!IS_ERR(dwc-usb2_phy))
- usb_phy_shutdown(dwc-usb2_phy);
- if (!IS_ERR(dwc-usb3_phy))
- usb_phy_shutdown(dwc-usb3_phy);
-
dwc3_free_scratch_buffers(dwc);
usb_phy_shutdown(dwc-usb2_phy);
usb_phy_shutdown(dwc-usb3_phy);
+ phy_exit(dwc-usb2_generic_phy);
+ phy_exit(dwc-usb3_generic_phy);
+
}
#define DWC3_ALIGN_MASK(16 - 1)
@@ -551,6 +565,32 @@ static int dwc3_probe(struct platform_device *pdev)
}
}
+ dwc-usb2_generic_phy = devm_phy_get(dev, usb2-phy);
+ if (IS_ERR(dwc-usb2_generic_phy)) {
+ ret = PTR_ERR(dwc-usb2_generic_phy);
+ if (ret == -ENOSYS || ret == -ENODEV) {
+ dwc-usb2_generic_phy = NULL;
+ } else if (ret == -EPROBE_DEFER) {
+ return ret;
+ } else {
+ dev_err(dev, no usb2 phy configured\n);
+ return ret;
+ }
+ }
+
+ dwc-usb3_generic_phy = devm_phy_get(dev, usb3-phy);
+ if (IS_ERR(dwc-usb3_generic_phy)) {
+ ret = PTR_ERR(dwc-usb3_generic_phy);
+ if (ret == -ENOSYS || ret == -ENODEV) {
+ dwc-usb3_generic_phy = NULL;
+ } else if (ret == -EPROBE_DEFER) {
+ return ret;
+ } else {
+ dev_err(dev, no usb3 phy configured\n);
+ return ret
[PATCH v5 5/6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-omap-usb2.c |2 +-
include/linux/{usb = phy}/omap_usb.h |3 ---
2 files changed, 1 insertion(+), 4 deletions(-)
rename include/linux/{usb = phy}/omap_usb.h (95%)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 705af5a..9c3f056 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -21,7 +21,7 @@
#include linux/slab.h
#include linux/of.h
#include linux/io.h
-#include linux/usb/omap_usb.h
+#include linux/phy/omap_usb.h
#include linux/usb/phy_companion.h
#include linux/clk.h
#include linux/err.h
diff --git a/include/linux/usb/omap_usb.h b/include/linux/phy/omap_usb.h
similarity index 95%
rename from include/linux/usb/omap_usb.h
rename to include/linux/phy/omap_usb.h
index 6ae2936..19d343c3 100644
--- a/include/linux/usb/omap_usb.h
+++ b/include/linux/phy/omap_usb.h
@@ -33,13 +33,10 @@ struct usb_dpll_params {
struct omap_usb {
struct usb_phy phy;
struct phy_companion*comparator;
- void __iomem*pll_ctrl_base;
struct device *dev;
struct device *control_dev;
struct clk *wkupclk;
- struct clk *sys_clk;
struct clk *optclk;
- u8 is_suspended:1;
};
#definephy_to_omapusb(x) container_of((x), struct omap_usb, phy)
--
1.7.9.5
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[PATCH v5 6/6] arm/dts: added dt properties to adapt to the new phy framwork
Added device tree bindings for dwc3, usb2 and usb3 PHYs. The documentation
of these can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt
and Documentation/devicetree/bindings/phy/ti-phy.txt.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a72813a..1c68558 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -732,7 +732,8 @@
compatible = snps,dwc3;
reg = 0x4a03 0x1;
interrupts = GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH;
- usb-phy = usb2_phy, usb3_phy;
+ phys = usb2_phy, usb3_phy;
+ phy-names = usb2-phy, usb3-phy;
dr_mode = peripheral;
tx-fifo-resize;
};
@@ -749,6 +750,7 @@
compatible = ti,omap-usb2;
reg = 0x4a084000 0x7c;
ctrl-module = omap_control_usb2phy;
+ #phy-cells = 0;
};
usb3_phy: usb3phy@4a084400 {
@@ -758,6 +760,7 @@
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb3phy;
+ #phy-cells = 0;
};
};
--
1.7.9.5
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[PATCH v5 3/6] drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework
Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3
driver in drivers/usb/phy to drivers/phy and also renamed the file to
phy-ti-pipe3 since this same driver will be used for SATA PHY and
PCIE PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
.../phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} | 240
drivers/usb/phy/Kconfig| 11 -
drivers/usb/phy/Makefile |1 -
5 files changed, 158 insertions(+), 106 deletions(-)
rename drivers/{usb/phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} (54%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c7a551c..e3ec7d1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -40,6 +40,17 @@ config OMAP_USB2
The USB OTG controller communicates with the comparator using this
driver.
+config TI_PIPE3
+ tristate TI PIPE3 PHY Driver
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ select GENERIC_PHY
+ select OMAP_CONTROL_USB
+ help
+ Enable this to support the PIPE3 PHY that is part of TI SOCs. This
+ driver takes care of all the PHY functionality apart from comparator.
+ This driver interacts with the OMAP Control PHY Driver to power
+ on/off the PHY.
+
config TWL4030_USB
tristate TWL4030 USB Transceiver Driver
depends on TWL4030_CORE REGULATOR_TWL4030 USB_MUSB_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..32e3f94 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
+obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/phy/phy-ti-pipe3.c
similarity index 54%
rename from drivers/usb/phy/phy-omap-usb3.c
rename to drivers/phy/phy-ti-pipe3.c
index 0c6ba29..67b189d 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -1,5 +1,5 @@
/*
- * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
+ * phy-ti-pipe3 - PIPE3 PHY driver.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -19,10 +19,11 @@
#include linux/module.h
#include linux/platform_device.h
#include linux/slab.h
-#include linux/usb/omap_usb.h
+#include linux/phy/phy.h
#include linux/of.h
#include linux/clk.h
#include linux/err.h
+#include linux/io.h
#include linux/pm_runtime.h
#include linux/delay.h
#include linux/usb/omap_control_usb.h
@@ -52,17 +53,34 @@
/*
* This is an Empirical value that works, need to confirm the actual
- * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
- * to be correctly reflected in the USB3PHY_PLL_STATUS register.
+ * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
+ * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
# define PLL_IDLE_TIME 100;
-struct usb_dpll_map {
+struct pipe3_dpll_params {
+ u16 m;
+ u8 n;
+ u8 freq:3;
+ u8 sd;
+ u32 mf;
+};
+
+struct ti_pipe3 {
+ void __iomem*pll_ctrl_base;
+ struct device *dev;
+ struct device *control_dev;
+ struct clk *wkupclk;
+ struct clk *sys_clk;
+ struct clk *optclk;
+};
+
+struct pipe3_dpll_map {
unsigned long rate;
- struct usb_dpll_params params;
+ struct pipe3_dpll_params params;
};
-static struct usb_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
@@ -71,7 +89,18 @@ static struct usb_dpll_map dpll_map[] = {
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
};
-static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
+static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+ return __raw_readl(addr + offset);
+}
+
+static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
+ u32 data)
+{
+ __raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
{
int i;
@@ -83,110 +112,123 @@ static struct usb_dpll_params
*omap_usb3_get_dpll_params(unsigned long rate)
return NULL;
}
-static int omap_usb3_suspend(struct usb_phy *x
[PATCH v5 4/6] usb: phy: omap-usb2: remove *set_suspend* callback from omap-usb2
Now that omap-usb2 is adapted to the new generic PHY framework,
*set_suspend* ops can be removed from omap-usb2 driver.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/phy/phy-omap-usb2.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 7699752..705af5a 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -98,28 +98,6 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb2_suspend(struct usb_phy *x, int suspend)
-{
- struct omap_usb *phy = phy_to_omapusb(x);
- int ret;
-
- if (suspend !phy-is_suspended) {
- omap_control_usb_phy_power(phy-control_dev, 0);
- pm_runtime_put_sync(phy-dev);
- phy-is_suspended = 1;
- } else if (!suspend phy-is_suspended) {
- ret = pm_runtime_get_sync(phy-dev);
- if (ret 0) {
- dev_err(phy-dev, get_sync failed with err %d\n, ret);
- return ret;
- }
- omap_control_usb_phy_power(phy-control_dev, 1);
- phy-is_suspended = 0;
- }
-
- return 0;
-}
-
static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
@@ -173,7 +151,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-phy.dev= phy-dev;
phy-phy.label = omap-usb2;
- phy-phy.set_suspend= omap_usb2_suspend;
phy-phy.otg= otg;
phy-phy.type = USB_PHY_TYPE_USB2;
@@ -190,8 +167,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
}
phy-control_dev = control_pdev-dev;
-
- phy-is_suspended = 1;
omap_control_usb_phy_power(phy-control_dev, 0);
otg-set_host = omap_usb_set_host;
--
1.7.9.5
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[PATCH v5 1/6] usb: dwc3: core: support optional PHYs
Since PHYs for dwc3 is optional (not all SoCs having PHYs for DWC3
should be programmed), do not return from probe if the USB PHY library
returns -ENODEV as that indicates the platform does not have a
programmable PHY.
While this can be considered as a temporary fix, a long term solution
would be to add 'nop' PHY for platforms that does not have programmable
PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Reviewed-by: Roger Quadros rog...@ti.com
---
drivers/usb/dwc3/core.c | 34 ++
1 file changed, 14 insertions(+), 20 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 7d0cb34..225a4d6 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -529,32 +529,26 @@ static int dwc3_probe(struct platform_device *pdev)
if (IS_ERR(dwc-usb2_phy)) {
ret = PTR_ERR(dwc-usb2_phy);
-
- /*
-* if -ENXIO is returned, it means PHY layer wasn't
-* enabled, so it makes no sense to return -EPROBE_DEFER
-* in that case, since no PHY driver will ever probe.
-*/
- if (ret == -ENXIO)
+ if (ret == -ENXIO || ret == -ENODEV) {
+ dwc-usb2_phy = NULL;
+ } else if (ret == -EPROBE_DEFER) {
return ret;
-
- dev_err(dev, no usb2 phy configured\n);
- return -EPROBE_DEFER;
+ } else {
+ dev_err(dev, no usb2 phy configured\n);
+ return ret;
+ }
}
if (IS_ERR(dwc-usb3_phy)) {
ret = PTR_ERR(dwc-usb3_phy);
-
- /*
-* if -ENXIO is returned, it means PHY layer wasn't
-* enabled, so it makes no sense to return -EPROBE_DEFER
-* in that case, since no PHY driver will ever probe.
-*/
- if (ret == -ENXIO)
+ if (ret == -ENXIO || ret == -ENODEV) {
+ dwc-usb3_phy = NULL;
+ } else if (ret == -EPROBE_DEFER) {
return ret;
-
- dev_err(dev, no usb3 phy configured\n);
- return -EPROBE_DEFER;
+ } else {
+ dev_err(dev, no usb3 phy configured\n);
+ return ret;
+ }
}
dwc-xhci_resources[0].start = res-start;
--
1.7.9.5
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Re: [PATCH V9 2/2] ARM: dts: Enable ahci sata and sata phy
On Monday 03 March 2014 10:52 AM, Yuvaraj Kumar C D wrote:
This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
This should go via exynos dt tree.
FWIW
Acked-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes since V8:
1.sata@122f and sata_phy@1217 disabled by default in
SOC specific dts file and enabled the same in board dts file.
Changes since V7:
1.syscon-phandle name updated.
Changes since V6:none
Changes since V5:none
Changes since V4:
1.Used the new phandle sata_phy_i2c in the DT entry.
2.Updated binding document.
Changes since V3:
1.Moved the binding info to the /bindings/phy/
Changes since V2:
1.Used syscon interface to PMU handling.
2.Changed sata-phy-i2c to exynos-sataphy-i2c.
Changes since V1:
1.Minor changes to node name convention.
2.Updated binding document.
.../devicetree/bindings/ata/exynos-sata-phy.txt| 14
.../devicetree/bindings/ata/exynos-sata.txt| 25 +-
.../devicetree/bindings/phy/samsung-phy.txt| 36
arch/arm/boot/dts/exynos5250-arndale.dts | 21
arch/arm/boot/dts/exynos5250-smdk5250.dts | 17 +
arch/arm/boot/dts/exynos5250.dtsi | 18 +++---
6 files changed, 98 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fa..000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible: compatible list, contains samsung,exynos5-sata-phy
-- reg : registers mapping
-
-Example:
-sata@ffe07000 {
-compatible = samsung,exynos5-sata-phy;
-reg = 0xffe07000 0x1000;
-};
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt
b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f10..b2adb1f 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA
controllers.
Each SATA controller should have its own node.
Required properties:
-- compatible: compatible list, contains samsung,exynos5-sata
-- interrupts: interrupt mapping for SATA IRQ
-- reg : registers mapping
-- samsung,sata-freq : frequency in MHz
+- compatible : compatible list, contains samsung,exynos5-sata
+- interrupts : interrupt mapping for SATA IRQ
+- reg : registers mapping
+- samsung,sata-freq: frequency in MHz
+- phys : as mentioned in phy-bindings.txt
+- phy-names: as mentioned in phy-bindings.txt
Example:
-sata@ffe08000 {
-compatible = samsung,exynos5-sata;
-reg = 0xffe08000 0x1000;
-interrupts = 115;
-};
+ sata@122f {
+ compatible = snps,dwc-ahci;
+ samsung,sata-freq = 66;
+ reg = 0x122f 0x1ff;
+ interrupts = 0 115 0;
+ clocks = clock 277, clock 143;
+ clock-names = sata, sclk_sata;
+ phys = sata_phy;
+ phy-names = sata-phy;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..a937f75 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,39 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung SATA PHY Controller
+---
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains samsung,exynos5250-sata-phy
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : from the generic phy bindings;
+
+Example:
+ sata_phy: sata-phy@1217 {
+ compatible = samsung,exynos5250-sata-phy;
+ reg = 0x1217 0x1ff;
+ clocks = clock 287;
+ clock-names = sata_phyctrl
Re: [PATCH v5 0/6] Make dwc3 use Generic PHY Framework
Roger,
On Monday 03 March 2014 05:51 PM, Roger Quadros wrote:
Hi Kishon,
Which tree are these patches based on?
mainline + Felipe's testing/next + Revert usb: dwc3: core: enable
Suspend bit for USB2/3 PHYs + Revert usb: dwc3: preparation for
adapting dwc3 to generic phy framework
Thanks
Kishon
cheers,
-roger
On 03/03/2014 01:38 PM, Kishon Vijay Abraham I wrote:
Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3
should be programmed. While this can be considered as a temporary fix,
a long term solution would be to add 'nop' PHY for platforms that does
not have programmable PHY.
Adapted DWC3 and USB3 PHY to use Generic PHY framework. Also changed the
name of USB3 PHY driver to PIPE3 PHY driver since the same driver has to
be used for SATA and PCIE too.
Changes from v4: (sending the entire patch series again)
* check the return values of phy_init and phy_power_on
* print errors if power_on or power_off of PHY fails.
Changes from v3: (Sent only adapt dwc3 core to use Generic PHY Framework)
* avoided using quirks and rely on the return values of PHY APIs to find the
presence of PHY.
Changes from v2:
* added a couple of fixes. One is invoking phy_resume after phy_init and the
other is power off phy in error patch
* used quirks to identify if a particular platform does not have PHYs
* removed using separate header for pipe3 driver and also removed all referencs
to SATA and PCIe in pipe3 driver since it's not yet adapted for those drivers.
Changes from v1:
* The logic in which the driver detects the presence of PHYs has changed.
* patch ordering has changed
* udelay is replaced with usleep_range
* A patch to remove set_suspend callback which was deferred from Generic
PHY Framework series has been included.
Kishon Vijay Abraham I (6):
usb: dwc3: core: support optional PHYs
usb: dwc3: adapt dwc3 core to use Generic PHY Framework
drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework
usb: phy: omap-usb2: remove *set_suspend* callback from omap-usb2
phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
arm/dts: added dt properties to adapt to the new phy framwork
Documentation/devicetree/bindings/usb/dwc3.txt |6 +-
arch/arm/boot/dts/omap5.dtsi |5 +-
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
drivers/phy/phy-omap-usb2.c| 27 +--
.../phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} | 240
drivers/usb/dwc3/core.c| 116 +++---
drivers/usb/dwc3/core.h|7 +
drivers/usb/phy/Kconfig| 11 -
drivers/usb/phy/Makefile |1 -
include/linux/{usb = phy}/omap_usb.h |3 -
11 files changed, 264 insertions(+), 164 deletions(-)
rename drivers/{usb/phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} (54%)
rename include/linux/{usb = phy}/omap_usb.h (95%)
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Re: [PATCH v6 5/8] phy: Add new Exynos USB PHY driver
Hi,
On Wednesday 29 January 2014 10:59 PM, Kamil Debski wrote:
Add a new driver for the Exynos USB PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Can the PHY part of this series be merged independently of the
controller part?
Thanks
Kishon
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 55
Documentation/phy/samsung-usb2.txt | 135
drivers/phy/Kconfig| 29 ++
drivers/phy/Makefile |3 +
drivers/phy/phy-exynos4210-usb2.c | 257
drivers/phy/phy-exynos4x12-usb2.c | 323
drivers/phy/phy-samsung-usb2.c | 227 ++
drivers/phy/phy-samsung-usb2.h | 67
8 files changed, 1096 insertions(+)
create mode 100644 Documentation/phy/samsung-usb2.txt
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4x12-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..6668c41 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,58 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usb2-phy
+ - samsung,exynos4x12-usb2-phy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system
registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clocks is required by the phy module
+ - next for each of the phys a clock has to be assigned, this clock
+ will be used to determine clocking frequency for the phys
+ (the labels are specified in the paragraph below)
+
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
+and Exynos 4212) it is as follows:
+ 0 - USB device (device),
+ 1 - USB host (host),
+ 2 - HSIC0 (hsic0),
+ 3 - HSIC1 (hsic1),
+
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+usbphy: phy@125b {
+ compatible = samsung,exynos4212-usb2-phy;
+ reg = 0x125b 0x100 0x10020704 0x0c 0x1001021c 0x4;
+ clocks = clock 305, clock 2, clock 2, clock 2,
+ clock 2;
+ clock-names = phy, device, host, hsic0, hsic1;
+ status = okay;
+ #phy-cells = 1;
+ samsung,sysreg-phandle = sys_reg;
+ samsung,pmureg-phandle = pmu_reg;
+};
+
+Then the PHY can be used in other nodes such as:
+
+phy-consumer@1234 {
+ phys = usbphy 2;
+ phy-names = phy;
+};
+
+Refer to DT bindings documentation of particular PHY consumer devices for more
+information about required PHYs and the way of specification.
diff --git a/Documentation/phy/samsung-usb2.txt
b/Documentation/phy/samsung-usb2.txt
new file mode 100644
index 000..9f5826e
--- /dev/null
+++ b/Documentation/phy/samsung-usb2.txt
@@ -0,0 +1,135 @@
+.--+
+| Samsung USB 2.0 PHY adaptation layer |
++-+'
+
+| 1. Description
++
+
+The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
+among many SoCs. In spite of the similarities it proved difficult to
+create a one driver that would fit all these PHY controllers. Often
+the differences were minor and were found in particular bits of the
+registers of the PHY. In some rare cases the order of register writes or
+the PHY powering up process had to be altered. This adaptation layer is
+a compromise between having separate drivers and having a single driver
+with added support for many special cases.
+
+| 2. Files description
++--
+
+- phy-samsung-usb2.c
+ This is the main file of the adaptation layer. This file contains
+ the probe function and
Re: [PATCH 01/12] phy: rename struct omap_control_usb to struct omap_control_phy
Roger, On Monday 03 March 2014 08:37 PM, Roger Quadros wrote: From: Kishon Vijay Abraham I kis...@ti.com Rename struct omap_control_usb to struct omap_control_phy since it can be used to control PHY of USB, SATA and PCIE. Also move the driver and include files under *phy* and made the corresponding changes in the users of phy-omap-control. Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Signed-off-by: Roger Quadros rog...@ti.com --- drivers/phy/Kconfig | 14 +- drivers/phy/Makefile | 1 + drivers/phy/phy-omap-control.c | 320 +++ drivers/phy/phy-omap-usb2.c | 8 +- drivers/phy/phy-ti-pipe3.c | 8 +- drivers/usb/musb/omap2430.c | 2 +- drivers/usb/phy/Kconfig | 10 -- drivers/usb/phy/Makefile | 1 - drivers/usb/phy/phy-omap-control.c | 319 -- include/linux/phy/omap_control_phy.h | 89 ++ include/linux/usb/omap_control_usb.h | 89 -- 11 files changed, 431 insertions(+), 430 deletions(-) create mode 100644 drivers/phy/phy-omap-control.c delete mode 100644 drivers/usb/phy/phy-omap-control.c create mode 100644 include/linux/phy/omap_control_phy.h delete mode 100644 include/linux/usb/omap_control_usb.h you can use git format-patch -M if a file is moved from one place to another. The diff count will be less in that case and reviewing will be easier ;-) Cheers Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH 03/12] phy: ti-pipe3: cleanup clock handling
Hi, On Monday 03 March 2014 08:37 PM, Roger Quadros wrote: As this driver is no longer USB specific, use generic clock names. - Fix PLL_SD_SHIFT from 9 to 10 - As optclk and wkupclk may not be always required, don't bail out if they aren't available. I think here too we face the same problem as for PHY. What if a particular platform needs a clock but is not available. I don't want this to be blocking though. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 0/6] Make dwc3 use Generic PHY Framework
On Monday 03 March 2014 10:10 PM, Felipe Balbi wrote: Hi, On Mon, Mar 03, 2014 at 05:08:09PM +0530, Kishon Vijay Abraham I wrote: Added support for optional PHY in dwc3 as not all SoCs having PHYs for DWC3 should be programmed. While this can be considered as a temporary fix, a long term solution would be to add 'nop' PHY for platforms that does not have programmable PHY. Adapted DWC3 and USB3 PHY to use Generic PHY framework. Also changed the name of USB3 PHY driver to PIPE3 PHY driver since the same driver has to be used for SATA and PCIE too. Changes from v4: (sending the entire patch series again) * check the return values of phy_init and phy_power_on * print errors if power_on or power_off of PHY fails. Changes from v3: (Sent only adapt dwc3 core to use Generic PHY Framework) * avoided using quirks and rely on the return values of PHY APIs to find the presence of PHY. Changes from v2: * added a couple of fixes. One is invoking phy_resume after phy_init and the other is power off phy in error patch * used quirks to identify if a particular platform does not have PHYs * removed using separate header for pipe3 driver and also removed all referencs to SATA and PCIe in pipe3 driver since it's not yet adapted for those drivers. Changes from v1: * The logic in which the driver detects the presence of PHYs has changed. * patch ordering has changed * udelay is replaced with usleep_range * A patch to remove set_suspend callback which was deferred from Generic PHY Framework series has been included. Kishon Vijay Abraham I (6): usb: dwc3: core: support optional PHYs usb: dwc3: adapt dwc3 core to use Generic PHY Framework drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework usb: phy: omap-usb2: remove *set_suspend* callback from omap-usb2 phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/ arm/dts: added dt properties to adapt to the new phy framwork patches 1 and 2 are in my testing/next, I guess 3,4,5 and 6 have no direct dependency on those, right ? that's right. I'll take 3, 4 and 5th patch in my tree and ping Tony to take 6th patch. -Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: RESEND [PATCH V9 2/2] ARM: dts: exynos5250: Enable ahci sata and sata phy
On Tuesday 04 March 2014 04:40 PM, Yuvaraj Kumar C D wrote:
This patch adds dt entry for ahci sata controller and its
corresponding phy controller.phy node has been added w.r.t
new generic phy framework.
Signed-off-by: Yuvaraj Kumar C D yuvaraj...@samsung.com
FWIW
Acked-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/ata/exynos-sata-phy.txt| 14
.../devicetree/bindings/ata/exynos-sata.txt| 25 +-
.../devicetree/bindings/phy/samsung-phy.txt| 36
arch/arm/boot/dts/exynos5250-arndale.dts | 21
arch/arm/boot/dts/exynos5250-smdk5250.dts | 17 +
arch/arm/boot/dts/exynos5250.dtsi | 18 +++---
6 files changed, 98 insertions(+), 33 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
b/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
deleted file mode 100644
index 37824fa..000
--- a/Documentation/devicetree/bindings/ata/exynos-sata-phy.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-* Samsung SATA PHY Controller
-
-SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
-Each SATA PHY controller should have its own node.
-
-Required properties:
-- compatible: compatible list, contains samsung,exynos5-sata-phy
-- reg : registers mapping
-
-Example:
-sata@ffe07000 {
-compatible = samsung,exynos5-sata-phy;
-reg = 0xffe07000 0x1000;
-};
diff --git a/Documentation/devicetree/bindings/ata/exynos-sata.txt
b/Documentation/devicetree/bindings/ata/exynos-sata.txt
index 0849f10..b2adb1f 100644
--- a/Documentation/devicetree/bindings/ata/exynos-sata.txt
+++ b/Documentation/devicetree/bindings/ata/exynos-sata.txt
@@ -4,14 +4,21 @@ SATA nodes are defined to describe on-chip Serial ATA
controllers.
Each SATA controller should have its own node.
Required properties:
-- compatible: compatible list, contains samsung,exynos5-sata
-- interrupts: interrupt mapping for SATA IRQ
-- reg : registers mapping
-- samsung,sata-freq : frequency in MHz
+- compatible : compatible list, contains samsung,exynos5-sata
+- interrupts : interrupt mapping for SATA IRQ
+- reg : registers mapping
+- samsung,sata-freq: frequency in MHz
+- phys : as mentioned in phy-bindings.txt
+- phy-names: as mentioned in phy-bindings.txt
Example:
-sata@ffe08000 {
-compatible = samsung,exynos5-sata;
-reg = 0xffe08000 0x1000;
-interrupts = 115;
-};
+ sata@122f {
+ compatible = snps,dwc-ahci;
+ samsung,sata-freq = 66;
+ reg = 0x122f 0x1ff;
+ interrupts = 0 115 0;
+ clocks = clock 277, clock 143;
+ clock-names = sata, sclk_sata;
+ phys = sata_phy;
+ phy-names = sata-phy;
+ };
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..a937f75 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,39 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung SATA PHY Controller
+---
+
+SATA PHY nodes are defined to describe on-chip SATA Physical layer controllers.
+Each SATA PHY controller should have its own node.
+
+Required properties:
+- compatible: compatible list, contains samsung,exynos5250-sata-phy
+- reg : offset and length of the SATA PHY register set;
+- #phy-cells : from the generic phy bindings;
+
+Example:
+ sata_phy: sata-phy@1217 {
+ compatible = samsung,exynos5250-sata-phy;
+ reg = 0x1217 0x1ff;
+ clocks = clock 287;
+ clock-names = sata_phyctrl;
+ #phy-cells = 0;
+ samsung,exynos-sataphy-i2c-phandle = sata_phy_i2c;
+ samsung,syscon-phandle = pmu_syscon;
+ };
+
+Device-Tree bindings for sataphy i2c client driver
+--
+
+Required properties:
+compatible: Should be samsung,exynos-sataphy-i2c
+- reg: I2C address of the sataphy i2c device.
+
+Example:
+
+ sata_phy_i2c:sata-phy@38 {
+ compatible = samsung,exynos-sataphy-i2c;
+ reg = 0x38;
+ };
diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts
b/arch/arm/boot/dts/exynos5250-arndale.dts
index 38b96a4..97eef40 100644
--- a/arch/arm/boot/dts/exynos5250-arndale.dts
+++ b/arch/arm/boot/dts
Re: [PATCH 2/3] phy: omap-usb2: Provide workaround for USB2PHY false disconnect
Hi,
On Monday 03 March 2014 03:52 PM, George Cherian wrote:
From: Austin Beam austinb...@ti.com
Enable the dra7x errata workaround for false disconnect problem
with USB2PHY. False disconnects were detected with some of the devices.
Reduce the sensitivity of the disconnect logic within the USB2PHY subsystem
to enusre these false disconnects are not registered.
[george.cher...@ti.com]
While at that, pass proper flags for each SoC's. This is a common driver
used across OMAP4,OMAP5,DRA7xx and AM437x USB2PHY.
False disconnect workaround is currently applicable for only DRA7x.
Update the Documentation also to add new comaptible.
Signed-off-by: Austin Beam austinb...@ti.com
Signed-off-by: George Cherian george.cher...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/usb-phy.txt | 3 +-
drivers/phy/phy-omap-usb2.c | 48 +++
include/linux/usb/omap_usb.h | 3 ++
3 files changed, 53 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt
b/Documentation/devicetree/bindings/usb/usb-phy.txt
index b3fa409..03de61a5 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -4,7 +4,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be either of
- * ti,omap-usb2 for OMAP4, OMAP5, DRA7
+ * ti,omap-usb2 for OMAP4 and OMAP5
+ * ti,dra7x-usb2 for DRA7
* ti,am437x-usb2 for AM437x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index d54f24b..80ba7f0 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -31,6 +31,9 @@
#include linux/phy/phy.h
#include linux/of_platform.h
+#define USB2PHY_DISCON_BYP_LATCH (1 31)
+#define USB2PHY_ANA_CONFIG1 0x4c
+
/**
* omap_usb2_set_comparator - links the comparator present in the sytem with
*this phy
@@ -138,7 +141,30 @@ static int omap_usb_power_on(struct phy *x)
return 0;
}
+static int omap_usb_init(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+ u32 val;
+
+ if (phy-flags OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+ /*
+*
+* Reduce the sensitivity of internal PHY by enabling the
+* DISCON_BYP_LATCH of the USB2PHY_ANA_CONFIG1 register. This
+* resolves issues with certain devices which can otherwise
+* be prone to false disconnects.
+*
+*/
+ val = omap_usb_readl(phy-phy_base, USB2PHY_ANA_CONFIG1);
+ val |= USB2PHY_DISCON_BYP_LATCH;
+ omap_usb_writel(phy-phy_base, USB2PHY_ANA_CONFIG1, val);
+ }
+
+ return 0;
+}
+
static struct phy_ops ops = {
+ .init = omap_usb_init,
.power_on = omap_usb_power_on,
.power_off = omap_usb_power_off,
.owner = THIS_MODULE,
@@ -150,6 +176,11 @@ static const struct usb_phy_data omap_usb2_data = {
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
};
+static const struct usb_phy_data dra7x_usb2_data = {
+ .label = dra7x_usb2,
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+};
+
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
@@ -161,6 +192,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.data = omap_usb2_data,
},
{
+ .compatible = ti,dra7x-usb2,
+ .data = dra7x_usb2_data,
+ },
+ {
.compatible = ti,am437x-usb2,
.data = am437x_usb2_data,
},
@@ -173,6 +208,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
{
struct omap_usb *phy;
struct phy *generic_phy;
+ struct resource *res;
struct phy_provider *phy_provider;
struct usb_otg *otg;
struct device_node *node = pdev-dev.of_node;
@@ -208,6 +244,18 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-phy.otg = otg;
phy-phy.type= USB_PHY_TYPE_USB2;
+ if (phy_data-flags OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(pdev-dev, memory resource not available\n);
+ return -ENODEV;
+ }
You can remove the error check here and..
+ phy-phy_base = devm_request_and_ioremap(pdev-dev, res);
use devm_ioremap_resource instead.
Thanks
Kishon
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Re: [PATCH v7 0/4] phy: Add new Exynos USB 2.0 PHY driver
Hi, On Tuesday 04 March 2014 08:53 PM, Kamil Debski wrote: Hi, This is the seventh version of this patchset. First and most significant change is that this patchset includes only patches touching the Generic PHY Framework. Patches to the USB controllers were stripped as they require additional work. S5PV210 support is also omitted - it requires more testing. Thank you to everyone who joined the discussion, reviewed the patched and contributed to making the code and consequently the Linux Kernel better. Can you refresh your patches on git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy.git next It's not applying cleanly. While at that pls fix these checkpatch errors/warnings on patch 3. ERROR: code indent should use tabs where possible #854: FILE: drivers/phy/phy-exynos4x12-usb2.c:233: +^I^I^IEXYNOS_4x12_MODE_SWITCH_OFFSET,$ CHECK: Alignment should match open parenthesis #854: FILE: drivers/phy/phy-exynos4x12-usb2.c:233: + regmap_update_bits(drv-reg_sys, + EXYNOS_4x12_MODE_SWITCH_OFFSET, ERROR: code indent should use tabs where possible #855: FILE: drivers/phy/phy-exynos4x12-usb2.c:234: +^I^I^IEXYNOS_4x12_MODE_SWITCH_MASK,$ CHECK: Alignment should match open parenthesis #986: FILE: drivers/phy/phy-samsung-usb2.c:29: + dev_dbg(drv-dev, Request to power_on \%s\ usb phy\n, + inst-cfg-label); CHECK: Alignment should match open parenthesis #1014: FILE: drivers/phy/phy-samsung-usb2.c:57: + dev_dbg(drv-dev, Request to power_off \%s\ usb phy\n, + inst-cfg-label); CHECK: Alignment should match open parenthesis #1146: FILE: drivers/phy/phy-samsung-usb2.c:189: + dev_err(drv-dev, Failed to create usb2_phy \%s\\n, + And on patch 4 CHECK: Alignment should match open parenthesis #350: FILE: drivers/phy/phy-exynos5250-usb2.c:212: + regmap_update_bits(drv-reg_sys, + EXYNOS_5250_MODE_SWITCH_OFFSET, -Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v5 6/6] arm/dts: added dt properties to adapt to the new phy framwork
Tony/Benoit,
On Monday 03 March 2014 05:08 PM, Kishon Vijay Abraham I wrote:
Added device tree bindings for dwc3, usb2 and usb3 PHYs. The documentation
of these can be found at Documentation/devicetree/bindings/phy/phy-bindings.txt
and Documentation/devicetree/bindings/phy/ti-phy.txt.
Can this patch be queued for 3.15 merge window?
Thanks
Kishon
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
arch/arm/boot/dts/omap5.dtsi |5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index a72813a..1c68558 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -732,7 +732,8 @@
compatible = snps,dwc3;
reg = 0x4a03 0x1;
interrupts = GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH;
- usb-phy = usb2_phy, usb3_phy;
+ phys = usb2_phy, usb3_phy;
+ phy-names = usb2-phy, usb3-phy;
dr_mode = peripheral;
tx-fifo-resize;
};
@@ -749,6 +750,7 @@
compatible = ti,omap-usb2;
reg = 0x4a084000 0x7c;
ctrl-module = omap_control_usb2phy;
+ #phy-cells = 0;
};
usb3_phy: usb3phy@4a084400 {
@@ -758,6 +760,7 @@
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb3phy;
+ #phy-cells = 0;
};
};
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Re: [PATCH v8 3/4] phy: Add new Exynos USB 2.0 PHY driver
Kamil,
On Wednesday 05 March 2014 07:48 PM, Kamil Debski wrote:
Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Pls fix these errors which I get while applying your patch.
Applying: phy: Add new Exynos USB 2.0 PHY driver
/home/kishon/repos/linux-phy/.git/rebase-apply/patch:534: new blank line
at EOF.
+
/home/kishon/repos/linux-phy/.git/rebase-apply/patch:869: new blank line
at EOF.
+
/home/kishon/repos/linux-phy/.git/rebase-apply/patch:1098: new blank
line at EOF.
+
/home/kishon/repos/linux-phy/.git/rebase-apply/patch:1171: new blank
line at EOF.
+
warning: 4 lines add whitespace errors.
Thanks
Kishon
Signed-off-by: Kamil Debski k.deb...@samsung.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 53
Documentation/phy/samsung-usb2.txt | 134
drivers/phy/Kconfig| 29 ++
drivers/phy/Makefile |3 +
drivers/phy/phy-exynos4210-usb2.c | 262
drivers/phy/phy-exynos4x12-usb2.c | 329
drivers/phy/phy-samsung-usb2.c | 223 +
drivers/phy/phy-samsung-usb2.h | 67
8 files changed, 1100 insertions(+)
create mode 100644 Documentation/phy/samsung-usb2.txt
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4x12-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..bf955ab 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,56 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usb2-phy
+ - samsung,exynos4x12-usb2-phy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system
registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clock is required by the phy module, used as a gate
+ - the ref clock is used to get the rate of the clock provided to the
+ PHY module
+
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
+and Exynos 4212) it is as follows:
+ 0 - USB device (device),
+ 1 - USB host (host),
+ 2 - HSIC0 (hsic0),
+ 3 - HSIC1 (hsic1),
+
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+usbphy: phy@125b {
+ compatible = samsung,exynos4x12-usb2-phy;
+ reg = 0x125b 0x100;
+ clocks = clock 305, clock 2;
+ clock-names = phy, ref;
+ status = okay;
+ #phy-cells = 1;
+ samsung,sysreg-phandle = sys_reg;
+ samsung,pmureg-phandle = pmu_reg;
+};
+
+Then the PHY can be used in other nodes such as:
+
+phy-consumer@1234 {
+ phys = usbphy 2;
+ phy-names = phy;
+};
+
+Refer to DT bindings documentation of particular PHY consumer devices for more
+information about required PHYs and the way of specification.
diff --git a/Documentation/phy/samsung-usb2.txt
b/Documentation/phy/samsung-usb2.txt
new file mode 100644
index 000..0c8e260
--- /dev/null
+++ b/Documentation/phy/samsung-usb2.txt
@@ -0,0 +1,134 @@
+.--+
+| Samsung USB 2.0 PHY adaptation layer |
++-+'
+
+| 1. Description
++
+
+The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
+among many SoCs. In spite of the similarities it proved difficult to
+create a one driver that would fit all these PHY controllers. Often
+the differences were minor and were found in particular bits of the
+registers of the PHY. In some rare cases the order of register writes or
+the PHY powering up process had to be altered. This adaptation layer is
+a compromise between having separate drivers and having a single driver
+with added support for many
Re: [PATCH v8 4/4] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
Hi, On Wednesday 05 March 2014 07:48 PM, Kamil Debski wrote: Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Pls fix this error too.. Applying: phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver /home/kishon/repos/linux-phy/.git/rebase-apply/patch:462: new blank line at EOF. + warning: 1 line adds whitespace errors. Thanks Kishon Signed-off-by: Kamil Debski k.deb...@samsung.com --- .../devicetree/bindings/phy/samsung-phy.txt|1 + drivers/phy/Kconfig| 11 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5250-usb2.c | 405 drivers/phy/phy-samsung-usb2.c |6 + drivers/phy/phy-samsung-usb2.h |1 + 6 files changed, 425 insertions(+) create mode 100644 drivers/phy/phy-exynos5250-usb2.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index bf955ab..28f9edb 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -28,6 +28,7 @@ Required properties: - compatible : should be one of the listed compatibles: - samsung,exynos4210-usb2-phy - samsung,exynos4x12-usb2-phy + - samsung,exynos5250-usb2-phy - reg : a list of registers used by phy driver - first and obligatory is the location of phy modules registers - samsung,sysreg-phandle - handle to syscon used to control the system registers diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index fc5a44a..c206e25 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -125,4 +125,15 @@ config PHY_EXYNOS4X12_USB2 Samsung USB 2.0 PHY driver is enabled and means that support for this particular SoC is compiled in the driver. In case of Exynos 4x12 four phys are available - device, host, HSIC0 and HSIC1. + +config PHY_EXYNOS5250_USB2 + bool Support for Exynos 5250 + depends on PHY_SAMSUNG_USB2 + depends on SOC_EXYNOS5250 + help + Enable USB PHY support for Exynos 5250. This option requires that + Samsung USB 2.0 PHY driver is enabled and means that support for this + particular SoC is compiled in the driver. In case of Exynos 5250 four + phys are available - device, host, HSIC0 and HSIC. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 0ea36ff..f76c239 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -14,3 +14,4 @@ obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o obj-$(CONFIG_PHY_SAMSUNG_USB2)+= phy-samsung-usb2.o obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o +obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c new file mode 100644 index 000..877994e --- /dev/null +++ b/drivers/phy/phy-exynos5250-usb2.c @@ -0,0 +1,405 @@ +/* + * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Kamil Debski k.deb...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/delay.h +#include linux/io.h +#include linux/phy/phy.h +#include linux/regmap.h +#include phy-samsung-usb2.h + +/* Exynos USB PHY registers */ +#define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0 +#define EXYNOS_5250_REFCLKSEL_XO 0x1 +#define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2 + +#define EXYNOS_5250_FSEL_9MHZ6 0x0 +#define EXYNOS_5250_FSEL_10MHZ 0x1 +#define EXYNOS_5250_FSEL_12MHZ 0x2 +#define EXYNOS_5250_FSEL_19MHZ20x3 +#define EXYNOS_5250_FSEL_20MHZ 0x4 +#define EXYNOS_5250_FSEL_24MHZ 0x5 +#define EXYNOS_5250_FSEL_50MHZ 0x7 + +/* Normal host */ +#define EXYNOS_5250_HOSTPHYCTRL0 0x0 + +#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31) +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19 +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK\ + (0x3 EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT16 +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \ + (0x7 EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNINBIT(11) +#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10) +#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK(0x3 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL(0x0 7) +#define
Re: [PATCH v5 2/6] usb: dwc3: adapt dwc3 core to use Generic PHY Framework
Roger,
On Wednesday 05 March 2014 08:13 PM, Roger Quadros wrote:
Hi Kishon,
On 03/03/2014 01:38 PM, Kishon Vijay Abraham I wrote:
Adapted dwc3 core to use the Generic PHY Framework. So for init, exit,
power_on and power_off the following APIs are used phy_init(), phy_exit(),
phy_power_on() and phy_power_off().
However using the old USB phy library wont be removed till the PHYs of all
other SoC's using dwc3 core is adapted to the Generic PHY Framework.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/dwc3.txt |6 +-
drivers/usb/dwc3/core.c| 86 +---
drivers/usb/dwc3/core.h|7 ++
3 files changed, 89 insertions(+), 10 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/dwc3.txt
b/Documentation/devicetree/bindings/usb/dwc3.txt
index e807635..471366d 100644
--- a/Documentation/devicetree/bindings/usb/dwc3.txt
+++ b/Documentation/devicetree/bindings/usb/dwc3.txt
@@ -6,11 +6,13 @@ Required properties:
- compatible: must be snps,dwc3
- reg : Address and length of the register set for the device
- interrupts: Interrupts used by the dwc3 controller.
+
+Optional properties:
- usb-phy : array of phandle for the PHY device. The first element
in the array is expected to be a handle to the USB2/HS PHY and
the second element is expected to be a handle to the USB3/SS PHY
-
-Optional properties:
+ - phys: from the *Generic PHY* bindings
+ - phy-names: from the *Generic PHY* bindings
- tx-fifo-resize: determines if the FIFO *has* to be reallocated.
This is usually a subnode to DWC3 glue to which it is connected.
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 225a4d6..497234a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -61,9 +61,10 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
* dwc3_core_soft_reset - Issues core soft reset and PHY reset
* @dwc: pointer to our context structure
*/
-static void dwc3_core_soft_reset(struct dwc3 *dwc)
+static int dwc3_core_soft_reset(struct dwc3 *dwc)
{
u32 reg;
+ int ret;
/* Before Resetting PHY, put Core in Reset */
reg = dwc3_readl(dwc-regs, DWC3_GCTL);
@@ -82,6 +83,15 @@ static void dwc3_core_soft_reset(struct dwc3 *dwc)
usb_phy_init(dwc-usb2_phy);
usb_phy_init(dwc-usb3_phy);
+ ret = phy_init(dwc-usb2_generic_phy);
you need to check if dwc-usb?_generic_phy is not NULL before using any of the
PHY APIs
throughout this patch.
Recently a patch to allow NULL in phy APIs was added to support optional
PHYs.
commit 04c2facad8fee66c981a51852806d8923336f362
Author: Andrew Lunn and...@lunn.ch
Date: Tue Feb 4 18:33:11 2014 +0100
drivers: phy: Make NULL a valid phy reference
Thanks
Kishon
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Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
On Thursday 06 March 2014 01:56 PM, Anton Tikhomirov wrote:
Hi Kamil,
...
+| 3. Supporting SoCs
++
+
+To support a new SoC a new file should be added to the drivers/phy
+directory. Each SoC's configuration is stored in an instance of the
+struct samsung_usb2_phy_config.
+
+struct samsung_usb2_phy_config {
+ const struct samsung_usb2_common_phy *phys;
+ unsigned int num_phys;
+ bool has_mode_switch;
You missed rate_to_clk here.
+};
+
...
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-samsung-
usb2.c
new file mode 100644
index 000..c3b7719
--- /dev/null
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -0,0 +1,222 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski k.deb...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include phy-samsung-usb2.h
+
+static int samsung_usb2_phy_power_on(struct phy *phy)
+{
+ struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
+ struct samsung_usb2_phy_driver *drv = inst-drv;
+ int ret;
+
+ dev_dbg(drv-dev, Request to power_on \%s\ usb phy\n,
+ inst-cfg-label);
+ ret = clk_prepare_enable(drv-clk);
clk_prepare_enable() can sleep, and therefore doesn't allow
samusng_usb2_phy_power_on() to be used in atomic context
(e.g. inside spin_lock-ed area), what sometimes may be desirable.
What about to prepare clock in probe, and just enable it here
(note: clk_enable() doesn't sleep).
The PHY power-on callback is anyway called with mutex held, so I guess
it's fine to have clk_prepare_enable() here.
Thanks
Kishon
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Re: [PATCH v13 2/3] PHY: add APM X-Gene SoC 15Gbps Multi-purpose PHY driver
Hi,
On Thursday 06 March 2014 04:13 AM, Loc Ho wrote:
This patch adds support for the APM X-Gene SoC 15Gbps Multi-purpose PHY.
This is the physical layer interface for the corresponding host
controller. Currently, only external clock and Gen3 SATA mode
are supported.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
---
drivers/phy/Kconfig |7 +
drivers/phy/Makefile|2 +
drivers/phy/phy-xgene.c | 1756 +++
3 files changed, 1765 insertions(+), 0 deletions(-)
create mode 100644 drivers/phy/phy-xgene.c
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index afa2354..221a1b7 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -64,4 +64,11 @@ config BCM_KONA_USB2_PHY
help
Enable this to support the Broadcom Kona USB 2.0 PHY.
+config PHY_XGENE
+ tristate APM X-Gene 15Gbps PHY support
+ depends on HAS_IOMEM OF (ARM64 || COMPILE_TEST)
+ select GENERIC_PHY
+ help
+ This option enables support for APM X-Gene SoC multi-purpose PHY.
+
endmenu
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..dee70f4 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -9,3 +9,5 @@ obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) +=
phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
+obj-$(CONFIG_PHY_XGENE)+= phy-xgene.o
+
.
.
snip
.
.
+ int i;
+
+ rc = xgene_phy_hw_initialize(ctx, CLK_EXT_DIFF, SSC_DISABLE);
+ if (rc) {
+ dev_err(ctx-dev, PHY initialize failed %d\n, rc);
+ return rc;
+ }
+
+ /* Setup clock properly after PHY configuration */
+ if (!IS_ERR(ctx-clk)) {
+ /* HW requires an toggle of the clock */
+ clk_prepare_enable(ctx-clk);
+ clk_disable_unprepare(ctx-clk);
+ clk_prepare_enable(ctx-clk);
+ }
+
+ /* Compute average value */
+ for (i = 0; i MAX_LANE; i++)
+ xgene_phy_gen_avg_val(ctx, i);
+
+ dev_dbg(ctx-dev, PHY initialized\n);
+ return 0;
+}
+
+static const struct phy_ops xgene_phy_ops = {
+ .init = xgene_phy_hw_init,
+ .owner = THIS_MODULE,
+};
+
+static struct phy *xgene_phy_xlate(struct device *dev,
+ struct of_phandle_args *args)
+{
+ struct xgene_phy_ctx *ctx = dev_get_drvdata(dev);
+
+ if (args-args_count 0) {
+ if (args-args[0] = MODE_MAX)
+ return NULL;
Are you sure you want to return NULL instead of error? NULL is
considered a valid value for optional PHYs.
+ ctx-mode = args-args[0];
+ }
I think it doesn't make sense to return the phy without the 'mode'. So
we should report error here too.
+ return ctx-phy;
+}
+
+static void xgene_phy_get_param(struct platform_device *pdev,
+ const char *name, u32 *buffer,
+ int count, u32 *default_val,
+ u32 conv_factor)
+{
+ int i;
+
+ if (!of_property_read_u32_array(pdev-dev.of_node, name, buffer,
+ count)) {
+ for (i = 0; i count; i++)
+ buffer[i] /= conv_factor;
+ return;
+ }
+ /* Does not exist, load default */
+ for (i = 0; i count; i++)
+ buffer[i] = default_val[i % 3];
+}
+
+static int xgene_phy_probe(struct platform_device *pdev)
+{
+ struct phy_provider *phy_provider;
+ struct xgene_phy_ctx *ctx;
+ struct resource *res;
+ int rc = 0;
+ u32 default_spd[] = DEFAULT_SATA_SPD_SEL;
+ u32 default_txboost_gain[] = DEFAULT_SATA_TXBOOST_GAIN;
+ u32 default_txeye_direction[] = DEFAULT_SATA_TXEYEDIRECTION;
+ u32 default_txeye_tuning[] = DEFAULT_SATA_TXEYETUNING;
+ u32 default_txamp[] = DEFAULT_SATA_TXAMP;
+ u32 default_txcn1[] = DEFAULT_SATA_TXCN1;
+ u32 default_txcn2[] = DEFAULT_SATA_TXCN2;
+ u32 default_txcp1[] = DEFAULT_SATA_TXCP1;
+ int i;
+
+ ctx = devm_kzalloc(pdev-dev, sizeof(*ctx), GFP_KERNEL);
+ if (!ctx) {
+ dev_err(pdev-dev, can't allocate PHY context\n);
remove dev_err here.. kzalloc will do that for you..
+ return -ENOMEM;
+ }
+ ctx-dev = pdev-dev;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(pdev-dev, no PHY resource address\n);
same here.. you don't have to even check for return value of res.
ioremap_resource will take care of that.
+ rc = -EINVAL;
+ goto error;
+ }
+ ctx-sds_base
Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
On Thursday 06 March 2014 02:22 PM, Anton Tikhomirov wrote:
Hello,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
On Thursday 06 March 2014 01:56 PM, Anton Tikhomirov wrote:
Hi Kamil,
...
+| 3. Supporting SoCs
++
+
+To support a new SoC a new file should be added to the drivers/phy
+directory. Each SoC's configuration is stored in an instance of the
+struct samsung_usb2_phy_config.
+
+struct samsung_usb2_phy_config {
+ const struct samsung_usb2_common_phy *phys;
+ unsigned int num_phys;
+ bool has_mode_switch;
You missed rate_to_clk here.
+};
+
...
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-
samsung-
usb2.c
new file mode 100644
index 000..c3b7719
--- /dev/null
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -0,0 +1,222 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski k.deb...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License version 2
as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include phy-samsung-usb2.h
+
+static int samsung_usb2_phy_power_on(struct phy *phy)
+{
+ struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
+ struct samsung_usb2_phy_driver *drv = inst-drv;
+ int ret;
+
+ dev_dbg(drv-dev, Request to power_on \%s\ usb phy\n,
+ inst-cfg-label);
+ ret = clk_prepare_enable(drv-clk);
clk_prepare_enable() can sleep, and therefore doesn't allow
samusng_usb2_phy_power_on() to be used in atomic context
(e.g. inside spin_lock-ed area), what sometimes may be desirable.
What about to prepare clock in probe, and just enable it here
(note: clk_enable() doesn't sleep).
The PHY power-on callback is anyway called with mutex held, so I guess
it's fine to have clk_prepare_enable() here.
If we rely totally on generic PHY functions such as phy_power_on()
and friends, why do we need to use locking in callbacks at all.
Didn't get you.. We don't want to invoke power_on when init is getting
executed or you don't want power on or power off to get executed
simultaneously right? So we need to protect it.
Cheers
Kishon
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Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
On Thursday 06 March 2014 02:49 PM, Anton Tikhomirov wrote:
Hi,
Subject: RE: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
On Thursday 06 March 2014 02:22 PM, Anton Tikhomirov wrote:
Hello,
Subject: Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
On Thursday 06 March 2014 01:56 PM, Anton Tikhomirov wrote:
Hi Kamil,
...
+| 3. Supporting SoCs
++
+
+To support a new SoC a new file should be added to the
drivers/phy
+directory. Each SoC's configuration is stored in an instance of
the
+struct samsung_usb2_phy_config.
+
+struct samsung_usb2_phy_config {
+ const struct samsung_usb2_common_phy *phys;
+ unsigned int num_phys;
+ bool has_mode_switch;
You missed rate_to_clk here.
+};
+
...
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-
samsung-
usb2.c
new file mode 100644
index 000..c3b7719
--- /dev/null
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -0,0 +1,222 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski k.deb...@samsung.com
+ *
+ * This program is free software; you can redistribute it
and/or
modify
+ * it under the terms of the GNU General Public License version
2
as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include phy-samsung-usb2.h
+
+static int samsung_usb2_phy_power_on(struct phy *phy)
+{
+ struct samsung_usb2_phy_instance *inst =
phy_get_drvdata(phy);
+ struct samsung_usb2_phy_driver *drv = inst-drv;
+ int ret;
+
+ dev_dbg(drv-dev, Request to power_on \%s\ usb phy\n,
+ inst-cfg-label);
+ ret = clk_prepare_enable(drv-clk);
clk_prepare_enable() can sleep, and therefore doesn't allow
samusng_usb2_phy_power_on() to be used in atomic context
(e.g. inside spin_lock-ed area), what sometimes may be desirable.
What about to prepare clock in probe, and just enable it here
(note: clk_enable() doesn't sleep).
The PHY power-on callback is anyway called with mutex held, so I
guess
it's fine to have clk_prepare_enable() here.
If we rely totally on generic PHY functions such as phy_power_on()
and friends, why do we need to use locking in callbacks at all.
Didn't get you.. We don't want to invoke power_on when init is
getting
executed or you don't want power on or power off to get executed
simultaneously right? So we need to protect it.
I mean callbacks such as samsung_usb2_phy_power_on() which uses
spin_lock.
It's already protected by mutex in phy_power_on().
Well... phy_power_on() uses mutex to protect power_on() callback.
power_on() is samsung_usb2_phy_power_on() in our case.
samsung_usb2_phy_power_on() uses spinlock.
My question is why do we need to use spinlock _inside_ callback
if it is already protected by mutex.
It is needed when the same PHY provider implements multiple PHYs.
phy-core can protect phy-ops of same PHY. However if the PHY provider
implements multiple PHYs, phy-core won't be able to protect.
Cheers
Kishon
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Re: [PATCH v5 3/6] drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework
On Monday 03 March 2014 05:08 PM, Kishon Vijay Abraham I wrote:
Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3
driver in drivers/usb/phy to drivers/phy and also renamed the file to
phy-ti-pipe3 since this same driver will be used for SATA PHY and
PCIE PHY.
merged 3rd, 4th and 5th patch of this series to linux-phy next.
Thanks
Kishon
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
.../phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} | 240
drivers/usb/phy/Kconfig| 11 -
drivers/usb/phy/Makefile |1 -
5 files changed, 158 insertions(+), 106 deletions(-)
rename drivers/{usb/phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} (54%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index c7a551c..e3ec7d1 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -40,6 +40,17 @@ config OMAP_USB2
The USB OTG controller communicates with the comparator using this
driver.
+config TI_PIPE3
+ tristate TI PIPE3 PHY Driver
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ select GENERIC_PHY
+ select OMAP_CONTROL_USB
+ help
+ Enable this to support the PIPE3 PHY that is part of TI SOCs. This
+ driver takes care of all the PHY functionality apart from comparator.
+ This driver interacts with the OMAP Control PHY Driver to power
+ on/off the PHY.
+
config TWL4030_USB
tristate TWL4030 USB Transceiver Driver
depends on TWL4030_CORE REGULATOR_TWL4030 USB_MUSB_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index b57c253..32e3f94 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,4 +8,5 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
+obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/phy/phy-ti-pipe3.c
similarity index 54%
rename from drivers/usb/phy/phy-omap-usb3.c
rename to drivers/phy/phy-ti-pipe3.c
index 0c6ba29..67b189d 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -1,5 +1,5 @@
/*
- * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
+ * phy-ti-pipe3 - PIPE3 PHY driver.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -19,10 +19,11 @@
#include linux/module.h
#include linux/platform_device.h
#include linux/slab.h
-#include linux/usb/omap_usb.h
+#include linux/phy/phy.h
#include linux/of.h
#include linux/clk.h
#include linux/err.h
+#include linux/io.h
#include linux/pm_runtime.h
#include linux/delay.h
#include linux/usb/omap_control_usb.h
@@ -52,17 +53,34 @@
/*
* This is an Empirical value that works, need to confirm the actual
- * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
- * to be correctly reflected in the USB3PHY_PLL_STATUS register.
+ * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
+ * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
# define PLL_IDLE_TIME 100;
-struct usb_dpll_map {
+struct pipe3_dpll_params {
+ u16 m;
+ u8 n;
+ u8 freq:3;
+ u8 sd;
+ u32 mf;
+};
+
+struct ti_pipe3 {
+ void __iomem*pll_ctrl_base;
+ struct device *dev;
+ struct device *control_dev;
+ struct clk *wkupclk;
+ struct clk *sys_clk;
+ struct clk *optclk;
+};
+
+struct pipe3_dpll_map {
unsigned long rate;
- struct usb_dpll_params params;
+ struct pipe3_dpll_params params;
};
-static struct usb_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
@@ -71,7 +89,18 @@ static struct usb_dpll_map dpll_map[] = {
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
};
-static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
+static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+ return __raw_readl(addr + offset);
+}
+
+static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
+ u32 data)
+{
+ __raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
{
int i
Re: [PATCH v9 3/4] phy: Add new Exynos USB 2.0 PHY driver
Hi,
On Thursday 06 March 2014 03:54 PM, Kamil Debski wrote:
Hi Anton, Kishon,
From: Anton Tikhomirov [mailto:av.tikhomi...@samsung.com]
Sent: Thursday, March 06, 2014 9:26 AM
Hi Kamil,
...
+| 3. Supporting SoCs
++
+
+To support a new SoC a new file should be added to the drivers/phy
+directory. Each SoC's configuration is stored in an instance of the
+struct samsung_usb2_phy_config.
+
+struct samsung_usb2_phy_config {
+ const struct samsung_usb2_common_phy *phys;
+ unsigned int num_phys;
+ bool has_mode_switch;
You missed rate_to_clk here.
Thank you for spotting this.
Kishon: I am sorry that this omission was made. I am happy to send an
updated patchset. However, I want to give some time for any additional
comments. Do you think that we have for this? Is today evening ok with you?
Would be great if you can send the patch in 2-3 hrs.. I'd like to give
enough time for auto build to detect any errors.
+};
+
...
diff --git a/drivers/phy/phy-samsung-usb2.c b/drivers/phy/phy-
samsung-
usb2.c new file mode 100644 index 000..c3b7719
--- /dev/null
+++ b/drivers/phy/phy-samsung-usb2.c
@@ -0,0 +1,222 @@
+/*
+ * Samsung SoC USB 1.1/2.0 PHY driver
+ *
+ * Copyright (C) 2013 Samsung Electronics Co., Ltd.
+ * Author: Kamil Debski k.deb...@samsung.com
+ *
+ * This program is free software; you can redistribute it and/or
modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include linux/clk.h
+#include linux/mfd/syscon.h
+#include linux/module.h
+#include linux/of.h
+#include linux/of_address.h
+#include linux/phy/phy.h
+#include linux/platform_device.h
+#include linux/spinlock.h
+#include phy-samsung-usb2.h
+
+static int samsung_usb2_phy_power_on(struct phy *phy) {
+ struct samsung_usb2_phy_instance *inst = phy_get_drvdata(phy);
+ struct samsung_usb2_phy_driver *drv = inst-drv;
+ int ret;
+
+ dev_dbg(drv-dev, Request to power_on \%s\ usb phy\n,
+ inst-cfg-label);
+ ret = clk_prepare_enable(drv-clk);
clk_prepare_enable() can sleep, and therefore doesn't allow
samusng_usb2_phy_power_on() to be used in atomic context (e.g. inside
spin_lock-ed area), what sometimes may be desirable.
What about to prepare clock in probe, and just enable it here
(note: clk_enable() doesn't sleep).
From the onward discussion between you and Kishon, I draw the conclusion
that this change is not necessary. Right?
right.
Cheers
Kishon
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Re: [PATCH 1/3] phy: omap-usb2: Adapt phy-omap-usb2 for AM437x
George,
On Monday 03 March 2014 03:40 PM, George Cherian wrote:
Adapt phy-omap-usb2 driver for AM437x.
- Add new comaptible ti,am437x-usb2 for AM437x
- Pass proper data to differentiate AM437x and others.
- AM437x doesnot support set_vbus and start_srp.
- Also update the Documentation to add new compatible.
Signed-off-by: George Cherian george.cher...@ti.com
---
Documentation/devicetree/bindings/usb/usb-phy.txt | 4 +-
drivers/phy/phy-omap-usb2.c | 49 +--
include/linux/usb/omap_usb.h | 9 +
3 files changed, 49 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt
b/Documentation/devicetree/bindings/usb/usb-phy.txt
index c0245c8..b3fa409 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -3,7 +3,9 @@ USB PHY
OMAP USB2 PHY
Required properties:
- - compatible: Should be ti,omap-usb2
+ - compatible: Should be either of
+ * ti,omap-usb2 for OMAP4, OMAP5, DRA7
+ * ti,am437x-usb2 for AM437x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 7699752..d54f24b 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -144,6 +144,31 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct usb_phy_data omap_usb2_data = {
+ .label = omap_usb2,
+ .flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+};
+
+static const struct usb_phy_data am437x_usb2_data = {
+ .label = am437x_usb2,
+ .flags = 0,
+};
+
+static const struct of_device_id omap_usb2_id_table[] = {
+ {
+ .compatible = ti,omap-usb2,
+ .data = omap_usb2_data,
+ },
+ {
+ .compatible = ti,am437x-usb2,
+ .data = am437x_usb2_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#endif
+
static int omap_usb2_probe(struct platform_device *pdev)
{
struct omap_usb *phy;
@@ -153,10 +178,16 @@ static int omap_usb2_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+ const struct of_device_id *of_id;
+ struct usb_phy_data *phy_data;
+
+ of_id = of_match_device(of_match_ptr(omap_usb2_id_table), pdev-dev);
- if (!node)
+ if (!of_id)
return -EINVAL;
+ phy_data = (struct usb_phy_data *)of_id-data;
+
phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
dev_err(pdev-dev, unable to allocate memory for USB2 PHY\n);
@@ -172,7 +203,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-dev = pdev-dev;
phy-phy.dev = phy-dev;
- phy-phy.label = omap-usb2;
+ phy-phy.label = phy_data-label;
phy-phy.set_suspend = omap_usb2_suspend;
phy-phy.otg = otg;
phy-phy.type= USB_PHY_TYPE_USB2;
@@ -196,8 +227,10 @@ static int omap_usb2_probe(struct platform_device *pdev)
otg-set_host= omap_usb_set_host;
otg-set_peripheral = omap_usb_set_peripheral;
- otg-set_vbus= omap_usb_set_vbus;
- otg-start_srp = omap_usb_start_srp;
+ if (phy_data-flags OMAP_USB2_HAS_SET_VBUS)
+ otg-set_vbus= omap_usb_set_vbus;
+ if (phy_data-flags OMAP_USB2_HAS_START_SRP)
+ otg-start_srp = omap_usb_start_srp;
otg-phy = phy-phy;
platform_set_drvdata(pdev, phy);
@@ -297,14 +330,6 @@ static const struct dev_pm_ops omap_usb2_pm_ops = {
#define DEV_PM_OPS NULL
#endif
-#ifdef CONFIG_OF
-static const struct of_device_id omap_usb2_id_table[] = {
- { .compatible = ti,omap-usb2 },
- {}
-};
-MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
-#endif
-
static struct platform_driver omap_usb2_driver = {
.probe = omap_usb2_probe,
.remove = omap_usb2_remove,
diff --git a/include/linux/usb/omap_usb.h b/include/linux/usb/omap_usb.h
index 6ae2936..034161d 100644
--- a/include/linux/usb/omap_usb.h
+++ b/include/linux/usb/omap_usb.h
@@ -42,6 +42,15 @@ struct omap_usb {
u8 is_suspended:1;
};
+struct usb_phy_data {
+ const char *label;
+ u32 flags;
u8 should be sufficient no?
Can you also refresh the patch on linux-phy next?
Thanks
Kishon
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Re: [PATCH v2 01/13] phy: rename struct omap_control_usb to struct omap_control_phy
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
From: Kishon Vijay Abraham I kis...@ti.com
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
---
drivers/phy/Kconfig| 14 +-
drivers/phy/Makefile | 1 +
drivers/{usb = }/phy/phy-omap-control.c | 165 +++--
drivers/phy/phy-omap-usb2.c| 8 +-
drivers/phy/phy-ti-pipe3.c | 8 +-
drivers/usb/musb/omap2430.c| 2 +-
drivers/usb/phy/Kconfig| 10 --
drivers/usb/phy/Makefile | 1 -
Hope you are fine with the changes in drivers/usb/? Can you give your
Acked-by?
Regards
Kishon
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 ++---
9 files changed, 123 insertions(+), 122 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (55%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b607d7..fe8c009 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -31,12 +31,22 @@ config PHY_MVEBU_SATA
depends on OF
select GENERIC_PHY
+config OMAP_CONTROL_PHY
+ tristate OMAP CONTROL PHY Driver
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate OMAP USB2 PHY Driver
depends on ARCH_OMAP2PLUS
depends on USB_PHY
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -47,7 +57,7 @@ config TI_PIPE3
tristate TI PIPE3 PHY Driver
depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ecf0d3f..8da05a8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO) += phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2) += phy-omap-usb2.o
obj-$(CONFIG_TI_PIPE3)+= phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
similarity index 55%
rename from drivers/usb/phy/phy-omap-control.c
rename to drivers/phy/phy-omap-control.c
index e725318..17fc200 100644
--- a/drivers/usb/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -1,5 +1,5 @@
/*
- * omap-control-usb.c - The USB part of control module.
+ * omap-control-phy.c - The PHY part of control module.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -24,36 +24,36 @@
#include linux/err.h
#include linux/io.h
#include linux/clk.h
-#include linux/usb/omap_control_usb.h
+#include linux/phy/omap_control_phy.h
/**
- * omap_control_usb_phy_power - power on/off the phy using control module reg
+ * omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
*/
-void omap_control_usb_phy_power(struct device *dev, int on)
+void omap_control_phy_power(struct device *dev, int on)
{
u32 val;
unsigned long rate;
- struct omap_control_usb *control_usb;
+ struct omap_control_phy *control_phy;
if (IS_ERR(dev) || !dev) {
pr_err(%s: invalid device\n, __func__);
return;
}
- control_usb = dev_get_drvdata(dev);
- if (!control_usb) {
- dev_err(dev, %s: invalid control usb device\n, __func__
Re: [PATCH v2 02/13] phy: omap-control: Update DT binding information
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
Move omap-control binding information to the right location.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 25 ++
This patch is dependent on
Documentation: dt bindings: move ..usb/usb-phy.txt to
..phy/ti-phy.txt
which got merged in your tree. So can you take this patch also?
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Regards
Kishon
Documentation/devicetree/bindings/usb/omap-usb.txt | 24 -
2 files changed, 25 insertions(+), 24 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index f671163..5c5b1b0 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -1,5 +1,30 @@
TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
+OMAP CONTROL PHY
+
+Required properties:
+ - compatible: Should be one of
+ ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
+ ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
+e.g. USB2_PHY on OMAP5.
+ ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
+e.g. USB3 PHY and SATA PHY on OMAP5.
+ ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+DRA7 platform.
+ ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+AM437 platform.
+ - reg : Address and length of the register set for the device. It contains
+ the address of otghs_control for control-phy-otghs or power register
+ for other types.
+ - reg-names: should be otghs_control control-phy-otghs and power for
+ other types.
+
+omap_control_usb: omap-control-usb@4a002300 {
+compatible = ti,control-phy-otghs;
+reg = 0x4a00233c 0x4;
+reg-names = otghs_control;
+};
+
OMAP USB2 PHY
Required properties:
diff --git a/Documentation/devicetree/bindings/usb/omap-usb.txt
b/Documentation/devicetree/bindings/usb/omap-usb.txt
index c495135..38b2fae 100644
--- a/Documentation/devicetree/bindings/usb/omap-usb.txt
+++ b/Documentation/devicetree/bindings/usb/omap-usb.txt
@@ -76,27 +76,3 @@ omap_dwc3 {
ranges;
};
-OMAP CONTROL USB
-
-Required properties:
- - compatible: Should be one of
- ti,control-phy-otghs - if it has otghs_control mailbox register as on OMAP4.
- ti,control-phy-usb2 - if it has Power down bit in control_dev_conf register
- e.g. USB2_PHY on OMAP5.
- ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
- e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
- DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
- AM437 platform.
- - reg : Address and length of the register set for the device. It contains
- the address of otghs_control for control-phy-otghs or power register
- for other types.
- - reg-names: should be otghs_control control-phy-otghs and power for
- other types.
-
-omap_control_usb: omap-control-usb@4a002300 {
- compatible = ti,control-phy-otghs;
- reg = 0x4a00233c 0x4;
- reg-names = otghs_control;
-};
--
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Re: [PATCH v2 03/13] phy: omap-control: update dra7 and am437 usb2 bindings
Felipe,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++--
Here too..
Acked-by: Kishon Vijay Abraham I kis...@ti.com
Regards
Kishon
drivers/phy/phy-omap-control.c | 4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 5c5b1b0..28e674b 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -9,9 +9,9 @@ Required properties:
e.g. USB2_PHY on OMAP5.
ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control
e.g. USB3 PHY and SATA PHY on OMAP5.
- ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-dra7-usb2 - if it has power down register like USB2 PHY on
DRA7 platform.
- ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on
+ ti,control-phy-am437-usb2 - if it has power down register like USB2 PHY on
AM437 platform.
- reg : Address and length of the register set for the device. It contains
the address of otghs_control for control-phy-otghs or power register
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
--
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Re: [PATCH v2 05/13] phy: ti-pipe3: Add SATA DPLL support
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Update the DT binding information.
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 3 +-
drivers/phy/phy-ti-pipe3.c | 76 +---
same here..
-Kishon
2 files changed, 57 insertions(+), 22 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 8d13349..2c2d66a 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -53,7 +53,8 @@ usb2phy@4a0ad080 {
TI PIPE3 PHY
Required properties:
- - compatible: Should be ti,phy-usb3. ti,omap-usb3 is deprecated.
+ - compatible: Should be ti,phy-usb3 or ti,phy-pipe3-sata.
+ ti,omap-usb3 is deprecated.
- reg : Address and length of the register set for the device.
- reg-names: The names of the register addresses corresponding to the
registers
filled in reg.
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
Re: [PATCH v2 04/13] phy: ti-pipe3: cleanup clock handling
Roger,
On Thursday 06 March 2014 08:08 PM, Roger Quadros wrote:
As this driver is no longer USB specific, use generic clock names.
- Use 'wkupclk', 'sysclk' and 'refclk' clock-names. Update DT binding info.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Update omap5 usb3_phy device tree node.
CC: Benoît Cousson bcous...@baylibre.com
CC: Tony Lindgren t...@atomide.com
Signed-off-by: Roger Quadros rog...@ti.com
---
Documentation/devicetree/bindings/phy/ti-phy.txt | 12 ++
arch/arm/boot/dts/omap5.dtsi | 7 ++-
drivers/phy/phy-ti-pipe3.c | 55
Here you have to split the patch. omap5.dtsi should be a separate patch
to Tony. I could take only phy-ti-pipe3.c again since ti-phy.txt is only
in Felipe's branch.
Regards
Kishon
3 files changed, 46 insertions(+), 28 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt
b/Documentation/devicetree/bindings/phy/ti-phy.txt
index 28e674b..8d13349 100644
--- a/Documentation/devicetree/bindings/phy/ti-phy.txt
+++ b/Documentation/devicetree/bindings/phy/ti-phy.txt
@@ -59,6 +59,12 @@ Required properties:
filled in reg.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
+ - clocks: a list of phandles and clock-specifier pairs, one for each entry in
+ clock-names.
+ - clock-names: should include:
+ * wkupclk - wakup clock.
+ * sysclk - system clock.
+ * refclk - reference clock.
Optional properties:
- ctrl-module : phandle of the control module used by PHY driver to power on
@@ -74,4 +80,10 @@ usb3phy@4a084400 {
reg-names = phy_rx, phy_tx, pll_ctrl;
ctrl-module = omap_control_usb;
#phy-cells = 0;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 859a800..e47601a 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -778,7 +778,12 @@
0x4a084800 0x64,
0x4a084c00 0x40;
reg-names = phy_rx, phy_tx, pll_ctrl;
- ctrl-module = omap_control_usb3phy;
+ clocks = usb_phy_cm_clk32k,
+sys_clkin,
+usb_otg_ss_refclk960m;
+ clock-names = wkupclk,
+ sysclk,
+ refclk;
#phy-cells = 0;
};
};
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#define PLL_SELFREQDCO_MASK 0x000E
#define PLL_SELFREQDCO_SHIFT0x1
#define PLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#define SET_PLL_GO 0x1
#define PLL_TICOPWDN0x1
#define PLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev = pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
[PATCH v3] phy: omap-control: update dra7 and am437 usb2 bindings
From: Roger Quadros rog...@ti.com
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
Kept only the drivers/phy part in this patch
drivers/phy/phy-omap-control.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-dra7-usb2,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-am437-usb2,
.data = am437usb2_data,
},
{},
--
1.7.9.5
--
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[PATCH v3] phy: ti-pipe3: cleanup clock handling
From: Roger Quadros rog...@ti.com
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
* Kept only the drivers/phy part in this patch
drivers/phy/phy-ti-pipe3.c | 55 ++--
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#definePLL_SELFREQDCO_MASK 0x000E
#definePLL_SELFREQDCO_SHIFT0x1
#definePLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
#definePLL_TICOPWDN0x1
#definePLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
return -EINVAL;
}
@@ -326,10 +324,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
static int ti_pipe3_remove(struct platform_device *pdev)
{
- struct ti_pipe3 *phy = platform_get_drvdata(pdev);
-
- clk_unprepare(phy-wkupclk);
- clk_unprepare(phy-optclk);
if (!pm_runtime_suspended(pdev-dev))
pm_runtime_put(pdev-dev);
pm_runtime_disable(pdev-dev);
@@ -343,8 +337,10 @@ static int ti_pipe3_runtime_suspend(struct device *dev)
{
struct ti_pipe3 *phy = dev_get_drvdata(dev);
- clk_disable(phy-wkupclk);
- clk_disable(phy-optclk);
+ if (!IS_ERR(phy-wkupclk))
+ clk_disable_unprepare(phy-wkupclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
return 0;
}
@@ -354,22 +350,27 @@ static int ti_pipe3_runtime_resume(struct device *dev)
u32 ret = 0;
struct ti_pipe3 *phy = dev_get_drvdata(dev);
- ret = clk_enable(phy-optclk);
- if (ret) {
- dev_err(phy-dev, Failed to enable optclk %d\n, ret);
- goto err1;
+ if (!IS_ERR(phy-refclk)) {
+ ret = clk_prepare_enable(phy-refclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable refclk %d\n, ret);
+ goto err1;
+ }
}
- ret = clk_enable(phy-wkupclk);
- if (ret) {
- dev_err(phy-dev, Failed to enable wkupclk %d\n, ret);
- goto err2;
+ if (!IS_ERR(phy-wkupclk)) {
+ ret = clk_prepare_enable(phy-wkupclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable wkupclk %d\n, ret);
+ goto err2;
+ }
}
return 0;
err2:
- clk_disable(phy-optclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
err1:
return ret;
--
1.7.9.5
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[PATCH v3] phy: ti-pipe3: Add SATA DPLL support
From: Roger Quadros rog...@ti.com
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v2:
* kept only the drivers/phy part
drivers/phy/phy-ti-pipe3.c | 76
1 file changed, 55 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+ const struct of_device_id *match;
- if (!node)
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table), pdev-dev);
+ if (!match)
return -EINVAL;
phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
@@ -263,6 +281,12 @@ static int ti_pipe3_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ phy-dpll_map = (struct pipe3_dpll_map *)match-data;
+ if (!phy-dpll_map) {
+ dev_err(pdev-dev, no DPLL data\n);
+ return -EINVAL;
+ }
+
res = platform_get_resource_byname(pdev
Re: [PATCH v4] phy: omap-control: update dra7 and am437 usb2 Documentation bindings
On Friday 07 March 2014 01:55 PM, Kishon Vijay Abraham I wrote: From: Felipe Balbi ba...@ti.com From: Roger Quadros rog...@ti.com There seems to be some problem with this patch. Pls ignore this. Thanks Kishon The dra7-usb2 and am437-usb2 bindings have not yet been used. Change them to be more elegant. Acked-by: Kishon Vijay Abraham I kis...@ti.com Signed-off-by: Roger Quadros rog...@ti.com Signed-off-by: Felipe Balbi ba...@ti.com --- Changes from v3: * changed the compatible name to 'ti,control-phy-usb2-dra7' and 'ti,control-phy-usb2-am437' Documentation/devicetree/bindings/phy/ti-phy.txt | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/ti-phy.txt b/Documentation/devicetree/bindings/phy/ti-phy.txt index 41dc132..8694aae 100644 --- a/Documentation/devicetree/bindings/phy/ti-phy.txt +++ b/Documentation/devicetree/bindings/phy/ti-phy.txt @@ -9,9 +9,9 @@ Required properties: e.g. USB2_PHY on OMAP5. ti,control-phy-pipe3 - if it has DPLL and individual Rx Tx power control e.g. USB3 PHY and SATA PHY on OMAP5. - ti,control-phy-dra7usb2 - if it has power down register like USB2 PHY on + ti,control-phy-usb2-dra7 - if it has power down register like USB2 PHY on DRA7 platform. - ti,control-phy-am437usb2 - if it has power down register like USB2 PHY on + ti,control-phy-usb2-am437 - if it has power down register like USB2 PHY on AM437 platform. - reg : Address and length of the register set for the device. It contains the address of otghs_control for control-phy-otghs or power register -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v4] phy: omap-control: update dra7 and am437 usb2 bindings
From: Roger Quadros rog...@ti.com
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v3:
Changed the compatible value to that suggested by Tony.
ti,control-phy-usb2-dra7 and ti,control-phy-usb2-am437.
Changes from v2:
Kept only the drivers/phy part in this patch
drivers/phy/phy-omap-control.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..a7e2d7f 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-usb2-dra7,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-usb2-am437,
.data = am437usb2_data,
},
{},
--
1.7.9.5
--
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Re: [PATCH 5/8] phy: omap-usb2: Add clock names to Documentation binding
Felipe, On Friday 07 March 2014 09:34 PM, Felipe Balbi wrote: On Fri, Mar 07, 2014 at 03:09:08PM +0200, Roger Quadros wrote: Add wkupclk and refclk information to DT binding information. Signed-off-by: Roger Quadros rog...@ti.com --- so, should I take this one ? yes.. the ti-phy.txt is only in your tree. Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH v6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Changes from v5:
fixes the following compilation error
drivers/usb/phy/phy-twl6030-usb.c:30:32:
fatal error: linux/usb/omap_usb.h: No such file or directory
drivers/phy/phy-omap-usb2.c |2 +-
drivers/usb/phy/phy-twl6030-usb.c |2 +-
include/linux/{usb = phy}/omap_usb.h |3 ---
3 files changed, 2 insertions(+), 5 deletions(-)
rename include/linux/{usb = phy}/omap_usb.h (95%)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 705af5a..9c3f056 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -21,7 +21,7 @@
#include linux/slab.h
#include linux/of.h
#include linux/io.h
-#include linux/usb/omap_usb.h
+#include linux/phy/omap_usb.h
#include linux/usb/phy_companion.h
#include linux/clk.h
#include linux/err.h
diff --git a/drivers/usb/phy/phy-twl6030-usb.c
b/drivers/usb/phy/phy-twl6030-usb.c
index 214172b..04778cf 100644
--- a/drivers/usb/phy/phy-twl6030-usb.c
+++ b/drivers/usb/phy/phy-twl6030-usb.c
@@ -27,7 +27,7 @@
#include linux/io.h
#include linux/usb/musb-omap.h
#include linux/usb/phy_companion.h
-#include linux/usb/omap_usb.h
+#include linux/phy/omap_usb.h
#include linux/i2c/twl.h
#include linux/regulator/consumer.h
#include linux/err.h
diff --git a/include/linux/usb/omap_usb.h b/include/linux/phy/omap_usb.h
similarity index 95%
rename from include/linux/usb/omap_usb.h
rename to include/linux/phy/omap_usb.h
index 6ae2936..19d343c3 100644
--- a/include/linux/usb/omap_usb.h
+++ b/include/linux/phy/omap_usb.h
@@ -33,13 +33,10 @@ struct usb_dpll_params {
struct omap_usb {
struct usb_phy phy;
struct phy_companion*comparator;
- void __iomem*pll_ctrl_base;
struct device *dev;
struct device *control_dev;
struct clk *wkupclk;
- struct clk *sys_clk;
struct clk *optclk;
- u8 is_suspended:1;
};
#definephy_to_omapusb(x) container_of((x), struct omap_usb, phy)
--
1.7.9.5
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Re: [PATCH v6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
On Friday 07 March 2014 10:20 PM, Felipe Balbi wrote:
On Fri, Mar 07, 2014 at 10:18:08PM +0530, Kishon Vijay Abraham I wrote:
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
does this depend in any other patch ? I get the following when applying
*only* this patch on top of v3.14-rc5:
yeah.. this is for linux-phy tree. I'll take this patch.
Thanks
Kishon
drivers/phy/phy-omap-usb2.c: In function ‘omap_usb2_suspend’:
drivers/phy/phy-omap-usb2.c:106:21: error: ‘struct omap_usb’ has no member
named ‘is_suspended’
if (suspend !phy-is_suspended) {
^
drivers/phy/phy-omap-usb2.c:109:6: error: ‘struct omap_usb’ has no member named
‘is_suspended’
phy-is_suspended = 1;
^
drivers/phy/phy-omap-usb2.c:110:28: error: ‘struct omap_usb’ has no member
named ‘is_suspended’
} else if (!suspend phy-is_suspended) {
^
drivers/phy/phy-omap-usb2.c:117:6: error: ‘struct omap_usb’ has no member named
‘is_suspended’
phy-is_suspended = 0;
^
drivers/phy/phy-omap-usb2.c: In function ‘omap_usb2_probe’:
drivers/phy/phy-omap-usb2.c:194:5: error: ‘struct omap_usb’ has no member named
‘is_suspended’
phy-is_suspended = 1;
^
make[1]: *** [drivers/phy/phy-omap-usb2.o] Error 1
make: *** [drivers/phy/] Error 2
make: *** Waiting for unfinished jobs
CC [M] drivers/usb/phy/phy-mxs-usb.o
drivers/usb/phy/phy-omap-usb3.c:22:32: fatal error: linux/usb/omap_usb.h: No
such file or directory
#include linux/usb/omap_usb.h
^
compilation terminated.
make[1]: *** [drivers/usb/phy/phy-omap-usb3.o] Error 1
make[1]: *** Waiting for unfinished jobs
make: *** [drivers/usb/phy/] Error 2
--
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Re: [PATCH v6] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
On Friday 07 March 2014 11:10 PM, Felipe Balbi wrote: On Fri, Mar 07, 2014 at 11:09:02PM +0530, Kishon Vijay Abraham I wrote: On Friday 07 March 2014 10:20 PM, Felipe Balbi wrote: On Fri, Mar 07, 2014 at 10:18:08PM +0530, Kishon Vijay Abraham I wrote: No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/. Also removed the unused members of struct omap_usb (after phy-omap-pipe3 started using it's own header file) does this depend in any other patch ? I get the following when applying *only* this patch on top of v3.14-rc5: yeah.. this is for linux-phy tree. I'll take this patch. looks like you're doing two things at once (renaming the header and removing some unnecessary fields). At least mention the second thing. The second line of the commit message mentions just that ;-) Regards Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
Re: [PATCH v10 2/4] phy: core: Add devm_of_phy_get to phy-core
Tobias, On Saturday 08 March 2014 01:04 AM, Tobias Jakobi wrote: Kamil Debski wrote: Adding devm_of_phy_get will allow to get phys by supplying a pointer to the struct device_node instead of struct device. Signed-off-by: Kamil Debski k.deb...@samsung.com --- drivers/phy/phy-core.c | 31 +++ include/linux/phy/phy.h |8 2 files changed, 39 insertions(+) Tested-by: Tobias Jakobi tjak...@math.uni-bielefeld.de Thanks for testing these patches. However I've already queued all these patches so won't be able to add your 'Tested-by' :-s Thanks Kishon -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 05/28] phy: Select PHY_EXYNOS_DP_VIDEO by default for ARCH_EXYNOS
From: Sylwester Nawrocki s.nawro...@samsung.com Instead of requiring user to figure out when PHY_EXYNOS_DP_VIDEO needs to be selected select it by default for Exynos SoCs. Also enable it when COMPILE_TEST is selected. If required the display port PHY driver can be then disabled or compiled in as module. Signed-off-by: Sylwester Nawrocki s.nawro...@samsung.com Acked-by: Kyungmin Park kyungmin.p...@samsung.com Acked-by: Jingoo Han jg1@samsung.com Acked-by: Felipe Balbi ba...@ti.com Acked-by: Uwe Kleine-König u.kleine-koe...@pengutronix.de Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- drivers/phy/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index f0fb429..5bf9ed3 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -57,6 +57,8 @@ config TWL4030_USB config PHY_EXYNOS_DP_VIDEO tristate EXYNOS SoC series Display Port PHY driver depends on OF + depends on ARCH_EXYNOS || COMPILE_TEST + default ARCH_EXYNOS select GENERIC_PHY help Support for Display Port PHY found on Samsung EXYNOS SoCs. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 11/28] phy: omap-usb2: move omap_usb.h from linux/usb/ to linux/phy/
No functional change. Moved omap_usb.h from linux/usb/ to linux/phy/.
Also removed the unused members of struct omap_usb (after phy-omap-pipe3
started using it's own header file)
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-omap-usb2.c |2 +-
drivers/usb/phy/phy-twl6030-usb.c |2 +-
include/linux/{usb = phy}/omap_usb.h |3 ---
3 files changed, 2 insertions(+), 5 deletions(-)
rename include/linux/{usb = phy}/omap_usb.h (95%)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 705af5a..9c3f056 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -21,7 +21,7 @@
#include linux/slab.h
#include linux/of.h
#include linux/io.h
-#include linux/usb/omap_usb.h
+#include linux/phy/omap_usb.h
#include linux/usb/phy_companion.h
#include linux/clk.h
#include linux/err.h
diff --git a/drivers/usb/phy/phy-twl6030-usb.c
b/drivers/usb/phy/phy-twl6030-usb.c
index 214172b..04778cf 100644
--- a/drivers/usb/phy/phy-twl6030-usb.c
+++ b/drivers/usb/phy/phy-twl6030-usb.c
@@ -27,7 +27,7 @@
#include linux/io.h
#include linux/usb/musb-omap.h
#include linux/usb/phy_companion.h
-#include linux/usb/omap_usb.h
+#include linux/phy/omap_usb.h
#include linux/i2c/twl.h
#include linux/regulator/consumer.h
#include linux/err.h
diff --git a/include/linux/usb/omap_usb.h b/include/linux/phy/omap_usb.h
similarity index 95%
rename from include/linux/usb/omap_usb.h
rename to include/linux/phy/omap_usb.h
index 6ae2936..19d343c3 100644
--- a/include/linux/usb/omap_usb.h
+++ b/include/linux/phy/omap_usb.h
@@ -33,13 +33,10 @@ struct usb_dpll_params {
struct omap_usb {
struct usb_phy phy;
struct phy_companion*comparator;
- void __iomem*pll_ctrl_base;
struct device *dev;
struct device *control_dev;
struct clk *wkupclk;
- struct clk *sys_clk;
struct clk *optclk;
- u8 is_suspended:1;
};
#definephy_to_omapusb(x) container_of((x), struct omap_usb, phy)
--
1.7.9.5
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[PATCH 25/28] phy: ti-pipe3: Fix suspend/resume and module reload
From: Roger Quadros rog...@ti.com Due to Errata i783, SATA breaks if its DPLL is idled. The recommeded workaround to issue a softreset to the SATA controller doesn't seem to work. Here we just prevent SATA DPLL from Idling and hence avoid the issue altogether. Signed-off-by: Roger Quadros rog...@ti.com Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- drivers/phy/phy-ti-pipe3.c |4 1 file changed, 4 insertions(+) diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c index 12cc900..5913676 100644 --- a/drivers/phy/phy-ti-pipe3.c +++ b/drivers/phy/phy-ti-pipe3.c @@ -238,6 +238,10 @@ static int ti_pipe3_exit(struct phy *x) u32 val; unsigned long timeout; + /* SATA DPLL can't be powered down due to Errata i783 */ + if (of_device_is_compatible(phy-dev-of_node, ti,phy-pipe3-sata)) + return 0; + /* Put DPLL in IDLE mode */ val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2); val |= PLL_IDLE; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 22/28] phy: ti-pipe3: Add SATA DPLL support
From: Roger Quadros rog...@ti.com
USB and SATA DPLLs need different settings. Provide
the SATA DPLL settings and use the proper DPLL settings
based on device tree node's compatible_id.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 76
1 file changed, 55 insertions(+), 21 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index 211703c..f141237 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -66,6 +66,11 @@ struct pipe3_dpll_params {
u32 mf;
};
+struct pipe3_dpll_map {
+ unsigned long rate;
+ struct pipe3_dpll_params params;
+};
+
struct ti_pipe3 {
void __iomem*pll_ctrl_base;
struct device *dev;
@@ -73,20 +78,27 @@ struct ti_pipe3 {
struct clk *wkupclk;
struct clk *sys_clk;
struct clk *refclk;
+ struct pipe3_dpll_map *dpll_map;
};
-struct pipe3_dpll_map {
- unsigned long rate;
- struct pipe3_dpll_params params;
-};
-
-static struct pipe3_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map_usb[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
{2000, {1000, 7, 4, 10, 0} }, /* 20 MHz */
{2600, {1250, 12, 4, 20, 0} }, /* 26 MHz */
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
+ { },/* Terminator */
+};
+
+static struct pipe3_dpll_map dpll_map_sata[] = {
+ {1200, {1000, 7, 4, 6, 0} },/* 12 MHz */
+ {1680, {714, 7, 4, 6, 0} }, /* 16.8 MHz */
+ {1920, {625, 7, 4, 6, 0} }, /* 19.2 MHz */
+ {2000, {600, 7, 4, 6, 0} }, /* 20 MHz */
+ {2600, {461, 7, 4, 6, 0} }, /* 26 MHz */
+ {3840, {312, 7, 4, 6, 0} }, /* 38.4 MHz */
+ { },/* Terminator */
};
static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
@@ -100,15 +112,20 @@ static inline void ti_pipe3_writel(void __iomem *addr,
unsigned offset,
__raw_writel(data, addr + offset);
}
-static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
{
- int i;
+ unsigned long rate;
+ struct pipe3_dpll_map *dpll_map = phy-dpll_map;
- for (i = 0; i ARRAY_SIZE(dpll_map); i++) {
- if (rate == dpll_map[i].rate)
- return dpll_map[i].params;
+ rate = clk_get_rate(phy-sys_clk);
+
+ for (; dpll_map-rate; dpll_map++) {
+ if (rate == dpll_map-rate)
+ return dpll_map-params;
}
+ dev_err(phy-dev, No DPLL configuration for %lu Hz SYS CLK\n, rate);
+
return NULL;
}
@@ -182,16 +199,11 @@ static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
{
u32 val;
- unsigned long rate;
struct pipe3_dpll_params *dpll_params;
- rate = clk_get_rate(phy-sys_clk);
- dpll_params = ti_pipe3_get_dpll_params(rate);
- if (!dpll_params) {
- dev_err(phy-dev,
- No DPLL configuration for %lu Hz SYS CLK\n, rate);
+ dpll_params = ti_pipe3_get_dpll_params(phy);
+ if (!dpll_params)
return -EINVAL;
- }
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION1);
val = ~PLL_REGN_MASK;
@@ -244,6 +256,10 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct of_device_id ti_pipe3_id_table[];
+#endif
+
static int ti_pipe3_probe(struct platform_device *pdev)
{
struct ti_pipe3 *phy;
@@ -253,8 +269,10 @@ static int ti_pipe3_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+ const struct of_device_id *match;
- if (!node)
+ match = of_match_device(of_match_ptr(ti_pipe3_id_table), pdev-dev);
+ if (!match)
return -EINVAL;
phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
@@ -263,6 +281,12 @@ static int ti_pipe3_probe(struct platform_device *pdev)
return -ENOMEM;
}
+ phy-dpll_map = (struct pipe3_dpll_map *)match-data;
+ if (!phy-dpll_map) {
+ dev_err(pdev-dev, no DPLL data\n);
+ return -EINVAL;
+ }
+
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, pll_ctrl);
phy-pll_ctrl_base
[PATCH 23/28] phy: ti-pipe3: Don't get 'wkupclk' and 'refclk' for SATA PHY
From: Roger Quadros rog...@ti.com
SATA PHY doesn't need 'wkupclk; and 'refclk' so don't
try to get them for SATA PHY.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index f141237..baa3f78d 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -294,16 +294,22 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
- if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get wkupclk\n);
- return PTR_ERR(phy-wkupclk);
- }
+ if (!of_device_is_compatible(node, ti,phy-pipe3-sata)) {
+
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
+ if (IS_ERR(phy-wkupclk)) {
+ dev_err(pdev-dev, unable to get wkupclk\n);
+ return PTR_ERR(phy-wkupclk);
+ }
- phy-refclk = devm_clk_get(phy-dev, refclk);
- if (IS_ERR(phy-refclk)) {
- dev_err(pdev-dev, unable to get refclk\n);
- return PTR_ERR(phy-refclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
+ }
+ } else {
+ phy-wkupclk = ERR_PTR(-ENODEV);
+ phy-refclk = ERR_PTR(-ENODEV);
}
phy-sys_clk = devm_clk_get(phy-dev, sysclk);
--
1.7.9.5
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[PATCH 21/28] phy: ti-pipe3: cleanup clock handling
From: Roger Quadros rog...@ti.com
As this driver is no longer USB specific, use generic clock names.
- Fix PLL_SD_SHIFT from 9 to 10
- Don't separate prepare/unprepare clock from enable/disable. This
ensures optimal power savings.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 55 ++--
1 file changed, 28 insertions(+), 27 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index fd029b1..211703c 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -45,7 +45,7 @@
#definePLL_SELFREQDCO_MASK 0x000E
#definePLL_SELFREQDCO_SHIFT0x1
#definePLL_SD_MASK 0x0003FC00
-#definePLL_SD_SHIFT0x9
+#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
#definePLL_TICOPWDN0x1
#definePLL_LOCK0x2
@@ -72,7 +72,7 @@ struct ti_pipe3 {
struct device *control_dev;
struct clk *wkupclk;
struct clk *sys_clk;
- struct clk *optclk;
+ struct clk *refclk;
};
struct pipe3_dpll_map {
@@ -270,23 +270,21 @@ static int ti_pipe3_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
- phy-wkupclk = devm_clk_get(phy-dev, usb_phy_cm_clk32k);
+ phy-wkupclk = devm_clk_get(phy-dev, wkupclk);
if (IS_ERR(phy-wkupclk)) {
- dev_err(pdev-dev, unable to get usb_phy_cm_clk32k\n);
+ dev_err(pdev-dev, unable to get wkupclk\n);
return PTR_ERR(phy-wkupclk);
}
- clk_prepare(phy-wkupclk);
- phy-optclk = devm_clk_get(phy-dev, usb_otg_ss_refclk960m);
- if (IS_ERR(phy-optclk)) {
- dev_err(pdev-dev, unable to get usb_otg_ss_refclk960m\n);
- return PTR_ERR(phy-optclk);
+ phy-refclk = devm_clk_get(phy-dev, refclk);
+ if (IS_ERR(phy-refclk)) {
+ dev_err(pdev-dev, unable to get refclk\n);
+ return PTR_ERR(phy-refclk);
}
- clk_prepare(phy-optclk);
- phy-sys_clk = devm_clk_get(phy-dev, sys_clkin);
+ phy-sys_clk = devm_clk_get(phy-dev, sysclk);
if (IS_ERR(phy-sys_clk)) {
- pr_err(%s: unable to get sys_clkin\n, __func__);
+ dev_err(pdev-dev, unable to get sysclk\n);
return -EINVAL;
}
@@ -326,10 +324,6 @@ static int ti_pipe3_probe(struct platform_device *pdev)
static int ti_pipe3_remove(struct platform_device *pdev)
{
- struct ti_pipe3 *phy = platform_get_drvdata(pdev);
-
- clk_unprepare(phy-wkupclk);
- clk_unprepare(phy-optclk);
if (!pm_runtime_suspended(pdev-dev))
pm_runtime_put(pdev-dev);
pm_runtime_disable(pdev-dev);
@@ -343,8 +337,10 @@ static int ti_pipe3_runtime_suspend(struct device *dev)
{
struct ti_pipe3 *phy = dev_get_drvdata(dev);
- clk_disable(phy-wkupclk);
- clk_disable(phy-optclk);
+ if (!IS_ERR(phy-wkupclk))
+ clk_disable_unprepare(phy-wkupclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
return 0;
}
@@ -354,22 +350,27 @@ static int ti_pipe3_runtime_resume(struct device *dev)
u32 ret = 0;
struct ti_pipe3 *phy = dev_get_drvdata(dev);
- ret = clk_enable(phy-optclk);
- if (ret) {
- dev_err(phy-dev, Failed to enable optclk %d\n, ret);
- goto err1;
+ if (!IS_ERR(phy-refclk)) {
+ ret = clk_prepare_enable(phy-refclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable refclk %d\n, ret);
+ goto err1;
+ }
}
- ret = clk_enable(phy-wkupclk);
- if (ret) {
- dev_err(phy-dev, Failed to enable wkupclk %d\n, ret);
- goto err2;
+ if (!IS_ERR(phy-wkupclk)) {
+ ret = clk_prepare_enable(phy-wkupclk);
+ if (ret) {
+ dev_err(phy-dev, Failed to enable wkupclk %d\n, ret);
+ goto err2;
+ }
}
return 0;
err2:
- clk_disable(phy-optclk);
+ if (!IS_ERR(phy-refclk))
+ clk_disable_unprepare(phy-refclk);
err1:
return ret;
--
1.7.9.5
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[PATCH 16/28] phy: omap-usb2: Adapt phy-omap-usb2 for AM437x
From: George Cherian george.cher...@ti.com
Adapt phy-omap-usb2 driver for AM437x.
- Add new comaptible ti,am437x-usb2 for AM437x
- Pass proper data to differentiate AM437x and others.
- AM437x doesnot support set_vbus and start_srp.
- Also update the Documentation to add new compatible.
Signed-off-by: George Cherian george.cher...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/usb-phy.txt |4 +-
drivers/phy/phy-omap-usb2.c | 49 -
include/linux/phy/omap_usb.h |9
3 files changed, 49 insertions(+), 13 deletions(-)
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt
b/Documentation/devicetree/bindings/usb/usb-phy.txt
index c0245c8..b3fa409 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -3,7 +3,9 @@ USB PHY
OMAP USB2 PHY
Required properties:
- - compatible: Should be ti,omap-usb2
+ - compatible: Should be either of
+ * ti,omap-usb2 for OMAP4, OMAP5, DRA7
+ * ti,am437x-usb2 for AM437x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 9c3f056..0c78f54 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -122,6 +122,31 @@ static struct phy_ops ops = {
.owner = THIS_MODULE,
};
+#ifdef CONFIG_OF
+static const struct usb_phy_data omap_usb2_data = {
+ .label = omap_usb2,
+ .flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
+};
+
+static const struct usb_phy_data am437x_usb2_data = {
+ .label = am437x_usb2,
+ .flags = 0,
+};
+
+static const struct of_device_id omap_usb2_id_table[] = {
+ {
+ .compatible = ti,omap-usb2,
+ .data = omap_usb2_data,
+ },
+ {
+ .compatible = ti,am437x-usb2,
+ .data = am437x_usb2_data,
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
+#endif
+
static int omap_usb2_probe(struct platform_device *pdev)
{
struct omap_usb *phy;
@@ -131,10 +156,16 @@ static int omap_usb2_probe(struct platform_device *pdev)
struct device_node *node = pdev-dev.of_node;
struct device_node *control_node;
struct platform_device *control_pdev;
+ const struct of_device_id *of_id;
+ struct usb_phy_data *phy_data;
+
+ of_id = of_match_device(of_match_ptr(omap_usb2_id_table), pdev-dev);
- if (!node)
+ if (!of_id)
return -EINVAL;
+ phy_data = (struct usb_phy_data *)of_id-data;
+
phy = devm_kzalloc(pdev-dev, sizeof(*phy), GFP_KERNEL);
if (!phy) {
dev_err(pdev-dev, unable to allocate memory for USB2 PHY\n);
@@ -150,7 +181,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-dev= pdev-dev;
phy-phy.dev= phy-dev;
- phy-phy.label = omap-usb2;
+ phy-phy.label = phy_data-label;
phy-phy.otg= otg;
phy-phy.type = USB_PHY_TYPE_USB2;
@@ -171,8 +202,10 @@ static int omap_usb2_probe(struct platform_device *pdev)
otg-set_host = omap_usb_set_host;
otg-set_peripheral = omap_usb_set_peripheral;
- otg-set_vbus = omap_usb_set_vbus;
- otg-start_srp = omap_usb_start_srp;
+ if (phy_data-flags OMAP_USB2_HAS_SET_VBUS)
+ otg-set_vbus = omap_usb_set_vbus;
+ if (phy_data-flags OMAP_USB2_HAS_START_SRP)
+ otg-start_srp = omap_usb_start_srp;
otg-phy= phy-phy;
platform_set_drvdata(pdev, phy);
@@ -272,14 +305,6 @@ static const struct dev_pm_ops omap_usb2_pm_ops = {
#define DEV_PM_OPS NULL
#endif
-#ifdef CONFIG_OF
-static const struct of_device_id omap_usb2_id_table[] = {
- { .compatible = ti,omap-usb2 },
- {}
-};
-MODULE_DEVICE_TABLE(of, omap_usb2_id_table);
-#endif
-
static struct platform_driver omap_usb2_driver = {
.probe = omap_usb2_probe,
.remove = omap_usb2_remove,
diff --git a/include/linux/phy/omap_usb.h b/include/linux/phy/omap_usb.h
index 19d343c3..35989a8 100644
--- a/include/linux/phy/omap_usb.h
+++ b/include/linux/phy/omap_usb.h
@@ -39,6 +39,15 @@ struct omap_usb {
struct clk *optclk;
};
+struct usb_phy_data {
+ const char *label;
+ u8 flags;
+};
+
+/* Driver Flags */
+#define OMAP_USB2_HAS_START_SRP (1 0)
+#define OMAP_USB2_HAS_SET_VBUS (1 1)
+
#definephy_to_omapusb(x) container_of((x), struct omap_usb, phy)
#if defined(CONFIG_OMAP_USB2) || defined(CONFIG_OMAP_USB2_MODULE)
--
1.7.9.5
[PATCH 27/28] Documentation: Add APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding documentation
From: Loc Ho l...@apm.com
This patch adds the APM X-Gene SoC 15Gbps Multi-purpose PHY driver binding
documentation.
Signed-off-by: Loc Ho l...@apm.com
Signed-off-by: Tuan Phan tp...@apm.com
Signed-off-by: Suman Tripathi stripa...@apm.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/phy/apm-xgene-phy.txt | 79
1 file changed, 79 insertions(+)
create mode 100644 Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
new file mode 100644
index 000..5f3a65a
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/apm-xgene-phy.txt
@@ -0,0 +1,79 @@
+* APM X-Gene 15Gbps Multi-purpose PHY nodes
+
+PHY nodes are defined to describe on-chip 15Gbps Multi-purpose PHY. Each
+PHY (pair of lanes) has its own node.
+
+Required properties:
+- compatible : Shall be apm,xgene-phy.
+- reg : PHY memory resource is the SDS PHY access resource.
+- #phy-cells : Shall be 1 as it expects one argument for setting
+ the mode of the PHY. Possible values are 0 (SATA),
+ 1 (SGMII), 2 (PCIe), 3 (USB), and 4 (XFI).
+
+Optional properties:
+- status : Shall be ok if enabled or disabled if disabled.
+ Default is ok.
+- clocks : Reference to the clock entry.
+- apm,tx-eye-tuning: Manual control to fine tune the capture of the serial
+ bit lines from the automatic calibrated position.
+ Two set of 3-tuple setting for each (up to 3)
+ supported link speed on the host. Range from 0 to
+ 127 in unit of one bit period. Default is 10.
+- apm,tx-eye-direction : Eye tuning manual control direction. 0 means sample
+ data earlier than the nominal sampling point. 1 means
+ sample data later than the nominal sampling point.
+ Two set of 3-tuple setting for each (up to 3)
+ supported link speed on the host. Default is 0.
+- apm,tx-boost-gain: Frequency boost AC (LSB 3-bit) and DC (2-bit)
+ gain control. Two set of 3-tuple setting for each
+ (up to 3) supported link speed on the host. Range is
+ between 0 to 31 in unit of dB. Default is 3.
+- apm,tx-amplitude : Amplitude control. Two set of 3-tuple setting for
+ each (up to 3) supported link speed on the host.
+ Range is between 0 to 199500 in unit of uV.
+ Default is 199500 uV.
+- apm,tx-pre-cursor1 : 1st pre-cursor emphasis taps control. Two set of
+ 3-tuple setting for each (up to 3) supported link
+ speed on the host. Range is 0 to 273000 in unit of
+ uV. Default is 0.
+- apm,tx-pre-cursor2 : 2st pre-cursor emphasis taps control. Two set of
+ 3-tuple setting for each (up to 3) supported link
+ speed on the host. Range is 0 to 127400 in unit uV.
+ Default is 0x0.
+- apm,tx-post-cursor : Post-cursor emphasis taps control. Two set of
+ 3-tuple setting for Gen1, Gen2, and Gen3. Range is
+ between 0 to 0x1f in unit of 18.2mV. Default is 0xf.
+- apm,tx-speed : Tx operating speed. One set of 3-tuple for each
+ supported link speed on the host.
+ 0 = 1-2Gbps
+ 1 = 2-4Gbps (1st tuple default)
+ 2 = 4-8Gbps
+ 3 = 8-15Gbps (2nd tuple default)
+ 4 = 2.5-4Gbps
+ 5 = 4-5Gbps
+ 6 = 5-6Gbps
+ 7 = 6-16Gbps (3rd tuple default)
+
+NOTE: PHY override parameters are board specific setting.
+
+Example:
+ phy1: phy@1f21a000 {
+ compatible = apm,xgene-phy;
+ reg = 0x0 0x1f21a000 0x0 0x100;
+ #phy-cells = 1;
+ status = disabled;
+ };
+
+ phy2: phy@1f22a000 {
+ compatible = apm,xgene-phy;
+ reg = 0x0 0x1f22a000 0x0 0x100;
+ #phy-cells = 1;
+ status = ok;
+ };
+
+ phy3: phy@1f23a000 {
+ compatible = apm,xgene-phy;
+ reg = 0x0 0x1f23a000 0x0 0x100;
+ #phy-cells = 1;
+ status = ok;
+ };
--
1.7.9.5
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[PATCH 20/28] phy: omap-control: update dra7 and am437 usb2 bindings
From: Roger Quadros rog...@ti.com
The dra7-usb2 and am437-usb2 bindings have not yet been used.
Change them to be more elegant.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-omap-control.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
index 17fc200..311b4f9 100644
--- a/drivers/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -228,11 +228,11 @@ static const struct of_device_id
omap_control_phy_id_table[] = {
.data = pipe3_data,
},
{
- .compatible = ti,control-phy-dra7usb2,
+ .compatible = ti,control-phy-usb2-dra7,
.data = dra7usb2_data,
},
{
- .compatible = ti,control-phy-am437usb2,
+ .compatible = ti,control-phy-usb2-am437,
.data = am437usb2_data,
},
{},
--
1.7.9.5
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[PATCH 18/28] phy: omap-usb2: Add different compatible for OMAP5
From: George Cherian george.cher...@ti.com
Add a new compatible for OMAP5 since it does not use any of the
OTG operations as of now.
HAS_SRP and SET_VBUS functionalities are used only for OMAP4.
Update the Documentation also to add new comaptible.
Signed-off-by: George Cherian george.cher...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/usb-phy.txt |3 ++-
drivers/phy/phy-omap-usb2.c |9 +
2 files changed, 11 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt
b/Documentation/devicetree/bindings/usb/usb-phy.txt
index 03de61a5..ec199a5 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -4,7 +4,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be either of
- * ti,omap-usb2 for OMAP4 and OMAP5
+ * ti,omap-usb2 for OMAP4
+ * ti,omap5-usb2 for OMAP5
* ti,dra7x-usb2 for DRA7
* ti,am437x-usb2 for AM437x
- reg : Address and length of the register set for the device.
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index b220202..3cc4aba 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -154,6 +154,11 @@ static const struct usb_phy_data omap_usb2_data = {
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
};
+static const struct usb_phy_data omap5_usb2_data = {
+ .label = omap5_usb2,
+ .flags = 0,
+};
+
static const struct usb_phy_data dra7x_usb2_data = {
.label = dra7x_usb2,
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
@@ -170,6 +175,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.data = omap_usb2_data,
},
{
+ .compatible = ti,omap5-usb2,
+ .data = omap5_usb2_data,
+ },
+ {
.compatible = ti,dra7x-usb2,
.data = dra7x_usb2_data,
},
--
1.7.9.5
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[PATCH 17/28] phy: omap-usb2: Provide workaround for USB2PHY false disconnect
From: Austin Beam austinb...@ti.com
Enable the dra7x errata workaround for false disconnect problem
with USB2PHY. False disconnects were detected with some of the devices.
Reduce the sensitivity of the disconnect logic within the USB2PHY subsystem
to enusre these false disconnects are not registered.
[george.cher...@ti.com]
While at that, pass proper flags for each SoC's. This is a common driver
used across OMAP4,OMAP5,DRA7xx and AM437x USB2PHY.
False disconnect workaround is currently applicable for only DRA7x.
Update the Documentation also to add new comaptible.
Signed-off-by: Austin Beam austinb...@ti.com
Signed-off-by: George Cherian george.cher...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
Documentation/devicetree/bindings/usb/usb-phy.txt |3 +-
drivers/phy/phy-omap-usb2.c | 44 +
include/linux/phy/omap_usb.h |4 ++
3 files changed, 50 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/usb/usb-phy.txt
b/Documentation/devicetree/bindings/usb/usb-phy.txt
index b3fa409..03de61a5 100644
--- a/Documentation/devicetree/bindings/usb/usb-phy.txt
+++ b/Documentation/devicetree/bindings/usb/usb-phy.txt
@@ -4,7 +4,8 @@ OMAP USB2 PHY
Required properties:
- compatible: Should be either of
- * ti,omap-usb2 for OMAP4, OMAP5, DRA7
+ * ti,omap-usb2 for OMAP4 and OMAP5
+ * ti,dra7x-usb2 for DRA7
* ti,am437x-usb2 for AM437x
- reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 0c78f54..b220202 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -31,6 +31,9 @@
#include linux/phy/phy.h
#include linux/of_platform.h
+#define USB2PHY_DISCON_BYP_LATCH (1 31)
+#define USB2PHY_ANA_CONFIG1 0x4c
+
/**
* omap_usb2_set_comparator - links the comparator present in the sytem with
* this phy
@@ -116,7 +119,30 @@ static int omap_usb_power_on(struct phy *x)
return 0;
}
+static int omap_usb_init(struct phy *x)
+{
+ struct omap_usb *phy = phy_get_drvdata(x);
+ u32 val;
+
+ if (phy-flags OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+ /*
+*
+* Reduce the sensitivity of internal PHY by enabling the
+* DISCON_BYP_LATCH of the USB2PHY_ANA_CONFIG1 register. This
+* resolves issues with certain devices which can otherwise
+* be prone to false disconnects.
+*
+*/
+ val = omap_usb_readl(phy-phy_base, USB2PHY_ANA_CONFIG1);
+ val |= USB2PHY_DISCON_BYP_LATCH;
+ omap_usb_writel(phy-phy_base, USB2PHY_ANA_CONFIG1, val);
+ }
+
+ return 0;
+}
+
static struct phy_ops ops = {
+ .init = omap_usb_init,
.power_on = omap_usb_power_on,
.power_off = omap_usb_power_off,
.owner = THIS_MODULE,
@@ -128,6 +154,11 @@ static const struct usb_phy_data omap_usb2_data = {
.flags = OMAP_USB2_HAS_START_SRP | OMAP_USB2_HAS_SET_VBUS,
};
+static const struct usb_phy_data dra7x_usb2_data = {
+ .label = dra7x_usb2,
+ .flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
+};
+
static const struct usb_phy_data am437x_usb2_data = {
.label = am437x_usb2,
.flags = 0,
@@ -139,6 +170,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.data = omap_usb2_data,
},
{
+ .compatible = ti,dra7x-usb2,
+ .data = dra7x_usb2_data,
+ },
+ {
.compatible = ti,am437x-usb2,
.data = am437x_usb2_data,
},
@@ -151,6 +186,7 @@ static int omap_usb2_probe(struct platform_device *pdev)
{
struct omap_usb *phy;
struct phy *generic_phy;
+ struct resource *res;
struct phy_provider *phy_provider;
struct usb_otg *otg;
struct device_node *node = pdev-dev.of_node;
@@ -185,6 +221,14 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-phy.otg= otg;
phy-phy.type = USB_PHY_TYPE_USB2;
+ if (phy_data-flags OMAP_USB2_CALIBRATE_FALSE_DISCONNECT) {
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ phy-phy_base = devm_ioremap_resource(pdev-dev, res);
+ if (!phy-phy_base)
+ return -ENOMEM;
+ phy-flags |= OMAP_USB2_CALIBRATE_FALSE_DISCONNECT;
+ }
+
control_node = of_parse_phandle(node, ctrl-module, 0);
if (!control_node) {
dev_err(pdev-dev, Failed to get control device phandle\n);
diff --git a/include/linux/phy/omap_usb.h b/include/linux/phy/omap_usb.h
index 35989a8..dc2c541 100644
--- a/include/linux/phy/omap_usb.h
+++ b/include/linux
[PATCH 24/28] phy: ti-pipe3: streamline PHY operations
From: Roger Quadros rog...@ti.com
Limit .power_on() and .power_off() to just control the
PHY power and not the DPLL. The DPLL will be enabled
in .init() and idled in .exit().
Don't reprogram the DPLL if it has been already locked
by the bootloader. This fixes a problem with SATA, where
it fails if SATA was used by the bootloader.
Signed-off-by: Roger Quadros rog...@ti.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-ti-pipe3.c | 114
1 file changed, 63 insertions(+), 51 deletions(-)
diff --git a/drivers/phy/phy-ti-pipe3.c b/drivers/phy/phy-ti-pipe3.c
index baa3f78d..12cc900 100644
--- a/drivers/phy/phy-ti-pipe3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -47,7 +47,8 @@
#definePLL_SD_MASK 0x0003FC00
#definePLL_SD_SHIFT10
#defineSET_PLL_GO 0x1
-#definePLL_TICOPWDN0x1
+#define PLL_LDOPWDNBIT(15)
+#define PLL_TICOPWDN BIT(16)
#definePLL_LOCK0x2
#definePLL_IDLE0x1
@@ -56,7 +57,8 @@
* value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
* to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
-# define PLL_IDLE_TIME 100;
+#define PLL_IDLE_TIME 100 /* in milliseconds */
+#define PLL_LOCK_TIME 100 /* in milliseconds */
struct pipe3_dpll_params {
u16 m;
@@ -132,24 +134,6 @@ static struct pipe3_dpll_params
*ti_pipe3_get_dpll_params(struct ti_pipe3 *phy)
static int ti_pipe3_power_off(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int val;
- int timeout = PLL_IDLE_TIME;
-
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
- val |= PLL_IDLE;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
-
- do {
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
- if (val PLL_TICOPWDN)
- break;
- udelay(5);
- } while (--timeout);
-
- if (!timeout) {
- dev_err(phy-dev, power off failed\n);
- return -EBUSY;
- }
omap_control_phy_power(phy-control_dev, 0);
@@ -159,44 +143,34 @@ static int ti_pipe3_power_off(struct phy *x)
static int ti_pipe3_power_on(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int val;
- int timeout = PLL_IDLE_TIME;
-
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
- val = ~PLL_IDLE;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
- do {
- val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
- if (!(val PLL_TICOPWDN))
- break;
- udelay(5);
- } while (--timeout);
-
- if (!timeout) {
- dev_err(phy-dev, power on failed\n);
- return -EBUSY;
- }
+ omap_control_phy_power(phy-control_dev, 1);
return 0;
}
-static void ti_pipe3_dpll_relock(struct ti_pipe3 *phy)
+static int ti_pipe3_dpll_wait_lock(struct ti_pipe3 *phy)
{
u32 val;
unsigned long timeout;
- ti_pipe3_writel(phy-pll_ctrl_base, PLL_GO, SET_PLL_GO);
-
- timeout = jiffies + msecs_to_jiffies(20);
+ timeout = jiffies + msecs_to_jiffies(PLL_LOCK_TIME);
do {
+ cpu_relax();
val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_STATUS);
if (val PLL_LOCK)
break;
- } while (!WARN_ON(time_after(jiffies, timeout)));
+ } while (!time_after(jiffies, timeout));
+
+ if (!(val PLL_LOCK)) {
+ dev_err(phy-dev, DPLL failed to lock\n);
+ return -EBUSY;
+ }
+
+ return 0;
}
-static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
+static int ti_pipe3_dpll_program(struct ti_pipe3 *phy)
{
u32 val;
struct pipe3_dpll_params *dpll_params;
@@ -230,27 +204,65 @@ static int ti_pipe3_dpll_lock(struct ti_pipe3 *phy)
val |= dpll_params-sd PLL_SD_SHIFT;
ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION3, val);
- ti_pipe3_dpll_relock(phy);
+ ti_pipe3_writel(phy-pll_ctrl_base, PLL_GO, SET_PLL_GO);
- return 0;
+ return ti_pipe3_dpll_wait_lock(phy);
}
static int ti_pipe3_init(struct phy *x)
{
struct ti_pipe3 *phy = phy_get_drvdata(x);
- int ret;
+ u32 val;
+ int ret = 0;
- ret = ti_pipe3_dpll_lock(phy);
- if (ret)
- return ret;
+ /* Bring it out of IDLE if it is IDLE */
+ val = ti_pipe3_readl(phy-pll_ctrl_base, PLL_CONFIGURATION2);
+ if (val PLL_IDLE) {
+ val = ~PLL_IDLE;
+ ti_pipe3_writel(phy-pll_ctrl_base, PLL_CONFIGURATION2, val);
+ ret = ti_pipe3_dpll_wait_lock(phy);
+ }
- omap_control_phy_power
[PATCH 26/28] phy: omap: Depend on OMAP_OCP2SCP bus driver
From: Roger Quadros rog...@ti.com The OMAP_USB2 and OMAP_PIPE3 PHY devices will not be detected if the OMAP_OCP2SCP bus driver is not present. Make them depend on it. Signed-off-by: Roger Quadros rog...@ti.com Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- drivers/phy/Kconfig |2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index fe8c009..2aead8b 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -47,6 +47,7 @@ config OMAP_USB2 depends on USB_PHY select GENERIC_PHY select OMAP_CONTROL_PHY + depends on OMAP_OCP2SCP help Enable this to support the transceiver that is part of SOC. This driver takes care of all the PHY functionality apart from comparator. @@ -58,6 +59,7 @@ config TI_PIPE3 depends on ARCH_OMAP2PLUS || COMPILE_TEST select GENERIC_PHY select OMAP_CONTROL_PHY + depends on OMAP_OCP2SCP help Enable this to support the PIPE3 PHY that is part of TI SOCs. This driver takes care of all the PHY functionality apart from comparator. -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 15/28] phy: Add Exynos 5250 support to the Exynos USB 2.0 PHY driver
From: Kamil Debski k.deb...@samsung.com Add support for Exynos 5250. This driver is to replace the old USB 2.0 PHY driver. Signed-off-by: Kamil Debski k.deb...@samsung.com Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- .../devicetree/bindings/phy/samsung-phy.txt|1 + drivers/phy/Kconfig| 11 + drivers/phy/Makefile |1 + drivers/phy/phy-exynos5250-usb2.c | 404 drivers/phy/phy-samsung-usb2.c |6 + drivers/phy/phy-samsung-usb2.h |1 + 6 files changed, 424 insertions(+) create mode 100644 drivers/phy/phy-exynos5250-usb2.c diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt b/Documentation/devicetree/bindings/phy/samsung-phy.txt index bf955ab..28f9edb 100644 --- a/Documentation/devicetree/bindings/phy/samsung-phy.txt +++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt @@ -28,6 +28,7 @@ Required properties: - compatible : should be one of the listed compatibles: - samsung,exynos4210-usb2-phy - samsung,exynos4x12-usb2-phy + - samsung,exynos5250-usb2-phy - reg : a list of registers used by phy driver - first and obligatory is the location of phy modules registers - samsung,sysreg-phandle - handle to syscon used to control the system registers diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3374836..1b607d7 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -136,4 +136,15 @@ config PHY_EXYNOS4X12_USB2 Samsung USB 2.0 PHY driver is enabled and means that support for this particular SoC is compiled in the driver. In case of Exynos 4x12 four phys are available - device, host, HSIC0 and HSIC1. + +config PHY_EXYNOS5250_USB2 + bool Support for Exynos 5250 + depends on PHY_SAMSUNG_USB2 + depends on SOC_EXYNOS5250 + help + Enable USB PHY support for Exynos 5250. This option requires that + Samsung USB 2.0 PHY driver is enabled and means that support for this + particular SoC is compiled in the driver. In case of Exynos 5250 four + phys are available - device, host, HSIC0 and HSIC. + endmenu diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index c4ddd23..ecf0d3f 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -15,3 +15,4 @@ obj-$(CONFIG_PHY_SUN4I_USB) += phy-sun4i-usb.o obj-$(CONFIG_PHY_SAMSUNG_USB2) += phy-samsung-usb2.o obj-$(CONFIG_PHY_EXYNOS4210_USB2) += phy-exynos4210-usb2.o obj-$(CONFIG_PHY_EXYNOS4X12_USB2) += phy-exynos4x12-usb2.o +obj-$(CONFIG_PHY_EXYNOS5250_USB2) += phy-exynos5250-usb2.o diff --git a/drivers/phy/phy-exynos5250-usb2.c b/drivers/phy/phy-exynos5250-usb2.c new file mode 100644 index 000..94179af --- /dev/null +++ b/drivers/phy/phy-exynos5250-usb2.c @@ -0,0 +1,404 @@ +/* + * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support + * + * Copyright (C) 2013 Samsung Electronics Co., Ltd. + * Author: Kamil Debski k.deb...@samsung.com + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include linux/delay.h +#include linux/io.h +#include linux/phy/phy.h +#include linux/regmap.h +#include phy-samsung-usb2.h + +/* Exynos USB PHY registers */ +#define EXYNOS_5250_REFCLKSEL_CRYSTAL 0x0 +#define EXYNOS_5250_REFCLKSEL_XO 0x1 +#define EXYNOS_5250_REFCLKSEL_CLKCORE 0x2 + +#define EXYNOS_5250_FSEL_9MHZ6 0x0 +#define EXYNOS_5250_FSEL_10MHZ 0x1 +#define EXYNOS_5250_FSEL_12MHZ 0x2 +#define EXYNOS_5250_FSEL_19MHZ20x3 +#define EXYNOS_5250_FSEL_20MHZ 0x4 +#define EXYNOS_5250_FSEL_24MHZ 0x5 +#define EXYNOS_5250_FSEL_50MHZ 0x7 + +/* Normal host */ +#define EXYNOS_5250_HOSTPHYCTRL0 0x0 + +#define EXYNOS_5250_HOSTPHYCTRL0_PHYSWRSTALL BIT(31) +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT 19 +#define EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_MASK\ + (0x3 EXYNOS_5250_HOSTPHYCTRL0_REFCLKSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT16 +#define EXYNOS_5250_HOSTPHYCTRL0_FSEL_MASK \ + (0x7 EXYNOS_5250_HOSTPHYCTRL0_FSEL_SHIFT) +#define EXYNOS_5250_HOSTPHYCTRL0_TESTBURNINBIT(11) +#define EXYNOS_5250_HOSTPHYCTRL0_RETENABLE BIT(10) +#define EXYNOS_5250_HOSTPHYCTRL0_COMMON_ON_N BIT(9) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_MASK(0x3 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_DUAL(0x0 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ID0 (0x1 7) +#define EXYNOS_5250_HOSTPHYCTRL0_VATESTENB_ANALOGTEST (0x2 7) +#define EXYNOS_5250_HOSTPHYCTRL0_SIDDQ BIT(6) +#define EXYNOS_5250_HOSTPHYCTRL0_FORCESLEEPBIT(5
[PATCH 19/28] phy: rename struct omap_control_usb to struct omap_control_phy
Rename struct omap_control_usb to struct omap_control_phy since it can
be used to control PHY of USB, SATA and PCIE. Also move the driver and
include files under *phy* and made the corresponding changes in the users
of phy-omap-control.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Signed-off-by: Roger Quadros rog...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
---
drivers/phy/Kconfig| 14 +-
drivers/phy/Makefile |1 +
drivers/{usb = }/phy/phy-omap-control.c | 165 ++--
drivers/phy/phy-omap-usb2.c|8 +-
drivers/phy/phy-ti-pipe3.c |8 +-
drivers/usb/musb/omap2430.c|2 +-
drivers/usb/phy/Kconfig| 10 --
drivers/usb/phy/Makefile |1 -
.../omap_control_usb.h = phy/omap_control_phy.h} | 36 ++---
9 files changed, 123 insertions(+), 122 deletions(-)
rename drivers/{usb = }/phy/phy-omap-control.c (55%)
rename include/linux/{usb/omap_control_usb.h = phy/omap_control_phy.h} (68%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 1b607d7..fe8c009 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -31,12 +31,22 @@ config PHY_MVEBU_SATA
depends on OF
select GENERIC_PHY
+config OMAP_CONTROL_PHY
+ tristate OMAP CONTROL PHY Driver
+ help
+ Enable this to add support for the PHY part present in the control
+ module. This driver has API to power on the USB2 PHY and to write to
+ the mailbox. The mailbox is present only in omap4 and the register to
+ power on the USB2 PHY is present in OMAP4 and OMAP5. OMAP5 has an
+ additional register to power on USB3 PHY/SATA PHY/PCIE PHY
+ (PIPE3 PHY).
+
config OMAP_USB2
tristate OMAP USB2 PHY Driver
depends on ARCH_OMAP2PLUS
depends on USB_PHY
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator.
@@ -47,7 +57,7 @@ config TI_PIPE3
tristate TI PIPE3 PHY Driver
depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY
- select OMAP_CONTROL_USB
+ select OMAP_CONTROL_PHY
help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator.
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index ecf0d3f..8da05a8 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -7,6 +7,7 @@ obj-$(CONFIG_BCM_KONA_USB2_PHY) += phy-bcm-kona-usb2.o
obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
+obj-$(CONFIG_OMAP_CONTROL_PHY) += phy-omap-control.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
diff --git a/drivers/usb/phy/phy-omap-control.c b/drivers/phy/phy-omap-control.c
similarity index 55%
rename from drivers/usb/phy/phy-omap-control.c
rename to drivers/phy/phy-omap-control.c
index e725318..17fc200 100644
--- a/drivers/usb/phy/phy-omap-control.c
+++ b/drivers/phy/phy-omap-control.c
@@ -1,5 +1,5 @@
/*
- * omap-control-usb.c - The USB part of control module.
+ * omap-control-phy.c - The PHY part of control module.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -24,36 +24,36 @@
#include linux/err.h
#include linux/io.h
#include linux/clk.h
-#include linux/usb/omap_control_usb.h
+#include linux/phy/omap_control_phy.h
/**
- * omap_control_usb_phy_power - power on/off the phy using control module reg
+ * omap_control_phy_power - power on/off the phy using control module reg
* @dev: the control module device
* @on: 0 or 1, based on powering on or off the PHY
*/
-void omap_control_usb_phy_power(struct device *dev, int on)
+void omap_control_phy_power(struct device *dev, int on)
{
u32 val;
unsigned long rate;
- struct omap_control_usb *control_usb;
+ struct omap_control_phy *control_phy;
if (IS_ERR(dev) || !dev) {
pr_err(%s: invalid device\n, __func__);
return;
}
- control_usb = dev_get_drvdata(dev);
- if (!control_usb) {
- dev_err(dev, %s: invalid control usb device\n, __func__);
+ control_phy = dev_get_drvdata(dev);
+ if (!control_phy) {
+ dev_err(dev, %s: invalid control phy device\n, __func__);
return
[PATCH 08/28] phy: mvebu-sata: prepare new Dove DT Kconfig variable
From: Sebastian Hesselbarth sebastian.hesselba...@gmail.com DT-enabled Dove will move over from ARCH_DOVE in mach-dove to MACH_DOVE in mach-mvebu. As non-DT ARCH_DOVE will stay to rot for a while, add a new DT-only MACH_DOVE Kconfig. Signed-off-by: Sebastian Hesselbarth sebastian.hesselba...@gmail.com Signed-off-by: Kishon Vijay Abraham I kis...@ti.com Acked-by: Jason Cooper ja...@lakedaemon.net --- drivers/phy/Kconfig |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index e677ee0..dc1756c 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -27,7 +27,7 @@ config PHY_EXYNOS_MIPI_VIDEO config PHY_MVEBU_SATA def_bool y - depends on ARCH_KIRKWOOD || ARCH_DOVE + depends on ARCH_KIRKWOOD || ARCH_DOVE || MACH_DOVE depends on OF select GENERIC_PHY -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
[PATCH 14/28] phy: Add new Exynos USB 2.0 PHY driver
From: Kamil Debski k.deb...@samsung.com
Add a new driver for the Exynos USB 2.0 PHY. The new driver uses the generic
PHY framework. The driver includes support for the Exynos 4x10 and 4x12
SoC families.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
.../devicetree/bindings/phy/samsung-phy.txt| 53
Documentation/phy/samsung-usb2.txt | 135
drivers/phy/Kconfig| 29 ++
drivers/phy/Makefile |3 +
drivers/phy/phy-exynos4210-usb2.c | 261
drivers/phy/phy-exynos4x12-usb2.c | 328
drivers/phy/phy-samsung-usb2.c | 222 +
drivers/phy/phy-samsung-usb2.h | 66
8 files changed, 1097 insertions(+)
create mode 100644 Documentation/phy/samsung-usb2.txt
create mode 100644 drivers/phy/phy-exynos4210-usb2.c
create mode 100644 drivers/phy/phy-exynos4x12-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.c
create mode 100644 drivers/phy/phy-samsung-usb2.h
diff --git a/Documentation/devicetree/bindings/phy/samsung-phy.txt
b/Documentation/devicetree/bindings/phy/samsung-phy.txt
index c0fccaa..bf955ab 100644
--- a/Documentation/devicetree/bindings/phy/samsung-phy.txt
+++ b/Documentation/devicetree/bindings/phy/samsung-phy.txt
@@ -20,3 +20,56 @@ Required properties:
- compatible : should be samsung,exynos5250-dp-video-phy;
- reg : offset and length of the Display Port PHY register set;
- #phy-cells : from the generic PHY bindings, must be 0;
+
+Samsung S5P/EXYNOS SoC series USB PHY
+-
+
+Required properties:
+- compatible : should be one of the listed compatibles:
+ - samsung,exynos4210-usb2-phy
+ - samsung,exynos4x12-usb2-phy
+- reg : a list of registers used by phy driver
+ - first and obligatory is the location of phy modules registers
+- samsung,sysreg-phandle - handle to syscon used to control the system
registers
+- samsung,pmureg-phandle - handle to syscon used to control PMU registers
+- #phy-cells : from the generic phy bindings, must be 1;
+- clocks and clock-names:
+ - the phy clock is required by the phy module, used as a gate
+ - the ref clock is used to get the rate of the clock provided to the
+ PHY module
+
+The first phandle argument in the PHY specifier identifies the PHY, its
+meaning is compatible dependent. For the currently supported SoCs (Exynos 4210
+and Exynos 4212) it is as follows:
+ 0 - USB device (device),
+ 1 - USB host (host),
+ 2 - HSIC0 (hsic0),
+ 3 - HSIC1 (hsic1),
+
+Exynos 4210 and Exynos 4212 use mode switching and require that mode switch
+register is supplied.
+
+Example:
+
+For Exynos 4412 (compatible with Exynos 4212):
+
+usbphy: phy@125b {
+ compatible = samsung,exynos4x12-usb2-phy;
+ reg = 0x125b 0x100;
+ clocks = clock 305, clock 2;
+ clock-names = phy, ref;
+ status = okay;
+ #phy-cells = 1;
+ samsung,sysreg-phandle = sys_reg;
+ samsung,pmureg-phandle = pmu_reg;
+};
+
+Then the PHY can be used in other nodes such as:
+
+phy-consumer@1234 {
+ phys = usbphy 2;
+ phy-names = phy;
+};
+
+Refer to DT bindings documentation of particular PHY consumer devices for more
+information about required PHYs and the way of specification.
diff --git a/Documentation/phy/samsung-usb2.txt
b/Documentation/phy/samsung-usb2.txt
new file mode 100644
index 000..ed12d43
--- /dev/null
+++ b/Documentation/phy/samsung-usb2.txt
@@ -0,0 +1,135 @@
+.--+
+| Samsung USB 2.0 PHY adaptation layer |
++-+'
+
+| 1. Description
++
+
+The architecture of the USB 2.0 PHY module in Samsung SoCs is similar
+among many SoCs. In spite of the similarities it proved difficult to
+create a one driver that would fit all these PHY controllers. Often
+the differences were minor and were found in particular bits of the
+registers of the PHY. In some rare cases the order of register writes or
+the PHY powering up process had to be altered. This adaptation layer is
+a compromise between having separate drivers and having a single driver
+with added support for many special cases.
+
+| 2. Files description
++--
+
+- phy-samsung-usb2.c
+ This is the main file of the adaptation layer. This file contains
+ the probe function and provides two callbacks to the Generic PHY
+ Framework. This two callbacks are used to power on and power off the
+ phy. They carry out the common work that has to be done on all version
+ of the PHY module. Depending on which SoC was chosen they execute SoC
[PATCH 10/28] usb: phy: omap-usb2: remove *set_suspend* callback from omap-usb2
Now that omap-usb2 is adapted to the new generic PHY framework,
*set_suspend* ops can be removed from omap-usb2 driver.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
Acked-by: Felipe Balbi ba...@ti.com
Reviewed-by: Sylwester Nawrocki s.nawro...@samsung.com
---
drivers/phy/phy-omap-usb2.c | 25 -
1 file changed, 25 deletions(-)
diff --git a/drivers/phy/phy-omap-usb2.c b/drivers/phy/phy-omap-usb2.c
index 7699752..705af5a 100644
--- a/drivers/phy/phy-omap-usb2.c
+++ b/drivers/phy/phy-omap-usb2.c
@@ -98,28 +98,6 @@ static int omap_usb_set_peripheral(struct usb_otg *otg,
return 0;
}
-static int omap_usb2_suspend(struct usb_phy *x, int suspend)
-{
- struct omap_usb *phy = phy_to_omapusb(x);
- int ret;
-
- if (suspend !phy-is_suspended) {
- omap_control_usb_phy_power(phy-control_dev, 0);
- pm_runtime_put_sync(phy-dev);
- phy-is_suspended = 1;
- } else if (!suspend phy-is_suspended) {
- ret = pm_runtime_get_sync(phy-dev);
- if (ret 0) {
- dev_err(phy-dev, get_sync failed with err %d\n, ret);
- return ret;
- }
- omap_control_usb_phy_power(phy-control_dev, 1);
- phy-is_suspended = 0;
- }
-
- return 0;
-}
-
static int omap_usb_power_off(struct phy *x)
{
struct omap_usb *phy = phy_get_drvdata(x);
@@ -173,7 +151,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
phy-phy.dev= phy-dev;
phy-phy.label = omap-usb2;
- phy-phy.set_suspend= omap_usb2_suspend;
phy-phy.otg= otg;
phy-phy.type = USB_PHY_TYPE_USB2;
@@ -190,8 +167,6 @@ static int omap_usb2_probe(struct platform_device *pdev)
}
phy-control_dev = control_pdev-dev;
-
- phy-is_suspended = 1;
omap_control_usb_phy_power(phy-control_dev, 0);
otg-set_host = omap_usb_set_host;
--
1.7.9.5
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[PATCH 12/28] phy: core: Add an exported of_phy_get function
From: Kamil Debski k.deb...@samsung.com
Previously the of_phy_get function took a struct device * and
was declared static. It was impossible to call it from
another driver and thus it was impossible to get phy defined
for a given node. The old function was renamed to _of_phy_get
and was left for internal use. of_phy_get function was added
and it was exported. The function enables to get a phy for
a given device tree node.
Signed-off-by: Kamil Debski k.deb...@samsung.com
Reviewed-by: Tomasz Figa t.f...@samsung.com
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/phy-core.c | 45 -
include/linux/phy/phy.h |6 ++
2 files changed, 42 insertions(+), 9 deletions(-)
diff --git a/drivers/phy/phy-core.c b/drivers/phy/phy-core.c
index 6c73837..7c1b0e1 100644
--- a/drivers/phy/phy-core.c
+++ b/drivers/phy/phy-core.c
@@ -274,8 +274,8 @@ int phy_power_off(struct phy *phy)
EXPORT_SYMBOL_GPL(phy_power_off);
/**
- * of_phy_get() - lookup and obtain a reference to a phy by phandle
- * @dev: device that requests this phy
+ * _of_phy_get() - lookup and obtain a reference to a phy by phandle
+ * @np: device_node for which to get the phy
* @index: the index of the phy
*
* Returns the phy associated with the given phandle value,
@@ -284,20 +284,17 @@ EXPORT_SYMBOL_GPL(phy_power_off);
* not yet loaded. This function uses of_xlate call back function provided
* while registering the phy_provider to find the phy instance.
*/
-static struct phy *of_phy_get(struct device *dev, int index)
+static struct phy *_of_phy_get(struct device_node *np, int index)
{
int ret;
struct phy_provider *phy_provider;
struct phy *phy = NULL;
struct of_phandle_args args;
- ret = of_parse_phandle_with_args(dev-of_node, phys, #phy-cells,
+ ret = of_parse_phandle_with_args(np, phys, #phy-cells,
index, args);
- if (ret) {
- dev_dbg(dev, failed to get phy in %s node\n,
- dev-of_node-full_name);
+ if (ret)
return ERR_PTR(-ENODEV);
- }
mutex_lock(phy_provider_mutex);
phy_provider = of_phy_provider_lookup(args.np);
@@ -317,6 +314,36 @@ err0:
}
/**
+ * of_phy_get() - lookup and obtain a reference to a phy using a device_node.
+ * @np: device_node for which to get the phy
+ * @con_id: name of the phy from device's point of view
+ *
+ * Returns the phy driver, after getting a refcount to it; or
+ * -ENODEV if there is no such phy. The caller is responsible for
+ * calling phy_put() to release that count.
+ */
+struct phy *of_phy_get(struct device_node *np, const char *con_id)
+{
+ struct phy *phy = NULL;
+ int index = 0;
+
+ if (con_id)
+ index = of_property_match_string(np, phy-names, con_id);
+
+ phy = _of_phy_get(np, index);
+ if (IS_ERR(phy))
+ return phy;
+
+ if (!try_module_get(phy-ops-owner))
+ return ERR_PTR(-EPROBE_DEFER);
+
+ get_device(phy-dev);
+
+ return phy;
+}
+EXPORT_SYMBOL_GPL(of_phy_get);
+
+/**
* phy_put() - release the PHY
* @phy: the phy returned by phy_get()
*
@@ -407,7 +434,7 @@ struct phy *phy_get(struct device *dev, const char *string)
if (dev-of_node) {
index = of_property_match_string(dev-of_node, phy-names,
string);
- phy = of_phy_get(dev, index);
+ phy = _of_phy_get(dev-of_node, index);
} else {
phy = phy_lookup(dev, string);
}
diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h
index 3f83459..50c7629 100644
--- a/include/linux/phy/phy.h
+++ b/include/linux/phy/phy.h
@@ -151,6 +151,7 @@ struct phy *devm_phy_get(struct device *dev, const char
*string);
struct phy *devm_phy_optional_get(struct device *dev, const char *string);
void phy_put(struct phy *phy);
void devm_phy_put(struct device *dev, struct phy *phy);
+struct phy *of_phy_get(struct device_node *np, const char *con_id);
struct phy *of_phy_simple_xlate(struct device *dev,
struct of_phandle_args *args);
struct phy *phy_create(struct device *dev, const struct phy_ops *ops,
@@ -259,6 +260,11 @@ static inline void devm_phy_put(struct device *dev, struct
phy *phy)
{
}
+static inline struct phy *of_phy_get(struct device_node *np, const char
*con_id)
+{
+ return ERR_PTR(-ENOSYS);
+}
+
static inline struct phy *of_phy_simple_xlate(struct device *dev,
struct of_phandle_args *args)
{
--
1.7.9.5
--
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[PATCH 09/28] drivers: phy: usb3/pipe3: Adapt pipe3 driver to Generic PHY Framework
Adapted omap-usb3 PHY driver to Generic PHY Framework and moved phy-omap-usb3
driver in drivers/usb/phy to drivers/phy and also renamed the file to
phy-ti-pipe3 since this same driver will be used for SATA PHY and
PCIE PHY.
Signed-off-by: Kishon Vijay Abraham I kis...@ti.com
---
drivers/phy/Kconfig| 11 +
drivers/phy/Makefile |1 +
.../phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} | 240
drivers/usb/phy/Kconfig| 11 -
drivers/usb/phy/Makefile |1 -
5 files changed, 158 insertions(+), 106 deletions(-)
rename drivers/{usb/phy/phy-omap-usb3.c = phy/phy-ti-pipe3.c} (54%)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index dc1756c..fde4192 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -43,6 +43,17 @@ config OMAP_USB2
The USB OTG controller communicates with the comparator using this
driver.
+config TI_PIPE3
+ tristate TI PIPE3 PHY Driver
+ depends on ARCH_OMAP2PLUS || COMPILE_TEST
+ select GENERIC_PHY
+ select OMAP_CONTROL_USB
+ help
+ Enable this to support the PIPE3 PHY that is part of TI SOCs. This
+ driver takes care of all the PHY functionality apart from comparator.
+ This driver interacts with the OMAP Control PHY Driver to power
+ on/off the PHY.
+
config TWL4030_USB
tristate TWL4030 USB Transceiver Driver
depends on TWL4030_CORE REGULATOR_TWL4030 USB_MUSB_OMAP2PLUS
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index 5d0b59e..977a50e 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_EXYNOS_DP_VIDEO) += phy-exynos-dp-video.o
obj-$(CONFIG_PHY_EXYNOS_MIPI_VIDEO)+= phy-exynos-mipi-video.o
obj-$(CONFIG_PHY_MVEBU_SATA) += phy-mvebu-sata.o
obj-$(CONFIG_OMAP_USB2)+= phy-omap-usb2.o
+obj-$(CONFIG_TI_PIPE3) += phy-ti-pipe3.o
obj-$(CONFIG_TWL4030_USB) += phy-twl4030-usb.o
obj-$(CONFIG_PHY_EXYNOS5250_SATA) += phy-exynos5250-sata.o
obj-$(CONFIG_PHY_SUN4I_USB)+= phy-sun4i-usb.o
diff --git a/drivers/usb/phy/phy-omap-usb3.c b/drivers/phy/phy-ti-pipe3.c
similarity index 54%
rename from drivers/usb/phy/phy-omap-usb3.c
rename to drivers/phy/phy-ti-pipe3.c
index 0c6ba29..c8d1674 100644
--- a/drivers/usb/phy/phy-omap-usb3.c
+++ b/drivers/phy/phy-ti-pipe3.c
@@ -1,5 +1,5 @@
/*
- * omap-usb3 - USB PHY, talking to dwc3 controller in OMAP.
+ * phy-ti-pipe3 - PIPE3 PHY driver.
*
* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
* This program is free software; you can redistribute it and/or modify
@@ -19,10 +19,11 @@
#include linux/module.h
#include linux/platform_device.h
#include linux/slab.h
-#include linux/usb/omap_usb.h
+#include linux/phy/phy.h
#include linux/of.h
#include linux/clk.h
#include linux/err.h
+#include linux/io.h
#include linux/pm_runtime.h
#include linux/delay.h
#include linux/usb/omap_control_usb.h
@@ -52,17 +53,34 @@
/*
* This is an Empirical value that works, need to confirm the actual
- * value required for the USB3PHY_PLL_CONFIGURATION2.PLL_IDLE status
- * to be correctly reflected in the USB3PHY_PLL_STATUS register.
+ * value required for the PIPE3PHY_PLL_CONFIGURATION2.PLL_IDLE status
+ * to be correctly reflected in the PIPE3PHY_PLL_STATUS register.
*/
# define PLL_IDLE_TIME 100;
-struct usb_dpll_map {
+struct pipe3_dpll_params {
+ u16 m;
+ u8 n;
+ u8 freq:3;
+ u8 sd;
+ u32 mf;
+};
+
+struct ti_pipe3 {
+ void __iomem*pll_ctrl_base;
+ struct device *dev;
+ struct device *control_dev;
+ struct clk *wkupclk;
+ struct clk *sys_clk;
+ struct clk *optclk;
+};
+
+struct pipe3_dpll_map {
unsigned long rate;
- struct usb_dpll_params params;
+ struct pipe3_dpll_params params;
};
-static struct usb_dpll_map dpll_map[] = {
+static struct pipe3_dpll_map dpll_map[] = {
{1200, {1250, 5, 4, 20, 0} }, /* 12 MHz */
{1680, {3125, 20, 4, 20, 0} }, /* 16.8 MHz */
{1920, {1172, 8, 4, 20, 65537} }, /* 19.2 MHz */
@@ -71,7 +89,18 @@ static struct usb_dpll_map dpll_map[] = {
{3840, {3125, 47, 4, 20, 92843} }, /* 38.4 MHz */
};
-static struct usb_dpll_params *omap_usb3_get_dpll_params(unsigned long rate)
+static inline u32 ti_pipe3_readl(void __iomem *addr, unsigned offset)
+{
+ return __raw_readl(addr + offset);
+}
+
+static inline void ti_pipe3_writel(void __iomem *addr, unsigned offset,
+ u32 data)
+{
+ __raw_writel(data, addr + offset);
+}
+
+static struct pipe3_dpll_params *ti_pipe3_get_dpll_params(unsigned long rate)
{
int i;
@@ -83,110 +112,123 @@ static struct
[PATCH 01/28] usb: phy: twl4030-usb: Silence checkpatch warnings
From: Sachin Kamat sachin.ka...@linaro.org Silences the following warnings: WARNING: sizeof *twl should be sizeof(*twl) WARNING: sizeof *otg should be sizeof(*otg) Signed-off-by: Sachin Kamat sachin.ka...@linaro.org Signed-off-by: Kishon Vijay Abraham I kis...@ti.com --- drivers/phy/phy-twl4030-usb.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/phy/phy-twl4030-usb.c b/drivers/phy/phy-twl4030-usb.c index c3ace1d..6c7cec7 100644 --- a/drivers/phy/phy-twl4030-usb.c +++ b/drivers/phy/phy-twl4030-usb.c @@ -661,7 +661,7 @@ static int twl4030_usb_probe(struct platform_device *pdev) struct phy_provider *phy_provider; struct phy_init_data*init_data = NULL; - twl = devm_kzalloc(pdev-dev, sizeof *twl, GFP_KERNEL); + twl = devm_kzalloc(pdev-dev, sizeof(*twl), GFP_KERNEL); if (!twl) return -ENOMEM; @@ -676,7 +676,7 @@ static int twl4030_usb_probe(struct platform_device *pdev) return -EINVAL; } - otg = devm_kzalloc(pdev-dev, sizeof *otg, GFP_KERNEL); + otg = devm_kzalloc(pdev-dev, sizeof(*otg), GFP_KERNEL); if (!otg) return -ENOMEM; -- 1.7.9.5 -- To unsubscribe from this list: send the line unsubscribe linux-kernel in the body of a message to majord...@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
