Hi Geert,
On 29/01/21 6:37 pm, Geert Uytterhoeven wrote:
> The help text for the PCI_EPF_NTB config symbol uses the acronym "NTB".
> However, this acronym is not explained there.
> Expand the acronym to make it easier for users to decide if they need to
> enable the PCI_EPF_NTB option or not.
>
Hi Arnd, Lorenzo,
On 25/01/21 5:04 pm, Arnd Bergmann wrote:
> From: Arnd Bergmann
>
> The newly added pci-epf-ntb driver uses configfs, which
> causes a link failure when that is disabled at compile-time:
>
> arm-linux-gnueabi-ld: drivers/pci/endpoint/functions/pci-epf-ntb.o: in
> function
Hi Randy,
On 29/01/21 6:35 am, Randy Dunlap wrote:
> On 1/4/21 7:28 AM, Kishon Vijay Abraham I wrote:
>> Add specification for the *PCI NTB* function device. The endpoint function
>> driver and the host PCI driver should be created based on this
>> specification.
>>
>
Hi Kunihiko,
On 24/01/21 8:39 pm, Kunihiko Hayashi wrote:
> Set the polling function and call the init function to enable EPC restart
> management. The polling function detects that the bus-reset signal is a
> rising edge.
>
> Signed-off-by: Kunihiko Hayashi
> ---
>
Hi Kunihiko,
On 24/01/21 8:39 pm, Kunihiko Hayashi wrote:
> This adds a member 'started' as a boolean value to struct pci_epc to set
> whether the controller is started, and also adds a function to get the
> value.
>
> Signed-off-by: Kunihiko Hayashi
> ---
> drivers/pci/endpoint/pci-epc-core.c
Hi Lorenzo,
On 28/01/21 5:41 pm, Lorenzo Pieralisi wrote:
> On Fri, Jan 22, 2021 at 07:48:52PM +0530, Kishon Vijay Abraham I wrote:
>> Hi Bjorn,
>>
>> On 20/01/21 12:04 am, Bjorn Helgaas wrote:
>>> On Mon, Jan 04, 2021 at 08:58:53PM +0530, Kishon Vijay Abraham I
Hi Steen,
On 15/01/21 9:44 pm, Steen Hegelund wrote:
> Hi Kishon,
>
> On Fri, 2021-01-15 at 21:22 +0530, Kishon Vijay Abraham I wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you
>> know the content is safe
>>
>> Hi,
>>
>&
On 22/12/20 12:35 pm, Kishon Vijay Abraham I wrote:
> The previous version of the patch series can be found @ [1]
>
> Changes from v1:
> 1) Remove the part that prevents configuration if the SERDES is already
>configured and focus only on using external clock and
Hi Bjorn,
On 20/01/21 12:04 am, Bjorn Helgaas wrote:
> On Mon, Jan 04, 2021 at 08:58:53PM +0530, Kishon Vijay Abraham I wrote:
>> Add specification for the *PCI NTB* function device. The endpoint function
>> driver and the host PCI driver should be created based on this
&
Hi Bjorn,
On 20/01/21 12:04 am, Bjorn Helgaas wrote:
> On Mon, Jan 04, 2021 at 08:59:09PM +0530, Kishon Vijay Abraham I wrote:
>> Add documentation to help users use pci-epf-ntb function driver and
>> existing host side NTB infrastructure for NTB functionality.
>>
>>
Hi Qinglang,
On 18/01/21 6:17 pm, Lorenzo Pieralisi wrote:
> On Wed, Oct 28, 2020 at 05:15:49PM +0800, Qinglang Miao wrote:
>> Add the missing destroy_workqueue() before return from
>> pci_epf_test_init() in the error handling case.
>>
>> Signed-off-by: Qinglang Miao
>> ---
>>
Hi,
On 04/01/21 9:16 pm, Kishon Vijay Abraham I wrote:
> +MAINTAINERS for platforms supporting PCIe EP mode
>
> Hi All,
>
> I've looped you in since the platform you maintain supports PCIe EP
> mode. This series builds NTB functionality on top of PCIe endpoint
> framework.
Hi,
On 07/01/21 2:49 pm, Steen Hegelund wrote:
> Provide a new ethernet phy configuration structure, that
> allow PHYs used for ethernet to be configured with
> speed, media type and clock information.
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
> Reviewed-by: Andrew Lunn
Hi,
On 07/01/21 2:49 pm, Steen Hegelund wrote:
> Provide a new ethernet phy configuration structure, that
> allow PHYs used for ethernet to be configured with
> speed, media type and clock information.
>
> Signed-off-by: Lars Povlsen
> Signed-off-by: Steen Hegelund
> Reviewed-by: Andrew Lunn
t;
> Fixes: 2c04c5b8eef79 ("PCI: pci-epf-test: Use pci_epc_get_features() to get
> EPC features")
> Reviewed-by: Pankaj Dubey
> Signed-off-by: Sriram Dash
> Signed-off-by: Shradha Todi
Reviewed-by: Kishon Vijay Abraham I
> ---
> drivers/pci/endpoint/functio
cro name.
> Changes in v2:
> - 16bit read in place of 8bit.
Could get GEN2 card enumerated in GEN2 mode in J7ES EVM.
Tested-by: Kishon Vijay Abraham I
Thanks
Kishon
>
> Nadeem Athani (2):
> PCI: cadence: Shifting of a function to support new code.
> PCI: cadence: Retrain Link
ate: 475400 KB/s
WRITE => Size: 67108864 bytes DMA: YESTime: 0.049701495
seconds Rate: 1318592 KB/s
With this series
READ => Size: 67108864 bytes DMA: YESTime: 0.045611175
seconds Rate: 1436840 KB/s
WRITE => Size: 67108864 bytes DMA: YESTime: 0.042737440
seconds Rate: 1533456 KB/s
Tested-by: Kishon Vijay Abraham I
Thanks
Kishon
Hi Peter,
On 08/01/21 4:16 pm, Peter Rosin wrote:
> Hi!
>
> On 2020-12-24 12:42, Kishon Vijay Abraham I wrote:
>> AM64 has a single lane SERDES which can be configured to be used
>> with either PCIe or USB. Define the possilbe values for the SERDES
>> function in AM64
Hi Rob,
On 08/01/21 8:33 am, Rob Herring wrote:
> On Thu, Dec 24, 2020 at 05:12:47PM +0530, Kishon Vijay Abraham I wrote:
>> AM64 has a single lane SERDES which can be configured to be used
>> with either PCIe or USB. Define the possilbe values for the SERDES
>> func
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 63 +++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64
x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Kishon Vijay Abraham I
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts| 15 +++
1 file changed, 15 insertions
value
as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
(Since this doesn't impact existing functionality, it need not be
backported to older kernels).
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4
1 file changed, 4 deletions(-)
1E DTS.
[1] -> http://lore.kernel.org/r/20201102101154.13598-1-kis...@ti.com
[2] -> http://lore.kernel.org/r/20201210130747.25436-1-kis...@ti.com
[3] -> http://lore.kernel.org/r/20210104122232.24071-1-kis...@ti.com
Kishon Vijay Abraham I (6):
arm64: dts: ti: k3-j721e-main: Fix supported max outb
Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j7200-common-proc-board.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
Remove "syscon" nodes added for pcieX_ctrl and have the PCIe node point
to the parent with an offset argument. This change is as discussed in [1].
[1] ->
http://lore.kernel.org/r/cal_jsqkiuco76bo1goepwm1tusjwoty_bry2hfsgtevmqtr...@mail.gmail.com
Signed-off-by: Kishon Vijay Abraha
075052.8911-1-kis...@ti.com
> [6] -> http://lore.kernel.org/r/20200915042110.3015-1-kis...@ti.com
> [7] -> http://lore.kernel.org/r/20200918064227.1463-1-kis...@ti.com
> [8] -> http://lore.kernel.org/r/20200924092519.17082-1-kis...@ti.com
> [9] -> https://youtu.be/dLKKxrg5-rY
to the user.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-ep-cfs.c | 23 +++
include/linux/pci-epf.h | 3 +++
2 files changed, 26 insertions(+)
diff --git a/drivers/pci/endpoint/pci-ep-cfs.c
b/drivers/pci/endpoint/pci-ep-cfs.c
index
Add binding documentation for pci-ntb endpoint function that helps in
adding and configuring pci-ntb endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/function/binding/pci-ntb.rst | 38 +++
Documentation/PCI/endpoint/index.rst | 1 +
2 files
ace).
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pcie-cadence-ep.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/pci/controller/cadence/pcie-cadence-ep.c
b/drivers/pci/controller/cadence/pcie-cadence-ep.c
index dc88078194cb..897cdde02
Add documentation to help users use pci-epf-ntb function driver and
existing host side NTB infrastructure for NTB functionality.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Randy Dunlap
---
Documentation/PCI/endpoint/index.rst | 1 +
Documentation/PCI/endpoint/pci-ntb
directly write to the physical address (in outbound
region) of the other interface to ring doorbell using MSI.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 41 +
include/linux/pci-epc.h | 8 ++
2 files changed, 49
Nishanth,
On 04/01/21 8:21 pm, Nishanth Menon wrote:
> On 18:52-20210104, Kishon Vijay Abraham I wrote:
>> Nishanth,
>>
>> On 04/01/21 6:46 pm, Nishanth Menon wrote:
>>> On 18:40-20210104, Kishon Vijay Abraham I wrote:
>>>> Nishanth,
>>&
device has configurable number of memory windows
(Max 4), configurable number of doorbell (Max 32), and configurable
number of scratch-pad registers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/ntb/hw/Kconfig | 1 +
drivers/ntb/hw/Makefile | 1 +
drivers/ntb/hw/epf
Add TI J721E device to the pci id database. Since this device has
a configurable PCIe endpoint, it could be used with different
drivers.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/misc/pci_endpoint_test.c | 1 -
include/linux/pci_ids.h | 1 +
2 files changed, 1 insertion(+), 1
64 bit BAR while
returning the first free unreserved BAR.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epc-core.c
b/drivers/pci/endpoint/pci-epc-co
Add a new endpoint function driver to provide NTB functionality
using multiple PCIe endpoint instances.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/Kconfig | 12 +
drivers/pci/endpoint/functions/Makefile |1 +
drivers/pci/endpoint/functions/pci-epf
Implement ->msi_map_irq() ops in order to map physical address to
MSI address and return MSI data.
Signed-off-by: Kishon Vijay Abraham I
---
.../pci/controller/cadence/pcie-cadence-ep.c | 53 +++
1 file changed, 53 insertions(+)
diff --git a/drivers/pci/controller/cadence/p
ops to be populated by the function driver if it has to
expose any function specific attributes and pci_epf_type_add_cfs() to
be invoked by pci-ep-cfs.c when sub-directory to main function directory
is created.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c |
Remove unused pci_epf_match_device() function added in pci-epf-core.c
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epf-core.c | 16
include/linux/pci-epf.h | 2 --
2 files changed, 18 deletions(-)
diff --git a/drivers/pci/endpoint/pci-epf
te a single EPC device with a EPF device will continue to work.
Signed-off-by: Kishon Vijay Abraham I
---
.../PCI/endpoint/pci-endpoint-cfs.rst | 10 ++
drivers/pci/endpoint/pci-ep-cfs.c | 147 ++
2 files changed, 157 insertions(+)
diff --git a/Documentat
. This is in
preparation for adding NTB endpoint function driver.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 11 ++--
drivers/pci/endpoint/pci-ep-cfs.c | 6 +-
drivers/pci/endpoint/pci-epc-core.c | 47 +++
drivers/pci
Modify pci_epc_get_next_free_bar() and pci_epc_get_first_free_bar() to
return error values if there are no free BARs available.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/functions/pci-epf-test.c | 2 ++
drivers/pci/endpoint/pci-epc-core.c | 12
Add an API to get the next unreserved BAR starting from a given BAR
number that can be used by the endpoint function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/endpoint/pci-epc-core.c | 26 ++
include/linux/pci-epc.h | 2 ++
2 files changed, 24
0201111153559.19050-1-kis...@ti.com
Kishon Vijay Abraham I (17):
Documentation: PCI: Add specification for the *PCI NTB* function
device
PCI: endpoint: Make *_get_first_free_bar() take into account 64 bit
BAR
PCI: endpoint: Add helper API to get the 'next' unreserved BAR
PCI: endpoi
Add specification for the *PCI NTB* function device. The endpoint function
driver and the host PCI driver should be created based on this
specification.
Signed-off-by: Kishon Vijay Abraham I
---
Documentation/PCI/endpoint/index.rst | 1 +
.../PCI/endpoint/pci-ntb-function.rst
Nishanth,
On 04/01/21 6:46 pm, Nishanth Menon wrote:
> On 18:40-20210104, Kishon Vijay Abraham I wrote:
>> Nishanth,
>>
>> On 04/01/21 6:29 pm, Nishanth Menon wrote:
>>> On 17:52-20210104, Kishon Vijay Abraham I wrote:
>>>> Patch series adds DT n
Hi Rob,
On 15/12/20 9:31 pm, Rob Herring wrote:
> On Wed, Nov 11, 2020 at 9:37 AM Kishon Vijay Abraham I wrote:
>>
>> Implement ->msi_map_irq() ops in order to map physical address to
>> MSI address and return MSI data.
>>
>> Signed-off-by: Kishon Vijay Abra
Nishanth,
On 04/01/21 6:29 pm, Nishanth Menon wrote:
> On 17:52-20210104, Kishon Vijay Abraham I wrote:
>> Patch series adds DT nodes in order to get PCIe working in J7200.
>> Also includes couple of fixes for J721e.
>>
>> v1 of the patch series can be found @ [1]
&g
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff
to the connector.
v1 of the patch series can be found @ [1]
Changes from v1:
*) Fixed missing initialization of "ret" variable in the error path.
[1] -> http://lore.kernel.org/r/20201224115658.2795-1-kis...@ti.com
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add binding to rep
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller/cadence/pci-j721e.c
Add binding to represent refclk to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/pci/ti,j721e-pci-host.yaml | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
b
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions
Add sub-nodes to SERDES0 DT node to represent SERDES0 is connected
to PCIe and QSGMII (multi-link SERDES).
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j7200-common-proc-board.dts | 23 +++
1 file changed, 23 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3
dts: ti: k3-j721e-main: Add PCIe device tree
nodes")
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Rob Herring
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 48 ---
1 file changed, 8 insertions(+), 40 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.
value
as 32, remove "cdns,max-outbound-regions" from endpoint DT node.
Fixes: 4e5833884f66 ("arm64: dts: ti: k3-j721e-main: Add PCIe device tree
nodes")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 4
1 file changed, 4 deletions(-)
x2 lane PCIe slot in the common processor board is enabled and connected to
j7200 SOM. Add PCIe DT node in common processor board to reflect the
same.
Signed-off-by: Kishon Vijay Abraham I
---
.../boot/dts/ti/k3-j7200-common-proc-board.dts| 15 +++
1 file changed, 15 insertions
Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j7200.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 48 +++
1 file changed, 48 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
b
Add dt node for the single instance of WIZ (SERDES wrapper) and
SERDES module shared by PCIe, CPSW (SGMII/QSGMII) and USB.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 63 +++
1 file changed, 63 insertions(+)
diff --git a/arch/arm64
36-1-kis...@ti.com
Kishon Vijay Abraham I (6):
arm64: dts: ti: k3-j721e-main: Fix supported max outbound regions
arm64: dts: ti: k3-j721e-main: Remove "syscon" nodes added for
pcieX_ctrl
arm64: dts: ti: k3-j7200-main: Add SERDES and WIZ device tree node
arm64: dts: ti: k3-j
Hi,
On 24/12/20 5:26 pm, Kishon Vijay Abraham I wrote:
> Add support to provide refclk to PCIe connector.
>
> Signed-off-by: Kishon Vijay Abraham I
> ---
> drivers/pci/controller/cadence/pci-j721e.c | 17 +
> 1 file changed, 17 insertions(+)
>
>
Add binding to represent refclk to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/pci/ti,j721e-pci-host.yaml | 17 +
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml
b
Add endpoint mode dt-bindings for TI's AM64 SoC. This is the same IP
used in J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-ep.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions
Add host mode dt-bindings for TI's AM64 SoC. This is the same IP used in
J7200, however AM64 is a non-coherent architecture.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/pci/ti,j721e-pci-host.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff
Add support to provide refclk to PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/pci/controller/cadence/pci-j721e.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/drivers/pci/controller/cadence/pci-j721e.c
b/drivers/pci/controller/cadence/pci-j721e.c
to the connector.
Kishon Vijay Abraham I (4):
dt-bindings: PCI: ti,j721e: Add binding to represent refclk to the
connector
dt-bindings: pci: ti,j721e: Add host mode dt-bindings for TI's AM64
SoC
dt-bindings: pci: ti,j721e: Add endpoint mode dt-bindings for TI's
AM64 SoC
PCI: j721e: Add
efclk both in local SERDES
and remote device. Add support here to drive refclk out.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-torrent.c | 158 ++
1 file changed, 158 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-torrent.c
b/drivers/p
The frequency of the txmclk between PCIe and SERDES has
changed to 250MHz from 500MHz. Configure full rate divider
for AM64 accordingly.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 43 +++---
1 file changed, 40 insertions(+), 3
Add DT binding for phy_en_refclk used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 13 +
1 file changed, 13 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e
wrapper (WIZ) bindings.
Kishon Vijay Abraham I (7):
dt-bindings: phy: ti,phy-j721e-wiz: Add bindings for AM64 SERDES
Wrapper
dt-bindings: phy: ti,phy-j721e-wiz: Add binding for phy_en_refclk
dt-bindings: phy: cadence-torrent: Add binding for refclk driver
dt-bindings: ti-serdes-mux: Add
as a clock, so that platforms like AM642 EVM can
enable it.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/ti/phy-j721e-wiz.c | 115 +
1 file changed, 115 insertions(+)
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 08acfab1ebe6
Add binding for refclk driver used to route the refclk out of the
SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-torrent.yaml | 17 +
1 file changed, 17 insertions(+)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence
AM64 has a single lane SERDES which can be configured to be used
with either PCIe or USB. Define the possilbe values for the SERDES
function in AM64 SoC here.
Signed-off-by: Kishon Vijay Abraham I
---
include/dt-bindings/mux/ti-serdes.h | 4
1 file changed, 4 insertions(+)
diff --git
Add bindings for AM64 SERDES Wrapper.
Signed-off-by: Kishon Vijay Abraham I
---
.../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml
b/Documentation
4: dts: ti: k3-j721e: Enable Super-Speed support for
USB0")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/a
Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 45 +++
1 file
the clock frequency.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++-
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 55 insertions
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
DT patches in this series (I can send this separately to DT
MAINTAINER once the driver patches are merged)
[1] -> http://lore.kernel.org/r/20201103035556.21260-1-kis...@ti.com
[2] -> http://lore.kernel.org/r/20201222070520.28132-1-kis...@ti.com
Kishon Vijay Abraham I (15):
phy: cadence:
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/dri
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
Add DT nodes for clocks within Sierra SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 --
1 file changed, 120 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3
Sierra has two PLLs, PLL_CMNLC and PLL_CMNLC1 and each of these PLLs has
two inputs, plllc_refclk and refrcv. Model PLL_CMNLC and PLL_CMNLC1 as
clocks so that it's possible to select one of these two inputs from
device tree.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy
to seamlessly use any of the external reference clocks.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/Kconfig | 1 +
drivers/phy/cadence/phy-cadence-sierra.c | 209 ++-
2 files changed, 207 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence
No functional change. Group devm_reset_control_get() and
devm_reset_control_get_optional() to a separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 36
1 file changed, 25 insertions(+), 11 deletions(-)
diff --git
d device tree) which represent the actual PHY.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy-cadence-sierra.c
index 19f32ae877b9.
node's name is "phy"
or "link" subnode.
Ideally all PHY dt nodes should have node name as "phy", however
existing devicetree used "link" as subnode. So in order to maintain old
DT compatibility get PHY properties for "phy" or "link" subnod
Add binding for the PLLs within SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
.../bindings/phy/phy-cadence-sierra.yaml | 89 ++-
1 file changed, 86 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
b/Documentation
wiz_init() immediately before invoking
of_platform_device_create().
Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in
TI J721E SoC")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.10
---
drivers/phy/ti/phy-j721e-wiz.c | 17 +++--
1 file
No functional change. Group all devm_clk_get_optional() to a
separate function.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 57 +++-
1 file changed, 35 insertions(+), 22 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence
No functional change. Since the reset controls obtained in
Sierra is exclusively used by the Sierra device, use
exclusive reset control request API calls.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions
4: dts: ti: k3-j721e: Enable Super-Speed support for
USB0")
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts
b/arch/a
Add DT nodes for clocks within Sierra SERDES.
Signed-off-by: Kishon Vijay Abraham I
---
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 128 --
1 file changed, 120 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
b/arch/arm64/boot/dts/ti/k3
Use external clock for all the SERDES used by PCIe controller. This will
make the same clock used by the local SERDES as well as the clock
provided to the PCIe connector.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 45 +++
1 file
the clock frequency.
Signed-off-by: Kishon Vijay Abraham I
---
.../dts/ti/k3-j721e-common-proc-board.dts | 4 ++
arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 58 ++-
2 files changed, 34 insertions(+), 28 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc
re.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I
Cc: # v5.4+
---
drivers/phy/cadence/phy-cadence-sierra.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/dri
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 56 +++-
1 file changed, 54 insertions
to seamlessly use any of the external reference clocks.
Signed-off-by: Kishon Vijay Abraham I
---
drivers/phy/cadence/phy-cadence-sierra.c | 391 ++-
1 file changed, 388 insertions(+), 3 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c
b/drivers/phy/cadence/phy
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